WO2024087320A1 - 半导体结构的形成方法及半导体结构 - Google Patents

半导体结构的形成方法及半导体结构 Download PDF

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Publication number
WO2024087320A1
WO2024087320A1 PCT/CN2022/136225 CN2022136225W WO2024087320A1 WO 2024087320 A1 WO2024087320 A1 WO 2024087320A1 CN 2022136225 W CN2022136225 W CN 2022136225W WO 2024087320 A1 WO2024087320 A1 WO 2024087320A1
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mask
layer
sub
material layer
etched
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PCT/CN2022/136225
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English (en)
French (fr)
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杨谦
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present disclosure relates to, but is not limited to, a method for forming a semiconductor structure and a semiconductor structure.
  • the feature size is small and the layout density is high.
  • the single exposure technology can no longer meet its lithography requirements, and only double or even multiple patterning technology can be used to complete the transfer of the design pattern.
  • the exposure-etching-exposure-etching (Litho-Etch-Litho-Etch, LELE) process is adopted, which decomposes the design pattern into multiple sets of independent low-density graphics, and transfers the design pattern to the chip through multiple exposures and multiple etches.
  • the present disclosure provides a method for forming a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method for forming a semiconductor structure, the method comprising:
  • the layer to be etched is etched according to the first mask layer to transfer the at least two mask patterns to the layer to be etched.
  • a second aspect of the present disclosure provides a semiconductor structure, characterized in that the semiconductor structure is formed according to the method for forming a semiconductor structure according to the first aspect of the present disclosure.
  • FIG. 1 is a flow chart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a flow chart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a flow chart showing a method for forming a semiconductor structure according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram showing a process of forming a first mask material layer above a layer to be etched according to an exemplary embodiment.
  • Fig. 5 is a schematic diagram showing splitting a design pattern into two sub-layouts according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram showing the formation of a first sub-mask layer according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram showing a process of forming a first mask pattern according to an exemplary embodiment.
  • FIG. 8 is a schematic diagram showing the formation of a second sub-mask layer according to an exemplary embodiment.
  • FIG. 9 is a schematic diagram showing a process of forming a second mask pattern according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram showing etching a layer to be etched using a first mask layer according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram showing a layer to be etched according to an exemplary embodiment.
  • FIG. 12 is a schematic diagram showing a process of forming a first mask material layer above a layer to be etched according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram showing a process of forming a first sub-mask pattern according to an exemplary embodiment.
  • FIG. 14 is a schematic diagram showing a process of forming a first mask pattern according to an exemplary embodiment.
  • FIG. 15 is a schematic diagram showing the formation of a second sub-mask layer according to an exemplary embodiment.
  • FIG. 16 is a schematic diagram showing a process of forming a second sub-mask pattern according to an exemplary embodiment.
  • FIG. 17 is a schematic diagram showing a process of forming a second mask pattern according to an exemplary embodiment.
  • FIG. 18 is a schematic diagram showing etching a layer to be etched using a first mask layer according to an exemplary embodiment.
  • FIG. 19 is a schematic diagram showing a semiconductor structure according to an exemplary embodiment.
  • the design pattern is transferred by the process of exposure-etching-exposure-etching, which is to decompose the high-density pattern into multiple sets of independent low-density patterns, expose and etch the layer to be etched multiple times, and transfer the multiple sets of independent low-density patterns to the layer to be etched one by one.
  • the process steps of multiple exposures and multiple etchings are many, expensive and time-consuming. Errors may occur in each process step, resulting in a relatively high scrap rate of the semiconductor structure; and, the layer to be etched is etched multiple times, and each etching consumes part of the layer to be etched.
  • the thickness of the layer to be etched decreases with the number of etchings.
  • the thickness of the layer to be etched each time is different, resulting in the size of the etching pattern first formed in the layer to be etched according to the etching sequence being larger than the size of the etching pattern formed later according to the etching sequence.
  • the etching pattern finally formed in the layer to be etched deviates from expectations, affecting the quality of the semiconductor structure.
  • the embodiments of the present disclosure provide a method for forming a semiconductor structure and a semiconductor structure, wherein a first mask material layer is patterned at least twice according to a design pattern to be transferred to a layer to be etched, so as to form a first mask layer including at least two mask patterns, and then an etching process is performed on the layer to be etched using the first mask layer as a mask, so that the design pattern can be transferred to the layer to be etched, thereby reducing the number of times the design pattern is transferred to the layer to be etched and the etching process is performed on the layer to be etched, shortening the time required for transferring the design pattern to the layer to be etched, and improving the efficiency of transferring the design pattern to the layer to be etched.
  • FIG. 1 shows a flow chart of the method for forming a semiconductor structure provided according to an exemplary embodiment of the present disclosure
  • Figures 4 to 19 are schematic diagrams of various stages of the method for forming a semiconductor structure. The method for forming a semiconductor structure is introduced below in conjunction with Figures 4 to 19.
  • This embodiment does not limit the semiconductor structure.
  • the semiconductor structure will be introduced as a dynamic random access memory (DRAM) as an example below, but this embodiment is not limited to this.
  • DRAM dynamic random access memory
  • the semiconductor structure in this embodiment can also be other structures.
  • a method for forming a semiconductor structure includes the following steps:
  • Step S110 providing a layer to be etched.
  • the layer to be etched 1 refers to a material layer that needs to be patterned.
  • the layer to be etched 1 can be a semiconductor wafer, or a semiconductor material layer used to form a semiconductor element, such as a dielectric layer or a metal layer.
  • the material of the semiconductor wafer can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); it can also be silicon on insulator (SOI), germanium on insulator (GOI); or it can also be other materials, such as III-V compounds such as gallium arsenide.
  • Certain impurity ions can be doped into the semiconductor wafer as needed, and the impurity ions can be N-type impurity ions or P-type impurity ions.
  • the layer 1 to be etched may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.
  • Step S120 forming a first mask material layer above the layer to be etched.
  • the first mask material layer 2 can be formed by a process such as deposition or coating.
  • the first mask material layer 2 can be formed on the top surface of the layer to be etched 1, or the first mask material layer 2 can be formed above the layer to be etched 1, and the first mask material layer 2 and the top surface of the layer to be etched 1 are separated by other film layers.
  • Step S130 performing patterning processing on the first mask material layer at least twice, forming at least two mask patterns in the first mask material layer, the at least two mask patterns are independently arranged, and the first mask material layer is formed into a first mask layer.
  • the first mask material layer 2 can be patterned at least twice according to at least two design patterns 3, and the at least two design patterns 3 can be transferred to the first mask material layer 2 in sequence.
  • at least two mask patterns 4 a are formed in the first mask material layer 2 to form a first mask layer 4.
  • a design pattern 3 can also be split into at least two sub-layouts 30, and the first mask material layer 2 is patterned at least twice according to the at least two sub-layouts 30, and the at least two sub-layouts 30 are respectively transferred to the first mask material layer 2, and with reference to FIG. 9 or 17 , at least two mask patterns 4a are formed in the first mask material layer 2 to form a first mask layer 4.
  • At least two mask patterns 4a are independently arranged. Each mask pattern 4a may include one or more graphics.
  • the at least two mask patterns 4a are independently arranged, which means that the projections formed by any graphics in the at least two mask patterns 4a on the layer to be etched 1 are independently arranged, and the projections formed by any two graphics in the two mask patterns 4a on the layer to be etched 1 do not overlap.
  • Step S140 etching the layer to be etched according to the first mask layer, and transferring at least two mask patterns to the layer to be etched.
  • the layer to be etched 1 is etched using the first mask layer 4 as a mask, a portion of the layer to be etched 1 is removed, at least two mask patterns 4a are transferred to the layer to be etched 1, and an etching pattern 1a is formed in the layer to be etched 1.
  • the first mask layer is used as an intermediate layer for transferring the design pattern
  • the design pattern is first transferred to the first mask layer
  • the layer to be etched is patterned according to the first mask layer, so that the design pattern can be transferred to the layer to be etched. Only one patterning process is required for the layer to be etched, so as to reduce the time for patterning the layer to be etched and improve the processing efficiency.
  • the first mask layer can be removed, and the first mask layer can be re-formed on the layer to be etched, and the step of transferring the design pattern to the first mask layer is repeated, so as to improve the fault tolerance of transferring the design pattern to the layer to be etched, avoid the semiconductor structure from becoming scrap, and have a higher qualified rate of the formed semiconductor structure.
  • FIG2 shows a flow chart of a method for forming a semiconductor structure provided in accordance with an exemplary embodiment of the present disclosure
  • FIGS. 4 to 10 are schematic diagrams of various stages of the method for forming a semiconductor structure. The method for forming a semiconductor structure is described below in conjunction with FIGS. 4 to 10.
  • a method for forming a semiconductor structure provided in an exemplary embodiment of the present disclosure comprises the following steps:
  • Step S210 providing a layer to be etched.
  • the layer 1 to be etched provided in this embodiment is the same as the layer 1 to be etched provided in the above embodiment.
  • Step S220 forming a first mask material layer above the layer to be etched.
  • the first mask material layer 2 formed in this embodiment is the same as the first mask material layer 2 formed in the above embodiment.
  • Step S230 providing a design pattern, and splitting the design pattern into at least two sub-layouts.
  • the design pattern 3 is used to pattern the layer to be etched 1 to form an etching pattern 1a in the layer to be etched 1, and the design pattern 3 is split into at least two sub-layouts 30 according to the number of patterns, pattern layout and pattern density of the design pattern 3, the number of patterns in each sub-layout 30 is less than the number of patterns in the design pattern 3, and/or the pattern density of each sub-layout 30 is lower than the pattern density of the design pattern 30.
  • the high-density and complex design pattern 3 is decomposed into at least two low-density and simple sub-layouts 30, and the difficulty of transferring the sub-layouts 30 to the first mask material layer 2 (the subsequent steps will be described in detail) is less difficult than the difficulty of directly transferring the design pattern 3 to the first mask material layer 2.
  • Step S240 performing patterning processing on the first mask material layer at least twice, forming at least two mask patterns in the first mask material layer, the at least two mask patterns are independently arranged, and the first mask material layer is formed into a first mask layer.
  • the first mask material layer 2 is patterned at least twice in sequence according to at least two sub-layouts 30, each sub-layout 30 is transferred to the first mask material layer 2, and a corresponding mask pattern 4a is formed in the first mask material layer 2, and at least two mask patterns 4a are formed in the first mask material layer 2, and the first mask material layer 2 is formed into a first mask layer 4.
  • the first mask material layer 2 is patterned at least twice, using the following implementation methods:
  • a sub-mask layer 5 is formed on the first mask material layer 2, and the sub-mask layer 5 includes a sub-mask pattern 5a, and the sub-mask pattern 5a exposes a portion of the top surface of the first mask material layer 2.
  • the first mask material layer 2 is then etched according to the sub-mask layer 5, and the sub-mask pattern 5a is transferred to the first mask material layer 2, so that a mask pattern 4a is formed in the first mask material layer 2.
  • the sub-mask layer 5 is patterned according to one of the at least two sub-layouts 30 , and the sub-layout 30 is transferred to the sub-mask layer 5 to form a sub-mask pattern 5a. Then, the sub-layout 30 is transferred to the first mask material layer 2 through the sub-mask layer 5 .
  • the sub-mask layer 5 formed on the first mask material layer 2 also fills the mask pattern 4 a in the first mask material layer 2 .
  • the projections of the sub-mask patterns 5a in the sub-mask layer 5 formed at least twice on the layer to be etched 1 have no overlapping parts, and the mask pattern 4a formed on the first mask material layer 2 according to the at least two sub-mask patterns 5a is independently arranged.
  • Step S250 etching the layer to be etched according to the first mask layer, and transferring at least two mask patterns to the layer to be etched.
  • the layer to be etched 1 is etched using the first mask layer 4 as a mask, and a portion of the layer to be etched 1 is removed by etching to transfer at least two mask patterns 4a to the layer to be etched 1, and an etching pattern 1a is formed in the layer to be etched 1, thereby completing the transfer of the design pattern 3 to the layer to be etched 1.
  • the method for forming a semiconductor structure of the present embodiment divides a high-density and complex design pattern into at least two low-density and simple sub-layouts, transfers the at least two sub-layouts to the first mask layer one by one, changes the etching step that should be performed on the layer to be etched to be performed on the first mask layer, and then etches the layer to be etched once using the first mask layer as a mask, thereby completing the transfer of the design pattern to the layer to be etched, reducing the number of etching times of the layer to be etched, improving the efficiency of transferring the design pattern to the layer to be etched, and at the same time reducing the process cost and shortening the process time.
  • the present embodiment only performs one etching on the layer to be etched, thereby avoiding the problem of different sizes of etching patterns formed in the layer to be etched due to different thicknesses of the layer to be etched each time, and optimizing the effect of the etching pattern formed in the layer to be etched, so that the etching pattern formed in the layer to be etched is closer to the expected design pattern. Therefore, the method for forming the semiconductor structure of the present embodiment can be applied to the etching process of design patterns with smaller feature sizes and complex and dense patterns, which is beneficial to the improvement of the integration and miniaturization development of semiconductor structures.
  • this embodiment is an explanation of the above embodiment.
  • the thickness of the sub-mask layer formed each time is the same.
  • the thickness of the sub-mask layer 5 formed each time is the same, so that the process thickness of the sub-mask pattern 5a formed in the sub-mask layer 5 is the same each time, ensuring that the sub-mask pattern 5a formed in each sub-mask layer 5 has the same size, so that at least two mask patterns 4a formed in the first mask layer 4 according to at least two sub-mask patterns 5a have the same size, so that the etching pattern 1a formed in the layer to be etched 1 is closer to the design pattern 3.
  • the design pattern 3 is decomposed into a first sub-layout 31 and a second sub-layout 32 , and the first mask material layer 2 is patterned twice according to the first sub-layout 31 and the second sub-layout 32 , to illustrate this embodiment.
  • a first sub-mask layer 51 is formed.
  • the first sub-mask layer 51 covers a portion of the top surface of the first mask material layer 2 .
  • the first sub-mask layer 51 includes a first sub-mask pattern 51 a .
  • the first sub-mask pattern 51 a exposes another portion of the top surface of the first mask material layer 2 .
  • the first mask material layer 2 is etched according to the first sub-mask layer 51, the second sub-mask layer 52 and the first sub-mask layer 51 have the same thickness, the first mask material layer 2 exposed by the first sub-mask pattern 51a is removed, and the first sub-mask pattern 51a is extended into the first mask material layer 2 to form a first mask pattern 41a.
  • a second sub-mask layer 52 is formed on the first mask material layer 2, the second sub-mask layer 52 fills the first mask pattern 41a and covers a portion of the top surface of the first mask material layer 2, the second sub-mask layer 52 includes a second sub-mask pattern 52a, and the second sub-mask pattern 52a exposes another portion of the top surface of the first mask material layer 2.
  • the first mask material layer 2 is etched according to the second sub-mask layer 52 to remove the first mask material layer 2 exposed by the second sub-mask pattern 52a, and the second sub-mask pattern 52a is extended into the first mask material layer 2 to form a second mask pattern 42a.
  • the first sub-mask layer 51 and the second sub-mask layer 52 have the same thickness, and the thickness of the first sub-mask pattern 51a formed by etching the first sub-mask layer 51 according to the first sub-layout 31 and the thickness of the second sub-mask pattern 52a formed by etching the second sub-mask layer 52 according to the second sub-layout 32 are the same, ensuring that the first sub-mask pattern 51a formed in the first sub-mask layer 51 and the second sub-mask pattern 52a formed in the second sub-mask layer 52 have the same size, thereby ensuring that the first mask pattern 41a and the second mask pattern 42a formed in the first mask material layer 2 according to the first sub-mask pattern 51a and the second sub-mask pattern 52a respectively have the same size.
  • FIG3 shows a flow chart of a method for forming a semiconductor structure provided in accordance with an exemplary embodiment of the present disclosure
  • FIGS. 11 to 19 are schematic diagrams of various stages of the method for forming a semiconductor structure. The method for forming a semiconductor structure is described below in conjunction with FIGS. 11 to 19.
  • a method for forming a semiconductor structure provided in an exemplary embodiment of the present disclosure includes the following steps:
  • Step S310 providing a layer to be etched.
  • the layer to be etched 1 is disposed on a substrate 6, and the substrate 6 includes a source region 61 and a drain region 62.
  • the material of the layer to be etched 1 includes an insulating material, for example, the material of the layer to be etched 1 may include at least one of silicon oxide or silicon nitride.
  • the substrate 6 includes an active region 63 and an isolation structure 64 .
  • the active region 63 includes a source region 61 and a drain region 62 . As shown in FIG. 7 , the source region 61 and the drain region 62 are respectively disposed at two ends of the active region 63 .
  • a gate 65 is also disposed on the substrate 6.
  • the gate 65 is located between the source region 61 and the drain region 62.
  • the gate 65 is in contact with the active region 63.
  • the layer 1 to be etched covers the gate 65, and the top surface of the layer 1 to be etched is higher than the top surface of the gate 65.
  • the etched layer 1 covers the top surface of the substrate 6 and may include a single layer or a multilayer structure. Referring to FIG7 , in this embodiment, the etched layer 1 includes a first dielectric layer 11 , a second dielectric layer 12 and a third dielectric layer 13 sequentially stacked on the substrate 6 .
  • Step S320 forming a hard mask layer and a first buffer layer in sequence on the layer to be etched.
  • a hard mask layer 7 can be formed on the layer to be etched 1 by spin coating a hard mask material (Spin-On Hard-mask material), and the material of the hard mask layer 7 can include spin-on carbon (Spin On Carbon, SOC).
  • any deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering may be selected to deposit and form the first buffer layer 81.
  • the material of the first buffer layer 81 may include silicon nitride.
  • Step S330 forming a first mask material layer above the layer to be etched.
  • any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering can be used to deposit and form the first mask material layer 2.
  • the first mask material layer 2 is disposed on the first buffer layer 81, and the hard mask layer 7 is separated from the first mask material layer 2 by the first buffer layer 81.
  • the material of the first mask material layer 2 is different from that of the first buffer layer 81 , and the first mask material layer 2 has a high etching selectivity relative to the first buffer layer 81 .
  • the material of the first mask material layer 2 may include silicon oxide.
  • Step S340 performing a first patterning process on the first mask material layer to form a first mask pattern in the first mask material layer.
  • the first mask material layer 2 is subjected to a first patterning process, including the following steps:
  • Step S341 forming a first sub-mask layer, the first sub-mask layer covers a portion of the top surface of the first mask material layer, the first sub-mask layer includes a first sub-mask pattern, and the first sub-mask pattern exposes another portion of the top surface of the first mask material layer.
  • the first sub-mask layer 51 is formed by spin-coating a hard mask material to form the first sub-mask layer 51 on the first mask material layer 2 .
  • the first sub-mask layer 51 has a high etching selectivity relative to the first mask material layer 2 .
  • the material of the first sub-mask layer 51 may include spin-coated carbon.
  • a second buffer layer 82 may be formed on the top surface of the first sub-mask layer 51 by any of the above-mentioned deposition processes, and the material of the second buffer layer 82 may include silicon nitride.
  • the thickness of the hard mask layer 7 is greater than the thickness of the first sub-mask layer 51, and the thickness of the first buffer layer 81 is greater than the thickness of the second buffer layer 82.
  • the thickness of the hard mask layer 7 may be 3 to 5 times the thickness of the first sub-mask layer 51.
  • the thickness of the hard mask layer 7 is 240 nm; the thickness of the first sub-mask layer 51 is 80 nm; the thickness of the first buffer layer 81 is 40 nm; and the thickness of the second buffer layer 82 is 30 nm.
  • a first photoresist mask 91 is then formed on the second buffer layer 82 .
  • the first photoresist mask 91 includes a first photoresist pattern 91 a .
  • the first photoresist pattern 91 a exposes a portion of the top surface of the second buffer layer 82 .
  • the second buffer layer 82 exposed by the first photoresist pattern 91a is then etched away, and the first photoresist pattern 91a is extended into the second buffer layer 82.
  • the first sub-mask layer 51 exposed by the first photoresist pattern 91a is etched further, a portion of the first sub-mask layer 51 is removed, a portion of the top surface of the first mask material layer 51 is exposed, and a first sub-mask pattern 51a is formed in the first sub-mask layer 51.
  • the second buffer layer 82 and the first sub-mask layer 51 may be dry-etched by plasma, or may be wet-etched by an etching solution.
  • part of the second buffer layer 82 may be consumed, the thickness of the second buffer layer 82 may be reduced, or the second buffer layer 82 may be completely removed.
  • the second buffer layer 82 buffers the consumption of the first sub-mask layer 51 by the etching process, thereby preventing the first sub-mask layer 51 from being consumed by the etching process, and ensuring that the thickness of the first sub-mask layer 51 remains unchanged after the first sub-mask pattern 51a is formed.
  • Step S342 etching the first mask material layer according to the first sub-mask layer to remove the first mask material layer exposed by the first sub-mask pattern, and extending the first sub-mask pattern into the first mask material layer to form a first mask pattern.
  • the first mask material layer 2 is etched according to the first sub-mask pattern 51 a , and the first sub-mask pattern 51 a is extended into the first mask material layer 2 to form a first mask pattern 41 a .
  • the first sub-mask layer 51 is etched away.
  • the etching process has a high etching selectivity ratio for etching the first sub-mask layer 51 relative to the first mask material layer 2, which can avoid damaging the first mask material layer 2 in the process of etching away the first sub-mask layer 51, ensuring that the thickness of the first mask material layer 2 remains unchanged, and at the same time ensuring that the morphology of the first mask pattern 41a remains unchanged, ensuring that the morphology of the first mask pattern 41a has high precision.
  • Step S350 performing a second patterning process on the first mask material layer to form a second mask pattern in the first mask material layer, wherein the first mask pattern and the second mask pattern are independently provided.
  • the second patterning process is performed on the first mask material layer 2, including the following steps:
  • Step S351 forming a second sub-mask layer on the first mask material layer, the second sub-mask layer filling the first mask pattern and covering a portion of the top surface of the first mask material layer, the second sub-mask layer including a second sub-mask pattern, and the second sub-mask pattern exposing another portion of the top surface of the first mask material layer.
  • the hard mask material fills the first mask pattern 41a in the first mask material layer 2 and covers the top surface of the first mask material layer 2, and a second sub-mask layer 52 is formed on the first mask material layer 2.
  • the second sub-mask layer 52 has a high etching selectivity relative to the first mask material layer 2, and the material of the second sub-mask layer 52 may include spin-coated carbon.
  • a third buffer layer 83 may be formed by deposition through any deposition process including chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering, and the third buffer layer 83 covers the top surface of the second sub-mask layer 52.
  • the material of the third buffer layer 83 may include silicon nitride.
  • the thickness of the second sub-mask layer 52 is the same as the thickness of the first sub-mask layer 51
  • the thickness of the third buffer layer 83 is the same as the thickness of the second buffer layer 82, so that the process thickness of forming the first mask pattern 41a in the first mask material layer 2 and the process thickness of forming the second mask pattern 42a (which will be described in detail in subsequent steps) in the first mask material layer 2 are the same, ensuring that the formed first mask pattern 41a and the second mask pattern 42 have the same size and morphology.
  • a second photoresist mask 92 is then formed on the third buffer layer 83 .
  • the second photoresist mask 92 includes a second photoresist pattern 92 a .
  • the second photoresist pattern 92 a exposes a portion of the top surface of the third buffer layer 83 .
  • the third buffer layer 83 exposed by the second photoresist pattern 92a is removed by etching, and the second photoresist pattern 92a is extended into the third buffer layer 83.
  • the second sub-mask layer 52 exposed by the second photoresist pattern 92a is further etched, a portion of the second sub-mask layer 52 is removed, and the second photoresist pattern 92a is extended into the second sub-mask layer 52 to form a second sub-mask pattern 52a.
  • the third buffer layer 83 and the second sub-mask layer 52 may be dry-etched by plasma, or the third buffer layer 83 and the second sub-mask layer 52 may be wet-etched by an etching solution.
  • the projection of the first sub-mask pattern 51a formed on the to-be-etched layer 1 and the projection of the second sub-mask pattern 52a formed on the to-be-etched layer 1 have no overlapping parts.
  • the projection formed by the first sub-mask pattern 51a on the substrate 6 falls on the source region 61 or the drain region 62
  • the projection formed by the first sub-mask pattern 52a on the substrate 6 falls on the drain region 62 or the source region 61.
  • the etching process consumes part of the third buffer layer 83, thereby avoiding consumption of the second sub-mask layer 52, ensuring that the thickness of the second sub-mask layer 52 remains unchanged after the second sub-mask pattern 52a is formed.
  • Step S352 etching the first mask material layer according to the second sub-mask layer to remove the first mask material layer exposed by the second sub-mask pattern, and extending the second sub-mask pattern into the first mask material layer to form a second mask pattern.
  • the second sub-mask layer 52 is used as a mask to etch the first mask material layer 2 , extending the second sub-mask pattern 52 a into the first mask material layer 2 , and forming a second mask pattern 42 a in the first mask material layer 2 .
  • the projection of the first mask pattern 41 a on the substrate 6 falls on the source region 61 or the drain region 62
  • the projection of the second mask pattern 42 a on the substrate 6 falls on the drain region 62 or the source region 61 .
  • the second sub-mask layer 52 is etched and removed.
  • the etching process etches the second sub-mask layer 52 with a high etching selectivity relative to the first mask material layer 2, and the process of removing the second sub-mask layer 52 will not damage the first mask material layer 2, thereby avoiding changes in the morphology of the first mask pattern 41a and the second mask pattern 42a, ensuring that the first mask pattern 41a and the second mask pattern 42a have high precision, and can improve the yield of the formed semiconductor structure.
  • Step S360 etching the layer to be etched according to the first mask layer, and transferring at least two mask patterns to the layer to be etched.
  • the first buffer layer 81, the hard mask layer 7 and the layer 1 to be etched exposed by the first mask pattern 41a and the second mask pattern 42a are etched in sequence according to the first mask layer 4 to expose portions of the top surfaces of the source region 61 and the drain region 62, and the first mask pattern 41a and the second mask pattern 42a are extended into the layer 1 to be etched, and a source contact hole 14 is formed above the source region 61, and the source contact hole 14 exposes portions of the top surface of the source region 61, and a drain contact hole 15 is formed above the drain region 62, and the drain contact hole 15 exposes portions of the top surface of the drain region 62.
  • the to-be-etched layer 1 is etched according to the first mask layer 4, and the following implementation methods may be adopted:
  • the first buffer layer 81 is etched using the first mask layer 4 as a mask, and the first mask pattern 41 a and the second mask pattern 42 a are transferred into the first buffer layer 81 .
  • etching the first buffer layer 81 may be performed in the following manner: placing the semiconductor structure in a reaction chamber, introducing a first etching gas into the reaction chamber, etching the first buffer layer 81 by the first etching gas, removing the first buffer layer 81 exposed by the first mask pattern 41a and the second mask pattern 42a, and extending the first mask pattern 41a and the second mask pattern 42a into the first buffer layer 81.
  • the first etching gas includes an oxygen-containing gas, for example, the first etching gas may include oxygen.
  • the first etching gas includes oxygen (O 2 ), and the first etching gas also includes a small amount of carbonyl sulfide (COS).
  • the hard mask layer 7 is then continuously etched to transfer the first mask pattern 41 a and the second mask pattern 42 a into the hard mask layer 7 .
  • etching the hard mask layer 7 may be performed in the following manner: a second etching gas is introduced into the reaction chamber, and the hard mask layer 7 is etched by the second etching gas to remove the hard mask layer 7 exposed by the first buffer layer 81.
  • the second etching gas includes a first gas and a second gas
  • the first gas includes a fluorine-containing compound gas
  • the first gas may include at least one of trifluoromethane (CHF 3 ), hexafluoroethane (C 2 F 6 ), octafluoropropane (C 3 F 8 ), and octafluorocyclobutane (C 4 F 8 )
  • the second gas includes at least one of oxygen or bromine (Br 2 ).
  • the second etching gas includes a mixture of trifluoromethane and oxygen; or, the second etching gas includes a mixture of octafluoropropane and bromine; or, the second etching gas includes a mixture of hexafluoroethane, oxygen and bromine.
  • the layer to be etched 1 is etched using the hard mask layer 7 as a mask, and the third dielectric layer 13, the second dielectric layer 12 and the first dielectric layer 11 exposed by the hard mask layer 7 are removed in sequence, and the etching is stopped after the top surface of the substrate 6 is exposed.
  • the first mask pattern 41a and the second mask pattern 42a are transferred to the layer to be etched 1, and a source contact hole 14 and a drain contact hole 15 are respectively formed in the layer to be etched 1.
  • the method for forming a semiconductor structure of the present embodiment before etching the layer to be etched, splits the design pattern to be formed into a first photoresist pattern and a second photoresist pattern, and performs two patterning processes on the first mask material layer according to the first photoresist pattern and the second photoresist pattern, respectively, to form a first mask layer, the first mask layer includes the first mask pattern and the second mask pattern, and the process thickness of the two patterning processes on the first mask material layer is the same, the sizes of the first mask pattern and the second mask pattern are uniform and highly accurate, ensuring that the source contact hole and the drain contact hole formed in the layer to be etched according to the first mask layer have the same size, avoiding the adverse effects of the inconsistent sizes of the source contact hole and the drain contact hole on the semiconductor structure, improving the overall uniformity of the semiconductor structure, and improving the yield and productivity of the semiconductor structure.
  • the method for forming the semiconductor structure of the present embodiment is suitable for forming source contact holes and drain contact holes with smaller feature sizes and smaller pitches, while ensuring that the sizes of the formed source contact holes and drain contact holes are the same; it is beneficial to the uniformity of the contact resistance of the source contact plug formed in the source contact hole and the drain contact plug formed in the drain contact hole in the subsequent process, and the current conduction of the transistor of the semiconductor structure is more stable.
  • Exemplary embodiments of the present disclosure provide a semiconductor structure.
  • the semiconductor structure is formed according to the method for forming the semiconductor structure in the above-mentioned embodiment.
  • the semiconductor structure of this embodiment can be a memory chip, which can be used in a dynamic random access memory (DRAM). However, it can also be applied to a static random access memory (SRAM), a flash EPROM, a ferroelectric random access memory (FRAM), a magnetic random access memory (MRAM), a phase change random access memory (PRAM), etc.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • PRAM phase change random access memory
  • first, second, etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.
  • At least two mask patterns are formed in a first mask layer through at least two patterning processes, and at least two mask patterns can be transferred to the layer to be etched by performing only one etching process on the layer to be etched according to the first mask layer, thereby reducing the number of etching processes performed on the layer to be etched, shortening the time required to transfer the design pattern to the layer to be etched, and improving the efficiency of transferring the design pattern to the layer to be etched.

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Abstract

本公开提供了一种半导体结构的形成方法及半导体结构，涉及半导体技术领域，半导体结构的形成方法包括：提供待刻蚀层；在待刻蚀层的上方形成第一掩膜材料层；对第一掩膜材料层进行至少两次图案化处理，在第一掩膜材料层中形成至少两个掩膜图案，至少两个掩膜图案独立设置，第一掩膜材料层形成为第一掩膜层；根据第一掩膜层刻蚀待刻蚀层，将至少两个掩膜图案转移到待刻蚀层中。

Description

半导体结构的形成方法及半导体结构
本公开基于申请号为202211328743.2、申请日为2022年10月27日、申请名称为“半导体结构的形成方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的形成方法及半导体结构。
背景技术
随着集成电路向着微型化方向发展，要求相应的集成电路具有更高的集成密度和更小的特征尺寸，芯片制造对光刻分辨率要求越来越高。
在第四代及以后的芯片，特征尺寸小、布局密度高，单次曝光技术已经无法满足其光刻要求，只能使用双重甚至多重图案化技术来完成设计图案的转移，通常采用曝光-刻蚀-曝光-刻蚀(Litho-Etch-Litho-Etch，LELE)，即将设计图案分解成多套独立的低密度图形，通过多次曝光多次刻蚀，将设计图案转移到芯片上。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的形成方法及半导体结构。
本公开的第一方面提供了一种半导体结构的形成方法，所述半导体结构的形成方法包括：
提供待刻蚀层；
在所述待刻蚀层的上方形成第一掩膜材料层；
对所述第一掩膜材料层进行至少两次图案化处理，在所述第一掩膜材料层中形成至少两个掩膜图案，所述至少两个掩膜图案独立设置，所述第一掩膜材料层形成为第一掩膜层；
根据所述第一掩膜层刻蚀所述待刻蚀层，将所述至少两个掩膜图案转移到所述待刻蚀层中。
本公开的第二方面提供了一种半导体结构半导体结构，其特征在于，所述半导体结构根据本公开的第一方面所述的半导体结构的形成方法形成。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的形成方法的流程图。
图2是根据一示例性实施例示出的半导体结构的形成方法的流程图。
图3是根据一示例性实施例示出的半导体结构的形成方法的流程图。
图4是根据一示例性实施例示出的在待刻蚀层的上方形成第一掩膜材料层的示意图。
图5是根据一示例性实施例示出的将设计图案拆分成两个子布局的示意图。
图6是根据一示例性实施例示出的形成第一子掩膜层的示意图。
图7是根据一示例性实施例示出的形成第一掩膜图案的示意图。
图8是根据一示例性实施例示出的形成第二子掩膜层的示意图。
图9是根据一示例性实施例示出的形成第二掩膜图案的示意图。
图10是根据一示例性实施例示出的根据第一掩膜层刻蚀待刻蚀层的示意图。
图11是根据一示例性实施例示出的待刻蚀层的示意图。
图12是根据一示例性实施例示出的在待刻蚀层的上方形成第一掩膜材料层的示意图。
图13是根据一示例性实施例示出的形成第一子掩膜图案的示意图。
图14是根据一示例性实施例示出的形成第一掩膜图案的示意图。
图15是根据一示例性实施例示出的形成第二子掩膜层的示意图。
图16是根据一示例性实施例示出的形成第二子掩膜图案的示意图。
图17是根据一示例性实施例示出的形成第二掩膜图案的示意图。
图18是根据一示例性实施例示出的根据第一掩膜层刻蚀待刻蚀层的示意图。
图19是根据一示例性实施例示出的半导体结构的示意图。
附图标记：
1、待刻蚀层；1a、刻蚀图案；11、第一介质层；12、第二介质层；13、第三介质层；14、源极接触孔；15、漏极接触孔；2、第一掩膜材料层；3、设计图案；30、子布局；31、第一子布局；32、第二子布局；4、第一掩膜层；4a、掩膜图案；41a、第一掩膜图案；42a、第二掩膜图案；5、子掩膜层；5a、子掩膜图案；51、第一子掩膜层；51a、第一子掩膜图案；52、第二子掩膜层；6、基底；61、源极区；62、漏极区；63、有源区；64、隔离结构；65、栅极；7、硬掩膜层；81、第一缓冲层；82、第二缓冲层；83、第三缓冲层；91、第一光刻胶掩膜；91a、第一光刻胶图案；92、第二光刻胶掩膜；92a、第二光刻胶图案。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
目前，采用曝光-刻蚀-曝光-刻蚀的工艺转移设计图案，是将高密度图案分解成多套独立的低密度图案，对待刻蚀层进行多次曝光、多次刻蚀，将多套独立的低密度图案逐次转移到待刻蚀层中。多次曝光、多次刻蚀的工艺步骤多、成本昂贵且耗时很长，每个工艺步骤中都可能出现误差，导致半导体结构的废品率比较高；并且，对待刻蚀层进行多次刻蚀，每次刻蚀会消耗部分待刻蚀层，待刻蚀层的厚度随着刻蚀次数逐次减薄，因此每次刻蚀处理的待刻蚀层的厚度不同，导致按刻蚀顺序在待刻蚀层中先形成的刻蚀图案的尺寸比按刻蚀顺序后形成的刻蚀图案的尺寸大，待刻蚀层中最终形成的刻蚀图案偏离预期，影响半导体结构的品质。
本公开实施例提供的一种半导体结构的形成方法及半导体结构，根据待转移到待刻蚀层中的设计图案对第一掩膜材料层进行至少两次图案化处理，形成包括至少两个掩膜图案的第一掩膜层，再以第一掩膜层作为掩膜对待刻蚀层执行一次刻蚀处理，即可将设计图案转移到待刻蚀层中，减少将设计图案转移到待刻蚀层中对待刻蚀层执行刻蚀处理的次数，缩短将设计图案转移到待刻蚀层中所需的时间，提高将设计图案向待刻蚀层转移的效率。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图，图4-图19为半导体结构的形成方法的各个阶段的示意图，下面结合图4-图19对半导体结构的形成方法进行介绍。
本实施例对半导体结构不作限制，下面将以半导体结构为动态随机存储器(Dynamic  Random Access Memory，DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的半导体结构还可以为其他的结构。
如图1所示，本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S110：提供待刻蚀层。
参照图4或图11所示，待刻蚀层1是指需要进行图案化处理的材料层，待刻蚀层1可以是半导体晶圆，也可以是用于形成半导体元件的半导体材料层，如介质层或金属层。半导体晶圆的材料可以为硅(Si)、锗(Ge)、或硅锗(GeSi)、碳化硅(SiC)；也可以是绝缘体上硅(SOI)，绝缘体上锗(GOI)；或者还可以为其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。半导体晶圆中根据需要可以掺杂一定的杂质离子，杂质离子可以为N型杂质离子或P型杂质离子。
待刻蚀层1可以为无定形碳层、氧化物层、氮化物层、铜层、钨层、铝层等，不限于此。
步骤S120：在待刻蚀层的上方形成第一掩膜材料层。
参照图4或图12所示，可以通过沉积或涂覆等工艺形成第一掩膜材料层2，第一掩膜材料层2可以形成在待刻蚀层1的顶面上，或者，第一掩膜材料层2可以形成在待刻蚀层1的上方，第一掩膜材料层2和待刻蚀层1的顶面通过其它的膜层隔开。
步骤S130：对第一掩膜材料层进行至少两次图案化处理，在第一掩膜材料层中形成至少两个掩膜图案，至少两个掩膜图案独立设置，第一掩膜材料层形成为第一掩膜层。
参照图4、图5所示，可以根据至少两个设计图案3对第一掩膜材料层2进行至少两次图案化处理，将至少两个设计图案3依次转移到第一掩膜材料层2中，参照图9或图17，在第一掩膜材料层2中形成至少两个掩膜图案4a，形成第一掩膜层4。
参照图4、图5所示，还可以将一个设计图案3拆分成至少两个子布局30，根据至少两个子布局30对第一掩膜材料层2进行至少两次图案化处理，将至少两个子布局30分别转移到第一掩膜材料层2中，参照图9或图17，在第一掩膜材料层2中形成至少两个掩膜图案4a，形成第一掩膜层4。
参照图9或图17，至少两个掩膜图案4a独立设置。每个掩膜图案4a可以包括一个或多个图形。其中，至少两个掩膜图案4a独立设置是指，至少两个掩膜图案4a中的任意图形在待刻蚀层1上形成的投影独立设置，且两个掩膜图案4a中的任意两个图形在待刻蚀层1上形成的投影没有重合的部分。
步骤S140：根据第一掩膜层刻蚀待刻蚀层，将至少两个掩膜图案转移到待刻蚀层中。
如图10、图19所示，参照图9、图17，以第一掩膜层4为掩膜刻蚀待刻蚀层1，去除部分待刻蚀层1，将至少两个掩膜图案4a转移到待刻蚀层1中，在待刻蚀层1中形成刻蚀图案1a。
本实施例的半导体结构的形成方法，设计图案向待刻蚀层转移的过程中，以第一掩膜层作为设计图案转移的中间层，将设计图案先转移到第一掩膜层中，再根据第一掩膜层对待刻蚀层执行图案化处理，即可将设计图案转移到待刻蚀层中，只需对待刻蚀层进行一次图案化处理，以减小图案化处理待刻蚀层的时间，提高处理效率；并且，本实施例的半导体结构的形成方法，将设计图案转移到第一掩膜层的过程中，如果形成的掩膜图案出现偏移或其它问题，可以移除第一掩膜层，在待刻蚀层上重新形成第一掩膜层，重复将设计图案转移到第一掩膜层中的步骤，提高了设计图案向待刻蚀层中转移的容错率，避免半导体结构成为废品，形成的半导体结构的合格率更高。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图2所示，图2示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图，图4-图10为半导体结构的形成方法的各个阶段的示意图，下面结合图4-图10对半导体结构的形成方 法进行介绍。本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S210：提供待刻蚀层。
如图4所示，本实施例中提供的待刻蚀层1和上述实施例中提供的待刻蚀层1相同。
步骤S220：在待刻蚀层的上方形成第一掩膜材料层。
如图4所示，本实施例中形成的第一掩膜材料层2和上述实施例中形成的第一掩膜材料层2相同。
步骤S230：提供设计图案，将设计图案拆分成至少两个子布局。
如图4、图5所示，参照图10，设计图案3用于图案化处理待刻蚀层1在待刻蚀层1中形成刻蚀图案1a，根据设计图案3的图案数量、图案布局和图案密度，将设计图案3拆分成至少两个子布局30，每个子布局30的图案数量比设计图案3的图案数量少，和/或，每个子布局30的图案密度比设计图案30的图案密度低。
如图4、图5所示，本实施例中，将高密度复杂的设计图案3分解成至少两个低密度简单的子布局30，子布局30向第一掩膜材料层2转移(后续步骤会进行详细说明)的难度比设计图案3直接向第一掩膜材料层2转移的难度小。
步骤S240：对第一掩膜材料层进行至少两次图案化处理，在第一掩膜材料层中形成至少两个掩膜图案，至少两个掩膜图案独立设置，第一掩膜材料层形成为第一掩膜层。
如图9所示，参照图4、图5，根据至少两个子布局30依次对第一掩膜材料层2进行至少两次图案化处理，将每个子布局30转移到第一掩膜材料层2，在第一掩膜材料层2中对应形成一个掩膜图案4a，在第一掩膜材料层2中形成至少两个掩膜图案4a，第一掩膜材料层2形成为第一掩膜层4。
在本实施例中，对第一掩膜材料层2进行至少两次图案化处理，采用以下实施方式：
如图6所示，在第一掩膜材料层2上形成子掩膜层5，子掩膜层5包括子掩膜图案5a，子掩膜图案5a暴露出第一掩膜材料层2的部分顶面。如图7所示，参照图9，然后，根据子掩膜层5刻蚀第一掩膜材料层2，将子掩膜图案5a转移到第一掩膜材料层2中，在第一掩膜材料层2中形成掩膜图案4a。
如图6所示，形成子掩膜层5后，根据至少两个子布局30中的一个子布局30对子掩膜层5进行图案化处理，将子布局30转移到子掩膜层5中形成子掩膜图案5a。然后，通过子掩膜层5将子布局30转移到第一掩膜材料层2。
如图8所示，参照图7，接着，重复在第一掩膜材料层2上形成子掩膜层5，根据子掩膜层5刻蚀第一掩膜材料层2的步骤，重复至少一次，参照图9，直至将至少两个子布局30的每个子布局30转移到第一掩膜材料层2中形成至少两个掩膜图案4a，以使形成的第一掩膜层4包括设计图案3的全部图案。
可以理解的是，重复在第一掩膜材料层2上形成子掩膜层5的过程中，第一掩膜材料层2中已形成有掩膜图案4a时，在第一掩膜材料层2上形成的子掩膜层5还填充第一掩膜材料层2中的掩膜图案4a。
本实施例中，至少两次形成的子掩膜层5中的子掩膜图案5a在待刻蚀层1上形成的投影无重合部分，根据至少两个子掩膜图案5a在第一掩膜材料层2上形成的掩膜图案4a独立设置。
步骤S250：根据第一掩膜层刻蚀待刻蚀层，将至少两个掩膜图案转移到待刻蚀层中。
如图10所示，参照图5、图9，以第一掩膜层4为掩膜刻蚀待刻蚀层1，刻蚀去除部分待刻蚀层1，以将至少两个掩膜图案4a转移到待刻蚀层1中，在待刻蚀层1中形成刻蚀图案1a，完成设计图案3向待刻蚀层1的转移。
本实施例的半导体结构的形成方法，将高密度复杂的设计图案拆分成至少两个低密度简单的子布局，将至少两个子布局逐次转移到第一掩膜层中，将本应对待刻蚀层执行 的刻蚀步骤改为对第一掩膜层执行，再以第一掩膜层为掩膜对待刻蚀层执行一次刻蚀，即完成设计图案向待刻蚀层的转移，减少了对待刻蚀层的刻蚀次数，提高设计图案向待刻蚀层的转移的效率，同时降低制程成本，缩短制程时间。
同时，本实施例只对待刻蚀层执行一次刻蚀，避免因每次刻蚀的待刻蚀层的厚度不同，导致在待刻蚀层中形成的刻蚀图案的尺寸不同的问题，优化在在待刻蚀层中形成的刻蚀图案的效果，以使在待刻蚀层中形成的刻蚀图案更接近预期的设计图案，因此，本实施例的半导体结构的形成方法可应用于特征尺寸更小、图案复杂密集的设计图案的刻蚀制程，有利于半导体结构的集成度提高和微缩化发展。
根据一个示例性实施例，本实施例是对上述实施例的说明，在本实施例中，对第一掩膜材料层进行至少两次图案化处理的过程中，每次形成的子掩膜层的厚度相同。
如图5所示，设计图案3向第一掩膜材料层2转移的过程中，每次形成的子掩膜层5的厚度相同，以使每次在子掩膜层5中形成子掩膜图案5a的制程厚度相同，确保在每个子掩膜层5中形成的子掩膜图案5a具有相同的尺寸，从而根据至少两个子掩膜图案5a在第一掩膜层4中形成的至少两个掩膜图案4a具有相同的尺寸，以使在待刻蚀层1中形成的刻蚀图案1a更接近设计图案3。
下面，将设计图案3分解成第一子布局31和第二子布局32，根据第一子布局31和第二子布局32对第一掩膜材料层2进行两次图案化处理，对本实施例进行说明。
如图6所示，首先，形成第一子掩膜层51，第一子掩膜层51覆盖第一掩膜材料层2的部分顶面，第一子掩膜层51包括第一子掩膜图案51a，第一子掩膜图案51a暴露出第一掩膜材料层2的另一部分顶面。
如图7所示，参照图6，然后，根据第一子掩膜层51刻蚀第一掩膜材料层2，第二子掩膜层52和第一子掩膜层51具有相同的厚度，去除被第一子掩膜图案51a暴露出的第一掩膜材料层2，将第一子掩膜图案51a延伸到第一掩膜材料层2中，形成第一掩膜图案41a。
如图8所示，参照图7，接着，在第一掩膜材料层2上形成第二子掩膜层52，第二子掩膜层52填充第一掩膜图案41a并覆盖第一掩膜材料层2的部分顶面，第二子掩膜层52包括第二子掩膜图案52a，第二子掩膜图案52a暴露出第一掩膜材料层2的另一部分顶面。
如图9所示，参照图8，接着，根据第二子掩膜层52刻蚀第一掩膜材料层2，去除被第二子掩膜图案52a暴露出的第一掩膜材料层2，将第二子掩膜图案52a延伸到第一掩膜材料层2中，形成第二掩膜图案42a。
本示例中，第一子掩膜层51和第二子掩膜层52的厚度相同，根据第一子布局31刻蚀第一子掩膜层51形成第一子掩膜图案51a的厚度和根据第二子布局32刻蚀第二子掩膜层52形成第二子掩膜图案52a的厚度相同，确保在第一子掩膜层51中形成的第一子掩膜图案51a和在第二子掩膜层52中形成的第二子掩膜图案52a的尺寸相同，从而保证根据第一子掩膜图案51a和第二子掩膜图案52a分别在第一掩膜材料层2中形成的第一掩膜图案41a和第二掩膜图案42a的尺寸相同。
本公开示例性的实施例中提供一种半导体结构的形成方法，如图3所示，图3示出了根据本公开一示例性的实施例提供的半导体结构的形成方法的流程图，图11-图19为半导体结构的形成方法的各个阶段的示意图，下面结合图11-图19对半导体结构的形成方法进行介绍。本公开一示例性的实施例提供的一种半导体结构的形成方法，包括如下的步骤：
步骤S310：提供待刻蚀层。
如图11所示，待刻蚀层1设置在基底6上，基底6包括源极区61和漏极区62。在本实施例中，待刻蚀层1的材料包括绝缘材料，例如，待刻蚀层1的材料可以包括氧化硅 或氮化硅中的至少一种。
在本实施例中，基底6包括有源区63和隔离结构64，有源区63包括源极区61和漏极区62，如图7所示，源极区61和漏极区62分别设置在有源区63的两端。
参照图11所示，基底6上还设置有栅极65，栅极65位于源极区61和漏极区62之间，栅极65和有源区63接触连接。待刻蚀层1覆盖栅极65，且待刻蚀层1的顶面高于栅极65的顶面。
待刻蚀层1覆盖基底6的顶面，待刻蚀层1可以包括单层或多层结构。参照图7所示，在本实施例中，待刻蚀层1包括依次叠置在基底6上的第一介质层11、第二介质层12以及第三介质层13。
步骤S320：在待刻蚀层上依次形成硬掩膜层和第一缓冲层。
参照图12所示，首先，可以通过旋涂硬掩膜材料(Spin-On Hard-maskmaterial)在待刻蚀层1上形成硬掩膜层7，硬掩膜层7的材料可以包括旋涂碳(Spin On Carbon，SOC)。
然后，可以选用化学气相沉积工艺(Chemical Vapor Deposition，CVD)、物理气相沉积工艺(Physical Vapor Deposition，PVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)或溅镀(sputtering)中的任一种沉积工艺沉积形成第一缓冲层81。第一缓冲层81的材料可以包括氮化硅。
步骤S330：在待刻蚀层的上方形成第一掩膜材料层。
参照图12所示，可以选用化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺沉积形成第一掩膜材料层2。第一掩膜材料层2设置在第一缓冲层81上，硬掩膜层7通过第一缓冲层81和第一掩膜材料层2隔开。
第一掩膜材料层2的材料和第一缓冲层81的材料不同，第一掩膜材料层2相对第一缓冲层81具有高刻蚀选择比，例如，在本实施例中，第一掩膜材料层2的材料可以包括氧化硅。
步骤S340：对第一掩膜材料层进行第一图案化处理，在第一掩膜材料层中形成第一掩膜图案。
本实施例中，对第一掩膜材料层2进行第一图案化处理，包括以下步骤：
步骤S341：形成第一子掩膜层，第一子掩膜层覆盖第一掩膜材料层的部分顶面，第一子掩膜层包括第一子掩膜图案，第一子掩膜图案暴露出第一掩膜材料层的另一部分顶面。
如图12所示，形成第一子掩膜层51采用以下实施方式：通过旋涂硬掩膜材料，在第一掩膜材料层2上形成第一子掩膜层51，第一子掩膜层51相对第一掩膜材料层2具有高刻蚀选择比，第一子掩膜层51的材料可以包括旋涂碳。
在本实施例中，形成第一子掩膜层51后，可以通过上述任一种沉积工艺在第一子掩膜层51的顶面上形成第二缓冲层82，第二缓冲层82的材料可以包括氮化硅。
在垂直于待刻蚀层1的顶面的截面上，硬掩膜层7的厚度大于第一子掩膜层51的厚度，第一缓冲层81的厚度大于第二缓冲层82的厚度。比如，硬掩膜层7的厚度可以为第一子掩膜层51的厚度的3倍～5倍。示例性的，硬掩膜层7的厚度为240nm；第一子掩膜层51的厚度为80nm；第一缓冲层81的厚度为40nm；第二缓冲层82的厚度为30nm。
如图12所示，然后，在第二缓冲层82上形成第一光刻胶掩膜91，第一光刻胶掩膜91包括第一光刻胶图案91a，第一光刻胶图案91a暴露出第二缓冲层82的部分顶面。
如图13所示，参照图12所示，然后，刻蚀去除被第一光刻胶图案91a暴露出的第二缓冲层82，将第一光刻胶图案91a延伸到第二缓冲层82中。接着，继续刻蚀被第一光刻胶图案91a暴露出的第一子掩膜层51，去除部分第一子掩膜层51，暴露出第一掩膜材料层51的部分顶面，在第一子掩膜层51中形成第一子掩膜图案51a。在本实施例中，可以通过等离子体干法刻蚀第二缓冲层82和第一子掩膜层51，也可以通过刻蚀液湿法刻蚀第 二缓冲层82和第一子掩膜层51。
参照图13所示，在刻蚀第一子掩膜层51形成第一子掩膜图案51a的制程中，可能消耗部分第二缓冲层82，减薄第二缓冲层82的厚度，或者将第二缓冲层82全部去除。第二缓冲层82缓冲了刻蚀制程对第一子掩膜层51的消耗，从而避免刻蚀制程消耗第一子掩膜层51，确保形成第一子掩膜图案51a后第一子掩膜层51的厚度不变。
本步骤中，在第一子掩膜层51中形成第一子掩膜图案51a之后，如果第一子掩膜层51上还残留部分第二缓冲层82，去除残留的第二缓冲层82。
步骤S342：根据第一子掩膜层刻蚀第一掩膜材料层，去除被第一子掩膜图案暴露出的第一掩膜材料层，将第一子掩膜图案延伸到第一掩膜材料层中，形成第一掩膜图案。
如图14所示，参照图13所示，根据第一子掩膜图案51a刻蚀第一掩膜材料层2，将第一子掩膜图案51a延伸到第一掩膜材料层2中，形成第一掩膜图案41a。
在第一掩膜材料层2中形成第一掩膜图案41a之后，刻蚀去除第一子掩膜层51，刻蚀工艺刻蚀第一子掩膜层51相对第一掩膜材料层2具有高刻蚀选择比，能够避免刻蚀去除第一子掩膜层51的过程损伤第一掩膜材料层2，确保第一掩膜材料层2的厚度不变，同时确保第一掩膜图案41a的形貌不变，确保第一掩膜图案41a的形貌具有高精度。
步骤S350：对第一掩膜材料层进行第二图案化处理，在第一掩膜材料层中形成第二掩膜图案，第一掩膜图案和第二掩膜图案独立设置。
本实施例中，对第一掩膜材料层2进行第二图案化处理，包括以下步骤：
步骤S351：在第一掩膜材料层上形成第二子掩膜层，第二子掩膜层填充第一掩膜图案并覆盖第一掩膜材料层的部分顶面，第二子掩膜层包括第二子掩膜图案，第二子掩膜图案暴露出第一掩膜材料层的另一部分顶面。
如图15所示，参照图14所示，首先，可以通过旋涂硬掩膜材料，硬掩膜材料填充第一掩膜材料层2中的第一掩膜图案41a并覆盖第一掩膜材料层2的顶面，在第一掩膜材料层2上形成第二子掩膜层52，第二子掩膜层52相对第一掩膜材料层2具有高刻蚀选择比，第二子掩膜层52的材料可以包括旋涂碳。
形成第二子掩膜层52后，还可以通过化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅镀中的任一种沉积工艺沉积形成第三缓冲层83，第三缓冲层83覆盖第二子掩膜层52的顶面。其中，第三缓冲层83的材料可以包括氮化硅。
如图15所示，参照图12所示，第二子掩膜层52的厚度和第一子掩膜层51的厚度相同，第三缓冲层83的厚度和第二缓冲层82的厚度相同，以使在第一掩膜材料层2中形成第一掩膜图案41a的制程厚度和在第一掩膜材料层2中形成第二掩膜图案42a(后续步骤中会进行详细说明)的制程厚度相同，确保形成的第一掩膜图案41a和第二掩膜图案42具有相同的尺寸和形貌。
如图15所示，然后，于第三缓冲层83上形成第二光刻胶掩膜92，第二光刻胶掩膜92包括第二光刻胶图案92a，第二光刻胶图案92a暴露出第三缓冲层83的部分顶面。
如图16所示，参照图15，接着，刻蚀去除被第二光刻胶图案92a暴露出的第三缓冲层83，将第二光刻胶图案92a延伸到第三缓冲层83中。继续刻蚀被第二光刻胶图案92a暴露出的第二子掩膜层52，去除部分第二子掩膜层52，将第二光刻胶图案92a延伸到第二子掩膜层52中，形成第二子掩膜图案52a。在本实施例中，可以通过等离子体干法刻蚀第三缓冲层83和第二子掩膜层52，也可以通过刻蚀液湿法刻蚀第三缓冲层83和第二子掩膜层52。
第一子掩膜图案51a在待刻蚀层1上形成的投影和第二子掩膜图案52a在待刻蚀层1上形成的投影无重合部分。本实施例中，第一子掩膜图案51a在基底6上形成投影落在源极区61或落在漏极区62中，第一子掩膜图案52a在基底6上形成投影落在漏极区62或落在源极区61中。
同样的，刻蚀制程消耗部分第三缓冲层83，从而避免消耗第二子掩膜层52，确保形成第二子掩膜图案52a后第二子掩膜层52的厚度不变。
本步骤中，在第二子掩膜层52中形成第二子掩膜图案52a之后，如果第二子掩膜层52上还残留部分第三缓冲层83，去除残留的第三缓冲层83。
步骤S352：根据第二子掩膜层刻蚀第一掩膜材料层，去除被第二子掩膜图案暴露出的第一掩膜材料层，将第二子掩膜图案延伸到第一掩膜材料层中，形成第二掩膜图案。
如图17所示，参照图16，第二子掩膜层52为掩膜刻蚀第一掩膜材料层2，将第二子掩膜图案52a延伸到第一掩膜材料层2中，在第一掩膜材料层2中形成第二掩膜图案42a。
本实施例中，第一掩膜图案41a在基底6上形成投影落在源极区61或落在漏极区62中，第二掩膜图案42a在基底6上形成的投影落在漏极区62或落在源极区61中。
形成第二掩膜图案42a之后，刻蚀去除第二子掩膜层52。本实施例中，刻蚀工艺刻蚀第二子掩膜层52相对于第一掩膜材料层2具有高刻蚀选择比，去除第二子掩膜层52的过程不会损伤第一掩膜材料层2，避免第一掩膜图案41a和第二掩膜图案42a的形貌发生变化，确保第一掩膜图案41a和第二掩膜图案42a具有高精度，能够提高形成的半导体结构的良率。
步骤S360：根据第一掩膜层刻蚀待刻蚀层，将至少两个掩膜图案转移到待刻蚀层中。
如图17、图18、图19所示，根据第一掩膜层4依次刻蚀被第一掩膜图案41a和第二掩膜图案42a暴露出的第一缓冲层81、硬掩膜层7以及待刻蚀层1，暴露出源极区61和漏极区62的部分顶面，将第一掩膜图案41a和第二掩膜图案42a延伸到待刻蚀层1中，在源极区61的上方形成源极接触孔14，源极接触孔14暴露出部分源极区61的部分顶面，在漏极区62的上方漏极接触孔15，漏极接触孔15暴露出漏极区62的部分顶面。
在本实施例中，根据第一掩膜层4刻蚀待刻蚀层1，可以采用以下实施方式：
参照图17，首先，以第一掩膜层4为掩膜刻蚀第一缓冲层81，将第一掩膜图案41a和第二掩膜图案42a转移到第一缓冲层81中。
在本实施例中，刻蚀第一缓冲层81可以采用以下实施方式：将半导体结构置于反应腔中，向反应腔中通入第一刻蚀气体，通过第一刻蚀气体刻蚀第一缓冲层81，去除被第一掩膜图案41a和第二掩膜图案42a暴露出的第一缓冲层81，将第一掩膜图案41a和第二掩膜图案42a延伸到第一缓冲层81中。其中，第一刻蚀气体包括含氧气体，例如，第一刻蚀气体可以包括氧气。在本实施例中，第一刻蚀气体包括氧气(O 2)，第一刻蚀气体中还包括少量硫化羰(COS)。
如图18所示，参照图17，然后，继续刻蚀硬掩膜层7，将第一掩膜图案41a和第二掩膜图案42a转移到硬掩膜层7中。
在本实施例中，刻蚀硬掩膜层7可以采用以下实施方式：向反应腔中通入第二刻蚀气体，通过第二刻蚀气体刻蚀硬掩膜层7，去除被第一缓冲层81暴露出的硬掩膜层7。其中，第二刻蚀气体包括第一气体和第二气体，第一气体包括含氟化合物气体，例如，第一气体可以包括三氟甲烷(CHF 3)、六氟乙烷(C 2F 6)、八氟丙烷(C 3F 8)、八氟环丁烷(C 4F 8)中的至少一种，第二气体包括氧气或溴气(Br 2)中的至少一种。
本实施例中，第二刻蚀气体包括三氟甲烷和氧气的混合气体；或者，第二刻蚀气体包括八氟丙烷和溴气的混合气体；再或者第二刻蚀气体包括六氟乙烷、氧气和溴气的混合气体。
如图18、图19所示，参照图17，接着，以硬掩膜层7为掩膜刻蚀待刻蚀层1，依次去除被硬掩膜层7暴露出的第三介质层13、第二介质层12和第一介质层11，直至暴露出基底6的顶面后停止刻蚀，第一掩膜图案41a和第二掩膜图案42a转移到待刻蚀层1中，在待刻蚀层1中分别形成了源极接触孔14和漏极接触孔15。
本实施例的半导体结构的形成方法，在刻蚀待刻蚀层之前，将待形成的设计图案拆分为第一光刻胶图案和第二光刻胶图案，根据第一光刻胶图案和第二光刻胶图案分别对第一掩膜材料层进行两次图案化处理，形成第一掩膜层，第一掩膜层包括第一掩膜图案和第二掩膜图案，并且，对第一掩膜材料层进行两次图案化处理的制程厚度相同，第一掩膜图案和第二掩膜图案的大小均匀且精确度高，确保根据第一掩膜层在待刻蚀层中形成的源极接触孔和漏极接触孔具有相同的大小，避免源极接触孔和漏极接触孔大小不一致对半导体结构造成不良影响，提高半导体结构整体的均匀性，提高了半导体结构的良率和产率。
本实施例的半导体结构的形成方法，适用于形成特征尺寸更小、间距更小的源极接触孔和漏极接触孔，同时能够确保形成的源极接触孔和漏极接触孔的尺寸相同；有利于后续制程中，在源极接触孔中形成的源极接触插塞和在漏极接触孔中形成的漏极接触插塞的接触电阻的均匀性，半导体结构的晶体管的电流传导更加稳定。
本公开示例性实施例提供一种半导体结构，半导体结构根据上述实施例中半导体结构的形成方法形成。
本实施例的半导体结构可以为存储芯片，存储芯片可以用在动态随机存储器(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random-Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random-Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实 施例技术方案的范围。
工业实用性
本公开提供的半导体结构的形成方法及半导体结构中，通过至少两次图案化处理在第一掩膜层中形成至少两个掩膜图案，只需根据第一掩膜层对待刻蚀层执行一次刻蚀处理，即可将至少两个掩膜图案转移到待刻蚀层中，减少对待刻蚀层执行刻蚀处理的次数，缩短将设计图案转移到待刻蚀层中所需的时间，提高将设计图案向待刻蚀层转移的效率。

Claims (15)

  1. 一种半导体结构的形成方法，包括：
    提供待刻蚀层；
    在所述待刻蚀层的上方形成第一掩膜材料层；
    对所述第一掩膜材料层进行至少两次图案化处理，在所述第一掩膜材料层中形成至少两个掩膜图案，所述至少两个掩膜图案独立设置，所述第一掩膜材料层形成为第一掩膜层；
    根据所述第一掩膜层刻蚀所述待刻蚀层，将所述至少两个掩膜图案转移到所述待刻蚀层中。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，对所述第一掩膜材料层进行至少两次图案化处理，包括重复执行以下步骤至少两次：
    在所述第一掩膜材料层上形成子掩膜层，所述子掩膜层包括子掩膜图案，所述子掩膜图案暴露出所述第一掩膜材料层的部分顶面；
    根据所述子掩膜层刻蚀所述第一掩膜材料层，将所述子掩膜图案转移到所述第一掩膜材料层中，在所述第一掩膜材料层中形成所述掩膜图案。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，至少两次形成的所述子掩膜层中的所述子掩膜图案在所述待刻蚀层上形成的投影无重合部分。
  4. 根据权利要求2所述的半导体结构的形成方法，其中，所述第一掩膜材料层中已形成有所述掩膜图案时，在所述第一掩膜材料层上形成的所述子掩膜层还填充所述第一掩膜材料层中的所述掩膜图案。
  5. 根据权利要求1所述的半导体结构的形成方法，其中，所述图案化处理的次数为两次，对所述第一掩膜材料层进行至少两次图案化处理，包括：
    对所述第一掩膜材料层进行第一图案化处理，在所述第一掩膜材料层中形成第一掩膜图案；
    对所述第一掩膜材料层进行第二图案化处理，在所述第一掩膜材料层中形成第二掩膜图案，所述第一掩膜图案和所述第二掩膜图案独立设置。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，对所述第一掩膜材料层进行第一图案化处理，包括：
    形成第一子掩膜层，所述第一子掩膜层覆盖所述第一掩膜材料层的部分顶面，所述第一子掩膜层包括第一子掩膜图案，所述第一子掩膜图案暴露出所述第一掩膜材料层的另一部分顶面；
    根据所述第一子掩膜层刻蚀所述第一掩膜材料层，去除被所述第一子掩膜图案暴露出的所述第一掩膜材料层，将所述第一子掩膜图案延伸到所述第一掩膜材料层中，形成所述第一掩膜图案。
  7. 根据权利要求6所述的半导体结构的形成方法，其中，对所述第一掩膜材料层进行第二图案化处理，包括：
    在所述第一掩膜材料层上形成第二子掩膜层，所述第二子掩膜层填充所述第一掩膜图案并覆盖所述第一掩膜材料层的部分顶面，所述第二子掩膜层包括第二子掩膜图案，所述 第二子掩膜图案暴露出所述第一掩膜材料层的另一部分顶面；
    根据所述第二子掩膜层刻蚀所述第一掩膜材料层，去除被所述第二子掩膜图案暴露出的所述第一掩膜材料层，将所述第二子掩膜图案延伸到所述第一掩膜材料层中，形成所述第二掩膜图案。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，所述第一子掩膜图案在所述待刻蚀层上形成的投影和所述第二子掩膜图案在所述待刻蚀层上形成的投影无重合部分。
  9. 根据权利要求7所述的半导体结构的形成方法，其中，所述第一子掩膜层和所述第二子掩膜层具有相同的厚度；所述第一子掩膜图案和所述第二子掩膜图案的尺寸相同；所述第一掩膜图案和所述第二掩膜图案的尺寸相同。
  10. 根据权利要求5所述的半导体结构的形成方法，其中，所述待刻蚀层设置在基底上，所述基底包括源极区和漏极区，所述第一掩膜图案在所述基底上形成投影落在所述源极区或落在所述漏极区中，所述第二掩膜图案在所述基底上形成的投影落在所述漏极区或落在所述源极区中。
  11. 根据权利要求10所述的半导体结构的形成方法，其中，根据所述第一掩膜层刻蚀所述待刻蚀层，包括：
    刻蚀去除被所述第一掩膜图案和所述第二掩膜图案暴露出的所述待刻蚀层，暴露出所述源极区的部分顶面，在所述源极区的上方形成源极接触孔，暴露出所述漏极区的部分顶面，在所述漏极区的上方形成漏极接触孔。
  12. 根据权利要求1所述的半导体结构的形成方法，还包括：
    在所述待刻蚀层上依次形成硬掩膜层和第一缓冲层，所述硬掩膜层通过所述第一缓冲层和所述第一掩膜材料层隔开，所述第一掩膜材料层设置在所述第一缓冲层上。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，根据所述第一掩膜层刻蚀所述待刻蚀层，包括：
    以所述第一掩膜层为掩膜依次刻蚀所述第一缓冲层和所述硬掩膜层，将所述至少两个掩膜图案转移到所述硬掩膜层中；
    以所述硬掩膜层为掩膜刻蚀所述待刻蚀层，将所述至少两个掩膜图案转移到所述待刻蚀层中。
  14. 根据权利要求12所述的半导体结构的形成方法，其中，所述第一掩膜材料层相对于所述第一缓冲层具有高刻蚀选择比。
  15. 一种半导体结构，所述半导体结构根据权利要求1-14所述的半导体结构的形成方法形成。
PCT/CN2022/136225 2022-10-27 2022-12-02 半导体结构的形成方法及半导体结构 WO2024087320A1 (zh)

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US20080076075A1 (en) * 2006-09-22 2008-03-27 Tokyo Electron Limited Method for double patterning a thin film
US8916475B1 (en) * 2013-11-01 2014-12-23 United Microelectronics Corp. Patterning method
CN110911272A (zh) * 2018-09-17 2020-03-24 长鑫存储技术有限公司 在半导体器件中形成微图案的方法
CN114068310A (zh) * 2020-07-30 2022-02-18 中国科学院微电子研究所 一种方形排列的孔的刻蚀方法

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US20080076075A1 (en) * 2006-09-22 2008-03-27 Tokyo Electron Limited Method for double patterning a thin film
US8916475B1 (en) * 2013-11-01 2014-12-23 United Microelectronics Corp. Patterning method
CN110911272A (zh) * 2018-09-17 2020-03-24 长鑫存储技术有限公司 在半导体器件中形成微图案的方法
CN114068310A (zh) * 2020-07-30 2022-02-18 中国科学院微电子研究所 一种方形排列的孔的刻蚀方法

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