WO2023197432A1 - 半导体结构的制作方法及半导体结构 - Google Patents

半导体结构的制作方法及半导体结构 Download PDF

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Publication number
WO2023197432A1
WO2023197432A1 PCT/CN2022/097671 CN2022097671W WO2023197432A1 WO 2023197432 A1 WO2023197432 A1 WO 2023197432A1 CN 2022097671 W CN2022097671 W CN 2022097671W WO 2023197432 A1 WO2023197432 A1 WO 2023197432A1
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Prior art keywords
mask pattern
target layer
semiconductor structure
layer
mask
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PCT/CN2022/097671
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English (en)
French (fr)
Inventor
吴玉雷
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长鑫存储技术有限公司
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Priority to US17/807,724 priority Critical patent/US11791163B1/en
Publication of WO2023197432A1 publication Critical patent/WO2023197432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask

Definitions

  • the present disclosure relates to, but is not limited to, a method of manufacturing a semiconductor structure and a semiconductor structure.
  • the present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.
  • a first aspect of the present disclosure provides a method of manufacturing a semiconductor structure, the method including:
  • a plurality of first mask patterns are formed on the top surface of the target layer, and any two adjacent first mask patterns in the first direction are spaced apart;
  • a plurality of second mask patterns are formed above the target layer, each of the second mask patterns extends along the first direction, and the second mask patterns are spaced apart from each other, and each of the second mask patterns extends along the first direction.
  • the second mask pattern covers at least part of the top surface of each of the first mask patterns and part of the top surface of the target layer in the direction in which it extends;
  • a second etching is performed on the target layer based on the first mask pattern.
  • a plurality of first mask patterns are formed on the top surface of the target layer, including:
  • the cross structure including an overlapping area
  • each initial mask pattern is removed, and the retained partial structure of each initial mask pattern forms the first mask pattern.
  • forming a cross structure on the target layer includes:
  • a plurality of first line structures are formed, each of the first line structures extends along a second direction, and a plurality of the first line structures are spaced apart in a direction perpendicular to the second direction, and the first line structures are The direction intersects obliquely with the second direction;
  • a plurality of second line structures are formed.
  • the plurality of second line structures are located above the first line structure.
  • the second line structures extend along a third direction. In a direction perpendicular to the third direction, a plurality of the second line structures are formed.
  • the two-line structures are spaced apart, and the first direction and the third direction intersect obliquely;
  • the plurality of first line structures and the plurality of second line structures together form the intersection structure, and the overlapping portions of the plurality of first line structures and the plurality of second line structures form the overlapping area.
  • a plurality of second mask patterns are formed above the target layer, including:
  • a projection formed by each second mask pattern on the target layer is divided by a projection formed by the first mask pattern on the target layer in its extension direction. into multiple independently configured sub-graphs.
  • performing a first etching on the target layer based on the second mask pattern includes:
  • the method further includes:
  • first isolation material to form a first isolation layer, the first isolation layer filling the first shallow trench and covering the first mask pattern and the active part exposed by the first mask pattern The top surface of the strip.
  • the method further includes:
  • the top surface of the first isolation layer is planarized to expose the top surfaces of a plurality of first mask patterns.
  • performing a second etching on the target layer based on the first mask pattern includes:
  • the method further includes:
  • the method further includes:
  • the first isolation layer and the second isolation layer above the top surface of the target layer are removed, and the remaining first isolation layer and the second isolation layer together form a shallow trench isolation structure.
  • the first isolation material and the second isolation material include the same or different materials.
  • the method further includes:
  • a plurality of word lines are formed, each of the word lines extends along the fourth direction and penetrates the plurality of active areas in its extending direction, and the plurality of word lines are spaced apart from each other.
  • the second direction and the third direction intersect at a first included angle
  • the first direction and the fourth direction intersect at a second included angle
  • the first included angle The relationship with the second included angle is as follows:
  • the first included angle is ⁇ 1
  • the second included angle is ⁇ 2.
  • a second aspect of the present disclosure provides a semiconductor structure, which is fabricated according to the above-mentioned method for fabricating a semiconductor structure.
  • FIG. 1 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 2 is a flowchart of a method of fabricating a semiconductor structure according to an exemplary embodiment.
  • FIG. 3 is a schematic diagram illustrating forming a first line structure on a target layer according to an exemplary embodiment.
  • FIG. 4 is a schematic diagram of forming a first layer structure according to an exemplary embodiment.
  • FIG. 5 is a schematic diagram of forming a second dielectric layer according to an exemplary embodiment.
  • FIG. 6 is a schematic diagram of forming a second line structure according to an exemplary embodiment.
  • Figure 7 is a schematic diagram of a formed cross structure according to an exemplary embodiment.
  • FIG 8 is a top view of a formed cross structure according to an exemplary embodiment.
  • FIG. 9 is a top view of etching the first layer structure according to the second line structure according to an exemplary embodiment.
  • FIG. 10 is a schematic diagram of forming an initial mask pattern according to an exemplary embodiment.
  • FIG. 11 is a schematic diagram of forming a second mask material layer according to an exemplary embodiment.
  • FIG. 12 is a top view of a third photomask and an initial mask pattern according to an exemplary embodiment.
  • FIG. 13 is a schematic diagram of forming a second mask pattern according to an exemplary embodiment.
  • FIG. 14 is a top view of the second mask pattern and the first mask pattern according to an exemplary embodiment.
  • FIG. 15 is a schematic diagram showing the first etching of the target layer according to an exemplary embodiment.
  • FIG. 16 is a schematic diagram of forming a first isolation layer according to an exemplary embodiment.
  • FIG. 17 is a schematic diagram of performing a second etching on the target layer according to an exemplary embodiment.
  • FIG. 18 is a schematic diagram of forming a second isolation layer according to an exemplary embodiment.
  • FIG. 19 is a schematic diagram of forming an isolation structure according to an exemplary embodiment.
  • Figure 20 is a top view of an active area according to an exemplary embodiment.
  • 21 is a top view illustrating the formation of word lines and bit lines according to an exemplary embodiment.
  • Figure 22 is a schematic diagram of a constructed coordinate system according to an exemplary embodiment.
  • Target layer 100.
  • Active strip 111. Active area
  • 120. First shallow trench; 130. Second shallow trench; 200.
  • Cross structure 201.
  • Initial mask pattern; 220. Second line structure; 221.
  • Second dielectric layer; 230. Auxiliary layer; 240. First layer structure; 250. Overlapping area; 260.
  • D1 first direction; D2, second direction; D3, third direction; D4, fourth direction; ⁇ 1, first included angle; ⁇ 2, second included angle; ⁇ 3, third included angle; ⁇ 4, fourth included angle horn.
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • the target layer is etched twice using the second mask pattern and the first mask pattern as masks respectively, so that the target layer can be formed in the target layer.
  • the manufacturing method of this embodiment reduces the difficulty of forming repeating structures with more sophisticated shapes and higher density, which is beneficial to the formation of highly integrated integrated circuits.
  • FIG. 1 shows a flow chart of a method of manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • An exemplary embodiment of the present disclosure provides a method of manufacturing a semiconductor structure. , including the following steps.
  • Step S110 Provide a target layer.
  • the target layer 100 refers to the material layer to be etched that needs to be patterned.
  • the target layer 100 can be any structure used to form a semiconductor element.
  • the target layer 100 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC); it may also be silicon on insulator (SOI) or on insulator. Germanium (GOI); or may also include other materials, such as gallium arsenide and other Group III-V compounds.
  • the semiconductor substrate may be doped with some impurity ions as needed, and the impurity ions may be N-type impurity ions or P-type impurity ions.
  • the target layer 100 may also be a material layer used to form a semiconductor element, such as a dielectric layer or a metal layer.
  • the material layer may be an amorphous carbon layer, an oxide layer, a nitride layer, a copper layer, a tungsten layer, an aluminum layer, etc., but is not limited thereto.
  • Step S120 Form a plurality of first mask patterns on the top surface of the target layer, and any two adjacent first mask patterns in the first direction are spaced apart.
  • a plurality of first mask patterns 201 are independently provided on the top surface of the target layer 100.
  • the plurality of first mask patterns 201 are arranged in multiple rows. Any two adjacent first mask patterns 201 in the first direction D1 are spaced apart.
  • Step S130 Form a plurality of second mask patterns above the target layer, each second mask pattern extends along the first direction, and the second mask patterns are spaced apart from each other, and each second mask pattern covers at least A portion of the top surface of each first mask pattern and a portion of the top surface of the target layer located in its extension direction.
  • each second mask pattern 310 formed in this embodiment is correspondingly arranged on a row of first mask patterns 201, and each second mask pattern 310 is correspondingly filled with adjacent ones located in the same row.
  • each second mask pattern 310 on the target layer 100 is divided into a plurality of independently arranged projections by the projection formed by the first mask pattern 201 on the target layer 100 in its extending direction.
  • Sprite 311 the shapes and arrangement densities of the first mask pattern 201 and the second mask pattern 310 are set according to the semiconductor structure to be formed.
  • Step S140 Perform a first etching on the target layer based on the second mask pattern.
  • the second mask pattern 310 is used as a mask to etch the target layer 100, the portion of the target layer 100 exposed by the second mask pattern 310 is removed, and the second mask pattern 310 is used as a mask to etch the target layer 100.
  • the pattern of the film pattern 310 extends into the target layer 100, and the retained target layer 100 forms a plurality of independently arranged structures.
  • the etching process of the first etching can be dry etching or wet etching.
  • Step S150 Perform a second etching on the target layer based on the first mask pattern.
  • the second mask pattern 310 is removed through dry or wet etching to expose the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310 .
  • the first mask pattern 201 and part of the target layer 100 covered by the first mask pattern 201 are etched away to extend the pattern of the first mask pattern 201 into the target layer 100 .
  • the target layer 100 retained by etching is divided into a plurality of independently arranged substructures.
  • the manufacturing method of the semiconductor structure of this embodiment forms two layers of masks, a first mask pattern and a second mask pattern, above the target layer, and sequentially performs two layers of masks on the target layer according to the second mask pattern and the first mask pattern. Second etching to form a high-density repeating structure in the target layer. Compared with the solution of forming an etching mask directly through the photolithography process, the production method of this embodiment has lower requirements for the resolution accuracy of the photolithography process and reduces the The process difficulty and process cost are reduced.
  • FIG. 2 shows a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.
  • FIGS. 3 to 22 are schematic diagrams of various stages of the method for manufacturing a semiconductor structure according to this embodiment. The following is combined with Figures 3 to 22 introduce the manufacturing method of the semiconductor structure of this embodiment.
  • Exemplary embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • This embodiment does not limit the semiconductor structure.
  • the following is an introduction where the semiconductor structure is a dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • This embodiment is described by forming an active region in the semiconductor structure.
  • the semiconductor structure in this embodiment can also be other structures.
  • An exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, as shown in Figure 2, including the following steps:
  • Step S210 Provide a target layer.
  • the target layer 100 is a semiconductor substrate, and the material of the semiconductor substrate is the same as the material of the semiconductor substrate in the above embodiment.
  • Step S220 Form multiple initial mask patterns on the top surface of the target layer, and any two adjacent initial mask patterns in the first direction are spaced apart.
  • Step S221 Form a cross structure on the target layer, where the cross structure includes an overlapping area.
  • a plurality of first line structures 210 are formed on the top surface of the target layer 100.
  • Each first line structure 210 extends along the second direction D2. In the direction perpendicular to the second direction D2, The plurality of first line structures 210 are spaced apart, and the first direction D1 and the second direction D2 intersect obliquely.
  • the dielectric material may be deposited through a chemical vapor deposition process or a physical vapor deposition process to form a first dielectric layer (not shown in the figure) on the top surface of the target layer 100, where the material of the first dielectric layer may include silicon nitride and/or or silicon oxide.
  • a first photomask (not shown in the figure) is formed on the top surface of the first dielectric layer. Part of the first dielectric layer is etched and removed according to the first photomask. The retained first dielectric layer forms multiple independent strips.
  • the first line structures 210 are provided. Each first line structure 210 extends along the second direction D2. In the direction perpendicular to the second direction D2, two adjacent first line structures 210 are spaced apart.
  • auxiliary materials can be deposited through an atomic layer deposition process (Atomic Layer Deposition, ALD) or a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
  • ALD atomic layer deposition
  • CVD chemical Vapor Deposition
  • the auxiliary materials form an auxiliary layer 230, and the auxiliary layer 230 covers the first
  • the line structures 210 and fill the trenches between adjacent first line structures 210 , and the auxiliary layer 230 and the first line structures 210 jointly form the first layer structure 240 .
  • the first layer structure 240 is polished to make the top surface of the first layer structure 240 flat, so that the second line structure 220 is subsequently formed on the top surface of the first layer structure 240 .
  • the material of the auxiliary layer 230 may include silicon nitride, silicon oxynitride, etc., but is not limited thereto.
  • the auxiliary layer 230 can also be formed through other processes.
  • the auxiliary layer 230 can be formed by spin coating an auxiliary material through a spin coating process.
  • the material of the auxiliary layer 230 can be Spin on Carbon (SOC).
  • a dielectric material may be deposited through a chemical vapor deposition process or a physical vapor deposition process to form a second dielectric layer 221 on the top surface of the target layer 100 , where the material of the second dielectric layer 221 may include nitride. Silicon and/or silicon oxide.
  • a second photomask (not shown in the figure) is formed on the top surface of the second dielectric layer 221, and a portion of the second dielectric layer 221 is etched and removed based on the second photomask.
  • the remaining second dielectric layer 221 forms a plurality of second line structures 220.
  • the plurality of second line structures 220 are located above the first line structure 210.
  • the plurality of second line structures 220 are independently arranged, and each second line structure 220 is along the third direction D3. Extending, in a direction perpendicular to the third direction D3, a plurality of second line structures 220 are spaced apart, and the first direction D1 and the third direction D3 obliquely intersect.
  • the first line structure 210 and the second line structure 220 form a cross structure 200 in the space above the target layer 100, and the first line structure 210 and the second line structure 220 exist in the space above the target layer 100.
  • the overlapping portion is the overlapping area 250 of the intersection structure 200 .
  • Step S222 Remove part of the intersection structure and retain some overlapping areas.
  • the retained overlapping areas form multiple initial mask patterns.
  • the first layer structure 240 is etched according to the second line structure 220 , the auxiliary layer 230 and the first line structure 210 exposed by the second line structure 220 are removed, and the pattern of the second line structure 220 is transferred.
  • the retained first layer structure 240 includes a portion of the first line structure 210 and a portion of the auxiliary layer 230 , wherein the retained portion of the first line structure 210 corresponds to the overlapping area 250 of the cross structure 200 .
  • all the second line structures 220 are dry etched or wet etched to expose the retained first layer structure 240 .
  • the auxiliary layer 230 in the retained first layer structure 240 can be removed by dry or wet etching.
  • the retained first line structure 210 forms a plurality of mutually independent initial mask patterns 211. Multiple initial mask patterns 211 are formed in this embodiment.
  • the initial mask patterns 211 are arranged in multiple rows along the first direction D1.
  • a stacked first line structure 210 and a second line structure 220 are formed above the target layer 100.
  • the feature size of the initial mask pattern 211 formed in the overlapping area of the second line structure 220 is small, and the size of the first mask pattern 201 (see FIG. 14 ) formed by the initial mask pattern 211 formed according to this embodiment is even smaller.
  • the target layer 100 can be etched according to the first mask pattern 201 to form a repeating structure with a higher repeat density and smaller size.
  • Step S230 Form a second mask material layer covering the initial mask pattern and the exposed top surface of the target layer.
  • the second mask material can be deposited through a chemical vapor deposition process (Chemical Vapor Deposition, CVD) or a physical vapor deposition process (Physical Vapor Deposition, PVD) to form the second mask material layer 300 , the second mask material layer 300 covers the initial mask pattern 211 and the exposed top surface of the target layer 100 .
  • CVD chemical Vapor Deposition
  • PVD Physical Vapor Deposition
  • Step S240 Remove part of the second mask material layer to form a plurality of second mask patterns extending along the first direction, while removing part of the structure of each initial mask pattern, and retaining part of the structure of each initial mask pattern. A first mask pattern is formed.
  • a third photomask 260 is formed on the top surface of the second mask material layer 300 , and the second mask material layer 300 and the initial mask pattern 211 are etched according to the third photomask 260 .
  • the retained second mask material layer 300 forms a plurality of second mask patterns 310 extending along the first direction D1
  • the retained partial structure of each initial mask pattern 211 forms a third A mask pattern 201.
  • any two adjacent second mask patterns 310 are separated by a first trench 320, and the first trench 320 exposes part of the target layer 100. top surface.
  • each second mask pattern 310 on the target layer 100 is divided into a plurality of independently arranged projections by the projection formed by the first mask pattern 201 on the target layer 100 in its extending direction.
  • Sprite 311 In order to subsequently etch the target layer 100 according to the first mask pattern 201 and the second mask pattern 310 to form a plurality of independently arranged active areas 111 .
  • a plurality of first mask patterns 201 and a plurality of second mask patterns 310 are formed at the same time, and the projection of each second mask pattern 310 formed on the target layer 100 is positioned on the third mask pattern in its extension direction.
  • the projection formed by a mask pattern 201 on the target layer 100 is divided into a plurality of independently arranged sub-patterns 311, and the projection formed by the first mask pattern 201 on the target layer 100 is located on the target layer 100 of the second mask pattern 310. in the projection formed above.
  • the placement and distribution of the first mask pattern 201 and the second mask pattern 310 formed in this embodiment can ensure that the target layer 100 is subsequently etched into multiple layers according to the first mask pattern 201 and the second mask pattern 310. Active area 111.
  • Step S250 Perform a first etching on the target layer based on the second mask pattern.
  • the target layer 100 is etched using the second mask pattern 310 as a mask, the portion of the target layer 100 exposed by the second mask pattern 310 is removed, and the remaining portion is etched.
  • the target layer 100 forms a plurality of active strips 110 extending along the first direction D1. In the direction perpendicular to the first direction D1, two adjacent active strips 110 are separated by the first shallow trench 120.
  • the etching process of the first etching can be dry etching or wet etching.
  • Step S260 Form a first isolation layer, and the first isolation layer fills the first shallow trench.
  • the second mask pattern 310 is removed through dry or wet etching, exposing the first mask pattern 201 and the top surface of the target layer 100 covered by the second mask pattern 310 .
  • the first isolation material can be deposited to form the first isolation layer 410 through any one of the atomic layer deposition process, the chemical vapor deposition process, or the physical vapor deposition process.
  • the layer 410 fills the first shallow trench 120 and covers the first mask pattern 201 and the top surface of the active strip 110 exposed by the first mask pattern 201 .
  • the first isolation material may include one of silicon oxide, silicon nitride, or silicon oxynitride.
  • the top surface of the first isolation layer 410 is planarized through a chemical mechanical polishing (CMP) process to expose the top surfaces of a plurality of first mask patterns 201 for subsequent alignment according to the first mask patterns 201
  • CMP chemical mechanical polishing
  • Step S270 Perform a second etching on the target layer based on the first mask pattern.
  • the following method may be used: remove the first mask pattern 201 and the portion covered by the first mask pattern 201
  • the active strip 110, the retained part of the active strip 110 forms a plurality of independently arranged active areas 111.
  • the active areas 111 extend along the first direction D1. In the first direction D1, two adjacent active areas 111 are separated by second shallow trenches 130 extending the pattern of the first mask pattern 201 into the active strip 110 .
  • Step S280 Fill the second shallow trench with the second isolation material to form a second isolation layer.
  • a second isolation material is deposited to form a second isolation layer 420 through any one of the atomic layer deposition process, the chemical vapor deposition process, or the physical vapor deposition process.
  • the second isolation layer 420 The second shallow trench 130 is filled and covers the first isolation layer 410 .
  • the second isolation material may include one of silicon oxide, silicon nitride, or silicon oxynitride, and the first isolation material and the second isolation material may include the same or different materials.
  • the first isolation layer 410 and the second isolation layer 420 located above the top surface of the target layer 100 are etched away, and the first isolation layer 410 and the second isolation layer 420 are retained.
  • a shallow trench isolation structure 400 is formed together, and the top surface of the shallow trench isolation structure 400 is flush with the top surface of the active area 111 .
  • the target layer is etched into multiple independently arranged active areas, which reduces the difficulty of forming the active areas and enables the formation of smaller active areas.
  • This embodiment improves the resolution accuracy of the photolithography process. The requirements are lower, the process difficulty and process cost are reduced, and it is suitable for forming highly integrated integrated circuits.
  • the shallow trench isolation structure is formed through two different deposition processes.
  • the two depositions can be filled with different materials according to the aspect ratios of the first shallow trench and the second shallow trench to ensure that the first shallow trench
  • Both the trench and the second shallow trench are filled with isolation materials, ensuring that the formed shallow trench isolation structure has high density, stable structure, good electrical isolation effect, can better avoid short circuits in the active area, and ensures the semiconductor structure It has good electrical properties and avoids the problem of difficulty in filling due to the complex shape of the trench between the active areas, resulting in partial areas of the trench being underfilled and reducing the isolation effect of the shallow trench isolation structure.
  • this embodiment adds the following steps:
  • Step S290 Form multiple word lines, each word line extends along the fourth direction and penetrates multiple active areas in its extending direction, and the multiple word lines are spaced apart from each other.
  • the second direction D2 and the third direction D3 intersect at the first included angle ⁇ 1, and the first direction D1 and the fourth direction D4 intersect at the second included angle ⁇ 2.
  • the relationship between the first included angle ⁇ 1 and the second included angle ⁇ 2 is as follows:
  • the first included angle is ⁇ 1
  • the second included angle is ⁇ 2.
  • a word line mask is first formed.
  • the word line mask covers part of the active area 111 and part of the top surface of the shallow trench isolation structure 400.
  • the word line mask Extending along the fourth direction D4.
  • the active area 111 and the shallow trench isolation structure 400 are etched according to the word line mask to form a word line trench.
  • the word line trench runs through the active area 111 along the fourth direction D4.
  • Each active area 111 is surrounded by two words. Line trench runs through.
  • word lines 500 are formed in the word line trenches.
  • Step S300 Form a bit line.
  • the bit line covers part of the top surface of the active area and part of the top surface of the isolation structure.
  • the bit line extends along a fifth direction, and the fifth direction is perpendicular to the fourth direction.
  • bit lines 600 are formed on the top surface of the active area 111 and the shallow trench isolation structure 400. Each bit line 600 extends along the fifth direction D5. The plurality of bit lines 600 are The fourth direction D4 is set at equal intervals.
  • the length and arrangement of the active areas formed in this embodiment can meet the process requirements of other electronic components.
  • the word lines and bit lines formed in the patterned target layer, the word lines, bit lines and active The setting of the area complies with the process requirements of DRAM memory.
  • this embodiment is an illustration of the implementation of the above step S220.
  • multiple initial mask patterns are formed on the top surface of the target layer, and the following steps are also included:
  • the arrangement direction of the first line structure 210 and the second line structure 220 to be formed is defined according to the target layer 100 . This step is performed before forming the cross structure 200 on the target layer 100 .
  • the process of DRAM memory usually includes the process of forming the word line 500 that runs through the active region 111 after the active region 111 is formed. .
  • the subsequently formed word line 500 extends along the fourth direction D4.
  • the first direction D1 and the fourth direction D4 intersect at a second included angle ⁇ 2.
  • the second included angle ⁇ 2 is an acute angle.
  • the second included angle ⁇ 2 may be 50° ⁇ 85°.
  • the second included angle ⁇ 2 may be 50°, 53°, 56°, 59°, 63°, 66°, 69°, 74°, 75°, 77°, 79°, 81°, 83° or 85° .
  • the coordinate system XOY is established using the fourth direction D4 in which the word line 500 is set in the subsequent process as the X-axis and the first direction D1 in which the active area 111 extends as the Y-axis.
  • the coordinate system XOY established in this embodiment is an oblique coordinate system.
  • the extension direction of the first line structure 210 and the extension direction of the second line structure 220 to be formed are determined according to the coordinate system XOY.
  • the extending direction of the first line structure 210 to be formed is defined as the second direction D2, and the extending direction of the second line structure 220 to be formed is defined as the third direction D3.
  • the second direction D2 and the third direction D3 intersect at a first included angle ⁇ 1.
  • the first included angle ⁇ 1 is 70° ⁇ 95°.
  • the first included angle may be 70°, 72°, 75°, 77°, 79°, 82°, 85°, 88°, 90°, 92° or 95°.
  • the second direction D2 and the first direction D1 intersect obliquely
  • the second direction D2 and the fourth direction D4 intersect obliquely.
  • the included angle between the second direction D2 and the fourth direction D4 is the third included angle ⁇ 3, and the third included angle ⁇ 3 is 30° ⁇ 50°.
  • the third included angle ⁇ 3 may be 30°, 32°, 34°, 36°, 37°, 39°, 41°, 45° or 50°.
  • the third direction D3 obliquely intersects the first direction D1
  • the third direction D3 obliquely intersects the fourth direction D4 .
  • the included angle between the third direction D3 and the fourth direction D4 is the fourth included angle ⁇ 4, and the fourth included angle ⁇ 4 is 30° to 50°.
  • the fourth included angle ⁇ 4 may be 30°, 32°, 34°, 36°, 37°, 39°, 41°, 45° or 50°.
  • the first included angle ⁇ 1 is equal to the sum of the third included angle ⁇ 3 and the fourth included angle ⁇ 4. For example, if the first included angle ⁇ 1 is 80 degrees, the third included angle ⁇ 3 is 30°, then the fourth included angle ⁇ 4 is 50°. In this embodiment, the third included angle ⁇ 3 and the fourth included angle ⁇ 4 are equal. For example, the first included angle ⁇ 1 is 82 degrees, the third included angle ⁇ 3 is 41°, and the fourth included angle ⁇ 4 is also 41°.
  • the relationship between the first included angle ⁇ 1 and the second included angle ⁇ 2 is as follows:
  • the extension direction of the first line structure to be formed and the arrangement direction and angle of the second line structure are defined according to the extension direction of the active area to be formed and the extension direction of the word line in the subsequent word line process, so as to Form a plurality of initial mask patterns and arrange them in multiple rows along the first direction to ensure that the projection of the subsequently formed second mask pattern on the target layer can be projected onto the target layer by the first mask pattern located in its extension direction.
  • the formed projection is divided into a plurality of independently arranged sub-patterns, and the arrangement of the active areas formed according to the first mask pattern and the second mask pattern meets the process requirements of the DRAM memory.
  • this embodiment provides a semiconductor structure.
  • the semiconductor structure of this embodiment is formed according to the manufacturing method of the semiconductor structure in the above embodiment.
  • the semiconductor structure of this embodiment can be a memory chip, and the memory chip can be used in dynamic random access memory (Dynamic Random Access Memory, DRAM).
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • flash memory flash EPROM
  • ferroelectric memory Feroelectric Random-Access Memory
  • MRAM Magnetic Random
  • PRAM Phase change Random-Access Memory
  • the target layer is etched twice using the second mask pattern and the first mask pattern as masks respectively, and the target layer is etched to form a more fine shape.
  • Complex and higher-density repeating structures reduce the difficulty of forming repeating structures and are conducive to the formation of highly integrated integrated circuits.

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Abstract

本公开提供一种半导体结构的制作方法及半导体结构，涉及半导体技术领域，半导体结构的制作方法包括，提供目标层；在目标层的顶面形成多个第一掩膜图形；在目标层的上方形成多个第二掩膜图形，每个第二掩膜图形至少覆盖位于其延伸方向上的每个第一掩膜图形的部分顶面以及目标层的部分顶面；基于第二掩膜图形对目标层进行第一刻蚀；移除第二掩膜图形；基于第一掩膜图形对目标层进行第二刻蚀。在本公开中，通过第二掩膜图形和第一掩膜图形分别对目标层进行两次刻蚀处理，刻蚀形成更加精细复杂、密度更高的重复结构，减小了形成重复结构的难度，利于形成高集成度的集成电路。

Description

半导体结构的制作方法及半导体结构
本公开基于申请号为202210385869.7、申请日为2022年04月13日、申请名称为“半导体结构的制作方法及半导体结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及但不限于一种半导体结构的制作方法及半导体结构。
背景技术
随着集成电路(Integrated Circuit，IC)发展的不断推进，集成电路中的电子元件的特征尺寸不断减小、集成密度不断提高，以使集成电路具有更高的集成度。然而，目前电子元件的特征尺寸已经减小到了主流光刻技术所能达到的尺寸物理极限，光刻技术的分辨率难以满足集成电路的制造需求，集成电路的制程工艺面临巨大挑战。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供了一种半导体结构的制作方法及半导体结构。
本公开的第一方面提供了一种半导体结构的制作方法，所述方法包括：
提供目标层；
在所述目标层的顶面形成多个第一掩膜图形，在第一方向上任意相邻的两个所述第一掩膜图形隔开设置；
在所述目标层的上方形成多个第二掩膜图形，每个所述第二掩膜图形沿所述第一方向延伸，且所述第二掩膜图形彼此隔开设置，每个所述第二掩膜图形至少覆盖位于其延伸方向上的每个所述第一掩膜图形的部分顶面以及所述目标层的部分顶面；
基于所述第二掩膜图形对所述目标层进行第一刻蚀；
基于所述第一掩膜图形对所述目标层进行第二刻蚀。
根据本公开的一些实施例，在所述目标层的顶面形成多个第一掩膜图形，包括：
在所述目标层上形成交叉结构，所述交叉结构包括重叠区域；
去除部分所述交叉结构，保留部分所述重叠区域，被保留的所述重叠区域形成多个初始掩膜图形；
去除每个初始掩膜图形的部分结构，每个所述初始掩膜图形被保留的部分结构形成所述第一掩膜图形。
根据本公开的一些实施例，在所述目标层上形成交叉结构，包括：
形成多个第一线结构，每个所述第一线结构沿第二方向延伸，在垂直于所述第二方向的方向上，多个所述第一线结构隔开设置，所述第一方向与所述第二方向倾斜相交；
形成多个第二线结构，多条所述第二线结构位于所述第一线结构的上方，所述第二线结构沿第三方向延伸，在垂直于第三方向的方向上，多个所述第二线结构隔开设置，所述第一方向与所述第三方向倾斜相交；
多个所述第一线结构和多个所述第二线结构共同形成所述交叉结构，多个所述第一线结构和多个所述第二线结构的重叠部分形成所述重叠区域。
根据本公开的一些实施例，在所述目标层的上方形成多条第二掩膜图形，包括：
形成第二掩膜材料层，所述第二掩膜材料层覆盖所述初始掩膜图形以及所述目标层暴露的顶面；
去除部分所述第二掩膜材料层，形成多个沿所述第一方向延伸的所述第二掩膜图形，在垂直于所述第一方向的方向上，任意相邻的两个所述第二掩膜图形被第一沟槽隔开。
根据本公开的一些实施例，每个所述第二掩膜图形在所述目标层上形成的投影被位于其延伸方向上的所述第一掩膜图形在所述目标层上形成的投影划分成多个独立设置的子图形。
根据本公开的一些实施例，基于所述第二掩膜图形对所述目标层进行第一刻蚀，包括：
去除所述第二掩膜图形暴露出的部分所述目标层，刻蚀被保留的部分所述目标层形成多条沿所述第一方向延伸的有源条，在垂直于所述第一方向的方向上，相邻的两条所述有源条被第一浅沟槽隔开。
根据本公开的一些实施例，所述方法还包括：
沉积第一隔离材料形成第一隔离层，所述第一隔离层填充所述第一浅沟槽并覆盖所述第一掩膜图形以及被所述第一掩膜图形暴露出的所述有源条的顶面。
根据本公开的一些实施例，所述方法还包括：
平坦化处理所述第一隔离层的顶面，暴露出多个所述第一掩膜图形的顶面。
根据本公开的一些实施例，基于所述第一掩膜图形对所述目标层进行第二刻蚀，包括：
去除所述第一掩膜图形以及被所述第一掩膜图形覆盖的部分所述有源条，被保留的部分所述有源条形成多个独立设置的有源区，所述有源区沿所述第一方向延伸，在所述第一方向上，相邻的两个所述有源区被第二浅沟槽隔开。
根据本公开的一些实施例，所述方法还包括：
于所述第二浅沟槽中填充第二隔离材料，形成第二隔离层。
根据本公开的一些实施例，所述方法还包括：
去除所述目标层的顶面以上的所述第一隔离层和所述第二隔离层，被保留的所述第一隔离层和所述第二隔离层共同形成浅沟槽隔离结构。
根据本公开的一些实施例，所述第一隔离材料和所述第二隔离材料包括相同或不同的材料。
根据本公开的一些实施例，所述方法，还包括：
形成多条字线，每条所述字线沿第四方向延伸并贯穿位于其延伸方向的多个所述有源区，且多条所述字线彼此隔开设置。
根据本公开的一些实施例，所述第二方向和所述第三方向以第一夹角交叉，所述第一方向和所述第四方向以第二夹角相交，所述第一夹角和所述第二夹角的关系如下：
Figure PCTCN2022097671-appb-000001
其中，所述第一夹角为α1，所述第二夹角为α2。
本公开的第二方面提供了一种半导体结构，所述半导体结构根据上述的半导体结构的制作方法制作得到。
在阅读并理解了附图和详细描述后，可以明白其它方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类 似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图2是根据一示例性实施例示出的半导体结构的制作方法的流程图。
图3是根据一示例性实施例示出的在目标层上形成第一线结构的示意图。
图4是根据一示例性实施例示出的形成第一层结构的示意图。
图5是根据一示例性实施例示出的形成第二介质层的示意图。
图6是根据一示例性实施例示出的形成第二线结构的示意图。
图7是根据一示例性实施例示出的形成的交叉结构的示意图。
图8是根据一示例性实施例示出的形成的交叉结构的俯视图。
图9是根据一示例性实施例示出的根据第二线结构刻蚀第一层结构的俯视图。
图10是根据一示例性实施例示出的形成初始掩膜图形的示意图。
图11是根据一示例性实施例示出的形成第二掩膜材料层的示意图。
图12是根据一示例性实施例示出的第三光罩和初始掩膜图形的俯视图。
图13是根据一示例性实施例示出的形成第二掩膜图形的示意图。
图14是根据一示例性实施例示出的第二掩膜图形和第一掩膜图形的俯视图。
图15是根据一示例性实施例示出的对目标层进行第一刻蚀的示意图。
图16是根据一示例性实施例示出的形成第一隔离层的示意图。
图17是根据一示例性实施例示出的对目标层进行第二刻蚀的示意图。
图18是根据一示例性实施例示出的形成第二隔离层的示意图。
图19是根据一示例性实施例示出的形成隔离结构的示意图。
图20是根据一示例性实施例示出的有源区的俯视图。
图21是根据一示例性实施例示出的形成字线和位线的俯视图。
图22是根据一示例性实施例示出的构建的坐标系的示意图。
附图标记：
100、目标层；110、有源条；111、有源区；120、第一浅沟槽；130、第二浅沟槽；200、交叉结构；201、第一掩膜图形；210、第一线结构；211、初始掩膜图形；220、第二线结构；221、第二介质层；230、辅助层；240、第一层结构；250、重叠区域；260、第三光罩；300、第二掩膜材料层；310、第二掩膜图形；311、子图形；320、第一沟槽；400、浅沟槽隔离结构；410、第一隔离层；420、第二隔离层；500、字线；600、位线；
D1、第一方向；D2、第二方向；D3、第三方向；D4、第四方向；α1、第一夹角；α2、第二夹角；α3、第三夹角；α4、第四夹角。
具体实施方式
下面将结合本公开实施例中的附图，对公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开示例性的实施例中提供了一种半导体结构的制作方法，分别以第二掩膜图形和第一掩膜图形作为掩膜对目标层进行两次刻蚀处理，能够在目标层中形成形状更加精细复杂、密度更高的重复结构，本实施例的制作方法减小了形成重复结构的难度，利于形成高集成度的集成电路。
如图1所示，图1示出了根据本公开一示例性的实施例提供的一种半导体结构的制作 方法的流程图，本公开示例性的实施例中提供了一种半导体结构的制作方法，包括如下的步骤。
步骤S110：提供目标层。
参照图13，目标层100是指需要进行图案化的待刻蚀材料层，目标层100可以是用于形成半导体元件的任何构造。
目标层100可以是半导体衬底，半导体衬底的材料可以包括硅(Si)、锗(Ge)、硅锗(GeSi)或碳化硅(SiC)；也可以是绝缘体上硅(SOI)或者绝缘体上锗(GOI)；或者还可以包括其它的材料，例如砷化镓等Ⅲ-Ⅴ族化合物。半导体衬底中根据需要可以掺杂部分杂质离子，杂质离子可以为N型杂质离子或P型杂质离子。
目标层100还可以是用于形成半导体元件的材料层，如介质层或金属层。示例性的，材料层可以为无定形碳层、氧化物层、氮化物层、铜层、钨层、铝层等，不限于此。
步骤S120：在目标层的顶面形成多个第一掩膜图形，在第一方向上任意相邻的两个第一掩膜图形隔开设置。
参照图13、图14，在本实施例中，多个第一掩膜图形201独立设置在目标层100的顶面，在第一方向D1上，多个第一掩膜图形201成多排，第一方向上D1任意相邻的两个第一掩膜图形201隔开设置。
步骤S130：在目标层的上方形成多个第二掩膜图形，每个第二掩膜图形沿第一方向延伸，且第二掩膜图形彼此隔开设置，每个第二掩膜图形至少覆盖位于其延伸方向上的每个第一掩膜图形的部分顶面以及目标层的部分顶面。
参照图13、图14，本实施例形成的每个第二掩膜图形310对应设置在一排第一掩膜图形201上，并且每个第二掩膜图形310对应填充位于同一排的相邻的两个第一掩膜图形201之间的部分区域。
在本实施例中，每个第二掩膜图形310在目标层100上形成的投影被位于其延伸方向上的第一掩膜图形201在目标层100上形成的投影划分成多个独立设置的子图形311。在其它实施例中，第一掩膜图形201、第二掩膜图形310的形状和排布密度根据待形成的半导体结构进行设置。
步骤S140：基于第二掩膜图形对目标层进行第一刻蚀。
参照图13、图14、图15，本实施例中，以第二掩膜图形310为掩膜刻蚀目标层100，去除第二掩膜图形310暴露出的部分目标层100，将第二掩膜图形310的图案延伸到目标层100中，被保留的目标层100形成多个独立设置的结构。其中，第一刻蚀的刻蚀工艺可以选用干法刻蚀或湿法刻蚀。
步骤S150：基于第一掩膜图形对目标层进行第二刻蚀。
首先，通过干法或湿法刻蚀，移除第二掩膜图形310，暴露出第一掩膜图形201以及被第二掩膜图形310覆盖的目标层100的顶面。
然后，参照17、图20，刻蚀去除第一掩膜图形201以及被第一掩膜图形201覆盖的部分目标层100，以将第一掩膜图形201的图案延伸到目标层100中，将被刻蚀保留的目标层100划分成多个独立设置的子结构。
本实施例的半导体结构的制作方法，在目标层上方形成第一掩膜图形和第二掩膜图形两层掩膜，并根据第二掩膜图形和第一掩膜图形先后对目标层进行两次刻蚀，在目标层中形成高密度的重复结构，本实施例的制作方法与直接通过光刻工艺形成刻蚀掩膜的方案相比，对光刻工艺的分辨率精度要求更低，降低了工艺难度和工艺成本。
图2示出了根据本公开一示例性的实施例提供的一种半导体结构的制作方法的流程图，图3-图22为本实施例的半导体结构的制作方法的各个阶段的示意图，下面结合图3-图22对本实施例的半导体结构的制作方法进行介绍。
本公开示例性的实施例中提供了一种半导体结构的制作方法，本实施例对半导体结构不作限制，下面将半导体结构为动态随机存储器(Dynamic Random Access Memory，DRAM)为例进行介绍，以在半导体结构中形成有源区对本实施例进行说明，但本实施例并不以此为限，本实施例中的半导体结构还可以为其它的结构。
本公开示例性的实施例中提供了一种半导体结构的制作方法，如图2所示，包括如下的步骤：
步骤S210：提供目标层。
如图3所示，在本实施例中，目标层100是半导体衬底，半导体衬底的材料和上述实施例中半导体衬底的材料相同。
步骤S220：在目标层的顶面形成多个初始掩膜图形，在第一方向上任意相邻的两个初始掩膜图形隔开设置。
在目标层100的顶面形成多个初始掩膜图形211，可以采用以下方法：
步骤S221：在目标层上形成交叉结构，交叉结构包括重叠区域。
首先，如图3所示，在目标层100的顶面上形成多个第一线结构210，每个第一线结构210沿第二方向D2延伸，在垂直于第二方向D2的方向上，多个第一线结构210隔开设置，第一方向D1与第二方向D2倾斜相交。
可以通过化学气相沉积工艺或物理气相沉积工艺沉积介质材料，在目标层100的顶面形成第一介质层(图中未示出)，其中，第一介质层的材料可以包括氮化硅和/或氧化硅。
参照图8，在第一介质层的顶面形成第一光罩(图中未示出)，根据第一光罩刻蚀去除部分第一介质层，被保留的第一介质层形成多条独立设置的第一线结构210，每个第一线结构210沿第二方向D2延伸，在垂直于第二方向D2的方向上，相邻的两个第一线结构210隔开设置。
然后，如图4所示，可以通过原子层沉积工艺(Atomic Layer Deposition，ALD)或化学气相沉积工艺(Chemical Vapor Deposition，CVD)沉积辅助材料，辅助材料形成辅助层230，辅助层230覆盖第一线结构210并填充相邻的第一线结构210之间的沟槽，辅助层230和第一线结构210共同形成第一层结构240。然后，研磨处理第一层结构240将第一层结构240的顶面研磨成平面，以便后续在第一层结构240的顶面形成第二线结构220。其中，辅助层230的材料可以包括氮化硅、氮氧化硅等，但不限于此。在一些实施例中还可以通过其它工艺形成辅助层230，例如可以通过旋涂工艺旋涂辅助材料形成辅助层230，辅助层230的材料可以为旋涂碳(Spin on Carbon，SOC)。
接着，如图5所示，可以通过化学气相沉积工艺或物理气相沉积工艺沉积介质材料，在目标层100的顶面形成第二介质层221，其中，第二介质层221的材料可以包括氮化硅和/或氧化硅。
如图6、图7、图8所示，在第二介质层221的顶面形成第二光罩(图中未示出)，根据第二光罩刻蚀去除部分第二介质层221，被保留的第二介质层221形成多个第二线结构220，多个第二线结构220位于第一线结构210的上方，多个第二线结构220独立设置，每个第二线结构220沿第三方向D3延伸，在垂直于第三方向D3的方向上，多个第二线结构220隔开设置，第一方向D1与第三方向D3倾斜相交。
如图7、图8所示，第一线结构210和第二线结构220在目标层100的上方空间形成交叉结构200，且第一线结构210和第二线结构220在目标层100的上方空间存在重叠部分，其重叠部分即为交叉结构200的重叠区域250。
步骤S222：去除部分交叉结构，保留部分重叠区域，被保留的重叠区域形成多个初始掩膜图形。
去除部分交叉结构200，可以采用以下方法：
如图9所示，参照图6，根据第二线结构220刻蚀第一层结构240，去除被第二线结 构220暴露出的辅助层230和第一线结构210，将第二线结构220的图案转移到第一层结构240中，被保留的第一层结构240包括部分第一线结构210以及部分辅助层230，其中，被保留的部分第一线结构210与交叉结构200的重叠区域250对应。
然后，如图10所示，参照图6、图9，通过干法刻蚀或湿法刻蚀全部的第二线结构220，暴露出被保留的第一层结构240。可以通过干法或湿法刻蚀去除被保留的第一层结构240中的辅助层230，被保留的第一线结构210形成多个相互独立的初始掩膜图形211，本实施例形成的多个初始掩膜图形211沿第一方向D1排成多排。
本实施例中，在目标层100上方形成层叠设置的第一线结构210和第二线结构220，通过刻蚀第二线结构220和第一线结构210的部分结构，仅保留第一线结构210和第二线结构220的重叠区域，形成初始掩膜图形211的特征尺寸小，根据本实施例的形成的初始掩膜图形211形成的第一掩膜图形201(参照图14)的尺寸更小，在后续的第二刻蚀制程中，可以根据第一掩膜图形201将目标层100刻蚀形成重复密度更大、尺寸更小的重复结构。
步骤S230：形成第二掩膜材料层，第二掩膜材料层覆盖初始掩膜图形以及目标层暴露的顶面。
如图11所示，参照图10，可以通过化学气相沉积工艺(Chemical Vapor Deposition，CVD)或物理气相沉积工艺(Physical Vapor Deposition，PVD)沉积第二掩膜材料，形成第二掩膜材料层300，第二掩膜材料层300覆盖初始掩膜图形211以及目标层100暴露的顶面。
步骤S240：去除部分第二掩膜材料层，形成多个沿第一方向延伸的第二掩膜图形，同时去除每个初始掩膜图形的部分结构，每个初始掩膜图形被保留的部分结构形成第一掩膜图形。
如图12所示，参照图11，在第二掩膜材料层300顶面形成第三光罩260，根据第三光罩260刻蚀第二掩膜材料层300以及初始掩膜图形211。如图13、图14所示，被保留的第二掩膜材料层300形成多个沿第一方向D1延伸的第二掩膜图形310，每个初始掩膜图形211被保留的部分结构形成第一掩膜图形201，在垂直于第一方向D1的方向上，任意相邻的两个第二掩膜图形310被第一沟槽320隔开，第一沟槽320暴露出目标层100的部分顶面。
如图14所示，每个第二掩膜图形310在目标层100上形成的投影被位于其延伸方向上的第一掩膜图形201在目标层100上形成的投影划分成多个独立设置的子图形311。以便后续根据第一掩膜图形201和第二掩膜图形310对目标层100进行刻蚀，形成多个独立设置的有源区111。
在本实施例中，多个第一掩膜图形201和多个第二掩膜图形310同时形成，每个第二掩膜图形310在目标层100上形成的投影被位于其延伸方向上的第一掩膜图形201在目标层100上形成的投影划分成多个独立设置的子图形311，且第一掩膜图形201在目标层100上形成的投影位于第二掩膜图形310在目标层100上形成的投影中。本实施例形成的第一掩膜图形201和第二掩膜图形310的设置位置和分布，能够确保后续根据第一掩膜图形201和第二掩膜图形310将目标层100刻蚀成多个有源区111。
步骤S250：基于第二掩膜图形对目标层进行第一刻蚀。
如图15，参照图113，本实施例中，以第二掩膜图形310为掩膜刻蚀目标层100，去除第二掩膜图形310暴露出的部分目标层100，刻蚀被保留的部分目标层100形成多条沿第一方向D1延伸的有源条110，在垂直于第一方向D1的方向上，相邻的两条有源条110被第一浅沟槽120隔开。其中，第一刻蚀的刻蚀工艺可以选用干法刻蚀或湿法刻蚀。
步骤S260：形成第一隔离层，第一隔离层填充第一浅沟槽。
参照图15，通过干法或湿法刻蚀，移除第二掩膜图形310，暴露出第一掩膜图形201 以及被第二掩膜图形310覆盖的目标层100的顶面。
如图16所示，本实施例中，可以通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺中的任一种沉积工艺，沉积第一隔离材料形成第一隔离层410，第一隔离层410填充第一浅沟槽120并覆盖第一掩膜图形201以及被第一掩膜图形201暴露出的有源条110的顶面。第一隔离材料可以包括氧化硅、氮化硅或氮氧化硅中的一种。然后，通过化学机械研磨(Chemical Mechanical Polish，CMP)工艺平坦化处理第一隔离层410的顶面，暴露出多个第一掩膜图形201的顶面，以便后续根据第一掩膜图形201对有源条110进行第二刻蚀。
步骤S270：基于第一掩膜图形对目标层进行第二刻蚀。
如图17所示，参照图16，基于第一掩膜图形201对目标层100进行第二刻蚀，可以采用以下方法：去除第一掩膜图形201以及被第一掩膜图形201覆盖的部分有源条110，被保留的部分有源条110形成多个独立设置的有源区111，有源区111沿第一方向D1延伸，在第一方向D1上，相邻的两个有源区111被第二浅沟槽130隔开，第二浅沟槽130将第一掩膜图形201的图案延伸到有源条110中。
步骤S280：于第二浅沟槽中填充第二隔离材料，形成第二隔离层。
如图18所示，参照图17，通过原子层沉积工艺、化学气相沉积工艺或物理气相沉积工艺中的任一种沉积工艺，沉积第二隔离材料形成第二隔离层420，第二隔离层420填充第二浅沟槽130并覆盖第一隔离层410。第二隔离材料可以包括氧化硅、氮化硅或氮氧化硅中的一种，第一隔离材料和第二隔离材料包括相同或不同的材料。
然后，如图19所示，参照图18，刻蚀去除位于目标层100的顶面以上的第一隔离层410以及第二隔离层420，被保留的第一隔离层410和第二隔离层420共同形成浅沟槽隔离结构400，浅沟槽隔离结构400的顶面和有源区111的顶面平齐。
本实施例中，将目标层刻蚀成多个独立设置的有源区，降低了形成有源区的难度，能够形成尺寸更小的有源区，本实施例对光刻工艺的分辨率精度要求更低，降低了工艺难度和工艺成本，适用于形成高集成度的集成电路。
本实施例中，浅沟槽隔离结构通过两次不同的沉积工艺形成，两次沉积可根据第一浅沟槽和第二浅沟槽的深宽比选用不同的材料填充，确保第一浅沟槽和第二浅沟槽均被隔离材料填满，确保形成的浅沟槽隔离结构的致密度高、结构稳定，具有良好的电隔离效果，能够更好地避免有源区短路，确保半导体结构具有良好的电性能，避免有源区之间的沟槽形状复杂导致填充困难，导致沟槽的部分区域填充不满，降低浅沟槽隔离结构的隔离效果的问题。
根据一个示例性实施例，如图2所示，本实施例相对上述实施例，又增加了以下步骤：
步骤S290：形成多条字线，每条字线沿第四方向延伸并贯穿位于其延伸方向的多个有源区，且多条字线彼此隔开设置。
第二方向D2和第三方向D3以第一夹角α1交叉，第一方向D1和第四方向D4以第二夹角α2相交，第一夹角α1和第二夹角α2的关系如下：
Figure PCTCN2022097671-appb-000002
其中，第一夹角为α1，第二夹角为α2。
如图21所示，参照图20，在形成字线500时，首先形成字线掩膜，字线掩膜覆盖部分有源区111以及部分浅沟槽隔离结构400的顶面，字线掩膜沿第四方向D4延伸。根据字线掩膜刻蚀有源区111和浅沟槽隔离结构400以形成字线沟槽，字线沟槽沿第四方向D4贯穿有源区111，每个有源区111被两条字线沟槽贯穿。然后，在字线沟槽中形成字线500。
步骤S300：形成位线，位线覆盖部分有源区的顶面和部分隔离结构的顶面，位线沿第五方向延伸，第五方向和第四方向垂直。
如图21所示，参照图20，在有源区111和浅沟槽隔离结构400的顶面形成多条位线600，每条位线600沿第五方向D5延伸，多条位线600在第四方向D4上等间隔设置。
本实施例形成的有源区的长度和排布方式能够满足其它电子元件的制程需求，本实施例在图案化后的目标层中形成的字线和位线，字线、位线和有源区的设置符合DRAM存储器的制程要求。
根据一个示例性实施例，本实施例是对上述步骤S220的实现方式的说明，在实施过程中，在目标层的顶面形成多个初始掩膜图形，还包括以下步骤：
根据目标层100定义待形成的第一线结构210和第二线结构220的设置方向。本步骤在目标层100上形成交叉结构200之前执行。
由于本示例性实施例以形成有源区111的过程进行说明，在半导体领域中，DRAM存储器的制程中，在形成有源区111之后，通常包括形成贯穿有源区111的字线500的制程。
在本实施例中，参照图21，后续形成的字线500沿第四方向D4延伸。在平行于目标层100的顶面的平面，第一方向D1和第四方向D4以第二夹角α2相交。在本实施例中，第二夹角α2为锐角。示例性的，第二夹角α2可以为50°～85°。例如，第二夹角α2可以为50°、53°、56°、59°、63°、66°、69°、74°、75°、77°、79°、81°、83°或85°。
在本步骤中，以后续制程中字线500设置的第四方向D4为X轴，以有源区111延伸的第一方向D1为Y轴，建立坐标系XOY。本实施例建立的坐标系XOY为斜坐标系。然后，根据坐标系XOY确定待形成的第一线结构210的延伸方向和第二线结构220的延伸方向。
在本实施例中，将待形成的第一线结构210的延伸方向定义为第二方向D2，将待形成的第二线结构220的延伸方向定义为第三方向D3。其中，第二方向D2与第三方向D3以第一夹角α1相交。在本实施例中，第一夹角α1为70°～95°。例如，第一夹角可以为70°、72°、75°、77°、79°、82°、85、°88°、90°、92°或95°。如图22所示，第二方向D2和第一方向D1倾斜相交，且第二方向D2与第四方向D4倾斜相交。第二方向D2和第四方向D4之间的夹角为第三夹角α3，第三夹角α3为30°～50°。示例性的，第三夹角α3可以为30°、32°、34°、36°、37°、39°、41°、45°或50°。如图22所示，第三方向D3和第一方向D1倾斜相交，且第三方向D3与第四方向D4倾斜相交。第三方向D3和第四方向D4之间的夹角为第四夹角α4，第四夹角α4为30°～50°。示例性的，第四夹角α4可以为30°、32°、34°、36°、37°、39°、41°、45°或50°。
第一夹角α1等于第三夹角α3和第四夹角α4之和。例如，第一夹角α1为80度，第三夹角α3为30°，则第四夹角α4为50°。本实施例中，第三夹角α3和第四夹角α4的角度相等。例如，第一夹角α1为82度，第三夹角α3为41°，第四夹角α4也为41°。同时，第一夹角α1和第二夹角α2的关系如下：
Figure PCTCN2022097671-appb-000003
本实施例中，根据待形成的有源区的延伸方向和后续的字线制程中字线的延伸方向，定义待形成的第一线结构的延伸方向和第二线结构的设置方向和夹角，以使形成多个初始掩膜图形沿第一方向排成多排，确保后续形成的第二掩膜图形在目标层上形成的投影能够被位于其延伸方向上的第一掩膜图形在目标层上形成的投影划分成多个独立设置的子图形，根据第一掩膜图形、第二掩膜图形形成的有源区的排布满足DRAM存储器的制程要 求。
根据一个示例性实施例，本实施例提供了一种半导体结构，本实施例的半导体结构根据上述实施例中半导体结构的制作方法形成。本实施例的半导体结构可以为存储芯片，存储芯片可以用在动态随机存储器(Dynamic Random Access Memory，DRAM)中。然而，也可以应用于静态随机存取存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random-Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random-Access Memory，MRAM)、相变随机存储器(Phase change Random-Access Memory，PRAM)等。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
在本公开的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
可以理解的是，本公开所使用的术语“第一”、“第二”等可在本公开中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的半导体结构的制备方法及半导体结构中，分别以第二掩膜图形和第一掩膜图形为掩膜对目标层进行两次刻蚀，将目标层刻蚀形成更加精细复杂、密度更高的重复结构，减小了形成重复结构的难度，利于形成高集成度的集成电路。

Claims (15)

  1. 一种半导体结构的制作方法，所述方法包括：
    提供目标层；
    在所述目标层的顶面形成多个第一掩膜图形，在第一方向上任意相邻的两个所述第一掩膜图形隔开设置；
    在所述目标层的上方形成多个第二掩膜图形，每个所述第二掩膜图形沿所述第一方向延伸，且所述第二掩膜图形彼此隔开设置，每个所述第二掩膜图形至少覆盖位于其延伸方向上的每个所述第一掩膜图形的部分顶面以及所述目标层的部分顶面；
    基于所述第二掩膜图形对所述目标层进行第一刻蚀；
    基于所述第一掩膜图形对所述目标层进行第二刻蚀。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，在所述目标层的顶面形成多个第一掩膜图形，包括：
    在所述目标层上形成交叉结构，所述交叉结构包括重叠区域；
    去除部分所述交叉结构，保留部分所述重叠区域，被保留的所述重叠区域形成多个初始掩膜图形；
    去除每个初始掩膜图形的部分结构，每个所述初始掩膜图形被保留的部分结构形成所述第一掩膜图形。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，在所述目标层上形成交叉结构，包括：
    形成多个第一线结构，每个所述第一线结构沿第二方向延伸，在垂直于所述第二方向的方向上，多个所述第一线结构隔开设置，所述第一方向与所述第二方向倾斜相交；
    形成多个第二线结构，多条所述第二线结构位于所述第一线结构的上方，所述第二线结构沿第三方向延伸，在垂直于第三方向的方向上，多个所述第二线结构隔开设置，所述第一方向与所述第三方向倾斜相交；
    多个所述第一线结构和多个所述第二线结构共同形成所述交叉结构，多个所述第一线结构和多个所述第二线结构的重叠部分形成所述重叠区域。
  4. 根据权利要求2所述的半导体结构的制作方法，其中，在所述目标层的上方形成多条第二掩膜图形，包括：
    形成第二掩膜材料层，所述第二掩膜材料层覆盖所述初始掩膜图形以及所述目标层暴露的顶面；
    去除部分所述第二掩膜材料层，形成多个沿所述第一方向延伸的所述第二掩膜图形，在垂直于所述第一方向的方向上，任意相邻的两个所述第二掩膜图形被第一沟槽隔开。
  5. 根据权利要求3所述的半导体结构的制作方法，其特征在于，每个所述第二掩膜图形在所述目标层上形成的投影被位于其延伸方向上的所述第一掩膜图形在所述目标层上形成的投影划分成多个独立设置的子图形。
  6. 根据权利要求5所述的半导体结构的制作方法，其中，基于所述第二掩膜图形对所述目标层进行第一刻蚀，包括：
    去除所述第二掩膜图形暴露出的部分所述目标层，刻蚀被保留的部分所述目标层形成多条沿所述第一方向延伸的有源条，在垂直于所述第一方向的方向上，相邻的两条所述有源条被第一浅沟槽隔开。
  7. 根据权利要求6所述的半导体结构的制作方法，所述方法还包括：
    沉积第一隔离材料形成第一隔离层，所述第一隔离层填充所述第一浅沟槽并覆盖所述第一掩膜图形以及被所述第一掩膜图形暴露出的所述有源条的顶面。
  8. 根据权利要求7所述的半导体结构的制作方法，所述方法还包括：
    平坦化处理所述第一隔离层的顶面，暴露出多个所述第一掩膜图形的顶面。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，基于所述第一掩膜图形对所述目标层进行第二刻蚀，包括：
    去除所述第一掩膜图形以及被所述第一掩膜图形覆盖的部分所述有源条，被保留的部分所述有源条形成多个独立设置的有源区，所述有源区沿所述第一方向延伸，在所述第一方向上，相邻的两个所述有源区被第二浅沟槽隔开。
  10. 根据权利要求9所述的半导体结构的制作方法，所述方法还包括：
    于所述第二浅沟槽中填充第二隔离材料，形成第二隔离层。
  11. 根据权利要求10所述的半导体结构的制作方法，所述方法还包括：
    去除所述目标层的顶面以上的所述第一隔离层和所述第二隔离层，被保留的所述第一隔离层和所述第二隔离层共同形成浅沟槽隔离结构。
  12. 根据权利要求10所述的半导体结构的制作方法，其中，所述第一隔离材料和所述第二隔离材料包括相同或不同的材料。
  13. 根据权利要求9所述的半导体结构的制作方法，所述方法，还包括：
    形成多条字线，每条所述字线沿第四方向延伸并贯穿位于其延伸方向的多个所述有源区，且多条所述字线彼此隔开设置。
  14. 根据权利要求13所述的半导体结构的制作方法，其中，所述第二方向和所述第三方向以第一夹角交叉，所述第一方向和所述第四方向以第二夹角相交，所述第一夹角和所述第二夹角的关系如下：
    Figure PCTCN2022097671-appb-100001
    其中，所述第一夹角为α1，所述第二夹角为α2。
  15. 一种半导体结构，所述半导体结构根据上述权利要求1～14中任一项所述的半导体结构的制作方法制作得到。
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