WO2024084621A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024084621A1
WO2024084621A1 PCT/JP2022/038906 JP2022038906W WO2024084621A1 WO 2024084621 A1 WO2024084621 A1 WO 2024084621A1 JP 2022038906 W JP2022038906 W JP 2022038906W WO 2024084621 A1 WO2024084621 A1 WO 2024084621A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
substrate
drain pad
wire
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/038906
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English (en)
French (fr)
Japanese (ja)
Inventor
翼 角野
敏 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to CN202280097058.5A priority Critical patent/CN120019727A/zh
Priority to US18/861,500 priority patent/US20250351479A1/en
Priority to JP2024551126A priority patent/JP7782714B2/ja
Priority to PCT/JP2022/038906 priority patent/WO2024084621A1/ja
Publication of WO2024084621A1 publication Critical patent/WO2024084621A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/483—Interconnections over air gaps, e.g. air bridges
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view

Definitions

  • This disclosure relates to a semiconductor device.
  • a source pad and a drain pad are formed on the front side of a substrate, and a back electrode is formed on the back side of the substrate.
  • the back electrode and the source pad are connected by a via hole.
  • the drain pad of a field effect transistor used in a high-output amplifier is formed large so that multiple wires can be inserted to allow a large current to flow.
  • a large parasitic capacitance is formed between this drain pad on the front side and the n-type semiconductor substrate or back electrode on the back side.
  • a technology has been proposed in which the substrate is etched from the back side to form a cavity below the drain pad (see, for example, Patent Document 1).
  • This disclosure has been made to solve the problems described above, and its purpose is to obtain a semiconductor device that can withstand the impact of wire bonds while reducing parasitic capacitance.
  • the semiconductor device comprises a substrate, an epitaxial layer formed on the substrate, a field effect transistor formed on the epitaxial layer, a drain pad formed on the epitaxial layer and connected to the drain electrode of the field effect transistor, a back electrode formed on the back surface of the substrate and connected to the source electrode of the field effect transistor, and a wire bonded to the drain pad, and is characterized in that a cavity is formed in the substrate directly below the drain pad, and the cavity is not formed directly below the bonding portion of the wire.
  • a cavity is formed in the substrate directly below the drain pad. Therefore, the parasitic capacitance between the drain pad and the back electrode can be reduced without reducing the area of the drain pad.
  • the cavity is not formed directly below the wire bonding portion. Therefore, it can withstand the impact of the wire bond.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment
  • FIG. 2 is a cross-sectional view taken along line I-II of FIG.
  • FIG. 2 is a cross-sectional view taken along line III-IV in FIG. 2 is a cross-sectional view taken along line V-VI of FIG. 1.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to a first comparative example.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a second comparative example.
  • FIG. 11 is a plan view showing a semiconductor device according to a second embodiment.
  • FIG. 8 is a cross-sectional view taken along line I-II of FIG.
  • FIG. 11 is a plan view showing a semiconductor device according to a third embodiment.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment.
  • FIG. 13 is a cross-sectional view showing a semiconductor device according to a fifth embodiment.
  • Fig. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • Fig. 2 is a cross-sectional view taken along line I-II in Fig. 1.
  • Fig. 3 is a cross-sectional view taken along line III-IV in Fig. 1.
  • Fig. 4 is a cross-sectional view taken along line V-VI in Fig. 1.
  • the substrate 1 is a semi-insulating substrate made of GaAs, SiC, InP, sapphire, GaN, diamond, or the like.
  • the material of the epitaxial layer 2 is, for example, GaAs, GaN, or InP.
  • the substrate 1 may also be an n-type semiconductor substrate made of n-type silicon, in which case the epitaxial layer 2 is also made of silicon.
  • a field effect transistor 3 is formed in the epitaxial layer 2.
  • the field effect transistor 3 has a plurality of gate electrodes 4, a plurality of drain electrodes 5, and a plurality of source electrodes 6.
  • Each gate electrode 4 is disposed between an adjacent drain electrode 5 and source electrode 6.
  • a gate pad 7, a drain pad 8, and a source pad 9 are formed on the epitaxial layer 2.
  • the gate pad 7 is connected to a plurality of gate electrodes 4 via gate wiring 10.
  • the drain pad 8 is connected to a plurality of drain electrodes 5 via air bridge wiring 11.
  • the source pad 9 is connected to a plurality of source electrodes 6 via air bridge wiring 12 that spans the gate wiring 10.
  • a back electrode 13 is formed on the back surface of the substrate 1.
  • the back electrode 13 is connected to the source pad 9 through a via hole 14 that penetrates the substrate 1 and the epitaxial layer 2.
  • a wire 15 is bonded to the gate pad 7.
  • a number of wires 16 are bonded to the drain pad 8.
  • the bonding size of the wires 15 and 16 is 50 to 60 ⁇ m.
  • the substrate 1 is etched from the back side, and multiple cavities 17 are formed in the substrate 1 and epitaxial layer 2 directly below the drain pad 8.
  • the width of each cavity 17 is approximately 80 ⁇ m.
  • the multiple cavities 17 are not formed directly below the bonding portions of the multiple wires 16.
  • Fig. 5 is a cross-sectional view showing a semiconductor device according to Comparative Example 1.
  • a cavity 17 is formed directly below the bonding portion of the wire 16. This makes it difficult to ensure the strength to withstand the impact of the wire bond.
  • Fig. 6 is a cross-sectional view showing a semiconductor device according to Comparative Example 2.
  • Comparative Example 2 no cavity 17 is provided in the substrate 1, and part of the back electrode 13 is removed directly below the drain pad 8.
  • the semiconductor device is mounted on the GND 18 of the package, a parasitic capacitance is generated between the drain pad 8 and the GND 18 of the package. Therefore, even if part of the back electrode 13 is removed, the parasitic capacitance remains almost unchanged.
  • a cavity 17 is formed in the substrate 1 directly below the drain pad 8.
  • the inside of the cavity 17 is air or vacuum, and the dielectric constant inside the cavity 17 is smaller than that of the substrate 1. Therefore, the parasitic capacitance between the drain pad 8 and the back electrode 13 can be reduced without reducing the area of the drain pad 8.
  • the cavity 17 is not formed directly below the bonding portion of the wire 16. Therefore, the thin drain pad 8 above the cavity 17 is not mechanically or physically destroyed and can withstand the impact of the wire bond. Even if part of the wire material that has been crushed and spread by the wire bond is present above the cavity 17, it is sufficient as long as the drain pad 8 above the cavity 17 is not destroyed.
  • the etching reaches the back surface of the drain pad 8, and a cavity 17 is formed not only in the substrate 1 but also in the epitaxial layer 2. This allows the parasitic capacitance to be further reduced. However, even if the thin epitaxial layer 2 remains, the parasitic capacitance can be sufficiently reduced.
  • Fig. 7 is a plan view showing a semiconductor device according to a second embodiment.
  • Fig. 8 is a cross-sectional view taken along line I-II in Fig. 7.
  • the drain pad 8 is separated into a plurality of pads by slits 19.
  • a wire 16 is bonded to the drain pad 8 across the slit 19.
  • the inside of the slit 19 is air or a vacuum. This makes it possible to reduce the parasitic capacitance between the drain pad 8 and the back electrode 13 while ensuring the substrate strength against wire bonding.
  • the other configurations and effects are the same as those of the first embodiment.
  • Embodiment 3. 9 is a plan view showing a semiconductor device according to a third embodiment.
  • the drain pad 8 is separated into a plurality of pads, and therefore the drain pad 8 must be probed with a plurality of probes when evaluating electrical characteristics during the wafer process or when testing the wafer.
  • the plurality of pads of the drain pad 8 separated by slits 19 are connected to each other by thin wiring 20. This makes it possible to probe the drain pad 8 with a single probe, making testing easier.
  • Other configurations and effects are the same as those of the second embodiment.
  • Embodiment 4. 10 is a cross-sectional view showing a semiconductor device according to a fourth embodiment. This figure corresponds to the cross-sectional view taken along line I-II in FIG. 7.
  • Each of the drain pads 8 separated by slits 19 has an underlying portion 8a and a protruding portion 8b formed on the outer periphery of the underlying portion 8a.
  • the underlying portion 8a and the protruding portion 8b are formed collectively by Au plating.
  • the wire 16 is bonded to the protrusions 8b arranged on both sides of the slit 19.
  • the height of the slit 19 is about 10 ⁇ m in the second embodiment and about 15 ⁇ m in the present embodiment. Therefore, the height of the slit 19 can be increased.
  • the parasitic capacitance is mainly a series connection of the capacitor in the slit 19 part and the capacitor in the substrate 1 part. Since the dielectric constant of the slit 19 is about 1/10 of the dielectric constant of the substrate 1, a large capacitance reduction effect can be expected simply by making the slit 19 slightly taller. Also, since only the outer periphery of the pad is thickened, the amount of Au material can be reduced compared to when the entire pad is thickened.
  • the protrusion 8b is formed at the same time as forming the air bridge wiring 11 that connects the drain electrode 5 and the drain pad 8, the plating time can be shortened. In this case, the material and thickness of the protrusion 8b in the portion not crushed by wire bonding will be the same as that of the air bridge wiring 11.
  • the other configurations and effects are the same as those of the second or third embodiment.
  • Embodiment 5. 11 is a cross-sectional view showing a semiconductor device according to a fifth embodiment. This figure corresponds to the cross-sectional view taken along line I-II in FIG. 7.
  • a back electrode 13 is formed on the entire back surface of the substrate 1.
  • a wafer-shaped metal plate is pressure-bonded to the back surface of the wafer-shaped substrate 1 using Au particles as the back electrode 13.
  • the back electrode 13 closes the cavity 17, thereby preventing conductive resin or solder from entering the cavity 17 during mounting.
  • Other configurations and effects are the same as those of the first to fourth embodiments.

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Wire Bonding (AREA)
PCT/JP2022/038906 2022-10-19 2022-10-19 半導体装置 Ceased WO2024084621A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202280097058.5A CN120019727A (zh) 2022-10-19 2022-10-19 半导体装置
US18/861,500 US20250351479A1 (en) 2022-10-19 2022-10-19 Semiconductor device
JP2024551126A JP7782714B2 (ja) 2022-10-19 2022-10-19 半導体装置
PCT/JP2022/038906 WO2024084621A1 (ja) 2022-10-19 2022-10-19 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2022/038906 WO2024084621A1 (ja) 2022-10-19 2022-10-19 半導体装置

Publications (1)

Publication Number Publication Date
WO2024084621A1 true WO2024084621A1 (ja) 2024-04-25

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ID=90737113

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PCT/JP2022/038906 Ceased WO2024084621A1 (ja) 2022-10-19 2022-10-19 半導体装置

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US (1) US20250351479A1 (https=)
JP (1) JP7782714B2 (https=)
CN (1) CN120019727A (https=)
WO (1) WO2024084621A1 (https=)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267331A (ja) * 2000-03-15 2001-09-28 Hitachi Ltd 半導体装置の製造方法
JP2002270822A (ja) * 2001-03-09 2002-09-20 Toshiba Corp 半導体装置
JP2008226871A (ja) * 2007-03-08 2008-09-25 Nec Corp 半導体装置及びその製造方法
US20160343809A1 (en) * 2015-05-22 2016-11-24 Freescale Semiconductor, Inc. Device with a conductive feature formed over a cavity and method therefor
WO2019150526A1 (ja) * 2018-02-01 2019-08-08 三菱電機株式会社 半導体装置およびその製造方法
WO2020255259A1 (ja) * 2019-06-18 2020-12-24 三菱電機株式会社 半導体装置およびその製造方法
WO2022102137A1 (ja) * 2020-11-16 2022-05-19 三菱電機株式会社 トランジスタ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106252310B (zh) 2016-06-02 2020-05-05 苏州能讯高能半导体有限公司 半导体器件及其制造方法
CN111354640B (zh) 2018-12-21 2022-08-12 苏州能讯高能半导体有限公司 一种半导体器件及其制备方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001267331A (ja) * 2000-03-15 2001-09-28 Hitachi Ltd 半導体装置の製造方法
JP2002270822A (ja) * 2001-03-09 2002-09-20 Toshiba Corp 半導体装置
JP2008226871A (ja) * 2007-03-08 2008-09-25 Nec Corp 半導体装置及びその製造方法
US20160343809A1 (en) * 2015-05-22 2016-11-24 Freescale Semiconductor, Inc. Device with a conductive feature formed over a cavity and method therefor
WO2019150526A1 (ja) * 2018-02-01 2019-08-08 三菱電機株式会社 半導体装置およびその製造方法
WO2020255259A1 (ja) * 2019-06-18 2020-12-24 三菱電機株式会社 半導体装置およびその製造方法
WO2022102137A1 (ja) * 2020-11-16 2022-05-19 三菱電機株式会社 トランジスタ

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JP7782714B2 (ja) 2025-12-09
CN120019727A (zh) 2025-05-16
JPWO2024084621A1 (https=) 2024-04-25
US20250351479A1 (en) 2025-11-13

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