WO2024082562A1 - Amplificateur de détection, son procédé de commande, et mémoire - Google Patents

Amplificateur de détection, son procédé de commande, et mémoire Download PDF

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Publication number
WO2024082562A1
WO2024082562A1 PCT/CN2023/085961 CN2023085961W WO2024082562A1 WO 2024082562 A1 WO2024082562 A1 WO 2024082562A1 CN 2023085961 W CN2023085961 W CN 2023085961W WO 2024082562 A1 WO2024082562 A1 WO 2024082562A1
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Prior art keywords
pull
units
moment
control signal
power supply
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PCT/CN2023/085961
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English (en)
Chinese (zh)
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武贤君
石小庆
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长鑫存储技术有限公司
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Publication of WO2024082562A1 publication Critical patent/WO2024082562A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Definitions

  • the present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a sense amplifier and a control method thereof, and a memory.
  • the sense amplifier is an important component of the memory and plays an important role in reading or writing the data stored in the memory.
  • the main function of the sense amplifier is to amplify the small signal on the bit line to perform the read or write operation.
  • the sense amplifier receives the input representing the data stored in the memory cell and amplifies the input to a voltage level that is recognizable by an external device so that the data of the memory cell can be read correctly.
  • the sense amplifier in the memory has the problem of inaccurate reading of data.
  • the main purpose of the present disclosure is to provide a sense amplifier and a control method thereof, and a memory.
  • the present disclosure provides a control method for a sense amplifier, wherein the sense amplifier comprises: an amplifying circuit, a pull-up circuit and a pull-down circuit; the pull-up circuit comprises N pull-up units, a first end of each of the pull-up units is connected to a first port of the amplifying circuit, and a control end of each of the pull-up units is used to access a pull-up control signal; the pull-down circuit comprises M pull-down units, a first end of each of the pull-down units is connected to a second port of the amplifying circuit, and a control end of each of the pull-down units is used to access a pull-down control signal, wherein M and N are both positive integers greater than 1;
  • the method comprises:
  • the sensing amplification stage of the sensing amplifier at a first moment, turning on X pull-up units in response to X first pull-up control signals, and/or turning on Y pull-down units in response to Y first pull-down control signals;
  • the second moment is later than the first moment, X is a positive integer greater than or equal to 1 and less than or equal to N, Y is a positive integer greater than or equal to 1 and less than or equal to M, and when X is N, Y is not M.
  • the first pull-up control signal and the first pull-down control signal are flipped from an invalid level to a valid level
  • the second pull-up control signal and the second pull-down control signal are flipped from an invalid level to a valid level.
  • the second moment is a moment that lags behind the first moment by a first preset time.
  • the second moment is the moment when the voltage difference between the bit line and the complementary bit line of the sense amplifier reaches a first preset value.
  • the second ends of the X pull-up units turned on at the first moment are connected to the first power supply terminal, and the second ends of the remaining pull-up units except the X pull-up units turned on at the second moment are connected to the second power supply terminal; the second ends of the Y pull-down units turned on at the first moment are connected to the third power supply terminal, and the second ends of the remaining pull-down units except the Y pull-down units turned on at the second moment are connected to the fourth power supply terminal.
  • the voltage value of the first power supply terminal is smaller than the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is larger than the voltage value of the fourth power supply terminal.
  • the method further includes: in the sensing amplification stage of the sensing amplifier: at a third moment, flipping the second pull-up control signal and the second pull-down control signal from a valid level to an invalid level, and in response to the second pull-up control signal at the invalid level, turning off the remaining pull-up units except the X pull-up units, and/or, in response to the second pull-down control signal at the invalid level, turning off the remaining pull-down units except the Y pull-down units;
  • the third moment is later than the second moment.
  • the third moment is a moment that lags behind the first moment by a second preset time.
  • the third moment is the moment when the voltage difference between the bit line and the complementary bit line of the sense amplifier reaches a second preset value.
  • the voltage value of the first power supply terminal is equal to the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is equal to the voltage value of the fourth power supply terminal;
  • the driving capabilities of the X pull-up units are smaller than the driving capabilities of the remaining pull-up units except the X pull-up units;
  • Driving capabilities of the Y pull-down units are smaller than driving capabilities of the remaining pull-down units except the Y pull-down units.
  • the method further comprises:
  • one or more of the first preset time, the second preset time, the first preset value, the second preset value, the value of X and the value of Y are set according to the received test command; or one or more of the first preset time, the second preset time, the first preset value, the second preset value, the value of X and the value of Y are set through the configuration parameters in the mode register.
  • the present disclosure also provides a sense amplifier, including:
  • Amplifier circuit pull-up circuit, pull-down circuit
  • the pull-up circuit comprises N pull-up units, a first end of each of the pull-up units is connected to a first port of the amplifier circuit, and a control end of each of the pull-up units is used to access a pull-up control signal;
  • the pull-down circuit comprises M pull-down units, a first end of each of the pull-down units is connected to the second port of the amplifier circuit, and a control end of each of the pull-down units is used to access a pull-down control signal, wherein M and N are both positive integers greater than 1;
  • the pull-up circuit and the pull-down circuit are configured to, in the sensing amplification stage of the sense amplifier: at a first moment, turn on X pull-up units in response to X first pull-up control signals, and/or turn on Y pull-down units in response to Y first pull-down control signals; at a second moment, turn on the remaining pull-up units except the X pull-up units in response to (N-X) second pull-up control signals, and/or turn on the remaining pull-down units except the Y pull-down units in response to (M-Y) second pull-down control signals; wherein the second moment is later than the first moment, X is a positive integer greater than or equal to 1 and less than or equal to N, Y is a positive integer greater than or equal to 1 and less than or equal to M, and when X is N, Y is not M.
  • the sense amplifier further comprises:
  • a control signal generating circuit is configured to generate a control signal, wherein the control signal includes the first pull-up control signal, the second pull-up control signal, the first pull-down control signal and the second pull-down control signal;
  • the first pull-up control signal is used to control the on or off of the X pull-up units
  • the first pull-down control signal is used to control the on or off of the Y pull-down units
  • the second pull-up control signal is used to control the turning on or off of the remaining pull-up units except the X pull-up units;
  • the second pull-down control signal is used to control the remaining pull-down units except the Y pull-down units to be turned on or off.
  • control signal generating circuit is also configured to: flip the first pull-up control signal and the first pull-down control signal from an invalid level to a valid level at the first moment, and flip the second pull-up control signal and the second pull-down control signal from an invalid level to a valid level at the second moment.
  • control signal generating circuit includes: a delay unit and a multiplexer, the output end of the delay unit is connected to the input end of the multiplexer;
  • the delay unit is configured to generate a plurality of delay times
  • the multiplexer is configured to select and output one of the multiple delay times as a first preset time in response to a first selection signal, wherein the first preset time is a time difference between the second moment and the first moment.
  • control signal generating circuit includes:
  • the signal detection unit is configured to detect a voltage difference between the bit line and the complementary bit line of the sense amplifier, and when the voltage difference reaches a first preset value, flip the second pull-up control signal and the second pull-down control signal from an invalid level to a valid level.
  • the amplifier circuit is specifically configured as follows:
  • the second ends of the X pull-up units turned on at the first moment are connected to the first power supply end, and the The second ends of the remaining pull-up units other than the X pull-up units are connected to the second power supply terminal; the second ends of the Y pull-down units turned on at the first moment are connected to the third power supply terminal, and the second ends of the remaining pull-down units other than the Y pull-down units turned on at the second moment are connected to the fourth power supply terminal.
  • the voltage value of the first power supply terminal is smaller than the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is larger than the voltage value of the fourth power supply terminal.
  • control signal generating circuit is further configured to: at a third moment of the sensing amplification phase of the sensing amplifier, flip the second pull-up control signal and the second pull-down control signal from a valid level to an invalid level;
  • the pull-up circuit and the pull-down circuit are further configured to: at the third moment, in response to the second pull-up control signal at an invalid level, turn off the remaining pull-up units except the X pull-up units, and/or, in response to the second pull-down control signal at an invalid level, turn off the remaining pull-down units except the Y pull-down units;
  • the third moment is later than the second moment.
  • control signal generating circuit includes: a delay unit and a multiplexer, the output end of the delay unit is connected to the input end of the multiplexer;
  • the delay unit is configured to generate a plurality of delay times
  • the multiplexer is configured to select and output one of the multiple delay times as a second preset time in response to a second selection signal, where the second preset time is a time difference between the third moment and the first moment.
  • control signal generating circuit includes: a signal detection unit, configured to: detect the voltage difference between the bit line and the complementary bit line of the sense amplifier, and when the voltage difference reaches a second preset value, flip the second pull-up control signal and the second pull-down control signal from a valid level to an invalid level.
  • the voltage value of the first power supply terminal is equal to the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is equal to the voltage value of the fourth power supply terminal;
  • the driving capability of the X pull-up units is less than the driving capability of the remaining pull-up units except the X pull-up units;
  • Driving capabilities of the Y pull-down units are smaller than driving capabilities of the remaining pull-down units except the Y pull-down units.
  • the amplifier circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a first switch, a second switch, a third switch and a fourth switch;
  • the second end of the first transistor is connected to the second end of the second transistor, the second end of the third transistor is connected to the first end of the first transistor, the first end of the third transistor is connected to the first end of the fourth transistor, and the second end of the fourth transistor is connected to the first end of the second transistor;
  • the control end of the first transistor is connected to the second end of the fourth transistor through the first switch, the control end of the first transistor is connected to the second end of the third transistor through the third switch, the control end of the second transistor is connected to the second end of the third transistor through the second switch, and the control end of the second transistor is connected to the second end of the fourth transistor through the fourth switch;
  • the control end of the third transistor is connected to the second end of the fourth transistor, and the control end of the fourth transistor is connected to the second end of the third transistor.
  • the embodiment of the present disclosure further provides a memory, comprising the sense amplifier as described in any of the above embodiments.
  • FIG1 is a schematic diagram of a circuit structure of a sense amplifier according to an embodiment of the present disclosure
  • FIG2 is a control timing diagram of a sense amplifier for a read operation according to an embodiment of the present disclosure
  • FIG3 is a schematic diagram of a circuit structure of a sense amplifier according to another embodiment of the present disclosure.
  • FIG4 is a control timing diagram of a sense amplifier for a read operation according to another embodiment of the present disclosure.
  • FIG5 is a module diagram of a control signal generating circuit according to an embodiment of the present disclosure.
  • FIG6 is a module diagram of a control signal generating circuit according to another embodiment of the present disclosure.
  • FIG7 is a schematic diagram of the structure of a control signal generating circuit according to another embodiment of the present disclosure.
  • FIG8 is a control timing diagram of a sense amplifier for a read operation according to yet another embodiment of the present disclosure.
  • FIG9 is a control timing diagram of a sense amplifier for a read operation according to yet another embodiment of the present disclosure.
  • FIG. 10 is a flow chart of a control method of a sense amplifier according to another embodiment of the present disclosure.
  • spatial relationship terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as “under other elements” or “under it” or “under it” will be oriented as “on” other elements or features. Therefore, the exemplary terms “under” and “under” may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.
  • the sense amplifier may have an offset voltage that affects the circuit sensitivity.
  • the offset voltage may be caused by a variety of factors, including but not limited to deviations between the threshold voltages of corresponding transistors in the cross-coupled inverters, mismatches between series resistances on the source/drain nodes of the transistors, mismatches between the sizes of the structures of the corresponding circuit elements, carrier mobility mismatches, substrate bias, conductivity mismatches, and node capacitance mismatches of the corresponding transistors.
  • the offset voltage may be caused by the difference between the threshold voltages of corresponding transistors in two inverter amplifiers in the sense amplifier.
  • the threshold voltage of a transistor in one inverter may be higher than the threshold voltage of a corresponding transistor in a coupled inverter in the sense amplifier circuit.
  • the offset voltage may cause mismatch noise, which may easily lead to sensing errors in the sense amplifier and reduce the sensing margin of the sense amplifier, so that the sense amplifier cannot amplify the signal quickly and effectively, thereby reducing the performance of the memory.
  • FIG. 1 is a schematic diagram of a circuit structure of a sensing amplifier shown in an embodiment of the present disclosure. As shown in FIG. 1 , the sensing amplifier includes two cross-coupled PMOS transistors P1 and P2 and two NMOS transistors N1 and N2, which are respectively connected to the voltage control terminals PCS and NCS of the sensing amplifier.
  • bit line BLa and the complementary bit line BLb are respectively connected to the above-mentioned four transistors through the offset cancellation unit, and the connection point is located between the connection point of the PMOS transistor and the NMOS transistor, which is set as SaBLa and SaBLb, that is, the bit line BLa is connected to SaBLb through the first offset cancellation unit 130, and the complementary bit line BLb is connected to SaBLa through the second offset cancellation unit 140, and the offset cancellation unit connecting the bit line BLa and the complementary bit line BLb is controlled by the same offset cancellation signal OC.
  • bit line BLa and the complementary bit line BLb are also connected to SaBLa and SaBLb through an isolation unit (ISO), that is, the bit line BLa is connected to SaBLa through a first isolation unit 110, and the complementary bit line BLb is connected to SaBLb through a second isolation unit 120.
  • the isolation unit connecting the bit line BLa and the complementary bit line BLb is controlled by the same isolation signal ISO.
  • the sense amplifier also includes a first precharge unit 150 and a second precharge unit 160, and the first precharge unit 150 and the second precharge unit 160 are controlled by the same precharge signal Eq.
  • the sense amplifier also includes a pull-up unit 170 and a pull-down unit 180, and the pull-up unit 170 is controlled by a pull-up signal SapEn, and the pull-down unit 180 is controlled by a pull-down signal SanEn.
  • the control timing of the sense amplifier shown in FIG1 for the read operation is shown in FIG2.
  • the process of reading the logic data "1" from the memory cell is described below.
  • the offset elimination signal OC and the precharge signal Eq are both at high levels, so that the first offset elimination unit 130, the second offset elimination unit 140, the first precharge unit 150 and the second precharge unit 160 are in the on state.
  • the voltages of the voltage control terminals PCS and NCS are both the precharge voltage Vad2, and the target word line (Target Word Line, WLT) voltage is at a low level, that is, the target word line is in the off state.
  • the voltages of the bit line BLa and the complementary bit line BLb are both the precharge voltage Vad2. This period is the precharge stage, during which the sense amplifier is in a balanced state, and the voltages of the bit line BLa and each point of the sense amplifier are all at the precharge voltage Vad2.
  • the precharge signal Eq is switched to a low level so that the first precharge unit 150 and the second precharge unit 160 are in the off state, and the offset cancellation signal OC is still at a high level so that the first offset cancellation unit 130 and the second offset cancellation unit 140 remain in the on state.
  • the pull-up signal SapEn is at a low level so that the pull-up unit 170 is in the on state, and the pull-down signal SanEn is at a high level so that the pull-down unit 180 is in the on state.
  • the pull-up unit 170 and the pull-down unit 180 provide a high power supply voltage Vblh and a low power supply voltage Vss, respectively, and the voltages of the voltage control terminals PCS and NCS are the high power supply voltage Vblh and the low power supply voltage Vss, respectively.
  • This period is the offset calibration stage, during which the offset calibration is implemented to offset the offset voltage caused by the threshold voltage mismatch between the transistors of the sense amplifier. Specifically, in the offset calibration stage, a compensation voltage is generated on the bit line BLa and the complementary bit line BLb to offset the offset voltage caused by the threshold voltage mismatch between the cross-coupled transistors in the sense amplifier, thereby improving the sensitivity of the sense amplifier.
  • the target word line is still not turned on.
  • the offset cancellation signal OC and the pull-down signal SanEn are switched to a low level
  • the pull-up signal SapEn is switched to a high level
  • the first offset cancellation unit 130, the second offset cancellation unit 140, the pull-up unit 170 and the pull-down unit 180 are all in the off state
  • the compensation voltage generated in the previous stage is retained on the bit line BLa and the complementary bit line BLb.
  • the voltage control terminals PCS and NCS are restored to the precharge voltage Vad2.
  • the period from t4 to t6 is the charge sharing stage.
  • the target word line is turned on, the storage cell selection transistor coupled to the target word line and the bit line BLa is turned on, the charge in the storage cell is shared with the charge in the bit line, while the complementary bit line BLb does not share charge.
  • the isolation signal ISO is switched to a high level to turn on the first isolation unit 110 and the second isolation unit 120, and transmit the information on the bit line BLa and the complementary bit line BLb to the connection points SaBLa and SaBLb.
  • the pull-up signal SapEn switches to a low level
  • the pull-down signal SanEn switches to a high level
  • the pull-up unit 170 and the pull-down unit 180 are in a conducting state, and then enters the sensing amplification stage, that is, the period from t6 to t7.
  • the voltage control terminals PCS and NCS will be switched back to the high power supply voltage Vblh and the low power supply voltage Vss respectively, the pull-up unit 170 will pull up the voltage on the bit line BLa, and the pull-down unit 180 will pull down the voltage on the complementary bit line BLb, so that the voltages of the bit line BLa and the complementary bit line BLb respectively reach the voltage amplitudes corresponding to the read data, so that the voltage difference between the bit line BLa and the complementary bit line BLb can reflect the data in the accessed storage cell, so as to read out the data.
  • the sense amplifier stabilizes the voltage on the bit line BLa at the logic data "1" corresponding to the accessed storage cell, and the voltage on the complementary bit line BLb at the logic data "0".
  • the external read circuit can read the storage data in the accessed storage cell from the bit line BLa and the complementary bit line BLb by controlling the signal in the column selection line.
  • the bit line BLa continues to charge the storage capacitor. After a certain period of charging, the charge in the storage capacitor is restored to the state before the read operation.
  • the target word line is turned off, the pull-up signal SapEn is switched to a high level, the isolation signal ISO and the pull-down signal SanEn are switched to a low level, the first isolation unit 110, the second isolation unit 120, the pull-up unit 170 and the pull-down unit 180 are all in the off state, the precharge signal Eq is switched to a high level, and the first precharge unit 150 and the second precharge unit 160 are in the on state.
  • the sense amplifier enters the precharge stage, and the potential of the bit line BLa and the complementary bit line BLb is maintained at the precharge voltage Vad2 through the charging power supply.
  • the bit line BLa shares charge with the memory cell, while the complementary bit line BLb does not share charge, resulting in a voltage difference.
  • the pull-up unit 170 and the pull-down unit 180 are turned on at the same time, a large current will be generated on the voltage control terminals PCS and NCS, and the signal will change dramatically, thereby generating a large coupling noise.
  • the voltage difference between the bit line BLa and the complementary bit line BLb due to charge sharing is very small, and is easily affected by the coupling noise, resulting in a reduction in the sensed voltage difference, which has an adverse effect on the sensing margin, thereby causing the signal sensed and amplified by the sense amplifier to be inconsistent with the actual data.
  • the present disclosure provides a sense amplifier, including: an amplifying circuit, a pull-up circuit, and a pull-down circuit;
  • the pull-up circuit includes N pull-up units, the first end of each pull-up unit is connected to the first port of the amplifying circuit, and the control end of each pull-up unit is used to access the pull-up control signal;
  • the pull-down circuit includes M pull-down units, the first end of each pull-down unit is connected to the second port of the amplifying circuit, and the control end of each pull-down unit is used to access the pull-down control signal, wherein M and N are both positive integers greater than 1;
  • the pull-up circuit and the pull-down circuit are configured to, in the sensing amplification stage of the sensing amplifier: at a first moment, turn on X pull-up units in response to X first pull-up control signals, and/or turn on Y pull-down units in response to Y first pull-down control signals; at a second moment, turn on the remaining pull-up units except the X pull-up units in response to (N-X) second pull-up control signals, and/or turn on the remaining pull-down units except the Y pull-down units in response to (M-Y) second pull-down control signals; wherein the second moment is later than the first moment, X is a positive integer greater than or equal to 1 and less than or equal to N, Y is a positive integer greater than or equal to 1 and less than or equal to M, and when X is N, Y is not M.
  • the sense amplifier includes: an amplification circuit, a pull-up circuit 310 and a pull-down circuit 320; the pull-up circuit 310 includes three pull-up units 311, each of which The first ends of the pull-up units 311 are connected to the first port PCS1 of the amplifier circuit, and the control end of each pull-up unit 311 is used to access the pull-up control signal; the pull-down circuit includes three pull-down units 321, and the first end of each pull-down unit 321 is connected to the second port NCS1 of the amplifier circuit, and the control end of each pull-down unit 321 is used to access the pull-down control signal; the amplifier circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first switch K1, a second switch K2, a third switch K3 and a fourth switch K4.
  • N is equal to 3
  • M is equal to 3
  • X is equal to 1
  • Y is equal to 1
  • the control end of one pull-up unit 311 is used to access the first pull-up control signal SapEn1
  • the control end of one pull-down unit 321 is used to access the first pull-down control signal SanEn1
  • the control ends of two pull-up units 311 are used to access the second pull-up control signal SapEn2
  • the control ends of two pull-down units 321 are used to access the second pull-down control signal SanEn2.
  • the first transistor M1 and the second transistor M2 are NMOS transistors
  • the third transistor M3 and the fourth transistor M4 are PMOS transistors.
  • the bit line BLa and the complementary bit line BLb are respectively connected to the above four transistors, and the connection point is located between the connection point of the PMOS transistor and the NMOS transistor, which is set as SaBLa and SaBLb, that is, the bit line BLa is connected to SaBLb through the third switch K3, and the complementary bit line BLb is connected to SaBLa through the fourth switch K4, and the third switch K3 and the fourth switch K4 connecting the bit line BLa and the complementary bit line BLb are both controlled by the first offset cancellation signal OC1.
  • bit line BLa and the complementary bit line BLb are also connected to SaBLa and SaBLb through the first switch K1 and the second switch K2, that is, the bit line BLa is connected to SaBLa through the first switch K1, and the complementary bit line BLb is connected to SaBLb through the second switch K2.
  • the first switch K1 and the second switch K2 connecting the bit line BLa and the complementary bit line BLb are both controlled by the first isolation signal ISO1.
  • the second end of the first transistor M1 is connected to the second end of the second transistor M2, the second end of the third transistor M3 is connected to the first end of the first transistor M1, the first end of the third transistor M3 is connected to the first end of the fourth transistor M4, and the second end of the fourth transistor M4 is connected to the first end of the second transistor M2;
  • the control end of the first transistor M1 is connected to the second end of the fourth transistor M4 through the first switch K1, the control end of the first transistor M1 is connected to the second end of the third transistor M3 through the third switch K3, the control end of the second transistor M2 is connected to the second end of the third transistor M3 through the second switch K2, and the control end of the second transistor M2 is connected to the second end of the fourth transistor M4 through the fourth switch K4;
  • the control end of the third transistor M3 is connected to the second end of the fourth transistor M4 , and the control end of the fourth transistor M4 is connected to the second end of the third transistor M3 .
  • the amplifier circuit further includes a first charging switch CK1 and a second charging switch CK2 , wherein the first charging switch CK1 and the second charging switch CK2 are controlled by a first pre-charging signal Eq1 .
  • the sense amplifier further includes: a control signal generating circuit 330 configured to generate a control signal, the control signal including a first pull-up control signal SapEn1, a second pull-up control signal SapEn2, a first pull-down control signal SanEn1, and a second pull-down control signal SanEn2; wherein,
  • the first pull-up control signal SapEn1 is used to control the on or off of X pull-up units
  • the first pull-down control signal SanEn1 is used to control the on or off of Y pull-down units
  • the second pull-up control signal SapEn2 is used to control the turning on or off of the remaining pull-up units except the X pull-up units;
  • the second pull-down control signal SanEn2 is used to control the turning on or off of the remaining pull-down units except the Y pull-down units.
  • control signal generating circuit is further configured to: flip the first pull-up control signal and the first pull-down control signal from an invalid level to a valid level at a first moment, and flip the second pull-up control signal and the second pull-down control signal from an invalid level to a valid level at a second moment.
  • FIG4 is a control timing of the sense amplifier for the read operation shown in FIG3.
  • the control signal generating circuit is configured to: at a first moment Q6, flip the first pull-up control signal SapEn1 and the first pull-down control signal SanEn1 from an invalid level to a valid level, and at a second moment Q7, flip the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 from an invalid level to a valid level.
  • the effective level of the first pull-up control signal SapEn1 and the second pull-up control signal SapEn2 is a low level to control the conduction of the X pull-up units and the remaining pull-up units except the X pull-up units; the ineffective level of the first pull-up control signal SapEn1 and the second pull-up control signal SapEn2 is a high level to control the turn-off of the X pull-up units and the remaining pull-up units except the X pull-up units.
  • the effective level of the first pull-down control signal SanEn1 and the second pull-down control signal SanEn2 is a high level to control the conduction of the Y pull-down units and the remaining pull-down units except the Y pull-down units; the ineffective level of the first pull-down control signal SanEn1 and the second pull-down control signal SanEn2 is a low level to control the turn-off of the Y pull-down units and the remaining pull-down units except the Y pull-down units.
  • the second moment Q7 is a moment that lags behind the first moment Q6 by a first preset time ⁇ T1 .
  • the first preset time may be determined based on a voltage difference between the bit line BLa and the complementary bit line BLb of the sense amplifier.
  • the control signal generating circuit 330 includes: a signal detection unit 331, configured to detect the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb of the sense amplifier, and when the voltage difference ⁇ V reaches the first preset value V1, the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the invalid level to the valid level, so that the remaining pull-up units except the X pull-up units and the remaining pull-down units except the Y pull-down units are turned on.
  • the second moment Q7 is the moment when the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb reaches the first preset value V1.
  • the voltage difference ⁇ V can be 150mV or 200mV.
  • the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the invalid level to the valid level, and the remaining pull-up units and the remaining pull-down units are turned on without drastic signal changes, and the voltages of the bit line BLa and the complementary bit line BLb are less affected, which is not easy to cause sensing errors.
  • a fixed time may also be set as the first preset time to determine the second moment.
  • the control signal generating circuit 330 includes: a delay unit 710 and a multiplexer 720, wherein the output end of the delay unit 710 is connected to the input end of the multiplexer 720; the delay unit 710 is configured to generate a plurality of delay times; and the multiplexer 720 is configured to select and output one of the plurality of delay times as a first preset time in response to a first selection signal, wherein the first preset time is the time difference between the second moment and the first moment.
  • N is equal to 3
  • M is equal to 3
  • X is equal to 1
  • Y is equal to 1
  • one pull-up unit and one pull-down unit slowly amplify the voltage difference between the bit line Bla and the complementary bit line Blb for a fixed time, and then turn on the remaining two pull-up units and two pull-down units. No drastic signal change occurs, which can reduce the interference to the voltages of the bit line BLa and the complementary bit line BLb and avoid sensing errors.
  • the delay unit 710 outputs five different delay times D1, D2, D3, D4 and D5 as an example.
  • the output end of the delay unit 710 is connected to the input end of the multiplexer 720; wherein the delay unit 710 includes a first delay unit 711, a second delay unit 712, a third delay unit 713, a fourth delay unit 714 and a fifth delay unit 715, and the first delay unit 711, the second delay unit 712, the third delay unit 713, the fourth delay unit 714 and the fifth delay unit 715 are respectively configured to generate a plurality of delay times D1, D2, D3, D4 and D5; the multiplexer 720 is configured to select and output one of the plurality of delay times D1, D2, D3, D4 and D5 as the first preset time in response to the first selection signal Select1.
  • the delay times D1, D2, D3, D4 and D5 are 1 ns, 1.5 ns, 2 ns
  • the number of delay times generated by the delay unit and the specific values of the delay times can be set according to actual needs.
  • the number of delay times generated here and the specific values of the multiple delay times are only examples, and the protection scope of the present disclosure should not be excessively limited here.
  • the first preset time is the time difference ⁇ T1 between the second moment Q7 and the first moment Q6.
  • the first preset time is set to 1ns or 1.5ns.
  • the amplification circuit is specifically configured as follows: the second ends of the X pull-up units turned on at the first moment Q6 are connected to the first power supply end, and the second ends of the remaining pull-up units other than the X pull-up units turned on at the second moment Q7 are connected to the second power supply end; the second ends of the Y pull-down units turned on at the first moment Q6 are connected to the third power supply end, and the second ends of the remaining pull-down units other than the Y pull-down units turned on at the second moment Q7 are connected to the fourth power supply end.
  • the voltage value of the first power supply terminal is less than the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is greater than the voltage value of the fourth power supply terminal.
  • the voltage value Vblh1 of the first power supply terminal is Vdd
  • the voltage value Vblh2 of the second power supply terminal is 1.2*Vdd
  • the voltage value Vss1 of the third power supply terminal is 0V
  • the voltage value Vss2 of the fourth power supply terminal is -0.2V.
  • the voltage value of the first power supply terminal is equal to the voltage value of the second power supply terminal, and the voltage value of the third power supply terminal is equal to the voltage value of the fourth power supply terminal; the driving capacity of the X pull-up units is less than the driving capacity of the remaining pull-up units except the X pull-up units; the driving capacity of the Y pull-down units is less than the driving capacity of the remaining pull-down units except the Y pull-down units.
  • the voltage value Vblh1 of the first power supply terminal and the voltage value Vblh2 of the second power supply terminal are both Vdd
  • the voltage value Vss1 of the third power supply terminal and the voltage value Vss2 of the fourth power supply terminal are both 0V.
  • the driving capacity of the pull-up unit turned on at the first moment of the sensing and amplification stage is less than the driving capacity of the pull-up unit turned on at the second moment; the driving capacity of the pull-down unit turned on at the first moment of the sensing and amplification stage is less than the driving capacity of the pull-down unit turned on at the second moment.
  • control signal generating circuit is further configured to: at a third moment in the sensing amplification phase of the sensing amplifier, flip the second pull-up control signal and the second pull-down control signal from the valid level to the invalid level; the pull-up circuit and the pull-down circuit are further configured to: at the third moment, in response to the second pull-up control signal at the invalid level, turn off the remaining pull-up units except the X pull-up units, and/or, in response to the second pull-down control signal at the invalid level, turn off the remaining pull-up units except the Y pull-down units. Pull-down unit; wherein the third moment is later than the second moment.
  • Figure 8 is another control timing of the sense amplifier shown in Figure 3 for the read operation.
  • the control signal generating circuit 330 is further configured to: at a third moment T3 of the sensing amplification phase of the sense amplifier, flip the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 from a valid level to an invalid level; the pull-up circuit and the pull-down circuit are further configured to: at a third moment T3, in response to the second pull-up control signal SapEn2 at an invalid level, turn off the remaining pull-up units except the X pull-up units, and/or, in response to the second pull-down control signal SanEn2 at an invalid level, turn off the remaining pull-down units except the Y pull-down units; wherein the third moment T3 is later than the second moment T2.
  • the third time T3 is a time that lags behind the first time T1 by a second preset time ⁇ T2 .
  • the second preset time may be determined based on a voltage difference between the bit line BLa and the complementary bit line BLb of the sense amplifier.
  • control signal generating circuit includes: a signal detection unit, configured to detect a voltage difference between a bit line BLa and a complementary bit line BLb of the sense amplifier, and when the voltage difference ⁇ V reaches a second preset value V2, flip the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 from a valid level to an invalid level, so that the remaining pull-up units except the X pull-up units and the remaining pull-down units except the Y pull-down units are turned off.
  • a signal detection unit configured to detect a voltage difference between a bit line BLa and a complementary bit line BLb of the sense amplifier, and when the voltage difference ⁇ V reaches a second preset value V2, flip the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 from a valid level to an invalid level, so that the remaining pull-up units except the X pull-up units and the remaining pull-down units except the Y pull-down units are turned off.
  • the second pull-up control signal SapEn2 is switched from a low level to a high level
  • the second pull-down control signal SanEn2 is switched from a high level to a low level, so that the second pull-up control signal SapEn2 and the second pull-down control signal SanEn are at an invalid level, thereby turning off the remaining pull-up units except the X pull-up units and the remaining pull-down units except the Y pull-down units, and only the X pull-up units and the Y pull-down units pull the voltage difference between the bit line BLa and the complementary bit line BLb to Vdd.
  • the third moment T3 is the moment when the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb reaches the second preset value V2.
  • the second preset value V2 can be other voltage values such as 0.9Vdd or 0.95Vdd.
  • a fixed time may also be set as the second preset time to determine the third moment.
  • the control signal generating circuit 330 includes: a delay unit 710 and a multiplexer 720, and the delay unit 710 outputs five different delay times D1, D2, D3, D4 and D5 as an example for explanation.
  • the output end of the delay unit 710 is connected to the input end of the multiplexer 720; wherein the delay unit 710 includes a first delay unit 711, a second delay unit 712, a third delay unit 713, a fourth delay unit 714 and a fifth delay unit 715, and the first delay unit 711, the second delay unit 712, the third delay unit 713, the fourth delay unit 714 and the fifth delay unit 715 are respectively configured to generate delay times D1, D2, D3, D4 and D5; the multiplexer 720 is configured to select one of the output delay times D1, D2, D3, D4 and D5 as the second preset time in response to the second selection signal Select2.
  • the delay times D1, D2, D3, D4 and D5 are 1 ns, 1.5 ns, 2 ns, 2.5 ns and 3 ns, respectively.
  • the second preset time is the time difference ⁇ T2 between the third moment T3 and the first moment T1.
  • the second preset time is set to 2ns or 2.5ns.
  • FIG10 is a flow chart of a control method of a sense amplifier provided by another embodiment of the present disclosure.
  • the present disclosure provides a control method of a sense amplifier, which will be described below in conjunction with FIG3, FIG4 and FIG10.
  • the circuit structure of the sense amplifier can refer to the relevant description in the above embodiment, which will not be repeated here.
  • the control method of the sense amplifier specifically includes the following steps:
  • Step S10 in the sensing amplification stage of the sensing amplifier: at a first moment, turning on X pull-up units in response to X first pull-up control signals, and/or turning on Y pull-down units in response to Y second pull-down control signals;
  • Step S20 at a second moment, in response to (N-X) second pull-up control signals, turning on the remaining pull-up units except the X pull-up units, and/or, in response to (M-Y) second pull-down control signals, turning on the remaining pull-down units except the Y pull-down units;
  • the second moment is later than the first moment, X is a positive integer greater than or equal to 1 and less than or equal to N, and Y is a positive integer greater than or equal to 1 and less than is a positive integer equal to M, and when X is N, Y is not M.
  • the second moment is the moment when the voltage difference between the bit line and the complementary bit line of the sense amplifier reaches a first preset value.
  • the second ends of the X pull-up units turned on at the first moment are connected to the first power supply terminal, and the second ends of the remaining pull-up units except the X pull-up units turned on at the second moment are connected to the second power supply terminal; the second ends of the Y pull-down units turned on at the first moment are connected to the third power supply terminal, and the second ends of the remaining pull-down units except the Y pull-down units turned on at the second moment are connected to the fourth power supply terminal.
  • the first offset cancellation signal OC1 and the first precharge signal Eq1 are both at high levels, so that the third switch K3, the fourth switch K4, the first charge switch CK1 and the second charge switch CK2 are in the on state.
  • the first isolation signal ISO1 is at a low level, so that the first switch K1 and the second switch K2 are in the off state.
  • the voltages of the first port PCS1 and the second port NCS1 are both the first precharge voltage V0, and at this time the target word line voltage is at a low level, that is, the target word line is in the off state.
  • the voltages of the bit line BLa and the complementary bit line BLb are both the first precharge voltage V0.
  • This period is the precharge stage of the sense amplifier. During this period, the sense amplifier is in a balanced state, and the voltages of the bit line BLa and each point of the sense amplifier are at the first precharge voltage V0. Exemplarily, the voltage value of the first precharge voltage V0 is Vdd/2.
  • the target word line is still not turned on, the first precharge signal Eq1 is switched to a low level so that the first charging switch CK1 and the second charging switch CK2 are in the off state, and the first isolation signal ISO1 is at a low level so that the first switch K1 and the second switch K2 are also in the off state.
  • the first offset cancellation signal OC1 is still at a high level so that the third switch K3 and the fourth switch K4 remain in the on state.
  • the first pull-up control signal SapEn1, the first pull-down control signal SanEn1, the second pull-up control signal SapEn2, and the second pull-down control signal SanEn2 are all at an effective level so that all pull-up units 311 and all pull-down units 321 are in the on state, and the voltages of the first port PCS1 and the second port NCS1 are the high power supply voltage Vblh2 and the low power supply voltage Vss2, respectively.
  • This period is the offset calibration stage, during which offset calibration is implemented to offset the offset voltage caused by the threshold voltage mismatch between the transistors of the sense amplifier. Specifically, in the offset calibration phase, a compensation voltage is generated on the bit line BLa and the complementary bit line BLb to offset the offset voltage caused by the threshold voltage mismatch between the cross-coupled transistors in the sense amplifier.
  • the target word line is still not turned on.
  • the first offset cancellation signal OC is switched to a low level
  • the first pull-up control signal SapEn1, the first pull-down control signal SanEn1, the second pull-up control signal SapEn2, and the second pull-down control signal SanEn2 are all at an invalid level
  • the third switch K3, the fourth switch K4 all the pull-up units 311, and all the pull-down units 321 are in the off state.
  • the first port PCS1 and the second port NCS1 are restored to the first precharge voltage Vdd/2.
  • the period from Q4 to Q6 is the charge sharing stage of the sense amplifier.
  • the first charge sharing stage of the sense amplifier i.e., the period from Q4 to Q5, the first charging switch CK1, the second charging switch CK2, the first switch K1, the second switch K2, the third switch K3, and the fourth switch K4 are disconnected, the target word line is turned on, the storage unit selection transistor commonly coupled to the target word line and the bit line BLa is turned on, the charge in the storage unit is shared with the charge in the bit line, and the complementary bit line BLb is not charged.
  • the first isolation signal ISO1 switches to a high level to turn on the first switch K1 and the second switch K2, and transmits the information on the bit line BLa and the complementary bit line BLb to the connection points SaBLa and SaBLb.
  • the first isolation signal ISO1 is switched to a high level to turn on the first switch K1 and the second switch K2, and the first pre-charge signal Eq1 and the first offset cancellation signal OC1 are both at a low level so that the first charging switch CK1, the second charging switch CK2, the third switch K3 and the fourth switch K4 are disconnected.
  • the first switch K1 and the second switch K2 are turned on, and the first charging switch CK1, the second charging switch CK2, the third switch K3, and the fourth switch K4 are turned off.
  • the first moment of the sensing amplification stage i.e., the moment Q6, the first pull-up control signal SapEn1 and the first pull-down control signal SanEn1 are flipped from the invalid level to the valid level, and one pull-up unit 311 is turned on in response to the first pull-up control signal SapEn1 at the valid level, and/or, one pull-down unit 321 is turned on in response to the first pull-down control signal SanEn1 at the valid level.
  • the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the invalid level to the valid level, and the remaining pull-up units 311 except one pull-up unit 311 are turned on in response to the second pull-up control signal SapEn2 at the valid level, and/or, the remaining pull-down units 321 except one pull-down unit are turned on in response to the second pull-down control signal SanEn2 at the valid level.
  • the second moment Q7 is later than the first moment Q6.
  • the effective level of the first pull-up control signal SapEn1 and the second pull-up control signal SapEn2 is a low level, and the ineffective level of the first pull-up control signal SapEn1 and the second pull-up control signal SapEn2 is a high level.
  • the effective level of the first pull-down control signal SanEn1 and the second pull-down control signal SanEn2 is a high level, and the first pull-down control signal SanEn1 and the second pull-down control signal SanEn2 are The invalid level of the control signal SanEn2 is low level.
  • the second moment Q7 is a moment that lags behind the first moment Q6 by a first preset time ⁇ T1 .
  • the first preset time may be determined based on a voltage difference between the bit line BLa and the complementary bit line BLb of the sense amplifier or a fixed time may be set as the first preset time.
  • the second pull-up control signal SanEn2 at the effective level and the second pull-down control signal SapEn2 at the effective level are responded to to turn on the remaining pull-up units except one pull-up unit and the remaining pull-down units except one pull-down unit.
  • the second moment Q7 is the moment when the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb reaches the first preset value V1.
  • the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb of the sensing amplifier reaches the first preset value V1
  • the remaining pull-up units and the remaining pull-down units will not undergo drastic signal changes, and the voltages of the bit line BLa and the complementary bit line BLb are less affected, which is less likely to cause sensing errors.
  • the first preset value is set to 150 mV or 200 mV.
  • N is equal to 3
  • M is equal to 3
  • X is equal to 1
  • Y is equal to 1
  • one pull-up unit and one pull-down unit slowly amplify the voltage difference between the bit line Bla and the complementary bit line Blb for a fixed time, and then turn on the remaining two pull-up units and two pull-down units. No drastic signal change occurs, which can reduce the interference to the voltages of the bit line BLa and the complementary bit line BLb and avoid sensing errors.
  • the fixed time may be a design experience value or a test value.
  • the configuration parameters of the mode register may be used to control the multiplexer 720 shown in FIG. 7 to select a corresponding fixed time value as the first preset time.
  • the first preset time is set to 1 ns or 1.5 ns.
  • the second end of a pull-up unit turned on by Q6 at the first moment is connected to the first power supply terminal, and the second ends of the remaining pull-up units except one pull-up unit turned on by Q7 at the second moment are connected to the second power supply terminal; the second end of a pull-down unit turned on by Q6 at the first moment is connected to the third power supply terminal, and the second ends of the remaining pull-down units except one pull-down unit turned on by Q7 at the second moment are connected to the fourth power supply terminal.
  • the voltage value Vblh1 of the first power supply terminal is less than the voltage value Vblh2 of the second power supply terminal, and the voltage value Vss1 of the third power supply terminal is greater than the voltage value Vss2 of the fourth power supply terminal.
  • the voltage value Vblh1 of the first power supply terminal is Vdd
  • the voltage value Vblh2 of the second power supply terminal is 1.2*Vdd
  • the voltage value Vss1 of the third power supply terminal is 0V
  • the voltage value Vss2 of the fourth power supply terminal is -0.2V.
  • the first pull-up control signal SapEn1 is switched to a low level
  • the first pull-down control signal SanEn1 is switched to a high level
  • one pull-up unit 311 and one pull-down unit 321 are in a conducting state, so that the first port PCS1 and the second port NCS1 are pulled back to the voltage value Vblh1 of the first power supply terminal and the voltage value Vss1 of the third power supply terminal, so that the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb reaches the first preset value V1.
  • the second pull-up control signal SapEn2 is switched to a low level
  • the second pull-down control signal SanEn2 is switched to a high level
  • the remaining two pull-up units 311 and the two pull-down units 321 are in the on state, so that the voltage value of the first port PCS1 is pulled from the voltage value Vblh1 of the first power supply terminal to the voltage value Vblh2 of the second power supply terminal
  • the voltage value of the second port NCS1 is pulled from the voltage value Vss1 of the third power supply terminal to the voltage value Vss2 of the fourth power supply terminal, so that the voltage difference ⁇ V between the bit line BLa and the complementary bit line BLb continues to be amplified to reach the voltage amplitude corresponding to the read data, so as to read out the data.
  • the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb in the period from Q6 to Q7 is less than the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb in the period from Q7 to Q8.
  • the same effect can be achieved by controlling the voltage values of the first pull-up control signal, the second pull-up control signal, the first pull-down control signal, and the second pull-down control signal.
  • the voltage value Vblh1 of the first power supply terminal is equal to the voltage value Vblh2 of the second power supply terminal
  • the voltage value Vss1 of the third power supply terminal is equal to the voltage value Vss2 of the fourth power supply terminal.
  • the first pull-up control signal SapEn1 and the first pull-down control signal SanEn1 are flipped from the invalid level to the valid level to turn on one pull-up unit 311 and one pull-down unit 321, that is, the first pull-up control signal SapEn1 is switched to the first low level, and the first pull-down control signal SanEn1 is switched to the first high level.
  • the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the invalid level to the valid level to turn on the remaining two pull-up units 311 and the remaining two pull-down units 321, that is, the second pull-up control signal SapEn2 is switched to the second low level, and the second pull-down control signal SanEn2 is switched to the second high level.
  • the voltage value of the first low level is greater than the voltage value of the second low level, and the voltage value of the first high level is less than the voltage value of the second high level, so that the driving voltage Vgs1 of the pull-up unit and the pull-down unit turned on by Q6 at the first moment is less than the driving voltage Vgs2 of the pull-up unit and the pull-down unit turned on by Q7 at the second moment. Therefore, the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb in the period from Q6 to Q7 is less than the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb in the period from Q7 to Q8.
  • a voltage value of the first power supply terminal is equal to a voltage value of the second power supply terminal
  • a voltage value of the third power supply terminal is equal to a voltage value of the fourth power supply terminal
  • a driving capability of the X pull-up units is less than a driving capability of the remaining pull-up units except the X pull-up units
  • a driving capability of the Y pull-down units is less than a driving capability of the remaining pull-down units except the Y pull-down units.
  • the voltage value Vblh1 of the first power supply terminal is equal to the voltage value Vblh2 of the second power supply terminal
  • the voltage value Vss1 of the third power supply terminal is equal to the voltage value Vss2 of the fourth power supply terminal.
  • the voltage value Vblh1 of the first power supply terminal and the voltage value Vblh2 of the second power supply terminal are both Vdd
  • the voltage value Vss1 of the third power supply terminal and the voltage value Vss2 of the fourth power supply terminal are both 0V.
  • the driving capability of the pull-up unit turned on at the first moment of the sensing amplification stage is less than the driving capability of the pull-up unit turned on at the second moment; the driving capability of the pull-down unit turned on at the first moment of the sensing amplification stage is less than the driving capability of the pull-down unit turned on at the second moment.
  • the pull-up speed of the voltage on the bit line Bla during the period from Q6 to Q7 is less than the pull-up speed of the voltage on the bit line Bla during the period from Q7 to Q8.
  • the driving capability of the pull-down unit turned on by Q7 at the second moment is greater than the driving capability of the pull-down unit turned on by Q6 at the first moment, the pull-down speed of the voltage on the complementary bit line BLb during the period from Q6 to Q7 is less than the pull-down speed of the voltage on the complementary bit line BLb during the period from Q7 to Q8.
  • the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb during the period from Q6 to Q7 is less than the voltage difference that can be amplified between the bit line BLa and the complementary bit line BLb during the period from Q7 to Q8.
  • the voltage difference between the bit line and the complementary bit line is gradually amplified by opening multiple pull-up units and multiple pull-down units in steps, thereby avoiding the problem of generating large coupling noise when multiple pull-up units and multiple pull-down units are opened at the same time, and reducing the influence of the voltage jump of the first port and the second port on the voltage difference between the bit line and the complementary bit line in the sensing amplification stage, so as to increase the anti-noise capability of the sensing amplifier and reduce the influence on the sensing margin.
  • the sense amplifier stabilizes the voltage on the bit line BLa at the logic data "1" corresponding to the accessed storage cell, and the voltage on the complementary bit line BLb is stabilized at the logic data "0".
  • the external read circuit can read the storage data in the accessed storage cell from the bit line BLa and the complementary bit line BLb by controlling the signal in the column selection line.
  • the bit line BLa continues to charge the storage capacitor. After a certain period of charging, the charge in the storage capacitor is restored to the state before the read operation.
  • the target word line is turned off, the first isolation signal ISO1, the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are switched from high level to low level, the first pull-up control signal SapEn1 and the first pull-down control signal SanEn1 are switched from low level to high level, the first switch K1, the second switch K2, all the pull-up units 311 and all the pull-down units 321 are in the off state.
  • the first pre-charge signal Eq1 is switched to a high level, the first charging switch CK1 and the second charging switch CK2 are in the on state, the sense amplifier enters the pre-charge stage, and the potential of the bit line BLa and the complementary bit line BLb is maintained at the first pre-charge voltage V0 (Vdd/2) through the charging power supply.
  • FIG8 is another control timing of a sense amplifier for a read operation according to the embodiment of the present disclosure.
  • the sensing amplification stage of the sense amplifier i.e., time T1 to T4: at the third time T3, the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from a valid level to an invalid level, and in response to the second pull-up control signal SapEn2 at an invalid level, the remaining pull-up units except the X pull-up units are turned off, and/or, in response to the second pull-down control signal SanEn2 at an invalid level, the remaining pull-down units except the Y pull-down units are turned off;
  • the third moment T3 is later than the second moment T2.
  • control method further includes: in a test mode, setting one or more of a first preset time, a second preset time, a first preset value, a second preset value, a value of X, and a value of Y according to a received test command; or, setting one or more of the first preset time, the second preset time, the first preset value, the second preset value, a value of X, and a value of Y through configuration parameters in a mode register.
  • the first preset time, the second preset time, the first preset value, the second preset value, the value of X and the value of Y can be changed as needed by rewriting the values of certain mode registers by setting a mode register write command.
  • the first pull-up control signal SapEn1 and the first pull-down control signal SanEn1 are flipped from the invalid level to the valid level, and one pull-up unit 311 is turned on in response to the first pull-up control signal SapEn1, and/or one pull-down unit 321 is turned on in response to the first pull-down control signal SanEn1.
  • the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the invalid level to the valid level, and the remaining pull-up units 311 except one pull-up unit 311 are turned on in response to the second pull-up control signal SapEn2, and/or, the remaining pull-down units 321 except one pull-down unit are turned on in response to the second pull-down control signal SanEn2.
  • the second moment T2 is later than the first moment T1.
  • the remaining pull-up units except 1 pull-up unit and the remaining pull-down units except 1 pull-down unit are turned on in response to the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 at the effective level.
  • the second pull-up control signal SapEn2 and the second pull-down control signal SanEn2 are flipped from the valid level to the invalid level, and in response to the second pull-up control signal SapEn2 at the invalid level, the remaining pull-up units except one pull-up unit are turned off, and/or, in response to the second pull-down control signal SanEn2 at the invalid level, the remaining pull-down units except one pull-down unit are turned off.
  • the third moment T3 is a moment that lags behind the first moment T1 by a second preset time ⁇ T2.
  • the second preset time may be determined based on a voltage difference between the bit line BLa and the complementary bit line BLb of the sense amplifier or a fixed time may be set as the second preset time.
  • the third moment T3 is the moment when the voltage difference ⁇ V2 between the bit line BLa and the complementary bit line BLb reaches the second preset value V2.
  • the voltage difference between the bit line BLa and the complementary bit line BLb that can be amplified is greater than Vdd. If all the pull-up power supplies and pull-down power supplies are turned on after the voltage difference between the bit line BLa and the complementary bit line BLb is greater than Vdd, it will lead to increased power consumption.
  • the second preset value is set to 0.9*Vdd or 0.95*Vdd.
  • the fixed time may be a design experience value or a test value.
  • the configuration parameters of the mode register may be used to control the multiplexer 720 shown in FIG. 7 to select a corresponding fixed time value as the second preset time.
  • the second preset time is set to 2ns or 2.5ns.
  • control methods of other stages in the control timing sequence of the sensing amplifier for the read operation shown in FIG. 8 can refer to the description of the control methods of the corresponding stages in FIG. 4 , which will not be repeated here.
  • the voltage difference between the bit line and the complementary bit line is gradually amplified by opening multiple pull-up units and multiple pull-down units step by step.
  • the voltages on the bit line and the complementary bit line respectively reach the voltage amplitude corresponding to the read data, that is, when the voltage difference between the bit line and the complementary bit line reaches the second preset value, some of the pull-up units and some of the pull-down units are closed, which can reduce the power consumption and noise generated when the multiple pull-up units and the multiple pull-down units are all turned on, and improve the performance of the sense amplifier.
  • the embodiment of the present disclosure further provides a memory, comprising the sense amplifier as described in any of the above embodiments.
  • the memory is dynamic random access memory (DRAM).
  • DRAM dynamic random access memory
  • the memory of the dynamic random access memory complies with the DDR4 memory specification.
  • the dynamic random access memory memory complies with the DDR5 memory specification.
  • the memory of the dynamic random access memory complies with the LPDDR4 memory specification.
  • the memory of the dynamic random access memory complies with the LPDDR5 memory specification.
  • the control method of the sense amplifier gradually amplifies the voltage difference between the bit line and the complementary bit line by opening multiple pull-up units and multiple pull-down units in steps during the sense amplification stage of the sense amplifier, thereby avoiding the problem of generating large coupling noise when multiple pull-up units and multiple pull-down units are opened at the same time, and reducing the influence of the voltage jump of the first port and the second port on the voltage difference between the bit line and the complementary bit line during the sense amplification stage, so as to increase the anti-noise capability of the sense amplifier and reduce the influence on the sensing margin.
  • the control method of the sense amplifier gradually amplifies the voltage difference between the bit line and the complementary bit line by opening multiple pull-up units and multiple pull-down units in steps during the sense amplification stage of the sense amplifier, thereby avoiding the problem of generating large coupling noise when multiple pull-up units and multiple pull-down units are opened at the same time, and reducing the influence of the voltage jump of the first port and the second port on the voltage difference between the bit line and the complementary bit line during the sense amplification stage, so as to increase the anti-noise capability of the sense amplifier and reduce the influence on the sensing margin.

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Abstract

Les modes de réalisation de la présente divulgation concernent un amplificateur de détection, son procédé de commande, et une mémoire, le procédé de commande comprenant les étapes suivantes : dans un étage d'amplification de détection d'un amplificateur de détection, activation de X unités de rappel vers le niveau haut et/ou activation de Y unités de rappel vers le niveau bas à un premier moment ; activation des unités de rappel vers le niveau haut restantes et/ou activation des unités de rappel vers le niveau bas restantes à un second moment qui est ultérieur au premier moment ; X est un nombre entier positif supérieur ou égal à 1 et inférieur ou égal à N, Y est un nombre entier positif supérieur ou égal à 1 et inférieur ou égal à M, et Y n'est pas M lorsque X est N.
PCT/CN2023/085961 2022-10-18 2023-04-03 Amplificateur de détection, son procédé de commande, et mémoire WO2024082562A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030003424A (ko) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 센스앰프 드라이버
CN105304122A (zh) * 2014-06-16 2016-02-03 爱思开海力士有限公司 半导体器件
CN106024053A (zh) * 2015-03-27 2016-10-12 爱思开海力士有限公司 感测放大器驱动器件及包括其的半导体器件
CN114730586A (zh) * 2020-02-06 2022-07-08 长鑫存储技术有限公司 感测放大器电路、存储器及其操作方法
CN115457997A (zh) * 2022-10-18 2022-12-09 长鑫存储技术有限公司 一种感测放大器及其控制方法、存储器

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010004910A (ko) * 1999-06-30 2001-01-15 김영환 센스 앰프
KR100331550B1 (ko) * 1999-09-02 2002-04-06 윤종용 반도체 메모리장치의 감지증폭기
KR100568253B1 (ko) * 2003-12-01 2006-04-07 삼성전자주식회사 반도체 메모리 장치 및 그의 기입 제어 방법
KR20050097066A (ko) * 2004-03-30 2005-10-07 주식회사 하이닉스반도체 비트라인 센스 증폭기 구동 회로
KR102234600B1 (ko) * 2014-07-09 2021-04-02 삼성전자주식회사 트랜지스터들 간의 미스매치를 보상할 수 있는 비트라인 센스 증폭기 및 이를 포함하는 반도체 메모리 장치
US11495284B2 (en) * 2020-07-17 2022-11-08 Samsung Electronics Co., Ltd. Memory device including bitline sense amplifier and operating method thereof
CN114863961A (zh) * 2022-05-09 2022-08-05 长鑫存储技术有限公司 灵敏放大器、存储器以及控制方法
CN114999543A (zh) * 2022-06-20 2022-09-02 长江存储科技有限责任公司 感测放大电路、存储装置、操作方法及系统
CN115620761A (zh) * 2022-10-21 2023-01-17 长鑫存储技术有限公司 灵敏放大器、存储器及其操作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030003424A (ko) * 2001-06-30 2003-01-10 주식회사 하이닉스반도체 센스앰프 드라이버
CN105304122A (zh) * 2014-06-16 2016-02-03 爱思开海力士有限公司 半导体器件
CN106024053A (zh) * 2015-03-27 2016-10-12 爱思开海力士有限公司 感测放大器驱动器件及包括其的半导体器件
CN114730586A (zh) * 2020-02-06 2022-07-08 长鑫存储技术有限公司 感测放大器电路、存储器及其操作方法
CN115457997A (zh) * 2022-10-18 2022-12-09 长鑫存储技术有限公司 一种感测放大器及其控制方法、存储器

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