WO2024077827A1 - 半导体结构制备方法及半导体结构 - Google Patents

半导体结构制备方法及半导体结构 Download PDF

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Publication number
WO2024077827A1
WO2024077827A1 PCT/CN2023/076179 CN2023076179W WO2024077827A1 WO 2024077827 A1 WO2024077827 A1 WO 2024077827A1 CN 2023076179 W CN2023076179 W CN 2023076179W WO 2024077827 A1 WO2024077827 A1 WO 2024077827A1
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preset
semiconductor structure
insulating material
layer
preparing
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PCT/CN2023/076179
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English (en)
French (fr)
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钱龙
杨琪
金炳秀
赵丹丹
周浩磊
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长鑫存储技术有限公司
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Publication of WO2024077827A1 publication Critical patent/WO2024077827A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure preparation method and a semiconductor structure.
  • Memory is a storage component used to store programs and various data information. It can be divided into ROM (Read-Only Memory) and RAM (Random Access Memory) according to the usage type of the memory. According to the different working principles of the storage unit, random access memory is divided into SRAM (Static RAM) and DRAM (Dynamic RAM). Compared with SRAM, DRAM has the advantages of high integration, low power consumption and low price, and is widely used in large-capacity storage.
  • a method for preparing a semiconductor structure and a semiconductor structure are provided.
  • one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a chip structure and a cutting path alternately distributed along a first direction on the substrate according to a preset rule, and an initial trench isolation structure located within the cutting path, the material of the initial trench isolation structure being a first insulating material; etching the initial trench isolation structure to obtain a preset isolation trench; the preset isolation trench exposes a target reference layer, the target reference layer being an adjacent layer to the initial trench isolation structure along its thickness direction; filling a second insulating material in the preset isolation trench, the hardness of the second insulating material being greater than the hardness of the first insulating material.
  • the first insulating material has a relative dielectric constant less than or equal to 3.0.
  • the target reference layer includes a third insulating material having a hardness greater than a hardness of the first insulating material, and the second insulating material is the same as the third insulating material.
  • the preset rule includes: if the distance between two adjacent chip structures along the first direction is less than a first preset threshold, then an initial trench isolation structure is not formed between the two adjacent chip structures; otherwise, an initial trench isolation structure is formed between the two adjacent chip structures.
  • the initial trench isolation structure and the distances between two adjacent chip structures are equal, and are both first preset distances.
  • test pads electrically connected to active areas in the substrate are distributed in the cutting lanes; a second preset spacing is provided between the initial trench isolation structure and the test pads adjacent thereto along a second direction, the second preset spacing is smaller than the first preset spacing, and the second direction intersects the first direction.
  • the initial trench isolation structure and the test pad adjacent to each other along the second direction are at least partially located on the same target straight line, and the target straight line is parallel to the second direction.
  • etching the initial trench isolation structure to obtain the preset isolation trench includes: over-etching the initial trench isolation structure to obtain the preset isolation trench with the bottom extending into the target reference layer.
  • filling the preset isolation trench with the second insulating material includes: using a high-density plasma deposition process and/or an atomic layer deposition process to fill the preset isolation trench with the second insulating material to form a first dielectric layer, wherein the first dielectric layer fills the preset isolation trench and covers the top surface of the chip structure and the top surface of the cutting path.
  • the method further includes: forming a first dielectric layer on a surface away from the substrate. Insulation protective layer.
  • a top surface of the insulating protection layer has a target groove, and the target groove is located directly above the preset isolation trench.
  • the material of the insulating protection layer is different from that of the first dielectric layer; and the material of the insulating protection layer is selected from silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or a combination thereof.
  • a method for preparing a semiconductor structure includes: a first preset threshold is selected from 25 ⁇ m-35 ⁇ m; and a second insulating material is selected from silicon oxide, carbon silicon oxyhydride, fluorine-doped silicon oxide, silicon carbide, silicon carbon nitride or a combination thereof.
  • the first preset spacing ranges from 13 ⁇ m to 16 ⁇ m.
  • the second preset spacing ranges from 2.4 ⁇ m to 2.7 ⁇ m.
  • the material of the test pad is selected from titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper, or a combination thereof.
  • another aspect of the present disclosure provides a semiconductor structure, which is prepared by the semiconductor structure preparation method in any of the above embodiments.
  • the second insulating material with greater hardness in the cutting path due to the second insulating material with greater hardness in the cutting path, defects such as peeling or cracking can be effectively avoided during wafer cutting, thereby improving product yield and reducing the process cost of wafer cutting.
  • the relative dielectric constant of the first insulating material is less than or equal to 3.0, the low dielectric constant material can reduce the leakage current of the integrated circuit, reduce the parasitic capacitance between the wires, reduce the heat generation of the integrated circuit, and reduce the parasitic effects between the displaced conductor layers.
  • the semiconductor structure preparation method and the semiconductor structure provided by the embodiments of the present disclosure can at least reduce the problems of peeling and cracking generated during the wafer cutting process.
  • FIG1 is a schematic diagram of a process for preparing a semiconductor structure according to an embodiment of the present disclosure
  • FIG2a is a schematic top view of a cross-sectional structure obtained by a method for preparing a semiconductor structure in one embodiment of the present disclosure
  • FIG2 b is a schematic top view of a cross-sectional structure obtained by a method for preparing a semiconductor structure in another embodiment of the present disclosure
  • 3a to 10 are schematic diagrams of cross-sectional structures obtained in different steps of a method for preparing a semiconductor structure in an embodiment of the present disclosure.
  • the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like, may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.
  • DRAM dynamic random access memory
  • RC Delay resistance-capacitance delay
  • researchers are constantly looking for low-dielectric constant materials to act as dielectric layers, thereby reducing the parasitic capacitance in the back-end.
  • the elastic modulus and hardness of low-dielectric constant materials are relatively small. In the process of cutting wafers during subsequent packaging, low-dielectric constant materials are prone to defects such as peeling or cracking, thereby affecting the product yield.
  • the present disclosure provides a method for preparing a semiconductor structure, including:
  • Step S202 providing a substrate
  • Step S204 forming chip structures and cutting streets alternately distributed along a first direction and an initial trench isolation structure located in the cutting streets on the substrate according to a preset rule, wherein the material of the initial trench isolation structure is a first insulating material;
  • Step S206 etching an initial trench isolation structure to obtain a preset isolation trench
  • Step S208 Preset the isolation trench to expose a target reference layer, where the target reference layer is a layer adjacent to the initial trench isolation structure along its thickness direction;
  • Step S210 filling a second insulating material in the predetermined isolation trench, wherein the hardness of the second insulating material is greater than the hardness of the first insulating material.
  • an initial trench isolation structure 41 is first pre-formed on the cutting road 40 according to a preset rule, and then the initial trench isolation structure 41 is etched to obtain a preset isolation trench. Then, a second insulating material is filled in the preset isolation trench, and the first insulating material originally in the initial trench isolation structure is replaced with a second insulating material with greater hardness.
  • the second insulating material with greater hardness in the cutting road in the semiconductor structure of this embodiment can effectively avoid defects such as peeling or cracking during wafer cutting, thereby improving product yield and reducing the process cost of wafer cutting.
  • the dielectric layer is easily severely peeled or cracked when the cutting knife is cutting, resulting in defects such as peeling and cracking. Peeling occurs due to the poor adhesion between the dielectric layer and the etch stop layer. Peeling may occur during the production process of semiconductor devices, or during the reliability test of the adhesion strength between the passivation layer and the external leads after the semiconductor device is produced. Defects such as peeling and cracking during the production process will cause the subsequent metal layer to warp or crack, affecting its electrical connection and ultimately causing electrical failure of the semiconductor device.
  • the substrate 10 in step S202 can be made of semiconductor material, insulating material, conductor material or any combination thereof.
  • the substrate 10 can be a single-layer structure or a multi-layer structure.
  • the substrate 10 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III/V semiconductor substrates or II/VI semiconductor substrates.
  • the substrate 10 can be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator. Therefore, the type of substrate 10 should not limit the scope of protection of the present disclosure.
  • P-type ions can be implanted into the substrate 10 by an ion implantation process to form a first type doped well region (not shown), and the P-type ions can include but are not limited to any one or more of boron (B) ions, gallium (Ga) ions, boron fluoride (BF 2 ) ions and indium (In) ions.
  • a chip structure 30 and a cutting path 40 are alternately distributed along a first direction on the substrate 10 according to a preset rule, and an initial trench isolation structure 41 is located in the cutting path 40.
  • the material of the initial trench isolation structure 41 is a first insulating material, and the first direction can be the ox direction.
  • the wafer is composed of a plurality of chips, and the chips are separated by cutting paths 40. Each chip is formed on the substrate 10 through processes such as deposition, etching, doping and heat treatment, wherein the chip structure 30 is used to form a device structure later, and the cutting path 40 is used as a cutting line for dividing the chip structure 30 in the packaging stage when the semiconductor structure is completed.
  • the relative dielectric constant of the first insulating material in the initial trench isolation structure 41 is less than or equal to 3.0.
  • the relative dielectric constant of the first insulating material in the initial trench isolation structure 41 can be 1.0, 2.2, 2.7, 2.6, 2.7, 2.9 or 3.0, etc.
  • the first insulating material can be porous carbon-doped oxide, nanoporous organic silicate, dry glue, aerogel, fluorine-doped amorphous carbon film, polyparaxylene, benzocyclobutene, SiLK and black diamond film (Black Diamond film, BD film).
  • BD film is a composite dielectric material SiOC:H prepared by introducing -CH 3 into a silicon dioxide substrate.
  • BD film has the characteristics of low dielectric constant and high performance.
  • Low dielectric constant materials can reduce the leakage current of integrated circuits, reduce parasitic capacitance between wires, reduce heating of integrated circuits, and reduce parasitic effects between displaced conductor layers.
  • Material hardness and elastic modulus are very important for cutting processes. However, the elastic modulus and hardness of the low dielectric constant material are relatively small. When cutting the wafer, the low dielectric constant material in the cutting lane 40 is prone to defects such as peeling and cracking, thereby affecting the product yield.
  • the preset rules in step S204 include: if the spacing between two adjacent chip structures 30 along the first direction is less than the first preset threshold, then an initial trench isolation structure 41 is not formed between the two adjacent chip structures 30; otherwise, an initial trench isolation structure 41 is formed between the two adjacent chip structures 30 to avoid damaging the internal structure of the chip when the wafer is cut due to the small spacing between the chip structures 30.
  • the first direction can be the ox direction.
  • the initial trench isolation structure 41 and the two adjacent chip structures 30 along the first direction have the same spacing, which are both the first preset spacing L1.
  • the first direction may be the ox direction.
  • test pads 42 electrically connected to the active area in the substrate 10 are distributed in the cutting road 40; the initial trench isolation structure 41 and the test pads 42 adjacent to it along the second direction have a second preset spacing L2, the second preset spacing L2 is less than the first preset spacing L1, the second direction intersects with the first direction, the first direction can be the ox direction, and the second direction can be the oy direction.
  • the test pad 42 is a test element added to a fixed position of the wafer in the semiconductor process factory in order to monitor the process during wafer processing.
  • the test pad 42 can be tested by performing a wafer parameter test (Wafer Acceptance Test, WAT) on the test pad 42 to obtain electrical parameters to monitor whether each step of the process is normal and stable.
  • WAT wafer Acceptance Test
  • the probe contacts the test pads 42 corresponding to the single or multiple chip structures 30 on the wafer, and the power supply and signal can be transmitted to the chip structures 30 in all or selected areas on the wafer through the input channel. After the chip structure 30 is formed on the wafer, it must go through WAT before it can be shipped.
  • the main purpose of WAT is to simulate the circuit designed by the customer and monitor the stability of the process to improve the product yield, reflect the problems of the production line by testing the basic electrical parameters, and determine whether there are problems with disconnection or bridging by measuring the electrical parameters during the operation of the circuit.
  • the cutting path 40 can also include components other than the test pad 42 in the test component group.
  • the test pad 42 can be set as a plurality of long strip substructures distributed at intervals to reduce the material and save costs. By setting the initial trench isolation structure 41 and the test pad 42 adjacent to it along the second direction, the initial trench isolation structure 41 can be separated from the test pad 42 by a plurality of strip substructures distributed at intervals to reduce the material and save costs. There is a second preset distance L2 to avoid damaging the test pads 42 in the dicing street 40 during wafer dicing.
  • the initial trench isolation structure 41 and the test pad 42 adjacent along the second direction are at least partially located on the same target straight line, and the target straight line is parallel to the second direction, and the second direction can be the oy direction.
  • This embodiment facilitates wafer cutting while avoiding damage to the functional structure in the cutting road 40, and meets the actual needs of various different application scenarios.
  • the cutting operation is performed on the active side of the wafer, where the chip structure 30 and the multi-layer wire layer of the chip structure 30 are formed.
  • the cutting lane 40 is located in the area between each individual chip structure 30.
  • the cutting lane 40 does not have the circuit elements of the chip structure 30 and because each chip structure 30 is an independent device, the metal body used for the internal connection conductor does not extend or cross into the cutting lane 40, but is confined to the chip structure 30 to prevent the cutting knife from cutting the wire layer.
  • some test pads 42 and baffles 43 used for wafer reliability or functional testing are set in the cutting lane 40 to facilitate wafer testing.
  • the preset rule stipulates that there is a first preset spacing L1 between the initial trench isolation structure 41 and the two chip structures 30 adjacent along the first direction, and a second preset spacing L2 between the initial trench isolation structure 41 and the test pad 42 adjacent to it along the second direction, and that the initial trench isolation structure 41 and the test pad 42 are at least partially located on the same target straight line, so that during the cutting operation, the cutting knife will not cut the test pad 42 and the baffle 43, thereby avoiding the occurrence of defects such as peeling and cracking.
  • step S206 of etching the initial trench isolation structure to obtain the preset isolation trench includes:
  • Step S2061 over-etching the initial trench isolation structure to obtain a preset isolation trench with a bottom extending into the target reference layer.
  • step S2061 the material of the initial trench isolation structure can be removed by controlling the etching rate and time, and then etching is continued for a preset time to obtain a preset isolation trench with the bottom extending into the target reference layer, thereby avoiding residual material of the initial trench isolation structure.
  • step S2061 over-etches the initial trench isolation structure to obtain a preset isolation trench with the bottom extending into the target reference layer, including:
  • Step S20611 forming a sacrificial layer covering the top surface of the chip structure and the top surface of the scribe line;
  • Step S20612 forming a patterned photoresist layer on the top surface of the sacrificial layer
  • Step S20613 over-etching the sacrificial layer and the initial trench isolation structure based on the patterned photoresist layer to obtain a preset isolation trench with a bottom extending into the target reference layer.
  • a deposition process can be used to form a sacrificial layer 50 on the top surface of the chip structure 30 and the top surface of the cutting path 40.
  • the sacrificial layer 50 can be a single-layer structure or a multi-layer stacked structure.
  • the material of the sacrificial layer 50 can be a hard mask, a spin-on hard mask (SOH), a photoresist or a combination thereof.
  • SOH is an auxiliary material for making semiconductor micro-patterns, which can fill the gap to make the surface flatter and enhance corrosion resistance. It should be understood that the sacrificial layer 50 involved in the present disclosure is a film layer that needs to be removed after the target pattern is formed.
  • the deposition process may include but is not limited to Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma Deposition (HDP), and other processes.
  • the sacrificial layer 50 may be formed by one or more processes such as HDP, plasma enhanced deposition, and spin-on dielectric (SOD).
  • the sacrificial layer 50 may be formed by an atomic layer deposition process. Since the atomic layer deposition process has excellent conformality and uniformity when depositing on a three-dimensional complex surface, a uniform sacrificial layer 50 may be formed on the top surface of the chip structure 30 and the top surface of the cutting path 40, thereby improving the conformality, uniformity, and coverage of the process of depositing the sacrificial layer 50.
  • a photoresist material layer 61 is coated on the top surface of the sacrificial layer 50, and a patterned photoresist layer 60 is formed through a series of steps such as exposure and development.
  • the patterned photoresist layer 60 has an opening pattern that defines the position and shape of a preset isolation groove 70.
  • the photoresist can be a positive photoresist or a negative photoresist, and the development method can be a positive development or a negative development.
  • an etching process can be used to etch the sacrificial layer 50 and the cutting path 40 using the patterned photoresist layer 60 as a mask to obtain a preset isolation groove 70.
  • the etching process may include, but is not limited to, a dry etching process and/or a wet etching process.
  • the dry etching process may include, but is not limited to, one or more of reactive ion etching (RIE), inductively coupled plasma etching (ICP), and high concentration plasma etching (HDP).
  • RIE reactive ion etching
  • ICP inductively coupled plasma etching
  • HDP high concentration plasma etching
  • a plasma etching process may be used to etch the sacrificial layer 50 and the cutting path 40.
  • Plasma etching refers to the use of a high-frequency glow discharge reaction to activate the reaction gas into active particles, such as from or free radicals. These active particles diffuse to the etched part and react with the etched material to form volatile products and be removed to achieve the purpose of etching.
  • the etching gas may include NF3, CF3, HF, CHF4 or a combination thereof, thereby increasing the etching rate.
  • step S20613 removes the remaining patterned photoresist layer 60 and the sacrificial layer 50 to expose the top surface of the chip structure 30.
  • the removal method may include ashing and wet cleaning; for the sacrificial layer 50 composed of a hard mask, etc., the removal method includes wet etching and/or dry etching, and the dry etching process may include but is not limited to one or more of RIE, ICP, HDP, etc.
  • the sacrificial layer 50 may be etched using a laser etching process.
  • the laser etching process is to use a high-energy laser beam to irradiate the surface of the etched part to melt or vaporize it, forming a groove of a certain depth to achieve the purpose of etching the material.
  • the use of the laser etching process can improve the yield and stability of the product, and realize one-time molding of different graphics and different angles, without consumables, pollution, and low cost.
  • the preset isolation trench 70 exposes the target reference layer 20, and the target reference layer 20 is an adjacent layer to the initial trench isolation structure 41 along its thickness direction.
  • the target reference layer 20 is an adjacent layer to the initial trench isolation structure 41 along its thickness direction, including the target reference layer 20 and the initial trench isolation structure 41 being directly adjacent to each other along the thickness direction of the target reference layer 20 or the target reference layer 20 and the initial trench isolation structure 41 being adjacent to each other along the thickness direction of the target reference layer 20 with an intermediate dielectric layer, and the thickness direction of the target reference layer 20 may be the oy direction.
  • the target reference layer 20 includes a third insulating material having a hardness greater than that of the first insulating material, and the second insulating material is the same as the third insulating material.
  • the material of the third insulating material is selected from silicon oxide, carbon silicon oxyhydride, fluorine-doped silicon oxide, silicon carbide, silicon nitride carbon or a combination thereof to meet the actual needs of different application scenarios.
  • filling the second insulating material in the predetermined isolation trench 70 includes: using a high The density plasma deposition process and/or the atomic layer deposition process fills the preset isolation groove 70 with a second insulating material to form a first dielectric layer 80.
  • the first dielectric layer 80 fills the preset isolation groove 70 and covers the top surface of the chip structure 30 and the top surface of the cutting path 40.
  • the first dielectric layer 80 replaces the first insulating material in the preset isolation groove 41 with the second insulating material of the first dielectric layer 80.
  • the hardness of the second insulating material is greater than that of the first insulating material.
  • the second insulating material with a hardness greater than that of the first insulating material can avoid defects such as peeling or cracking during wafer cutting, improve product yield, and reduce the process cost of wafer cutting.
  • a high-density plasma deposition process can be used to fill the preset isolation trench 70 with a second insulating material to form a first dielectric layer 80, and the first dielectric layer 80 fills the preset isolation trench 70 and covers the top surface of the chip structure 30 and the top surface of the cutting path 40.
  • the high-density plasma deposition process can be a high-density plasma chemical vapor deposition (HDP CVD) process.
  • the HDP CVD process is a process that performs deposition and etching simultaneously in the same reaction chamber, and the gas used in the reaction can be selected from silane, oxygen, hydrogen, argon, helium or a combination thereof.
  • the deposition process is usually achieved by the reaction of silane and oxygen, and the etching process is usually completed by sputtering of argon and oxygen.
  • the deposition process of the HDP CVD process can be roughly divided into two steps. The first step is to use an unbiased RF power source to deposit a layer of oxygen-rich silicon dioxide as a protective layer; the second step is to use a biased RF power source to deposit the main film. Since the silicon dioxide deposited in the first step is used as a protective layer, the plasma damage in the second step of depositing the main film will be partially absorbed by the protective layer. Therefore, the plasma damage in the deposition process of the HDP CVD process is relatively small.
  • the film produced by the lack of plasma-assisted deposition will depend on the surface of the lower layer and show different deposition characteristics. In addition, it has low density and moisture absorption.
  • the HDP CVD process has excellent hole filling ability, stable deposition quality and reliable electrical characteristics in the process of synchronous deposition and etching in the same reaction chamber. Therefore, according to the characteristics of the high-density plasma deposition process itself, the high-density plasma deposition process is used to form the first dielectric layer 80, so as to achieve excellent filling of the high aspect ratio interval of the preset isolation trench 70, and make the deposited first dielectric layer 80 have the advantages of high density, low impurity defects and excellent adhesion to the silicon wafer, so as to avoid the generation of air gaps.
  • an atomic layer deposition process can also be used to form a first dielectric layer 80 in the preset isolation groove 70, and the first dielectric layer 80 fills the preset isolation groove 70 and covers the top surface of the chip structure 30 and the top surface of the cutting path 40.
  • the atomic layer deposition process is a technology that forms a deposited film by alternately passing a gas phase precursor pulse into a reactor and chemically adsorbing and reacting on a deposition substrate. When the precursor reaches the surface of the deposition substrate, it will chemically adsorb on its surface and react on the surface.
  • the surface reaction of atomic layer deposition is self-limiting. The desired structure is formed by continuously repeating the self-limiting reaction in atomic layer deposition.
  • the precursor material may include a non-metallic precursor material and/or a metal precursor material.
  • non-metallic precursors include halides (SiCl 4 or AlCl 3 , etc.), nitrides (NH 3 , (CH 3 )NH 2 or BuNH 2 , etc.), and metal precursors include alkyl precursors (Ga(CH 3 ) 3 or Mg(C 2 H 5 ) 2 ), ⁇ -diketone precursors (La(thd) 3 or Ca(thd) 2 ), alkoxide precursors (Ta(OC 2 H 5 ) 5 or Zr[(OC)(CH 3 ) 3 ] 4 ), or alkylamine and silanamine-based precursors (Ti[N(C 2 H 5 CH 3 ) 2 ] 4 or Pr[N(SiMe 3 ) 2 ] 3 ) etc.; Traditional solution chemical deposition technology and physical deposition technology such as sputtering or evaporation have poor deposition effects on the surface of three-dimensional
  • atomic layer deposition technology is based on surface self-limitation and self-saturation adsorption reactions, thus It has surface controllability, and the prepared structure has excellent three-dimensional conformality and large-area uniformity. It is more adaptable to complex high-aspect-ratio surface deposition processes.
  • the atomic layer deposition process can produce a smooth surface morphology, which fits the filling layer tightly, thereby reducing the stress generated by the deposition process.
  • the atomic layer deposition low-fluorine tungsten technology can reduce the stress by an order of magnitude (GPa to hMPa), the fluorine content by 99%, and the resistivity by 30%.
  • the atomic layer deposition process is used to form the first dielectric layer 80 to achieve uniform coverage of the preset isolation groove 70, the top surface of the chip structure 30 and the cutting path 40, so that the conformality, uniformity and coverage of the deposition process of the first dielectric layer 80 are improved, and air gaps are avoided.
  • the temperature range of the high-density plasma deposition process can be set to 300° C.-500° C., for example, the temperature of the high-density plasma deposition process can be set to 300° C., 400° C., or 500° C., etc.
  • the pressure range of the reaction chamber of the high-density plasma deposition process can be set to 1 Torr-10 Torr, for example, the pressure of the reaction chamber of the high-density plasma deposition process can be set to 1 Torr, 3 Torr, 5 Torr, 7 Torr, 9 Torr, or 10 Torr, etc.
  • the flow rate of the gas in the high-density plasma deposition process can be set to 100 sccm-1000 sccm, for example, the flow rate of the gas in the high-density plasma deposition process can be set to 100 sccm, 300 sccm, 500 sccm, 700 sccm, 900 sccm, or 1000 sccm, etc.
  • the RF power range of the high-density plasma deposition process can be set to 1000-8000W.
  • the RF power of the high-density plasma deposition process can be set to 1000W, 3000W, 5000W, 7000W or 8000W, etc., so as to improve the adaptability to deposition of different structures and materials, accurately and controllably reduce parasitic capacitance, and further improve the reliability and stability of semiconductor devices.
  • the deposition rate of the atomic layer deposition process can be set to a range of 0.5 angstroms per second to 2 angstroms per second, for example, the deposition rate of the atomic layer deposition process can be set to 0.5 angstroms per second, 0.8 angstroms per second, 1.1 angstroms per second, 1.4 angstroms per second, 1.7 angstroms per second, or 2 angstroms per second.
  • the atomic layer deposition process pressure can be set to a range of 0.1 torr-50 torr, for example, the atomic layer deposition process pressure can be set to 0.1 torr, 0.5 torr, 2.5 torr, 12.5 torr, or 50 torr.
  • the atomic layer deposition process temperature can be set to a range of 25°C-600°C, for example, the atomic layer deposition process temperature can be set to 25°C, 140°C, 255°C, 370°C, 485°C, or 600°C.
  • the flow rate of oxygen in the atomic layer deposition process can be set to a range of 0.1L-10L, for example, the flow rate of oxygen in the atomic layer deposition process can be set to 0.1L, 0.5L, 1L, 5L, or 10L.
  • the precursor material of the atomic layer deposition process may include silane, for example, the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the silane includes: di(isopropylamino)silane, bis(tert-butylamino)silane, bis(diethylamino)silane or a combination thereof.
  • the method further includes: forming an insulating protection layer 90 on a surface of the first dielectric layer 80 away from the substrate 10 .
  • a deposition process may be used to form an insulating protective layer 90 on the surface of the first dielectric layer 80 away from the substrate 10, and the deposition process may include but is not limited to one or more of CVD, ALD, HDP process, SOD process, etc.
  • the formation of the insulating protective layer 90 can prevent short circuits and leakage caused by the solder easily moving to the side of the semiconductor device during the subsequent semiconductor device packaging process.
  • the insulating protective layer 90 can separate the solder to avoid Solder climb causes short circuits and sparks.
  • first dielectric layer 80 and the insulating protection layer 90 are not deposited after the initial trench isolation structure 41 is over-etched to obtain the preset isolation trench 70 whose bottom extends to the target reference layer 20, it is easy to cause an air gap inside the wafer, and the stress at various positions of the wafer is difficult to control, resulting in defects such as peeling and cracking. After the first dielectric layer 80 and the insulating protection layer 90 are deposited, the stress at various positions of the wafer is similar, avoiding defects such as peeling and cracking.
  • the top surface of the insulating protection layer 90 has a target groove 91, and the target groove 91 is located directly above the preset isolation groove 70, making it easier to find the cutting position when cutting the wafer, which is more conducive to wafer cutting and improves product yield.
  • the material of the insulating protection layer 90 is different from the material of the first dielectric layer 80; and the material of the insulating protection layer 90 is selected from silicon oxide, silicon nitride, silicon carbide, silicon nitride oxide or a combination thereof to meet the actual needs of different application scenarios.
  • the method for preparing the semiconductor structure 100 includes: the spacing between two adjacent chip structures 30 along the first direction is less than a first preset threshold, the first preset threshold is selected from 25 ⁇ m-35 ⁇ m, for example, the first preset threshold can be: 25 ⁇ m, 27 ⁇ m, 29 ⁇ m, 31 ⁇ m, 33 ⁇ m or 35 ⁇ m, etc., the first direction can be the ox direction; the material of the second insulating material is selected from silicon oxide, carbon silicon oxyhydride, fluorine-doped silicon oxide, silicon carbide, silicon carbon nitride or a combination thereof to meet the actual needs of different application scenarios.
  • the spacing between the initial trench isolation structure 41 and the two adjacent chip structures 30 is a first preset spacing L1
  • the range of the first preset spacing L1 is 13 ⁇ m-16 ⁇ m.
  • the first preset spacing can be 13 ⁇ m, 14 ⁇ m, 15 ⁇ m or 16 ⁇ m, etc.
  • the spacing between the initial trench isolation structure 41 and the test pad 42 adjacent to it along the second direction is a second preset spacing L2, and the range of the second preset spacing L2 is 2.4 ⁇ m-2.7 ⁇ m.
  • the second preset spacing can be: 2.4 ⁇ m, 2.45 ⁇ m, 2.5 ⁇ m, 2.55 ⁇ m, 2.6 ⁇ m, 2.65 ⁇ m or 2.7 ⁇ m, etc.
  • the second direction can be the oy direction.
  • the material of the test pad 42 is selected from titanium, tungsten, nickel, gold, silver, tungsten silicide, aluminum, palladium, copper or a combination thereof to meet the actual needs of different application scenarios.
  • a semiconductor structure 100 is provided, which is manufactured by using the semiconductor structure manufacturing method in any of the above embodiments.
  • an initial cutout is pre-formed on the cutting path 40 according to a preset rule.
  • An initial trench isolation structure 41 is formed, and after etching the initial trench isolation structure 41 to obtain a preset isolation trench 70, a second insulating material is filled in the preset isolation trench 70, and the first insulating material originally in the initial trench isolation structure 41 is replaced with a second insulating material with greater hardness.
  • the second insulating material with greater hardness in the cutting path 40 in the semiconductor structure 100 of this embodiment can effectively avoid defects such as peeling or cracking during the wafer cutting process, thereby improving the product yield and reducing the process cost of wafer cutting.

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Abstract

本公开涉及一种半导体结构制备方法及半导体结构，半导体结构制备方法包括：提供衬底；按照预设规则于衬底上形成沿第一方向交替分布的芯片结构及切割道，以及位于切割道内的初始沟槽隔离结构，初始沟槽隔离结构的材料为第一绝缘材料；刻蚀初始沟槽隔离结构，得到预设隔离沟槽；预设隔离沟槽暴露出目标参考层，目标参考层为与初始沟槽隔离结构沿其厚度方向的相邻层；于预设隔离沟槽内填充第二绝缘材料，第二绝缘材料的硬度大于第一绝缘材料的硬度。

Description

半导体结构制备方法及半导体结构
相关申请的交叉引用
本公开要求于2022年10月13日提交中国专利局、申请号为202211255077.4、申请名称为“半导体结构制备方法及半导体结构”的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体制造领域，特别是涉及半导体结构制备方法及半导体结构。
背景技术
存储器是用来存储程序和各种数据信息的记忆部件，按存储器的使用类型可分为ROM(Read-Only Memory，只读存储器)和RAM(Random Access Memory，随机存取存储器)，根据存储单元的工作原理不同，随机存取存储器分为SRAM(Static RAM，静态随机存取存储器)和DRAM(Dynamic RAM，动态随机存取存储器)，DRAM与SRAM相比具有集成度高、功耗低及价格便宜等优点，在大容量存储器中被普遍采用。
然而，在存储器的制造工艺中，随着工艺节点的不断缩小，低介电常数材料的应用，在后续封装过程中切割晶圆时会出现剥离及崩裂等缺陷。
发明内容
根据本公开的各种实施例，提供一种半导体结构制备方法及半导体结构。
根据一些实施例，本公开的一方面提供一种半导体结构制备方法，包括：提供衬底；按照预设规则于衬底上形成沿第一方向交替分布的芯片结构及切割道，以及位于切割道内的初始沟槽隔离结构，初始沟槽隔离结构的材料为第一绝缘材料；刻蚀初始沟槽隔离结构，得到预设隔离沟槽；预设隔离沟槽暴露出目标参考层，目标参考层为与初始沟槽隔离结构沿其厚度方向的相邻层；于预设隔离沟槽内填充第二绝缘材料，第二绝缘材料的硬度大于第一绝缘材料的硬度。
根据一些实施例，第一绝缘材料的相对介电常数小于或等于3.0。
根据一些实施例，目标参考层包括硬度大于第一绝缘材料的硬度的第三绝缘材料，第二绝缘材料与第三绝缘材料相同。
根据一些实施例，预设规则包括：若沿第一方向相邻的两个芯片结构的间距小于第一预设阈值，则不在相邻的两个芯片结构之间形成初始沟槽隔离结构；反之，则在相邻的两个芯片结构之间形成初始沟槽隔离结构。
根据一些实施例，初始沟槽隔离结构与相邻的两个芯片结构之间的间距相等，均为第一预设间距。
根据一些实施例，切割道内分布有与衬底内有源区电连接的测试垫；初始沟槽隔离结构与其沿第二方向相邻的测试垫之间具有第二预设间距，第二预设间距小于第一预设间距，第二方向与第一方向相交。
根据一些实施例，沿第二方向相邻的初始沟槽隔离结构与测试垫均至少部分位于同一目标直线上，目标直线与第二方向平行。
根据一些实施例，刻蚀初始沟槽隔离结构，得到预设隔离沟槽包括：过刻蚀初始沟槽隔离结构，得到底部延伸至目标参考层内的预设隔离沟槽。
根据一些实施例，于预设隔离沟槽内填充第二绝缘材料包括：采用高密度等离子体沉积工艺及/或原子层沉积工艺于预设隔离沟槽内填充第二绝缘材料，形成第一介质层，第一介质层填充满预设隔离沟槽并覆盖芯片结构的顶面及切割道的顶面。
根据一些实施例，在形成第一介质层之后还包括：于第一介质层远离衬底的表面形成 绝缘保护层。
根据一些实施例，绝缘保护层的顶面具有目标凹槽，目标凹槽位于预设隔离沟槽的正上方。
根据一些实施例，绝缘保护层的材料与第一介质层的材料不同；以及绝缘保护层的材料选自氧化硅、氮化硅、氮碳化硅、氮氧化硅或其组合。
根据一些实施例，半导体结构制备方法包括：第一预设阈值选自25μm-35μm；第二绝缘材料选自氧化硅、碳硅氧氢化物、掺氟氧化硅、碳化硅、氮化硅碳或其组合。
根据一些实施例，第一预设间距的范围包括：13μm-16μm。
根据一些实施例，第二预设间距的范围包括：2.4μm-2.7μm。
根据一些实施例，测试垫的材料选自钛、钨、镍、金、银、硅化钨、铝、钯、铜或其组合。
根据一些实施例，本公开的另一方面提供了一种半导体结构，采用上述任一实施例中半导体结构制备方法制备而成。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的半导体结构制备方法及半导体结构中，由于切割道内硬度更大的第二绝缘材料，可以有效地避免晶圆切割过程中出现剥离或崩裂等缺陷，从而提高产品良率，降低晶圆切割的工艺成本。由于第一绝缘材料的相对介电常数小于或等于3.0，低介电常数材料可以降低集成电路的漏电流、降低导线之间的寄生电容、降低集成电路发热，以及减少移位的导体层之间的寄生效应。通过设置沿第二方向相邻的初始沟槽隔离结构与测试垫均至少部分位于同一目标直线上，目标直线与第二方向平行，方便晶圆切割的同时避免破坏切割道中的功能结构。
综上，本公开实施例提供的半导体结构制备方法及半导体结构，至少能够减少在切割晶圆过程中产生剥离及崩裂等问题。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种半导体结构制备方法的流程示意图；
图2a为本公开一实施例中半导体结构制备方法所得截面结构俯视图示意图；
图2b为本公开另一实施例中半导体结构制备方法所得截面结构俯视图示意图；
图3a-图10为本公开一实施例中半导体结构制备方法中不同步骤所得截面结构示意图。
具体实施方式
为了便于理解本公开，下面将参阅相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的 实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本公开的基本构想，虽图示中仅显示与本公开中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
随着集成电路制造工艺的不断发展，半导体器件的集成度不断提高，动态随机存取存储器(Dynamic Random Access Memory，DRAM)的尺寸在不断缩小,后段的电阻─电容延时(RC Delay)在不断影响着DRAM的性能。为了改善后段的电阻-电容延时，研究者不断在寻找低介电常数材料来充当介电层，从而可以降低后段的寄生电容。但低介电常数材料的弹性模量和硬度都比较小，在后续封装时切割晶圆的过程中，低介电常数材料容易产生剥离或崩裂等缺陷，从而影响产品良率。
在一些实施例中，请参考图1，本公开提供了一种半导体结构制备方法，包括：
步骤S202：提供衬底；
步骤S204：按照预设规则于衬底上形成沿第一方向交替分布的芯片结构及切割道，以及位于切割道内的初始沟槽隔离结构，初始沟槽隔离结构的材料为第一绝缘材料；
步骤S206：刻蚀初始沟槽隔离结构，得到预设隔离沟槽；
步骤S208：预设隔离沟槽暴露出目标参考层，目标参考层为与初始沟槽隔离结构沿其厚度方向的相邻层；
步骤S210：于预设隔离沟槽内填充第二绝缘材料，第二绝缘材料的硬度大于第一绝缘材料的硬度。
作为示例，请继续参考图1-图2b，本实施例首先按照预设规则在切割道40上预先形成初始沟槽隔离结构41，再刻蚀初始沟槽隔离结构41得到预设隔离沟槽之后，于预设隔离沟槽内填充第二绝缘材料，将原本在初始沟槽隔离结构内的第一绝缘材料替换成硬度更大的第二绝缘材料，与传统晶圆切割时会因为切割道中的材料硬度较小导致剥离及崩裂等缺陷相比，本实施例的半导体结构中切割道内硬度更大的第二绝缘材料，可以有效地避免晶圆切割过程中出现剥离或崩裂等缺陷，从而提高产品良率，降低晶圆切割的工艺成本。
作为示例，请继续参考图1-图2b，在晶圆切割操作中，切割刀切割时容易使介电层产生严重的剥离或龟裂现象，导致剥离及崩裂等缺陷。由于介质层和刻蚀停止层粘附性不好产生剥离，剥离可能发生在半导体器件生产过程中，或半导体器件生产完成后在对钝化层与外引线粘附强度进行可靠性测试过程中。在生产过程中产生剥离及崩裂等缺陷会导致后层金属层翘起或崩裂，影响其电连接并最终导致半导体器件电性失效。
作为示例，请参考图3a，步骤S202中的衬底10可以采用半导体材料、绝缘材料、导体材料或者它们的任意组合构成。衬底10可以为单层结构，也可以为多层结构。例如，衬底10可以是诸如硅(Si)衬底、硅锗(SiGe)衬底、硅锗碳(SiGeC)衬底、碳化硅(SiC)衬底、砷化镓(GaAs)衬底、砷化铟(InAs)衬底、磷化铟(InP)衬底或其它的III/V半导体衬底或II/VI半导体衬底。或者，还例如，衬底10可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。因此衬底10的类型不应限制本公开的保护范围。可以采用离子注入工艺向衬底10内注入P型离子，以形成第一类型掺杂阱区(未图示)，P型离子可以包括但不限于硼(B)离子、镓(Ga)离子、氟化硼(BF2)离子及铟(In)离子等中任一种或多种。
作为示例，请继续参考图2a-图3b，步骤S204按照预设规则于衬底10上形成沿第一方向交替分布的芯片结构30及切割道40，以及位于切割道40内的初始沟槽隔离结构41，初始沟槽隔离结构41的材料为第一绝缘材料，第一方向可以为ox方向。晶圆由多个芯片构成，芯片之间以切割道40相隔。每个芯片通过沉积、刻蚀、掺杂及热处理等工艺，在衬底10上形成元件、叠层、金属互连层等，其中芯片结构30用于后续形成器件结构，切割道40用于在半导体结构制作完成时，作为封装阶段分割芯片结构30的切割线。
在一些实施例中，请继续参考图2a-图3b，初始沟槽隔离结构41中第一绝缘材料的相对介电常数小于或等于3.0。例如，初始沟槽隔离结构41中第一绝缘材料的相对介电常数可以为1.0、2.2、2.7、2.6、2.7、2.9或3.0等等。示例地，第一绝缘材料可以为多孔碳掺杂氧化物、纳米多孔有机硅酸盐、干胶、气胶、掺氟的非晶系碳膜、聚对二甲基苯、苯环丁烯、SiLK及黑色金刚石膜(Black Diamond film，BD film)。BD film是通过将-CH3引入二氧化硅衬底制备的复合电介质材料SiOC：H，作为典型的低介电常数材料，BD film具有低介电常数,高性能等特点。低介电常数材料可以降低集成电路的漏电流、降低导线之间的寄生电容、降低集成电路发热，以及减少移位的导体层之间的寄生效应。材料硬度和弹性模量对于切割工艺非常重要。但低介电常数材料的弹性模量和硬度都比较小，在切割晶圆的时候切割道40里的低介电常数材料容易导致剥离及崩裂等缺陷，从而影响产品良率。
在一些实施例中，请继续参考图2a-图3b，步骤S204中预设规则包括：若沿第一方向相邻的两个芯片结构30的间距小于第一预设阈值，则不在相邻的两个芯片结构30之间形成初始沟槽隔离结构41；反之，则在相邻的两个芯片结构30之间形成初始沟槽隔离结构41，避免因芯片结构30间的间距过小导致晶圆切割时破坏芯片的内部结构，第一方向可以为ox方向。
在一些实施例中，请继续参考图2a-图3b，初始沟槽隔离结构41与沿第一方向相邻的两个芯片结构30之间的间距相等，均为第一预设间距L1。通过设置初始沟槽隔离结构41与相邻的两个芯片结构30之间均为第一预设间距L1，避免在切割晶圆的过程中破坏切割道40中的挡片43，第一方向可以为ox方向。
请注意，本领域技术人员可以毫无疑义的确定，本公开实施例中的“相等”不局限于绝对相等，可以指二者的差异值在预设精度范围内。
在一些实施例中，请继续参考图2a-图3b，切割道40内分布有与衬底10内有源区电连接的测试垫42；初始沟槽隔离结构41与其沿第二方向相邻的测试垫42之间具有第二预设间距L2，第二预设间距L2小于第一预设间距L1，第二方向与第一方向相交，第一方向可以为ox方向，第二方向可以为oy方向。测试垫42是半导体工艺厂在晶圆加工中为了监测工艺而加入在晶圆固定位置的测试元件，可以通过对测试垫42进行晶圆参数测试(Wafer Acceptance Test，WAT)，得到电参数来监控各步工艺是否正常和稳定。测试时，探针接触到晶圆上单数个或复数个芯片结构30对应的测试垫42，即可通过输入信道将电源和信号传输到晶圆上全部的或选定区域中的芯片结构30。芯片结构30形成于晶圆上之后，必须经过WAT才能出厂。WAT的主要目的是仿真客户所设计的电路，并监控工艺的稳定性来增进产品良率、通过测试基本电性参数来反应产线的问题，以及通过测量电路运行过程中的电性参数来判断是否有断线或桥接上的问题。切割道40中还可以包括测试元件组中除测试垫42以外的元件。可以设置测试垫42为多个间隔分布的长条状子结构来减少用料，节约成本。通过设置初始沟槽隔离结构41与其沿第二方向相邻的测试垫42之间具 有第二预设间距L2，避免在切割晶圆的过程中破坏切割道40中的测试垫42。
在一些实施例中，请继续参考图2a-图3b，沿第二方向相邻的初始沟槽隔离结构41与测试垫42均至少部分位于同一目标直线上，目标直线与第二方向平行，第二方向可以为oy方向。本实施例方便晶圆切割的同时避免破坏切割道40中的功能结构，同时满足多种不同应用场景的实际需求。
作为示例，请继续参考图2a-图3b，切割操作是在晶圆的有源侧进行，有源侧形成有芯片结构30及芯片结构30的多层导线层，切割道40位于每一单独的芯片结构30之间的区域。切割道40不具有芯片结构30的电路元件且由于每一芯片结构30为一独立装置，所以用于内连线导体的金属体未延伸或跨越至切割道40内，而局限于芯片结构30内，避免切割刀切断导线层。然而，一些用于晶圆可靠度或功能性测试的测试垫42及挡片43会设置于切割道40内，以助于晶圆的测试。在切割操作中，如果切割刀切割到测试垫42及挡片43会使介电层产生剥离及崩裂等缺陷，所以预设规则中限定初始沟槽隔离结构41与沿第一方向相邻的两个芯片结构30之间具有第一预设间距L1，限定初始沟槽隔离结构41与其沿第二方向相邻的测试垫42之间具有第二预设间距L2，以及限定初始沟槽隔离结构41与测试垫42均至少部分位于同一目标直线上，使得在切割操作中，切割刀不会切割到测试垫42及挡片43，避免了剥离及崩裂等缺陷的产生。
在一些实施例中，步骤S206刻蚀初始沟槽隔离结构，得到预设隔离沟槽包括：
步骤S2061：过刻蚀初始沟槽隔离结构，得到底部延伸至目标参考层内的预设隔离沟槽。
作为示例，步骤S2061中可以通过控制刻蚀的速率及时间来去除初始沟槽隔离结构的材料，然后再继续刻蚀预设时间，得到底部延伸至目标参考层内的预设隔离沟槽，避免残留部分初始沟槽隔离结构的材料。
作为示例，步骤S2061过刻蚀初始沟槽隔离结构，得到底部延伸至目标参考层内的预设隔离沟槽，包括：
步骤S20611：形成覆盖芯片结构的顶面及切割道的顶面的牺牲层；
步骤S20612：于牺牲层的顶面形成图形化光刻胶层；
步骤S20613：基于图形化光刻胶层过刻蚀牺牲层及初始沟槽隔离结构，得到底部延伸至目标参考层内的预设隔离沟槽。
作为示例，请参考图4，步骤S20611中可以采用沉积工艺于芯片结构30的顶面及切割道40的顶面上形成牺牲层50，牺牲层50可以是单层结构，也可以是多层堆叠结构。牺牲层50材质可以是硬掩模、旋涂硬掩模(Spin-on Hardmask，SOH)、光刻胶或其组合。SOH是制作半导体微图形的辅助材料，可以填补间隙使表面更加平坦，并加强耐腐蚀性。应当理解的是，本公开涉及的牺牲层50是在形成目标图案之后需要被去掉的膜层。沉积工艺可以包括但不限于化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺(Atomic Layer Deposition，ALD)、高密度等离子沉积(High Density Plasma， HDP)工艺、等离子体增强沉积工艺及旋涂介质层(Spin-on Dielectric，SOD)等工艺中的一种或多种。例如，可以采用原子层沉积工艺形成牺牲层50，由于原子层沉积工艺在三维复杂表面进行沉积时具有优异的共形性及均匀性，从而能够在芯片结构30的顶面及切割道40的顶面形成均匀的牺牲层50，使得沉积牺牲层50制程的保形性、均匀性及覆盖率提升。
作为示例，请参考图5-图6，步骤S20612中在牺牲层50的顶面涂覆光刻胶材料层61，并经曝光、显影等一系列步骤，形成图形化光刻胶层60，图形化光刻胶层60具有限定预设隔离沟槽70的位置及形状的开口图形，光刻胶可以是正光刻胶或负光刻胶，显影方式可以是正性显影或负性显影。
作为示例，请参考图7，步骤S20613中可以采用刻蚀工艺以图形化光刻胶层60为掩膜版刻蚀牺牲层50及切割道40，得到预设隔离沟槽70。刻蚀工艺可以包括但不限于干法刻蚀工艺及/或湿法刻蚀工艺。干法刻蚀工艺可以包括但不限于反应离子刻蚀(RIE)、感应耦合等离子体刻蚀(ICP)及高浓度等离子体刻蚀(HDP)等中一种或多种。例如，刻蚀牺牲层50及切割道40可以采用等离子刻蚀工艺，等离子体刻蚀是是指利用高频辉光放电反应，将反应气体激活成活性粒子，例如源自或游离基，这些活性粒子扩散到刻蚀的部位与被刻蚀材料进行反应，形成挥发性生成物而被去除，达到刻蚀的目的，刻蚀气体可以包括NF3、CF3、HF、CHF4或其组合，从而提高刻蚀速率。
作为示例，请继续参考图7，步骤S20613在形成预设隔离沟槽70之后，去除剩余的图形化光刻胶层60及牺牲层50从而暴露出芯片结构30的顶面。对于去除图形化光刻胶层60，去除方法可以包括灰化去胶及湿法清洗；对于由硬掩膜等构成的牺牲层50，去除方法包括湿法刻蚀及/或干法刻蚀，干法刻蚀工艺可以包括但不限于RIE、ICP、HDP等中一种或多种。例如，刻蚀牺牲层50可以采用激光刻蚀工艺，激光刻蚀工艺是利用高能量激光光束照射到被刻蚀件表面，使其融化或气化，形成一定深度的凹槽，实现对材料刻蚀的目的，采用激光刻蚀工艺可以提升产品的良率及稳定性，实现不同图形不同角度的一次性成型，且无耗材、无污染，成本低。
作为示例，请继续参考图7，步骤S208中预设隔离沟槽70暴露出目标参考层20，目标参考层20为与初始沟槽隔离结构41沿其厚度方向的相邻层。目标参考层20为与初始沟槽隔离结构41沿其厚度方向的相邻层包括目标参考层20与初始沟槽隔离结构41沿目标参考层20的厚度方向上直接相邻或目标参考层20与初始沟槽隔离结构41沿目标参考层20的厚度方向上存在中间介质层相邻，目标参考层20的厚度方向可以为oy方向。
在一些实施例中，请继续参考图7，目标参考层20包括硬度大于第一绝缘材料的硬度的第三绝缘材料，第二绝缘材料与第三绝缘材料相同。第三绝缘材料的材料选自氧化硅、碳硅氧氢化物、掺氟氧化硅、碳化硅、氮化硅碳或其组合，以满足不同应用场景的实际需求。
在一些实施例中，请参考图8，于预设隔离沟槽70内填充第二绝缘材料包括：采用高 密度等离子体沉积工艺及/或原子层沉积工艺于预设隔离沟槽70内填充第二绝缘材料，形成第一介质层80，第一介质层80填充满预设隔离沟槽70并覆盖芯片结构30的顶面及切割道40的顶面。第一介质层80将预设隔离沟槽41中的第一绝缘材料替换成第一介质层80的第二绝缘材料，第二绝缘材料的硬度大于第一绝缘材料的硬度，硬度大于第一绝缘材料的硬度的第二绝缘材料可以避免晶圆切割过程中出现剥离或崩裂等缺陷，提高产品良率，降低晶圆切割的工艺成本。
作为示例，请继续参考图8，可以采用高密度等离子体沉积工艺于预设隔离沟槽70内填充第二绝缘材料，形成第一介质层80，第一介质层80填充满预设隔离沟槽70并覆盖芯片结构30的顶面及切割道40的顶面。高密度等离子体沉积工艺可以为高密度等离子体化学气相淀积(High Density Plasma Chemical Vapor Deposition,HDP CVD)工艺，HDP CVD工艺是在同一个反应腔中同步地进行淀积和刻蚀的工艺，其在反应中所用的气体可以选自硅烷、氧气、氢气、氩气、氦气或其组合。在常见的HDP CVD制程中，淀积工艺通常是由硅烷和氧气的反应来实现，而蚀刻工艺通常是由氩气和氧气的溅射来完成。HDP CVD工艺的淀积工艺可以大致分为两个步骤，第一步是利用无偏置的射频电源淀积一层富氧二氧化硅作为保护层；第二步是用含有偏置的射频电源淀积主体薄膜，由于有第一步所淀积的二氧化硅作为保护层，第二步淀积主体薄膜的过程中，其等离子体的损伤会被保护层部分吸收，因此HDP CVD工艺的淀积工艺的过程其等离子体损伤较小。与传统工艺缺乏等离子体辅助淀积产生的膜会依赖下层表面而显示出不同的淀积特性，另外还有低密度和吸潮性，HDP CVD工艺在同一个反应腔中同步地进行淀积和刻蚀的工艺具有卓越的填孔能力、稳定的淀积质量及可靠的电学特性。因此，根据高密度等离子体沉积工艺自身的特性，采用高密度等离子体沉积工艺形成第一介质层80，实现对于预设隔离沟槽70高深宽比间隔的优良填充，并使得沉积第一介质层80具有高密度、低杂质缺陷及对硅片有优良的粘附能力等优点，避免产生空气间隙。
作为示例，请继续参考图8，还可以采用原子层沉积工艺于预设隔离沟槽70内形成第一介质层80，第一介质层80填充满预设隔离沟槽70并覆盖芯片结构30的顶面及切割道40的顶面。原子层沉积工艺是通过将气相前驱体脉冲交替地通入反应器并在沉积基体上化学吸附并反应而形成沉积膜的一种技术，当前驱体达到沉积基体表面时，会在其表面化学吸附并发生表面反应，原子层沉积的表面反应具有自限制性(self-limiting)，通过在原子层沉积中不断重复自限制反应形成所需要的结构，前驱体材料可以包括非金属前驱体材料及/或金属前驱体材料。例如，非金属前驱体包括卤化物(SiCl4或AlCl3等)、氮化物(NH3、(CH3)NH2或BuNH2等)，金属前驱体包括烷基前驱体(Ga(CH3)3或Mg(C2H5)2)、β-二酮前驱体(La(thd)3或Ca(thd)2)、醇盐前驱体(Ta(OC2H5)5或Zr[(OC)(CH3)3]4)或烷基胺及硅胺基前驱体(Ti[N(C2H5CH3)2]4或Pr[N(SiMe3)2]3)等；传统的溶液化学沉积技术以及溅射或蒸镀等物理沉积技术由于缺乏表面控制性或存在溅射阴影区，在三维复杂结构的表面进行沉积的效果较差，然而原子层沉积技术基于表面自限制性、自饱和吸附反应，从而 具有表面控制性，所制备的结构具有优异的三维共形性及大面积的均匀性，对于复杂高深宽比的表面沉积制程的适应性更强，同时原子层沉积工艺可以制造出光滑的表面形貌，紧密地贴合填充层，从而减小沉积制程产生的应力，例如，相比于传统的钨沉积技术，原子层沉积低氟钨技术可以降低一个数量级(GPa至hMPa)的应力、99％的氟含量以及30％的电阻率，因此，根据原子层沉积工艺自身的特性，采用原子层沉积工艺形成第一介质层80，实现对于预设隔离沟槽70、芯片结构30的顶面及切割道40的均匀覆盖，使得沉积第一介质层80制程的保形性、均匀性及覆盖率提升，避免产生空气间隙。
作为示例，请继续参考图8，可以设置高密度等离子体沉积工艺的温度范围为300℃-500℃，例如可以设置高密度等离子体沉积工艺的温度为300℃、400℃或500℃等等。可以设置高密度等离子体沉积工艺的反应腔压力范围为1Torr-10Torr，例如可以设置高密度等离子体沉积工艺的反应腔压力为1Torr、3Torr、5Torr、7Torr、9Torr或10Torr等等。可以设置高密度等离子体沉积工艺中气体的流量范围为100sccm-1000sccm，例如可以设置高密度等离子体沉积工艺中气体的流量为100sccm、300sccm、500sccm、700sccm、900sccm或1000sccm等等。可以设置高密度等离子体沉积工艺的射频功率范围为1000～8000W，例如可以设置高密度等离子体沉积工艺的射频功率为1000W、3000W、5000W、7000W或8000W等等，从而提升对不同结构及材料进行沉积的适应性，精准可控地降低寄生电容，从而进一步提高半导体器件的可靠性与稳定性。
作为示例，请继续参考图8，可以设置原子层沉积工艺沉积的速率范围为每秒0.5埃-每秒2埃，例如可以设置原子层沉积工艺沉积的速率为每秒0.5埃、每秒0.8埃、每秒1.1埃、每秒1.4埃、每秒1.7埃或每秒2埃等。可以设置原子层沉积工艺压力的范围为0.1torr-50torr，例如可以设置原子层沉积工艺压力为0.1torr、0.5torr、2.5torr、12.5torr或50torr等。可以设置原子层沉积工艺温度的范围为25℃-600℃，例如可以设置原子层沉积工艺温度为25℃、140℃、255℃、370℃、485℃或600℃等。可以设置原子层沉积工艺中氧气的流量范围为0.1L-10L，例如可以设置原子层沉积工艺中氧气的流量为0.1L、0.5L、1L、5L或10L等。原子层沉积工艺的前驱体材料可以包括硅烷，例如，硅烷包括：二(异丙氨基)硅烷、双(叔丁基氨基)硅烷、双(二乙氨基)硅烷或其组合。通过在原子层沉积工艺中采取不同的沉积速率、压力、温度、氧气流量及前驱体材料，提升对不同结构及材料进行沉积的适应性，精准可控地降低寄生电容，从而进一步提高半导体器件的可靠性与稳定性。
在一些实施例中，请参考图9，在形成第一介质层80之后还包括：于第一介质层80远离衬底10的表面形成绝缘保护层90。
作为示例，请继续参考图9，可以采用沉积工艺于第一介质层80远离衬底10的表面形成绝缘保护层90，沉积工艺可以包括但不限于CVD、ALD、HDP工艺、SOD等工艺中的一种或多种。绝缘保护层90的形成可以防止在后续的半导体器件封装过程中，由于焊料容易移到半导体器件侧面，导致的短路和漏电。绝缘保护层90可以将焊料分隔，避免因为 焊料爬升导致的短路和打火现象。
作为示例，请继续参考图9，如果在过刻蚀初始沟槽隔离结构41，得到底部延伸至目标参考层20内的预设隔离沟槽70后不沉积第一介质层80和绝缘保护层90，容易导致晶圆内部产生空气间隙，并导致晶圆各个位置的应力不好控制，产生剥离及崩裂等缺陷，而沉积第一介质层80和绝缘保护层90后，晶圆各个位置的应力类似，避免产生剥离及崩裂等缺陷。
在一些实施例中，请参考图10，绝缘保护层90的顶面具有目标凹槽91，目标凹槽91位于预设隔离沟槽70的正上方，使得在晶圆切割时更容易找到切割的位置，更有利于晶圆切割，提高产品良率。
在一些实施例中，请继续参考图10，绝缘保护层90的材料与第一介质层80的材料不同；以及绝缘保护层90的材料选自氧化硅、氮化硅、氮碳化硅、氮氧化硅或其组合，以满足不同应用场景的实际需求。
在一些实施例中，请继续参考图10，半导体结构100制备方法包括：沿第一方向相邻的两个芯片结构30的间距小于第一预设阈值，第一预设阈值选自25μm-35μm，例如第一预设阈值可以为：25μm、27μm、29μm、31μm、33μm或35μm等等，第一方向可以为ox方向；第二绝缘材料的材料选自氧化硅、碳硅氧氢化物、掺氟氧化硅、碳化硅、氮化硅碳或其组合，以满足不同应用场景的实际需求。
在一些实施例中，请继续参考图10及图2b，初始沟槽隔离结构41与相邻的两个芯片结构30之间的间距为第一预设间距L1，第一预设间距L1的范围为13μm-16μm，例如第一预设间距可以为13μm、14μm、15μm或16μm等等。
在一些实施例中，请继续参考图10及图2b，初始沟槽隔离结构41与其沿第二方向相邻的测试垫42之间的间距为第二预设间距L2，第二预设间距L2的范围为2.4μm-2.7μm，例如第二预设间距可以为：2.4μm、2.45μm、2.5μm、2.55μm、2.6μm、2.65μm或2.7μm等等，第二方向可以为oy方向。
在一些实施例中，请继续参考图10，测试垫42的材料选自钛、钨、镍、金、银、硅化钨、铝、钯、铜或其组合，以满足不同应用场景的实际需求。
应该理解的是，虽然图1的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，虽然图1中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请继续参考图10，在一些实施例中，提供了一种半导体结构100，采用上述任一实施例中半导体结构制备方法制备而成。
作为示例，请继续参考图10及图2b，首先按照预设规则在切割道40上预先形成初 始沟槽隔离结构41，再刻蚀初始沟槽隔离结构41得到预设隔离沟槽70之后，于预设隔离沟槽70内填充第二绝缘材料，将原本在初始沟槽隔离结构41内的第一绝缘材料替换成硬度更大的第二绝缘材料，与传统晶圆切割时会因为切割道40中的材料硬度较小导致剥离及崩裂等缺陷相比，本实施例的半导体结构100中切割道40内硬度更大的第二绝缘材料，可以有效地避免晶圆切割过程中出现剥离或崩裂等缺陷，从而提高产品的良率，降低晶圆切割的工艺成本。
请注意，上述实施例仅出于说明性目的而不意味对本公开的限制。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对公开专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体结构制备方法，包括：
    提供衬底；
    按照预设规则于所述衬底上形成沿第一方向交替分布的芯片结构及切割道，以及位于所述切割道内的初始沟槽隔离结构，所述初始沟槽隔离结构的材料为第一绝缘材料；
    刻蚀所述初始沟槽隔离结构，得到预设隔离沟槽；
    所述预设隔离沟槽暴露出目标参考层，所述目标参考层为与所述初始沟槽隔离结构沿其厚度方向的相邻层；
    于所述预设隔离沟槽内填充第二绝缘材料，所述第二绝缘材料的硬度大于所述第一绝缘材料的硬度。
  2. 根据权利要求1所述的半导体结构制备方法，其中，所述第一绝缘材料的相对介电常数小于或等于3.0。
  3. 根据权利要求1所述的半导体结构制备方法，其中，所述目标参考层包括硬度大于所述第一绝缘材料的硬度的第三绝缘材料，所述第二绝缘材料与所述第三绝缘材料相同。
  4. 根据权利要求1所述的半导体结构制备方法，其中，所述预设规则包括：
    若沿所述第一方向相邻的两个所述芯片结构的间距小于第一预设阈值，则不在所述相邻的两个所述芯片结构之间形成所述初始沟槽隔离结构；
    反之，则在所述相邻的两个所述芯片结构之间形成所述初始沟槽隔离结构。
  5. 根据权利要求4所述的半导体结构制备方法，其中，所述初始沟槽隔离结构与所述相邻的两个所述芯片结构之间的间距相等，均为第一预设间距。
  6. 根据权利要求5所述的半导体结构制备方法，其中，所述切割道内分布有与所述衬底内有源区电连接的测试垫；
    所述初始沟槽隔离结构与其沿第二方向相邻的测试垫之间具有第二预设间距，所述第二预设间距小于所述第一预设间距，所述第二方向与所述第一方向相交。
  7. 根据权利要求6所述的半导体结构制备方法，其中，沿所述第二方向相邻的所述初始沟槽隔离结构与所述测试垫均至少部分位于同一目标直线上，所述目标直线与所述第二方向平行。
  8. 根据权利要求1-7任一项所述的半导体结构制备方法，其中，所述刻蚀所述初始沟槽隔离结构，得到预设隔离沟槽，包括：
    过刻蚀所述初始沟槽隔离结构，得到底部延伸至所述目标参考层内的预设隔离沟槽。
  9. 根据权利要求8所述的半导体结构制备方法，其中，所述于所述预设隔离沟槽内填充第二绝缘材料，包括：
    采用高密度等离子体沉积工艺及/或原子层沉积工艺于所述预设隔离沟槽内填充所述第二绝缘材料，形成第一介质层，所述第一介质层填充满所述预设隔离沟槽并覆盖所述芯片结构的顶面及所述切割道的顶面。
  10. 根据权利要求9所述的半导体结构制备方法，其中，在形成所述第一介质层之后，还包括：
    于所述第一介质层远离所述衬底的表面形成绝缘保护层。
  11. 根据权利要求10所述的半导体结构制备方法，其中，所述绝缘保护层的顶面具有目标凹槽，所述目标挖槽位于所述预设隔离沟槽的正上方。
  12. 根据权利要求10所述的半导体结构制备方法，其中，所述绝缘保护层的材料与所述第一介质层的材料不同；以及
    所述绝缘保护层的材料包括：氧化硅、氮化硅、氮碳化硅、氮氧化硅或其组合。
  13. 根据权利要求4-7任一项所述的半导体结构制备方法，其中：
    所述第一预设阈值选自25μm-35μm；及/或
    所述第二绝缘材料选自氧化硅、碳硅氧氢化物、掺氟氧化硅、碳化硅、氮化硅碳或其组合。
  14. 根据权利要求6或7所述的半导体结构制备方法，其中，包括如下特征中至少一个：
    所述第一预设间距的范围包括：13μm-16μm；
    所述第二预设间距的范围包括：2.4μm-2.7μm；
    所述测试垫的材料选自钛、钨、镍、金、银、硅化钨、铝、钯、铜或其组合。
  15. 一种半导体结构，其中，采用权利要求1-14任一项所述的半导体结构制备方法制备而成。
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CN113937065A (zh) * 2021-10-12 2022-01-14 长鑫存储技术有限公司 半导体结构及其制备方法
CN114203648A (zh) * 2022-02-21 2022-03-18 安建科技(深圳)有限公司 一种改善晶圆翘曲变形的芯片结构及其制备方法
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