WO2024067569A1 - 芯片组件、电子设备以及芯片组件的制备方法 - Google Patents

芯片组件、电子设备以及芯片组件的制备方法 Download PDF

Info

Publication number
WO2024067569A1
WO2024067569A1 PCT/CN2023/121497 CN2023121497W WO2024067569A1 WO 2024067569 A1 WO2024067569 A1 WO 2024067569A1 CN 2023121497 W CN2023121497 W CN 2023121497W WO 2024067569 A1 WO2024067569 A1 WO 2024067569A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
chip
substrate
adhesive layer
metal connector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/121497
Other languages
English (en)
French (fr)
Inventor
陈成杰
张劭东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vivo Mobile Communication Co Ltd
Original Assignee
Vivo Mobile Communication Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Publication of WO2024067569A1 publication Critical patent/WO2024067569A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W95/00—Packaging processes not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07232—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/237—Multiple bump connectors having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present application belongs to the technical field of communication equipment, and specifically relates to a chip assembly, an electronic device, and a method for preparing the chip assembly.
  • the versatility of electronic devices has become one of the important factors that users pay attention to.
  • the versatility of electronic devices needs to rely on the internal integration of multiple electronic components to improve.
  • the intervals between the metal connectors become smaller, resulting in holes in the packaging material during the filling process, thus affecting the structural reliability of the SOC.
  • thermal compression flip chip (TCFC) packaging In practical applications, in order to solve the problem of packaging material filling, most of the thermal compression flip chip (TCFC) packaging is used to reduce the holes caused by packaging material filling.
  • TCFC thermal compression flip chip
  • hot compression welding will cause packaging materials to remain on the welding surface of the metal connector and the substrate, resulting in the problem of poor structural reliability of the chip assembly.
  • the purpose of the embodiments of the present application is to provide a chip assembly, an electronic device, and a method for preparing a chip assembly, which can solve the problem of poor structural reliability of the current chip assembly.
  • the present application is implemented as follows:
  • an embodiment of the present application provides a chip assembly, comprising a substrate, an adhesive layer, a chip and a first metal connector, wherein the substrate, the adhesive layer and the chip are stacked in sequence, and the first metal connector A metal connector is protrudingly disposed on a side of the substrate facing the adhesive layer, and the chip is connected to the substrate via the first metal connector.
  • an embodiment of the present application further provides an electronic device comprising the above-mentioned chip assembly.
  • an embodiment of the present application also provides a method for preparing a chip assembly, comprising: preparing a first metal connector on a substrate; setting an adhesive layer on the substrate, the adhesive layer covering the first metal connector; setting a chip on the adhesive layer; heating the chip and pressing the chip to connect the chip to the first metal connector.
  • the first metal connector is first prepared on the substrate, then the adhesive layer is arranged on the substrate, and then the chip is pressed onto the adhesive layer. Since the first metal connector protrudes from the substrate, the portion of the adhesive layer located above the first metal connector can be effectively squeezed out, avoiding the adhesive layer from remaining between the first metal connector and the chip, thereby ensuring the connection reliability between the chip and the substrate. Therefore, the embodiment of the present application can solve the problem of poor structural reliability of the current chip assembly.
  • FIG1 is a schematic diagram of the structure of a chip assembly disclosed in an embodiment of the present application.
  • FIG2 is a partial enlarged view of the structure shown in FIG1 ;
  • 3a to 3d are schematic diagrams of partial structures of a chip assembly disclosed in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of a chip assembly disclosed in another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a partial structure of a chip assembly disclosed in another embodiment of the present application.
  • the embodiment of the present application discloses a chip assembly.
  • the chip assembly may be an integrated circuit, or other chip assembly, without specific limitation.
  • the chip assembly includes a substrate 110, an adhesive layer 120, a chip 130, and a first metal connector 140.
  • the adhesive layer 120 may be a non-conductive paste (NCP), or other adhesive materials with conductive functions, without specific limitation.
  • the thickness of the adhesive layer 120 may be 40 um, or may be selected according to actual needs, without specific limitation.
  • the substrate 110, the adhesive layer 120 and the chip 130 are stacked in sequence, and the first metal connector 140 is protrudingly arranged on the side of the substrate 110 facing the adhesive layer 120.
  • the first metal connector 140 and the substrate 110 can be an integrated structure.
  • the first metal connector 140 is first prepared on the substrate 110 by electroplating or the like, and then the adhesive layer 120 is arranged on the substrate 110.
  • the chip 130 is connected to the substrate 110 through the first metal connector 140.
  • the chip 130 and the first metal connector 140 can be connected by welding, bonding, etc., which is not specifically limited here.
  • the first metal connector 140 is first prepared on the substrate 110, then the adhesive layer 120 is arranged on the substrate 110, and then the chip 130 is pressed onto the adhesive layer 120. Since the first metal connector 140 protrudes from the substrate 110, the portion of the adhesive layer 120 located above the first metal connector 140 can be effectively squeezed out, so that the adhesive layer 120 is prevented from remaining between the first metal connector 140 and the chip 130, thereby ensuring the connection reliability between the chip 130 and the substrate 110. Therefore, the embodiment of the present application can solve the problem of poor structural reliability of the current chip assembly.
  • the substrate 110 has a first pad 111 on one side facing the adhesive layer 120, and the first metal connector 140 is protrudingly disposed on the side of the first pad 111 facing the adhesive layer 120.
  • the first pad 111 can not only realize the electrical connection of the chip 130, but also ensure the first metal connector 140 is electrically connected to the chip 130.
  • the chip 130 is more reliably connected to the substrate 110 to prevent the first metal connector 140 from falling off.
  • the chip 130 has a second pad 121 on one side facing the adhesive layer 120, and the first metal connector 140 is connected between the first pad 111 and the second pad 121, thereby further improving the connection reliability between the chip 130 and the substrate 110.
  • the first metal connector 140 includes a first metal column 141 and a first metal ball 142.
  • the first metal ball 142 is in a natural state, it is spherical, that is, the first metal ball 142 is spherical when it has not yet deformed.
  • the first metal ball 142 is arranged at the first end of the first metal column 141, and the first end of the first metal column 141 is connected to the chip 130 through the first metal ball 142.
  • the adhesive layer 120 has not yet solidified and has a certain fluidity.
  • the arc surface of the first metal ball 142 can provide a guiding effect for the movement of the adhesive layer 130, so as to fully squeeze out the adhesive layer between the chip 130 and the first metal ball 142; in addition, since the first metal column 141 has a certain height, when the chip 130 is arranged, the moving stroke of the chip 130 is short, which is conducive to improving the connection efficiency between the first chip 130 and the first metal connector 140.
  • the second end of the first metal column 141 is connected to the substrate 110.
  • the first metal column 141 is first prepared on the substrate 110, and then the first metal ball 142 is arranged at the first end of the first metal column 141, that is, the end of the first metal column 141 away from the substrate 110, so as to facilitate the arrangement of the first metal ball 142.
  • the first metal ball 142 is deformed after being heated. After the chip 130 is placed on the adhesive layer 120, the chip 130 is heated, and the first metal ball 142 is deformed after being heated by heat transfer, so that the first metal column 141 is arranged in affixed with the chip 130 through the first metal ball 142, thereby improving the connection reliability between the first metal column 141 and the chip 130.
  • the first metal ball 142 can be made of a material such as aluminum, magnesium, titanium, etc., which can change its structural shape after heat treatment, and there is no specific limitation on this.
  • the first metal column 141 is optionally a copper column, which not only facilitates the production of the first metal column 141, but also can reliably prevent the generation of static electricity after grounding, which is beneficial to protecting other electronic components such as chips.
  • the first metal ball 142 is a solder ball, which can be used to replace the pins in the chip component packaging structure to meet the requirements of electrical interconnection and mechanical connection.
  • the solder ball does not need to bend the pins, which is beneficial to improving the chip component yield.
  • the solder ball also has better heat dissipation, which can make the package product thinner, reduce the packaging area, and shorten the distance between the joints to improve the electronic characteristics.
  • the first metal ball 142 in this embodiment is a solder ball, which is deformed after heating, which is not only beneficial to
  • the first metal pillar 141 is used to improve the connection reliability between the chip 130 , and as a connecting member between the first metal pillar 141 and the chip 130 , it is beneficial to improve the lightness and thinness and the yield rate of the chip component.
  • the first metal connector 140 is a hemispherical structure
  • the arc surface of the hemispherical structure is arranged opposite to the chip 130
  • the plane of the hemispherical structure is connected to the substrate 110. Since the plane of the hemispherical structure has a larger area, it is beneficial to increase the connection area between the first metal connector 140 and the substrate 110, thereby improving the connection reliability between the chip 130 and the substrate 110; and the chip 130 is connected to the substrate 110 through the first metal connector 140 of the hemispherical structure, which can simplify the preparation process of the substrate 110 and improve the processing efficiency.
  • the first metal connector 140 of the hemispherical structure can be connected to the chip 130 through a solder ball, and the solder ball is deformed by heat, which is beneficial to increase the connection area between the first metal connector 140 and the chip 130, thereby improving the connection firmness between the two.
  • the chip assembly further includes a second metal connector 150, which is disposed on a side of the chip 130 facing the adhesive layer 120, and the first metal connector 140 is connected to the chip 130 through the second metal connector 150.
  • the chip 130 and the second metal connector 150 can be connected by welding, bonding, etc., which are not specifically limited here.
  • the first metal connector 140 is first prepared on the substrate 110, and then the adhesive layer 120 is disposed on the substrate 110, and then the chip 130 provided with the second metal connector 150 is disposed on the adhesive layer 120, and the second metal connector 150 is disposed opposite to the first metal connector 140. Since the adhesive layer 130 is affected by gravity, the adhesive layer 120 between the second metal connector 150 and the first metal connector 140 can be effectively squeezed out when the chip 130 is pressed, thereby improving the connection firmness between the second metal connector 150 and the first metal connector 140.
  • the second metal connector 150 includes a second metal column 151 and a second metal ball 152.
  • the second metal ball 152 When the second metal ball 152 is in a natural state, it is spherical, that is, the second metal ball 152 is spherical when it has not yet deformed.
  • the first end of the first metal column 141 is connected to the chip 130, and the second metal ball 152 is arranged at the second end of the second metal column 151.
  • the second end of the second metal column 151 is connected to the first metal connector 140 through the second metal ball 152.
  • the second metal ball 152 is arranged opposite to the arc surface of the first metal connector 140 with a hemispherical structure. In this embodiment, the second metal connector 150 of this structure is used.
  • the adhesive layer 120 After the chip 130 is arranged on the adhesive layer 120, during the process of pressing the chip 130, the adhesive layer 120 has not yet solidified and has a certain fluidity.
  • the arc surface of the second metal ball 152 and the arc surface of the first metal connector 140 can provide a guiding effect for the movement of the adhesive layer 120, so as to effectively squeeze out the adhesive layer 130 between the two, thereby further improving the first metal connector.
  • the connection reliability between 140 and the second metal connection member 150 The connection reliability between 140 and the second metal connection member 150.
  • the second metal ball 152 is deformed after being heated. After the chip 130 is placed on the adhesive layer 130, the chip 130 is heated, and the second metal ball 152 is deformed after being heated by heat transfer, so that the second metal column 151 is arranged in affixed with the first metal connector 140 through the second metal ball 152, thereby improving the connection reliability between the second metal column 151 and the first metal connector 140.
  • the second metal ball 152 can be made of a material such as aluminum or magnesium that can change its structural shape after heat treatment, and there is no specific limitation on this.
  • the first metal connector 140 is a copper hemisphere and the second metal column 151 is a copper column. This not only facilitates the manufacture of the first metal connector 140 and the second metal column 151, but also can reliably prevent the generation of static electricity after the first metal connector 140 and the second metal column 151 are grounded, which is beneficial to protecting other electronic components such as chips.
  • the second metal ball 152 is a solder ball, which can be used to replace the pins in the chip component packaging structure to meet the requirements of electrical interconnection and mechanical connection.
  • the solder ball does not need to bend the pins, which is conducive to improving the chip component yield.
  • the solder ball also has better heat dissipation, which can make the package product thinner, reduce the packaging area, and shorten the distance between the joints to improve the electronic characteristics.
  • the first metal ball 142 in this embodiment is a solder ball, which is deformed after heating, which is not only conducive to improving the connection reliability between the second metal column 151 and the first metal connector 140, but also as a connector between the second metal column 151 and the first metal connector 140, it is conducive to improving the thinness and yield of the chip component.
  • the number of the first metal connectors 140 may be one or at least two.
  • the size of the first metal connector 140 needs to be set larger to ensure the connection reliability between the chip 130 and the substrate 110.
  • the number of the first metal connectors 140 is at least two, and the first metal connectors 141 are arranged at intervals. In this case, a plurality of first metal connectors 140 with smaller sizes may be provided to ensure the connection reliability between the chip 130 and the substrate 110, thereby saving the cost of manufacturing chip components.
  • the chip assembly further includes a copper core ball 160 and a packaging layer 170.
  • the copper core ball 160 is disposed on the substrate 110, and the copper core ball 160 and the first metal connector 140 are disposed in the same layer.
  • the packaging layer 170 is disposed on the side of the substrate 110 facing the copper core ball 160, and the packaging layer 170 covers the chip 130.
  • the packaging layer 170 is used to isolate the external water and oxygen, thereby protecting the chip 130, the first metal connector 140 and other structures.
  • the packaging layer 170 can be made of epoxy molding compound (EMC). It can certainly be made of other materials, and there is no specific limitation here.
  • the embodiments of the present application also disclose an electronic device, which includes the chip assembly of any of the above embodiments.
  • the embodiment of the present application further provides a method for preparing the chip assembly.
  • the disclosed preparation method is applied to the chip assembly of any embodiment described above.
  • the disclosed preparation method includes:
  • a metal material may be attached to the surface of the substrate 110 by chemical evaporation or electroplating to form the first metal connector 140 , and the first metal connector 140 protrudes from the surface of the substrate 110 .
  • the adhesive layer 120 covers the first metal connector 140 to reserve a certain amount of deformation for the adhesive layer 120 during the curing process.
  • the adhesive layer 120 may be NCP, or other adhesive materials with conductive function, which are not specifically limited.
  • the chip 130 may be grasped by the suction cup 200 , and then the chip 130 and the first metal connector 140 are aligned and arranged.
  • the chip 130 and the first metal connector 140 can be connected by welding, and the chip 130 can be heated to ensure the welding reliability between the chip 130 and the first metal connector 140 through heat transfer; and the curing rate of the adhesive layer 120 at the connection between the chip 130 and the first metal connector 140 can be slowed down, so that the adhesive layer 130 between the two can be fully squeezed out.
  • the first metal connector 140 is first prepared on the substrate 110, and then the adhesive layer 120 is arranged on the substrate 110, and then the chip 130 is pressed onto the adhesive layer 120. Since the first metal connector 140 protrudes from the substrate 110, the portion of the adhesive layer 120 located above the first metal connector 140 can be effectively squeezed out, so as to avoid the adhesive layer 120 remaining between the first metal connector 140 and the chip 130, thereby ensuring that the chip 130 and the substrate 110 are bonded to each other. Therefore, the embodiment of the present application can solve the problem of poor structural reliability of current chip components.
  • step S300 specifically includes:
  • the second metal connector 150 and the chip 130 may be connected by welding, bonding, or the like, which is not specifically limited here.
  • the chip 130 in this embodiment is connected to the substrate 110 via the first metal connector 140 and the second metal connector 150, which is beneficial to further squeeze out the adhesive layer 120 between the first metal connector 140 and the second metal connector 150 to avoid residual adhesive layer 120, thereby improving the connection firmness between the chip 130 and the substrate 110.
  • the electronic device disclosed in the embodiments of the present application may be a smart phone, a tablet computer, an e-book reader, a wearable device (such as a smart watch), an electronic game console, or other electronic device.
  • the embodiments of the present application do not impose any specific restrictions on the type of electronic device.

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

本申请公开了一种芯片组件、电子设备以及芯片组件的制备方法，涉及通信设备技术领域。该芯片组件包括基板、粘接层、芯片和第一金属连接件，所述基板、所述粘接层和所述芯片依次叠置，所述第一金属连接件凸出设置于所述基板朝向所述粘接层的一面，且所述芯片通过所述第一金属连接件与所述基板相连。

Description

芯片组件、电子设备以及芯片组件的制备方法
交叉引用
本申请要求在2022年09月30日提交中国专利局、申请号为202211211097.1、名称为“芯片组件、电子设备以及芯片组件的制备方法”的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请属于通信设备技术领域，具体涉及一种芯片组件、电子设备以及芯片组件的制备方法。
背景技术
随着科技的不断发展，电子设备的多功能性已经成为用户关注的重要因素之一，然而电子设备的多功能性需要依赖于电子设备的内部集成多个电子元器件来提升，但是由于集成电路的系统级芯片(System on Chip，SOC)的芯片的面积受限，导致放置同样数量的金属连接件时，金属连接件之间的间隔变小，致使封装材料在填充过程中存在孔洞，从而影响SOC的结构可靠性。
实际应用中，为解决封装材料填充的问题，大多采用热压倒装芯片(Thermal Compress Flip Chip，TCFC)封装，从而减少封装材料填充造成的孔洞，然而热压焊接将导致封装材料残留在金属连接件与基板的焊接面上，导致仍然存在芯片组件的结构可靠性较差的问题。
发明内容
本申请实施例的目的是提供一种芯片组件、电子设备以及芯片组件的制备方法，能够解决目前芯片组件的结构可靠性较差的问题。为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种芯片组件，包括基板、粘接层、芯片和第一金属连接件，所述基板、所述粘接层和所述芯片依次叠置，所述第 一金属连接件凸出设置于所述基板朝向所述粘接层的一面，且所述芯片通过所述第一金属连接件与所述基板相连。
第二方面，本申请实施例还提供了一种电子设备，包括上述的芯片组件。
第三方面，本申请实施例还提供了一种芯片组件的制备方法，包括：在基板上制备第一金属连接件；在所述基板上设置粘接层，所述粘接层覆盖所述第一金属连接件；将芯片设置于所述粘接层；加热所述芯片并按压所述芯片，以使所述芯片与所述第一金属连接件连接。
在本申请实施例中，在封装芯片组件的过程中，先在基板上制备第一金属连接件，接着在基板上设置粘接层，然后将芯片压接于粘接层，由于第一金属连接件凸出于基板，因此粘接层中位于第一金属连接件上方的部分可以被有效挤压出去，避免粘接层残留在第一金属连接件与芯片之间，从而确保芯片与基板的连接可靠性。因此，本申请实施例能够解决目前芯片组件的结构可靠性较差的问题。
附图说明
图1为本申请实施例公开的芯片组件的结构示意图；
图2为图1所示结构的局部放大图；
图3a至图3d为本申请实施例公开的芯片组件的部分结构的示意图；
图4为本申请另一实施例公开的芯片组件的结构示意图；
图5为本申请另一实施例公开的芯片组件的部分结构的示意图。
附图标记说明：
110-基板、111-第一焊盘、120-粘接层、121-第二焊盘、130-芯片、140-
第一金属连接件、141-第一金属柱、142-第一金属球、150-第二金属连接件、151-第二金属柱、152-第二金属球、160-铜芯球、170-封装层；
200-吸盘。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创 造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的芯片组件、电子设备以及芯片组件的制备方法进行详细地说明。
参考图1至图5，本申请实施例公开一种芯片组件，可选地，该芯片组件可以为集成电路，当然也可以为其它芯片组件，这里不作具体限制。该芯片组件包括基板110、粘接层120、芯片130和第一金属连接件140，可选地，该粘接层120可以为非导电胶(Non Conductive Paste，NCP)，当然也可以为其它具有导电功能的粘接材料，这里不作具体限制。可选地，粘接层120的厚度可以为40um，当然也可以根据实际需要进行选择，这里不作具体限制。
基板110、粘接层120和芯片130依次叠置，第一金属连接件140凸出设置于基板110朝向粘接层120的一面，可选地，第一金属连接件140和基板110可以为一体式结构，在制作芯片组件的过程中，先在基板110上通过电镀等方式制备第一金属连接件140，接着在基板110上设置粘接层120。芯片130通过第一金属连接件140与基板110相连。可选地，芯片130与第一金属连接件140之间可以通过焊接、粘接等方式连接，这里不作具体限制。
在本申请实施例中，在封装芯片组件的过程中，先在基板110上制备第一金属连接件140，接着在基板110上设置粘接层120，然后将芯片130压接于粘接层120，由于第一金属连接件140凸出于基板110，因此粘接层120中位于第一金属连接件140上方的部分可以被有效挤压出去，避免粘接层120残留在第一金属连接件140与芯片130之间，从而确保芯片130与基板110的连接可靠性。因此，本申请实施例能够解决目前芯片组件的结构可靠性较差的问题。
可选地，基板110朝向粘接层120的一面具有第一焊盘111，第一金属连接件140凸出设置于第一焊盘111朝向粘接层120的一面，第一焊盘111的设置不仅可以实现芯片130的电连接，而且能够确保第一金属连接件140 与基板110更可靠地连接，防止第一金属连接件140脱落。进一步可选地，芯片130朝向粘接层120的一面具有第二焊盘121、第一金属连接件140连接于第一焊盘111与第二焊盘121之间，从而更进一步地提升芯片130与基板110之间的连接可靠性。
参考图1至图4，一种可选的实施例中，第一金属连接件140包括第一金属柱141和第一金属球142，第一金属球142处于自然状态下时，其呈球形，即第一金属球142尚未变形的情况下呈球形。第一金属球142设置于第一金属柱141的第一端，第一金属柱141的第一端通过第一金属球142与芯片130相连。将芯片130设置于粘接层120后，在按压芯片130的过程中，此时粘接层120还未固结，具有一定的流动性，该第一金属球142的弧形面能够为粘接层130的运动提供导向作用，以便于将芯片130与第一金属球142之间的粘接层充分挤压出去；另外，由于第一金属柱141具有一定的高度，在设置芯片130时，该芯片130的移动行程较短，有利于提升第一芯片130与第一金属连接件140的连接效率。第一金属柱141的第二端与基板110相连。可选地，先在基板110上制备第一金属柱141，然后在第一金属柱141的第一端，即第一金属柱141远离基板110的一端设置第一金属球142，以便于第一金属球142的设置。
可选地，第一金属球142加热后发生形变。将芯片130放置到粘接层120后，对芯片130进行加热，通过热传递方式使第一金属球142加热后发生形变，以使第一金属柱141通过第一金属球142与芯片130贴合设置，从而提升第一金属柱141与芯片130的连接可靠性。可选地，第一金属球142可以为铝、镁、钛等经热处理能够改变其结构形状的材料制成，这里对此不作具体限制。
由于铜结构耐腐蚀性较好，且具有机械性能和加工性能优良的特点，故可选地，第一金属柱141为铜柱，不仅方便第一金属柱141的制作，而且接地后可以可靠地防止产生静电作用，有利于保护芯片等其它电子元件。
可选地，第一金属球142为锡球，该锡球可以用于代替芯片组件封装结构中的引脚，从而满足电性互连以及机械连接的要求，并且，该锡球无需弯曲引脚，有利于提升芯片组件发优良率；另外，还锡球还具备较佳的散热性，能够使封装产品薄型化，并缩小封装区，且能缩短接合点距离以提高电子特性。因此，本实施例中的第一金属球142为锡球，其加热后变形，不仅有利 于提高第一金属柱141与芯片130之间的连接可靠性，而且作为第一金属柱141与芯片130之间的连接件，有利于提升芯片组件的轻薄化和良品率。
参考图4至图5，另一种可选的实施例中，第一金属连接件140为半球形结构，半球形结构的弧形面与芯片130相对设置，半球形结构的平面与基板110相连，由于半球形结构的平面的面积较大，有利于增大第一金属连接件140与基板110的连接面积，从而提升芯片130与基板110的连接可靠性；并且，芯片130通过半球形结构的第一金属连接件140与基板110连接，可以简化基板110的制备工艺，提高加工效率。可选地，半球形结构的第一金属连接件140可以通过锡球与芯片130连接，锡球受热变形，有利于增大第一金属连接件140与芯片130之间的连接面积，从而提升二者之间的连接牢固性。
进一步可选的实施例中，芯片组件还包括第二金属连接件150，第二金属连接件150设置于芯片130朝向粘接层120的一面，第一金属连接件140通过第二金属连接件150与芯片130相连。可选地，芯片130与第二金属连接件150之间可以通过焊接、粘接等方式连接，这里不作具体限制。在制作芯片组件的过程中，先在基板110上制备第一金属连接件140，接着在基板110上设置粘接层120，然后将设有第二金属连接件150的芯片130设置于粘接层120，并且使第二金属连接件150与第一金属连接件140相对设置，由于粘接层130受重力影响，按压芯片130时能够有效地将第二金属连接件150与第一金属连接件140之间的粘接层120挤压出去，从而提升第二金属连接件150与第一金属连接件140的连接牢固性。
进一步可选的实施例中，第二金属连接件150包括第二金属柱151和第二金属球152，第二金属球152处于自然状态下时，其呈球形，即第二金属球152尚未变形的情况下呈球形。第一金属柱141的第一端与芯片130相连，第二金属球152设置于第二金属柱151的第二端，第二金属柱151的第二端通过第二金属球152与第一金属连接件140相连，第二金属球152与半球形结构的第一金属连接件140的弧形面相对设置。本实施例采用此种结构的第二金属连接件150，将芯片130设置于粘接层120后，在按压芯片130的过程中，此时粘接层120还未固结，具有一定的流动性，第二金属球152的弧形面和第一金属连接件140的弧形面均能够为粘接层120的运动提供导向作用，以有效挤压出二者之间的粘接层130，从而进一步提升第一金属连接件 140与第二金属连接件150之间的连接可靠性。
可选地，第二金属球152加热后发生形变。将芯片130放置到粘接层130后，对芯片130进行加热，通过热传递方式使第二金属球152加热后发生形变，以使第二金属柱151通过第二金属球152与第一金属连接件140贴合设置，从而提升第二金属柱151与第一金属连接件140之间的连接可靠性。可选地，第二金属球152可以由铝、镁等经热处理能够改变其结构形状的材料制成，这里对此不作具体限制。
由于铜结构耐腐蚀性较好，且具有机械性能和加工性能优良的特点，可选的实施例中，第一金属连接件140为铜半球，第二金属柱151为铜柱，不仅方便第一金属连接件140和第二金属柱151的制作，而且在第一金属连接件140和第二金属柱151接地后可以可靠地防止产生静电作用，有利于保护芯片等其它电子元件。
可选地，第二金属球152为锡球，该锡球可以用于代替芯片组件封装结构中的引脚，从而满足电性互连以及机械连接的要求，并且，该锡球无需弯曲引脚，有利于提升芯片组件发优良率；另外，还锡球还具备较佳的散热性，能够使封装产品薄型化，并缩小封装区，且能缩短接合点距离以提高电子特性。因此，本实施例中的第一金属球142为锡球，其加热后变形，不仅有利于提高第二金属柱151与第一金属连接件140之间的连接可靠性，而且作为第二金属柱151与第一金属连接件140之间的连接件，有利于提升芯片组件的轻薄化和良品率。
可选地，第一金属连接件140的数量可以为一个也可以为至少两个，当第一金属连接件140的数量为一个时，为确保芯片130与基板110之间的连接可靠性，需要将第一金属连接件140的尺寸设置的较大。可选地，第一金属连接件140的数量为至少两个，各第一金属连接件141间隔设置，此时可以设置多个尺寸较小的第一金属连接件140，在确保芯片130与基板110之间的连接可靠性的基础上，以节省制作芯片组件的成本。
可选的实施例中，芯片组件还包括铜芯球160和封装层170，铜芯球160设置于基板110，且铜芯球160与第一金属连接件140同层设置，封装层170设置于基板110朝向铜芯球160的一侧，且封装层170覆盖芯片130，封装层170用于隔绝外界的水氧，从而保护芯片130、第一金属连接件140等结构。可选地，封装层170可以由环氧模塑料(Epoxy molding compound，EMC) 制成，当然也可以由其它材料制成，这里不作具体限制。
基于本申请实施例公开的芯片组件，本申请实施例还公开了一种电子设备，其包括上述任意实施例的芯片组件。
基于本申请实施例公开的芯片组件，本申请实施例还提供了一种芯片组件的制备方法，所公开的制备方法应用于上文所述任意实施例的芯片组件，所公开的制备方法包括：
S100、在基板110上制备第一金属连接件140。
可选地，该步骤可以采用化学蒸镀或电镀的方法将金属材料附着在基板110的表面，以形成第一金属连接件140，且该第一金属连接件140凸出于基板110的表面。
S200、在基板110上设置粘接层120，粘接层120覆盖第一金属连接件140。
由于粘接层受自身重力和粘稠度等因素的影响，会发生形变，因此将粘接层120覆盖第一金属连接件140，从而为粘接层120在固化过程中预留一定形变量。
S300、将芯片130设置于粘接层120。
可选地，这里粘接层120可以为NCP，当然也可以为其它具有导电功能的粘接材料，这里不作具体限制。可选地，可以通过吸盘200抓起芯片130，然后将芯片130与第一金属连接件140对齐设置。
S400、加热芯片130并按压芯片130，以使芯片130与第一金属连接件140连接。
可选地，芯片130与第一金属连接件140之间可以采用焊接的方式连接，加热芯片130，通过热传递的方式，有利于确保芯片130与第一金属连接件140之间的焊接可靠性；并且，可以减缓芯片130与第一金属连接件140的连接处的粘接层120的固化速率，从而将二者之间的粘接层130充分挤压出去。
在本申请实施例中，在封装芯片组件的过程中，先在基板110上制备第一金属连接件140，接着在基板110上设置粘接层120，然后将芯片130压接于粘接层120，由于第一金属连接件140凸出于基板110，因此粘接层120中位于第一金属连接件140上方的部分可以被有效挤压出去，避免粘接层120残留在第一金属连接件140与芯片130之间，从而确保芯片130与基板110 的连接可靠性。因此，本申请实施例能够解决目前芯片组件的结构可靠性较差的问题。
另一可选的实施例中，当芯片组件还包括第二金属连接件150时，步骤S300具体包括：
S310、将第二金属连接件150设置于芯片130。
可选地，第二金属连接件150与芯片130之间可以采用焊接、粘接等方式连接，这里不作具体限制。
S310、将芯片130和第二金属连接件150均设置于粘接层120，并将第二金属连接件150与第一金属连接件140对齐设置。
本实施例中的芯片130通过第一金属连接件140和第二金属连接件150与基板110连接，有利于进一步将第一金属连接件140与第二金属连接件150之间的粘接层120挤压出去，避免粘接层120残留，从而提升芯片130与基板110之间的连接牢固性。
本申请实施例公开的电子设备可以是智能手机、平板电脑、电子书阅读器、可穿戴设备(例如智能手表)、电子游戏机等电子设备，本申请实施例对电子设备的种类不作具体限制。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (10)

  1. 一种芯片组件，包括基板(110)、粘接层(120)、芯片(130)和第一金属连接件(140)，所述基板(110)、所述粘接层(120)和所述芯片(130)依次叠置，所述第一金属连接件(140)凸出设置于所述基板(110)朝向所述粘接层(120)的一面，且所述芯片(130)通过所述第一金属连接件(140)与所述基板(110)相连。
  2. 根据权利要求1所述的芯片组件，其中，所述第一金属连接件(140)包括第一金属柱(141)和第一金属球(142)，所述第一金属球(142)设置于所述第一金属柱(141)的第一端，所述第一金属柱(141)的第一端通过所述第一金属球(142)与所述芯片(130)相连，所述第一金属柱(141)的第二端与所述基板(110)相连。
  3. 根据权利要求2所述的芯片组件，其中，所述第一金属柱(141)为铜柱，所述第一金属球(142)为锡球。
  4. 根据权利要求1所述的芯片组件，其中，所述第一金属连接件(140)为半球形结构，所述半球形结构的弧形面与所述芯片(130)相对设置，所述半球形结构的平面与所述基板(110)相连。
  5. 根据权利要求4所述的芯片组件，其中，所述芯片组件还包括第二金属连接件(150)，所述第二金属连接件(150)设置于所述芯片(130)朝向所述粘接层(120)的一面，所述第一金属连接件(140)通过所述第二金属连接件(150)与所述芯片(130)相连。
  6. 根据权利要求5所述的芯片组件，其中，所述第二金属连接件(150)包括第二金属柱(151)和第二金属球(152)，所述第一金属柱(141)的第一端与所述芯片(130)相连，所述第二金属球(152)设置于所述第二金属柱(151)的第二端，所述第二金属柱(151)的第二端通过所述第二金属球(152)与所述第一金属连接件(140)相连。
  7. 根据权利要求6所述的芯片组件，其中，所述第一金属连接件(140)为铜半球，所述第二金属柱(151)为铜柱，所述第二金属球(152)为锡球。
  8. 根据权利要求1所述的芯片组件，其中，所述第一金属连接件(140)的数量为至少两个，各所述第一金属连接件(141)间隔设置。
  9. 一种电子设备，包括权利要求1-8中任一项所述的芯片组件。
  10. 一种芯片组件的制备方法，包括：
    在基板上制备第一金属连接件；
    在所述基板上设置粘接层，所述粘接层覆盖所述第一金属连接件；
    将芯片设置于所述粘接层；
    加热所述芯片并按压所述芯片，以使所述芯片与所述第一金属连接件连接。
PCT/CN2023/121497 2022-09-30 2023-09-26 芯片组件、电子设备以及芯片组件的制备方法 Ceased WO2024067569A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202211211097.1 2022-09-30
CN202211211097.1A CN115513159A (zh) 2022-09-30 2022-09-30 芯片组件、电子设备以及芯片组件的制备方法

Publications (1)

Publication Number Publication Date
WO2024067569A1 true WO2024067569A1 (zh) 2024-04-04

Family

ID=84507785

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2023/121497 Ceased WO2024067569A1 (zh) 2022-09-30 2023-09-26 芯片组件、电子设备以及芯片组件的制备方法

Country Status (2)

Country Link
CN (1) CN115513159A (zh)
WO (1) WO2024067569A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115513159A (zh) * 2022-09-30 2022-12-23 维沃移动通信有限公司 芯片组件、电子设备以及芯片组件的制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100743653B1 (ko) * 2006-06-29 2007-07-30 주식회사 하이닉스반도체 적층 반도체 패키지 및 그 제조 방법
KR20080023823A (ko) * 2006-09-12 2008-03-17 엠텍비젼 주식회사 웨이퍼 레벨 패키지 적층 구조를 가지는 시스템 인 패키지및 그 제조 방법
TW201117328A (en) * 2009-11-10 2011-05-16 Powertech Technology Inc Thin type multi-chip package
CN112164659A (zh) * 2020-09-23 2021-01-01 湖北三江航天险峰电子信息有限公司 一种射频组件的焊接方法
CN113113402A (zh) * 2019-12-25 2021-07-13 盛合晶微半导体(江阴)有限公司 3dic封装结构及制备方法
WO2022016470A1 (zh) * 2020-07-23 2022-01-27 华为技术有限公司 一种芯片封装结构、电子设备
CN115513159A (zh) * 2022-09-30 2022-12-23 维沃移动通信有限公司 芯片组件、电子设备以及芯片组件的制备方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2581456B2 (ja) * 1994-06-27 1997-02-12 日本電気株式会社 部品の接続構造及びその製造方法
JPH1084055A (ja) * 1996-09-06 1998-03-31 Seiko Epson Corp 半導体装置及びその製造方法
KR100415239B1 (ko) * 2001-02-28 2004-01-14 에버그랜드 홀딩스 리미티드 기판에 반도체 칩을 실장하기 위한 방법 및 기판 상에실장하기에 적합한 반도체 장치
JP4175138B2 (ja) * 2003-02-21 2008-11-05 日本電気株式会社 半導体装置
TWI368978B (en) * 2007-09-21 2012-07-21 Unimicron Technology Corp Method for fabricating ball-implantation side surface structure of package substrate
CN112117258A (zh) * 2020-10-14 2020-12-22 立讯电子科技（昆山）有限公司 一种芯片封装结构及其封装方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100743653B1 (ko) * 2006-06-29 2007-07-30 주식회사 하이닉스반도체 적층 반도체 패키지 및 그 제조 방법
KR20080023823A (ko) * 2006-09-12 2008-03-17 엠텍비젼 주식회사 웨이퍼 레벨 패키지 적층 구조를 가지는 시스템 인 패키지및 그 제조 방법
TW201117328A (en) * 2009-11-10 2011-05-16 Powertech Technology Inc Thin type multi-chip package
CN113113402A (zh) * 2019-12-25 2021-07-13 盛合晶微半导体(江阴)有限公司 3dic封装结构及制备方法
WO2022016470A1 (zh) * 2020-07-23 2022-01-27 华为技术有限公司 一种芯片封装结构、电子设备
CN112164659A (zh) * 2020-09-23 2021-01-01 湖北三江航天险峰电子信息有限公司 一种射频组件的焊接方法
CN115513159A (zh) * 2022-09-30 2022-12-23 维沃移动通信有限公司 芯片组件、电子设备以及芯片组件的制备方法

Also Published As

Publication number Publication date
CN115513159A (zh) 2022-12-23

Similar Documents

Publication Publication Date Title
TW523894B (en) Semiconductor device and its manufacturing method
CN111312690A (zh) 系统级封装及其制备方法
CN102403275B (zh) 一种堆叠封装结构及其制作方法
CN100590643C (zh) 指纹辨识器的薄膜封装构造
CN101887885B (zh) 半导体封装体的堆叠构造
TW546792B (en) Manufacturing method of multi-chip stack and its package
CN101241904A (zh) 四方扁平无接脚型的多芯片封装结构
CN108022887B (zh) 一种柔性封装结构及其制备方法、可穿戴设备
CN206179848U (zh) 一种PoP堆叠封装结构
CN112151528A (zh) 包括相对表面上的接触指的半导体装置
WO2024067569A1 (zh) 芯片组件、电子设备以及芯片组件的制备方法
CN102169553B (zh) 带倒装裸芯片灌注胶料成型的sim贴膜卡封装制造方法
CN102937663B (zh) 智能电表核心模块的封装结构及封装方法
CN211088260U (zh) 天线的封装结构
CN101118901B (zh) 堆叠式芯片封装结构及其制程
WO2024153008A1 (zh) 芯片封装结构、电子设备和芯片封装结构的制作方法
WO2024125547A1 (zh) 封装结构、电子设备和封装方法
CN213692052U (zh) 双面封装结构及电子设备
CN210778554U (zh) 一种芯片的封装结构
CN207602549U (zh) 一种三维芯片堆叠芯片尺寸封装结构
CN114843238A (zh) 封装结构、电子设备及封装方法
CN209087816U (zh) 天线封装结构
CN112614830A (zh) 一种封装模组及电子设备
TW201036113A (en) Substrateless chip package and fabricating method
CN101226918A (zh) 芯片封装基板及其封装结构

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23870798

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 23870798

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 23870798

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 05/09/2025)