WO2024060339A1 - 半导体结构及版图结构 - Google Patents

半导体结构及版图结构 Download PDF

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Publication number
WO2024060339A1
WO2024060339A1 PCT/CN2022/125615 CN2022125615W WO2024060339A1 WO 2024060339 A1 WO2024060339 A1 WO 2024060339A1 CN 2022125615 W CN2022125615 W CN 2022125615W WO 2024060339 A1 WO2024060339 A1 WO 2024060339A1
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Prior art keywords
power
area
conductive
pad
pattern
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PCT/CN2022/125615
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English (en)
French (fr)
Inventor
徐静
冀康灵
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长鑫存储技术有限公司
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Priority to US18/450,798 priority Critical patent/US20240105618A1/en
Publication of WO2024060339A1 publication Critical patent/WO2024060339A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and relate to but are not limited to a semiconductor structure and layout structure.
  • LPDDR Low Power Double Data Rate Synchronous Dynamic Random-Access Memory, Low Power Double Data Rate Synchronous Dynamic Random Access Memory
  • LPDDR Low Power Double Data Rate Synchronous Dynamic Random-Access Memory
  • Low Power Double Data Rate Synchronous Dynamic Random Access Memory is a dynamic random access memory with low power consumption and high speed characteristics. In order to meet its high-speed and low-power consumption requirements, the design of power supply and related circuits is very important.
  • RDL Distribution Layer
  • embodiments of the present disclosure provide a semiconductor structure and a layout structure.
  • embodiments of the present disclosure provide a semiconductor structure, including:
  • a high-speed circuit module includes a clock signal, the frequency of the clock signal is greater than the first threshold
  • a first conductive metal layer includes a plurality of power conductors extending along the first direction and arranged at intervals, electrically connected to the high-speed circuit module;
  • a rewiring layer, located on the first conductive metal layer, the rewiring layer includes: a plurality of power pads, and conductive lines connected to the power pads; wherein the power pads are located on the high-speed One side of the circuit module, and the projected area of the power pad does not overlap with the high-speed circuit module; the conductive line includes a first conductor area formed by repeated bending, and the first conductor area at least partially covers the High-speed circuit module, the conductive wire is used to electrically connect the power wire and the power pad.
  • multiple power pads are used to provide different power voltages
  • Each of the power wires includes a plurality of power wires, and the plurality of power wires are respectively used to connect different power pads; wherein the power wires are electrically connected to the conductive wires of the corresponding power supply through a plurality of connection holes.
  • the conductive lines connected to the plurality of power pads with different power supply voltages are equally spaced in the first conductor area.
  • the plurality of power supply pads with different power supply voltages at least include: a first power supply pad, a second power supply pad and a third power supply pad arranged sequentially along the first direction; the first power supply pad The direction is the extension direction of the power conductor;
  • the conductive wire connected to the first power supply pad is the first conductive wire
  • the conductive wire connected to the second power supply pad is a second conductive wire
  • the conductive wire connected to the third power supply pad is a third conductive wire.
  • the second conductive line is bent in the first conductor area to form: a plurality of alternately arranged first recessed areas and second recessed areas extending along the first direction;
  • the notch of the first recessed area and the notch of the second recessed area are in opposite directions;
  • the first conductive line includes a plurality of first branch lines extending into the first recessed area along the first direction; the third conductive line includes a plurality of first branch lines extending into the second recessed area along the first direction. Second branch line within the recessed area.
  • it also includes:
  • the memory cell array area is located on the side of the high-speed circuit module away from the power pad; the memory cell array area includes a plurality of memory cell arrays; the power pad and the memory cell array are connected through the rewiring layers of conductive wire connections.
  • the conductive lines of the redistribution layer further include a second conductive line area for connecting the memory cell array; wherein the conductive lines of the second conductive line area and the projection area of the high-speed circuit module There is no overlap; the conductive lines of the first conductor area and the second conductor area are connected to each other.
  • the semiconductor structure includes a first region and a second region disposed in parallel;
  • the redistribution layer of the first region and the redistribution layer of the second region each include a plurality of power pads; wherein the power pads of the first region pass through the conductive Lines are connected to the memory cell array in the first area; and the power pads in the second area are connected to the memory cell array in the second area through the conductive lines in the second area.
  • the at least one power pad in the first region and the at least one power pad in the second region provide the same power voltage.
  • the difference in resistance values of the conductive lines connected to the power pads used to provide the same power supply voltage in the first region and the second region is less than a preset threshold.
  • the resistance values of conductive lines connected to the power pads used to provide the same power supply voltage in the first region and the second region are the same.
  • the first conductor area of the conductive line connected to the power pad in the first area is axially symmetrical with the first conductor area of the conductive line connected to the power pad in the second area. distributed.
  • the present disclosure also provides a layout structure, including:
  • the high-speed circuit module layout includes at least one signal for indicating a clock signal having a frequency greater than a first threshold
  • a first conductive metal layer layout includes a plurality of power conductor patterns extending along the first direction, used to represent the electrical connection to the high-speed circuit module layout;
  • a rewiring layer layout is located on the first conductive metal layer layout.
  • the rewiring layer layout includes: a plurality of power supply pad patterns, and a conductive line pattern connected to the power supply pad pattern; wherein, the power supply The pad pattern is located on one side of the high-speed circuit module layout, and the projection area of the power pad pattern does not overlap with the high-speed circuit module layout; the conductive line pattern includes a first conductor area formed by repeated bending, The first conductor area at least partially covers the high-speed circuit module layout, and the conductive line pattern connects the power conductor pattern and the power pad pattern.
  • the plurality of power pad patterns include at least: a first power pad pattern, a second power pad pattern, and a third power pad pattern arranged sequentially along the first direction; the first power pad pattern The direction is the extension direction of the power conductor pattern;
  • the conductive line pattern connected to the first power pad pattern is a first conductive line pattern
  • the conductive line pattern connected to the second power supply pad pattern is a second conductive line pattern
  • the conductive line pattern connected to the third power pad pattern is a third conductive line pattern.
  • the second conductive line pattern is bent in the first conductor area to form: a plurality of alternately arranged first recessed areas and second recessed areas extending along the first direction;
  • the notch of the first recessed area and the notch of the second recessed area are in opposite directions;
  • the first conductive line pattern includes a plurality of first branch line patterns extending into the first recessed area along the first direction; the third conductive line pattern includes a plurality of first branch line patterns extending into the first recessed area along the first direction.
  • the second branch line pattern in the second recessed area.
  • the layout structure further includes:
  • the memory cell array area layout is located on the side of the high-speed circuit module layout away from the power supply pad pattern; the memory unit array area layout includes a plurality of memory cell array patterns; the power supply pad pattern and the memory unit The array patterns are connected through the conductive line patterns of the redistribution layer layout.
  • a plurality of power pads are located on the redistribution layer, and are connected to the first conductive metal layer through conductive lines having first conductive line areas formed by repeated bending on the redistribution layer, and are electrically connected to High-speed circuit modules.
  • the contact area between the conductive wire and the high-speed circuit module can be effectively increased, so that the power supply can directly supply power to the high-speed circuit, thereby reducing power consumption.
  • the conductive lines in the rewiring layer can also be extended and connected to other circuit modules without affecting the power supply to high-speed circuits.
  • Figure 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure
  • Figure 2 is a schematic diagram of a partial cross-section of a semiconductor structure according to an embodiment of the present disclosure
  • Figure 3 is a schematic diagram of power supply wires arranged at intervals in a semiconductor structure according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of multiple power lines included in a power conductor in a semiconductor structure according to an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the distribution of conductive lines in a semiconductor structure according to an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of a semiconductor structure including a memory cell array according to an embodiment of the present disclosure
  • Figure 7 is a schematic diagram of a semiconductor structure including different partitions according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a layout structure according to an embodiment of the present disclosure.
  • terms can be understood, at least in part, from context of use.
  • the term "one or more” as used herein may be used in the singular to describe any feature, structure or characteristic, or may be used in the plural to describe a combination of features, structures or characteristics.
  • terms such as “a” or “the” may equally be understood to convey a singular usage or to convey a plural usage, depending at least in part on the context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on context.
  • an embodiment of the present disclosure provides a semiconductor structure 100, including:
  • the high-speed circuit module 110 includes a clock signal, the frequency of the clock signal is greater than the first threshold;
  • a first conductive metal layer 120 wherein the first conductive metal layer 120 includes a plurality of power supply wires 121 extending along a first direction and arranged at intervals, and is electrically connected to the high-speed circuit module 110;
  • the redistribution layer 130 is located on the first conductive metal layer 120.
  • the redistribution layer 130 includes: a plurality of power supply pads 131, and conductive lines 132 connected to the power supply pads 131; wherein, the power supply
  • the bonding pad 131 is located on one side of the high-speed circuit module 110, and the projected area of the power bonding pad 131 does not overlap with the high-speed circuit module 110;
  • the conductive wire 132 includes a first conductor area 132a formed by repeated bending. , the first conductive wire area 132a at least partially covers the high-speed circuit module 110, and the conductive wire 132 is used to electrically connect the power wire 121 and the power pad 131.
  • the semiconductor structure involved in the embodiments of the present disclosure can be applied to memory, which can include but is not limited to DRAM, static random access memory (Static Random Access Memory, SRAM), ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), magnetic random access memory Memory (Magnetoresistive Random Access Memory, MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (Nano Random Access Memory, NRAM), etc. Especially applicable to LPDDR memory.
  • DDR is an ordinary memory stick
  • LPDDR is a memory with low power consumption. It can be used in products that are sensitive to power consumption, volume, etc., such as smartphones and smart watches.
  • LPDDR5 also has high-speed characteristics. Its digital logic circuit adopts high-speed circuit design to increase the data processing rate. Generally speaking, high-speed circuits can also be called high-frequency circuits. The operation of high-speed circuits is based on the signal edges of high-speed transition clock signals to implement digital circuit operations. When the data transmission rate of the digital logic circuit is higher than the first threshold (for example, 4800 megabits per second (Mbps)), the circuit can be considered to be a high-speed circuit.
  • the high-speed circuit module 110 generally refers to any logic circuit module with high-speed characteristics in the memory used in the semiconductor structure 100 of the embodiment of the present disclosure.
  • the first conductive metal layer 120 at least includes power wires 121 for providing power signals to the high-speed circuit module 110 .
  • These power wires 121 may be part of the high-speed circuit module 110 , that is, the high-speed circuit module 110 may include power wires located on the first conductive metal layer 120 Some power wires.
  • the high-speed circuit module 110 may also include devices and circuit modules located in other metal layers or structural layers of the semiconductor structure.
  • the first conductive metal layer 120 may be the top metal layer M4 in the memory structure.
  • the power wires 121 in the first conductive metal layer 120 may include a plurality of wires extending along the first direction, and each wire may be used to provide power signals to different locations of the high-speed circuit module 110.
  • the first direction may be the X direction as shown in FIG. 1 .
  • the redistribution layer 130 is located on the first conductive metal layer 120 , which means in the Z direction as shown in FIG. 1 , that is, the redistribution layer 130 is another layer covering the first conductive metal layer 120 .
  • the first conductive metal layer 120 may be covered with an insulating material layer 124 , such as an oxide, or an organic compound such as TEOS (tetraethoxysilane) as shown in the figure.
  • the redistribution layer 130 covers the insulating material layer, and the redistribution layer 130 can be connected to the first conductive metal layer 120 through the through hole 122 penetrating the insulating material layer.
  • the rewiring layer 130 may include various signal pads, including power pads, data interface pads, ground pads, and so on. As shown in FIG. 2 , the redistribution layer 130 may be covered with another layer of insulating material 125 , such as PI (Polyimide, polyimide), silicon nitride, and other oxide or organic compound materials. The positions of various signal pads may not be covered by insulating materials and exposed to facilitate the access of other signal terminals.
  • PI Polyimide, polyimide
  • silicon nitride silicon nitride
  • the materials used for the first conductive metal layer 120 and the redistribution layer 130 may be metal aluminum, metal copper, or various other conductive materials, such as titanium nitride (TiN).
  • the conductive line 132 in the redistribution layer 130 has a first conductive line area 132a formed by repeated bending.
  • the first conductive line area 132a is located at a point where the power pad 131 is located in the Y direction as shown in FIG. 1 side.
  • the conductive wire 132 extends from the power pad 131 to the first conductor area 132a and is repeatedly bent, so that the conductive wire 132 and the power conductor 121 located above the power conductor 121 of the first conductive metal layer 120 have more overlapping positions. .
  • electrical connections can be made between the first conductive metal layer 120 and the redistribution layer 130 through more through holes, thereby increasing the contact area between the two layers of wires and reducing the contact resistance. Since the power wires 121 in the first conductive metal layer 120 can be directly used to supply power to the high-speed circuit, the above design can effectively reduce power consumption and ensure the power supply of the high-speed circuit.
  • the plurality of power supply wires 121 can be arranged in parallel and spaced apart, so as to cover more areas and provide power supply voltages to different nodes of the first conductive metal layer 120 . In this way, different nodes can be connected to corresponding metal lines nearby without the need for too many jumpers.
  • Each power wire 121 can be electrically connected to the above-mentioned conductive wire 132 through a through hole (not shown in FIG. 3 ). Therefore, each power wire 121 can include a power wire that provides the same power signal.
  • multiple power pads are used to provide different power voltages
  • Each of the power wires includes a plurality of power wires, and the plurality of power wires are respectively used to connect different power pads; wherein, the power wires are electrically connected to the conductive wires of the corresponding power supply through a plurality of connection holes.
  • Each power wire 121 may include multiple power wires, and these power wires may also be arranged in parallel and at intervals, as shown in FIG. 4 .
  • Different power lines are used to connect different power sources.
  • the conductive lines 132 connected to different power supply pads can be provided with through holes 122 to connect the conductive lines 132 at positions that overlap with the projections of the corresponding power lines in the first conductor area 132a. with a power cord.
  • the power supply wire 121 includes a first power line VDD2H, a second power line VSS and a third power line VDD2L arranged at intervals.
  • FIG. 4 only exemplarily shows the spacing arrangement relationship between the three power lines, and is not used to limit these power lines to be straight lines, nor does it indicate that the power lines must be distributed in parallel.
  • each power cord may be bent, for example, several power cords may also be intertwined with each other.
  • each power line may have multiple through holes 122 for connecting to the conductive line 132.
  • the through holes 122 on two adjacent power lines may be staggered, and adjacent through holes 122 on the same power line may also be interlaced.
  • the distribution can be staggered, thereby reducing signal interference between individual vias, and improving the stability of the structure during the manufacturing process.
  • the conductive lines connected to the plurality of power pads with different power supply voltages are equally spaced in the first conductor area.
  • a plurality of power pads for providing different power voltages are connected to respective conductive lines, and are repeatedly bent in the first conductor area.
  • the conductive lines connected to different power supply pads cannot cross each other, and they can also be regularly distributed alternately at the bending positions.
  • different conductive lines can be distributed at equal intervals, which on the one hand facilitates connection to the first conductive metal layer 120 and on the other hand, can reduce crosstalk between signals.
  • the plurality of power supply pads with different power supply voltages at least include: a first power supply pad 501 , a second power supply pad 502 and a third power supply pad 502 arranged sequentially along the first direction.
  • Power pad 503; the first direction is the extension direction of the power wire 121;
  • the conductive wire connected to the first power pad 501 is the first conductive wire 511;
  • the conductive wire connected to the second power pad 502 is the second conductive wire 512;
  • the conductive wire connected to the third power pad 503 is the third conductive wire 513 .
  • the above-mentioned first power pad 501 may be a pad VDD2H that provides a first high power voltage
  • the second power pad 502 may be a pad VSS that is used to provide a low power voltage or grounding
  • the third power pad 503 may be Provides a second high supply voltage pad, VDD2L.
  • VDD2H and VDD2L can be used to provide different power signals to the high-speed circuit module through the first conductive metal layer 120 to achieve more flexible and complex circuit functions.
  • the above design is only an exemplary embodiment. In actual applications, the above-mentioned power pads may also include other pads that provide power supply voltages of different sizes, which may depend on the functions and requirements of the high-speed circuit module.
  • first power pad 501, second power pad 502 and third power pad 503 may also include one or more, that is, each power pad may not be limited to one, thereby facilitating the layout and routing of the circuit. line design.
  • the second conductive line 512 is bent in the first conductor area 132a to form a plurality of alternately arranged first recessed areas s1 and second recessed areas s2 extending in the first direction. ;
  • the notch of the first recessed area s1 and the notch of the second recessed area s2 are in opposite directions;
  • the first conductive line 511 includes a plurality of first branches 521 extending into the first recessed area s1 along the first direction; the third conductive line 513 includes a plurality of second branches 523 extending into the second recessed area s2 along the first direction.
  • the second power pad 502 is located between the first power pad 501 and the third power pad 503.
  • the first power pad 501, the second power pad 502 and the third power pad 503 are The connected first conductive line 511, the second conductive line 512 and the third conductive line 513 extend from each power pad to the first conductive line area 132a and are bent.
  • the three conductive lines are located at
  • the second conductive line 512 in the middle may adopt a serpentine structure and extend in the first direction (X direction).
  • the bent shape of the second conductive line 512 has a plurality of recessed areas on both sides in the second direction.
  • the first conductive line 511 and the third conductive line 513 can each be provided with a plurality of finger-shaped branch lines extending into the opening. .
  • the first branch line 521 of the first conductive line 511 can extend to the first recessed area s1 in one direction
  • the second branch line 523 of the third conductive line 513 can extend to the second recessed area in the opposite direction to the first recessed area s1 s2.
  • the three conductive wires can be bent to increase the contact area with the first conductive metal layer 120.
  • the voltage balance of the three power supplies at each position can be maintained, improving the stability of the circuit.
  • the semiconductor structure 100 further includes:
  • the memory cell array area 610 is located on a side of the high-speed circuit module 110 away from the power pad 131 ; the memory cell array area 610 includes a plurality of memory cell arrays 611 ; the power pad 131 is connected to the memory cell arrays 611 via a conductive line 132 of the redistribution layer 130 .
  • the power pad 131 can also be used to provide power signals to the memory cell array 611 .
  • the conductive lines 132 connected to each power pad 131 may extend to the memory cell array area 610 to connect each memory cell array.
  • the conductive lines 132 of the redistribution layer 130 also include a second conductive line area 132b for connecting the memory cell array 611; wherein the conductive lines 132 of the second conductive line area 132b and the The projected areas of the high-speed circuit module 110 do not overlap; the conductive lines 132 of the first conductor area 132a and the second conductor area 132b are connected to each other.
  • the conductive lines in the second conductive line area 132b may be straight lines, or may have some bends to connect to the required positions of the memory cell array 611.
  • the semiconductor structure 100 includes a first region 710 and a second region 720 arranged side by side;
  • the rewiring layer 130 of the first area 710 and the rewiring layer 130 of the second area 720 respectively include a plurality of power pads 131; wherein, the power pads 131 of the first area 710 pass through the first
  • the conductive lines 132 of the area 710 are connected to the memory cell array 611 of the first area 710; the power pad 131 of the second area 720 is connected to the memory cells of the second area through the conductive lines 132 of the second area 720.
  • the above-mentioned semiconductor structure 100 can also include more partitions.
  • Each partition can have the same power pads, conductive lines and other structures, and can be connected to different memory cell arrays respectively, thereby facilitating the expansion of the memory cell array. quantity.
  • the power wire 121 extending along the first direction in the first conductive metal layer 120 can directly penetrate the first area 710 and the second area 720 , and connected to the corresponding high-speed circuit module 110.
  • the at least one power pad 131 of the first region 710 and the at least one power pad 131 of the second region 720 provide the same power voltage.
  • the circuit structures, pads, conductive lines and other structures in the first area 710 and the second area 720 may be the same.
  • the circuit structures, pads, conductive lines and other structures in the first area 710 and the second area 720 may also be different, but they may have some identical power supply pads for providing the same power supply voltage.
  • the first area 710 and the second area 720 respectively include a first power pad VDD2H, a second power pad VSS, and a third power pad VDD2L.
  • the difference in resistance values of the conductive lines connected to the power pads used to provide the same power supply voltage in the first region and the second region is less than a preset threshold.
  • the extension paths of the conductive lines between the same power pad and the corresponding memory cell array may also be different. That is, the structures such as the power pads and conductive lines in the first area and the second area are not completely symmetrical, which may result in differences in the power supply voltages provided to different memory cell arrays.
  • a threshold can be preset according to actual requirements, and the difference in resistance values of the two conductive lines needs to be less than the preset threshold.
  • the total length of the conductive wire can be adjusted by designing the bending shape, and then the corresponding resistance value can be set so that the resistance values of the two conductive wires are as equal as possible .
  • the resistance values of conductive lines connected to the power pads used to provide the same power supply voltage in the first region and the second region are the same.
  • the first conductor area of the conductive line connected to the power pad in the first area is axially symmetrical with the first conductor area of the conductive line connected to the power pad in the second area. distributed.
  • the corresponding conductive lines in the first area and the second area are axially symmetrically distributed in the first conductor area and have the same total length and resistance value. If the distribution of power pads in the first area is not symmetrical to the distribution of power pads in the second area, the resistance values of the conductive lines on both sides can be achieved by adjusting the length and shape of the conductive lines in areas other than the first conductor area. consistency. As shown in FIG. 7 , considering that the positions of the power pads in the first area 710 and the second area 720 are not completely symmetrical, the same power pads 131 in the first area 710 and the second area 720 are connected to their respective The distances between the memory cell array areas 610 are different.
  • the length and shape of the conductive lines can be flexibly designed.
  • the additional extended portion of the conductive lines (the position in the dotted circle in the figure) connected to the power pad VDD2H of the second area 720 in Figure 7 is used to The resistance of the conductive line connected to the power pad VDD2H in the first area 710 is maintained consistent.
  • the additional bent portion of the power pad VSS in the second area 720 (the position in the dotted circle in the figure) is also used to maintain consistency with the resistance of the conductive line connected to the power pad VSS in the first area 710 .
  • An embodiment of the present disclosure also provides a memory, including:
  • the memory can be any kind of memory, and its circuit structure and distribution of the memory cell array can be designed in the above-mentioned semiconductor structure.
  • this embodiment of the present disclosure also provides a layout structure 200, including:
  • the high-speed circuit module layout 210 at least includes a clock signal indicating that the frequency is greater than the first threshold
  • a first conductive metal layer layout 220 wherein the first conductive metal layer layout 220 includes a plurality of power conductor patterns 221 extending along a first direction, and is used to indicate electrical connection to the high-speed circuit module layout 210;
  • the rewiring layer layout 230 is located on the first conductive metal layer layout 220.
  • the rewiring layer layout 230 includes: a plurality of power pad patterns 231, and a conductive line pattern 232 connected to the power pad pattern 231. ;
  • the power pad pattern 231 is located on one side of the high-speed circuit module layout 210, and the projection area of the power pad pattern 231 does not overlap with the high-speed circuit module layout 210;
  • the conductive line pattern 232 It includes a first conductor area 232a formed by repeated bending.
  • the first conductor area 232a at least partially covers the high-speed circuit module layout 210.
  • the conductive line pattern 232 connects the power conductor pattern 221 and the power pad pattern. 231.
  • the conductive line pattern 232 is repeatedly bent within the range of the first conductive line area 232a, which can have more overlapping areas with the first conductive metal layer layout 220, thereby facilitating the setting of more through hole patterns 240 to represent The connection relationship between the conductive line pattern 232 and the power supply wire pattern 221 in the first conductive metal layer layout 220.
  • the plurality of power pad patterns include at least: a first power pad pattern, a second power pad pattern, and a third power pad pattern arranged sequentially along the first direction; the first power pad pattern The direction is the extension direction of the power conductor pattern;
  • the conductive line pattern connected to the first power pad pattern is a first conductive line pattern
  • the conductive line pattern connected to the second power supply pad pattern is a second conductive line pattern
  • the conductive line pattern connected to the third power pad pattern is a third conductive line pattern.
  • the second conductive line pattern is bent in the first conductor area to form: a plurality of alternately arranged first recessed areas and second recessed areas extending along the first direction;
  • the notch of the first recessed area and the notch of the second recessed area are in opposite directions;
  • the first conductive line pattern includes a plurality of first branch line patterns extending into the first recessed area along the first direction; the third conductive line pattern includes a plurality of first branch line patterns extending into the first recessed area along the first direction.
  • the second branch line pattern in the second recessed area.
  • the layout structure further includes:
  • the memory unit array area layout is located on the side of the high-speed circuit module layout away from the power supply pad pattern; the memory unit array area layout includes a plurality of memory unit array patterns; the power supply pad pattern and the memory unit The array patterns are connected through the conductive line patterns of the redistribution layer layout.
  • the disclosed devices and methods can be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of the devices or units may be electrical, mechanical, or other forms. of.
  • the units described above as separate components may or may not be physically separated; the components shown as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure can be all integrated into one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • a plurality of power pads are located on the redistribution layer, and are connected to the first conductive metal layer through conductive lines having first conductive line areas formed by repeated bending on the redistribution layer, and are electrically connected to High speed circuit module.
  • the contact area between the conductive wire and the high-speed circuit module can be effectively increased, so that the power supply can directly supply power to the high-speed circuit, thereby reducing power consumption.
  • the conductive lines in the rewiring layer can also be extended and connected to other circuit modules without affecting the power supply to high-speed circuits.

Abstract

本公开实施例公开了一种半导体结构、存储器及版图结构，该半导体结构包括：高速电路模块，包括时钟信号，所述时钟信号的频率大于第一阈值；第一导电金属层，所述第一导电金属层包括多条沿第一方向延伸且间隔排布的电源导线，电连接所述高速电路模块；重布线层，位于所述第一导电金属层上，所述重布线层包括：多个电源焊盘，以及与所述电源焊盘连接的导电线；其中，所述电源焊盘位于所述高速电路模块的一侧，且所述电源焊盘的投影区域与所述高速电路模块不重叠；所述导电线包括反复弯折形成的第一导线区，所述第一导线区至少部分覆盖所述高速电路模块，所述导电线用于电连接所述电源导线与所述电源焊盘。

Description

半导体结构及版图结构
相关申请的交叉引用
本公开基于申请号为202211160024.4、申请日为2022年09月22日、发明名称为“半导体结构及版图结构”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术领域，涉及但不限于一种半导体结构及版图结构。
背景技术
LPDDR(Low Power Double Data Rate Synchronous Dynamic Random-Access Memory，低功耗双倍数据率同步动态随机存取内存)是一种具有低功耗和高速率特点的动态随机存储器。为了满足其高速和低功耗的要求，电源及相关电路的设计是十分重要的。
相关技术中，在电源焊盘位置固定的情况下，要使用RDL(Redistribution Layer，重布线层)直接将电源信号接入LPDDR的高速电路，并同时对存储器的其他模块，如存储单元阵列等进行供电是一个设计难点。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及版图结构。
第一方面，本公开实施例提供一种半导体结构，包括：
高速电路模块，包括时钟信号，所述时钟信号的频率大于第一阈值；
第一导电金属层，所述第一导电金属层包括多条沿第一方向延伸且间隔排布的电源导线，电连接所述高速电路模块；
重布线层，位于所述第一导电金属层上，所述重布线层包括：多个电源焊盘，以及与所述电源焊盘连接的导电线；其中，所述电源焊盘位于所述高速电路模块的一侧，且所述电源焊盘的投影区域与所述高速电路模块不重叠；所述导电线包括反复弯折形成的第一导线区，所述第一导线区至少部分覆盖所述高速电路模块，所述导电线用于电连接所述电源导线与所述电源焊盘。
在一些实施例中，多个所述电源焊盘用于提供不同电源电压；
每条所述电源导线包括多个电源线，多个所述电源线分别用于连接不 同的电源焊盘；其中，所述电源线与对应电源的所述导电线通过多个连接孔电连接。
在一些实施例中，所述多个不同电源电压的电源焊盘所连接的导电线在所述第一导线区等间距分布。
在一些实施例中，所述多个不同电源电压的电源焊盘至少包括：沿第一方向依次排布的第一电源焊盘、第二电源焊盘和第三电源焊盘；所述第一方向为所述电源导线的延伸方向；
所述第一电源焊盘连接的导电线为第一导电线；
所述第二电源焊盘连接的导电线为第二导电线；
所述第三电源焊盘连接的导电线为第三导电线。
在一些实施例中，所述第二导电线在所述第一导线区内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域和第二凹陷区域；
其中，所述第一凹陷区域的凹口与所述第二凹陷区域的凹口的朝向相反；
所述第一导电线沿所述第一方向包括多个延伸至所述第一凹陷区域内的第一支线；所述第三导电线沿所述第一方向包括多个延伸至所述第二凹陷区域内的第二支线。
在一些实施例中，还包括：
存储单元阵列区，位于所述高速电路模块远离所述电源焊盘的一侧；所述存储单元阵列区包括多个存储单元阵列；所述电源焊盘与所述存储单元阵列通过所述重布线层的导电线连接。
在一些实施例中，所述重布线层的导电线还包括用于连接所述存储单元阵列的第二导线区；其中，所述第二导线区的导电线与所述高速电路模块的投影区域不重叠；所述第一导线区与所述第二导线区的所述导电线相互连接。
在一些实施例中，所述半导体结构包括并列设置的第一区和第二区；
所述第一区的重布线层和所述第二区的重布线层分别包括多个所述电源焊盘；其中，所述第一区的电源焊盘通过所述第一区的所述导电线连接至所述第一区的存储单元阵列；所述第二区的电源焊盘通过所述第二区的所述导电线连接至所述第二区的存储单元阵列。
在一些实施例中，所述第一区的至少一个电源焊盘与所述第二区的至少一个电源焊盘提供的电源电压相同。
在一些实施例中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值之差小于预设阈值。
在一些实施例中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值相同。
在一些实施例中，所述第一区中电源焊盘连接的导电线的所述第一导线区与所述第二区中电源焊盘连接的导电线的所述第一导线区呈轴对称分 布。
第二方面，本公开实施例还提供一种版图结构，包括：
高速电路模块版图，至少包括用于表示包含有频率大于第一阈值的时钟信号；
第一导电金属层版图，所述第一导电金属层版图包括多条沿第一方向延伸的电源导线图形，用于表示电连接所述高速电路模块版图；
重布线层版图，位于所述第一导电金属层版图上，所述重布线层版图包括：多个电源焊盘图形，以及与所述电源焊盘图形连接的导电线图形；其中，所述电源焊盘图形位于所述高速电路模块版图的一侧，且所述电源焊盘图形的投影区域与所述高速电路模块版图不重叠；所述导电线图形包括反复弯折形成的第一导线区，所述第一导线区至少部分覆盖所述高速电路模块版图，所述导电线图形连接所述电源导线图形与所述电源焊盘图形。
在一些实施例中，多个所述电源焊盘图形至少包括：沿第一方向依次排布的第一电源焊盘图形、第二电源焊盘图形和第三电源焊盘图形；所述第一方向为所述电源导线图形的延伸方向；
所述第一电源焊盘图形连接的导电线图形为第一导电线图形；
所述第二电源焊盘图形连接的导电线图形为第二导电线图形；
所述第三电源焊盘图形连接的导电线图形为第三导电线图形。
在一些实施例中，所述第二导电线图形在所述第一导线区内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域和第二凹陷区域；
其中，所述第一凹陷区域的凹口与所述第二凹陷区域的凹口的朝向相反；
所述第一导电线图形沿所述第一方向包括多个延伸至所述第一凹陷区域内的第一支线图形；所述第三导电线图形沿所述第一方向包括多个延伸至所述第二凹陷区域内的第二支线图形。
在一些实施例中，所述版图结构还包括：
存储单元阵列区版图，位于所述高速电路模块版图远离所述电源焊盘图形的一侧；所述存储单元阵列区版图包括多个存储单元阵列图形；所述电源焊盘图形与所述存储单元阵列图形通过所述重布线层版图的导电线图形连接。
本公开实施例的技术方案中，多个电源焊盘位于重布线层，并通过重布线层上具有反复弯折形成的第一导线区的导电线与第一导电金属层连接，并电连接至高速电路模块。这样，可以有效增大导电线与高速电路模块的接触面积，使得电源可以直接对高速电路进行供电，便于降低功耗。同时，重布线层中的导电线也可以延伸并连接其他电路模块，且不会影响对高速电路的供电。
附图说明
图1为本公开实施例的一种半导体结构的示意图；
图2为本公开实施例的一种半导体结构的部分截面的示意图；
图3为本公开实施例的一种半导体结构中间隔排布的电源导线示意图；
图4为本公开实施例的一种半导体结构中电源导线包含的多条电源线的示意图；
图5为本公开实施例的一种半导体结构中导电线的分布示意图；
图6为本公开实施例的一种半导体结构包含有存储单元阵列的示意图；
图7为本公开实施例的一种半导体结构中包含有不同分区的示意图；
图8为本公开实施例的一种版图结构的示意图。
具体实施方式
为了便于理解本公开，下面将参照相关附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在一些实施例中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述，即可以不描述实际实施例的全部特征，不详细描述公知的功能和结构。
一般地，术语可以至少部分地从上下文中的使用来理解。例如，至少部分地取决于上下文，如本文中所用的术语“一个或多个”可以用于以单数意义描述任何特征、结构或特性，或者可以用于以复数意义描述特征、结构或特性的组合。类似地，诸如“一”或“所述”的术语同样可以被理解为传达单数用法或传达复数用法，这至少部分地取决于上下文。另外，属于“基于”可以被理解为不一定旨在传达排他的一组因素，并且可以替代地允许存在不一定明确地描述的附加因素，这同样至少部分地取决于上下文。
除非另有定义，本文使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在使用时，单数形式的“一”、“一个”和“/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
如图1所示，本公开实施例提供一种半导体结构100，包括：
高速电路模块110，包括时钟信号，所述时钟信号的频率大于第一阈值；
第一导电金属层120，所述第一导电金属层120包括多条沿第一方向延伸且间隔排布的电源导线121，电连接所述高速电路模块110；
重布线层130，位于所述第一导电金属层120上，所述重布线层130包括：多个电源焊盘131，以及与所述电源焊盘131连接的导电线132；其中，所述电源焊盘131位于所述高速电路模块110的一侧，且所述电源焊盘131的投影区域与所述高速电路模块110不重叠；所述导电线132包括反复弯折形成的第一导线区132a，所述第一导线区132a至少部分覆盖所述高速电路模块110，所述导电线132用于电连接所述电源导线121与所述电源焊盘131。
本公开实施例所涉及的半导体结构可以应用于存储器，该存储器可以包括但不限于DRAM、静态随机存储器(Static Random Access Memory，SRAM)、铁电随机存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存储器(Magnetoresistive Random Access Memory，MRAM)、相变随机存储器(Phase Change Random Access Memory，PCRAM)、阻变随机存储器(Resistive Random Access Memory，RRAM)、纳米随机存储器(Nano Random Access Memory，NRAM)等。尤其可以应用于LPDDR存储器。
DDR是一种普通的内存条，LPDDR则是具有低功耗特点的内存，可以应用于智能手机、智能手表等对于功耗、体积等比较敏感的产品。
此外，LPDDR5还具有高速的特点，其数字逻辑电路采用高速电路的设计来提升数据处理速率。一般来说，高速电路也可以称为高频电路，高速电路的工作时基于高速跳变的时钟信号的信号沿来实现数字电路的运算的。在数字逻辑电路的数据传输速率高于第一阈值(例如，4800兆比特每秒(Mbps))时，则可以认为该电路为高速电路。这里，高速电路模块110泛指在本公开实施例的半导体结构100所应用的存储器中的任意具有高速特性的逻辑电路模块。
第一导电金属层120至少包括是为提供高速电路模块110的电源信号的电源导线121，这些电源导线121可以是高速电路模块110的一部分，即高速电路模块110可以包括位于第一导电金属层120的一些电源导线，另外，高速电路模块110也可以包括位于该半导体结构其他金属层或者结构层中的器件和电路模块。示例性地，第一导电金属层120可以为存储器结构中的顶层金属层M4。
在本公开实施例中，上述第一导电金属层120中的电源导线121可以 包括沿第一方向延伸的多条导线，每条导线都可以用于向高速电路模块110的不同位置提供电源信号。这里，第一方向可以是如图1所示的X方向。
在本公开实施例中，重布线层130位于第一导电金属层120上，是指在如图1所示的Z方向上，即重布线层130是覆盖在第一导电金属层120上的另一金属层。如图2所示，第一导电金属层120上可以覆盖有绝缘材料层124，例如氧化物、或者如图中示出的TEOS(四乙氧基硅烷)等有机化合物。重布线层130则覆盖于绝缘材料层上，重布线层130可通过贯穿绝缘材料层的通孔122与第一导电金属层120连接。重布线层130可以包括各种信号焊盘，包括电源焊盘、数据接口焊盘、接地焊盘等等。如图2所示，重布线层130上可以覆盖另一层绝缘材料125，例如PI(Polyimide，聚酰亚胺)、氮化硅以及其他氧化物或者有机化合物材料等。各种信号焊盘的位置则可以不被绝缘材料覆盖，裸露在外，以便其他信号端接入。
上述第一导电金属层120以及重布线层130所使用的材料可以为金属铝、金属铜或者其他各种导电材料，如氮化钛(TiN)等。
在本公开实施例中，重布线层130中的导电线132具有反复弯折形成的第一导线区132a，第一导线区132a位于电源焊盘131位于如图1所示的Y方向上的一侧。导电线132由电源焊盘131延伸出来至第一导线区132a的位置进行反复弯折，使得位于第一导电金属层120的电源导线121上方的导电线132与电源导线121具有更多的重叠位置。这样，可以在第一导电金属层120与重布线层130之间通过更多的通孔进行电连接，从而增大两层导线之间的接触面积，减少接触电阻。由于第一导电金属层120中的电源导线121可以直接用于向高速电路供电，因此，通过上述设计可以有效降低功耗并保证高速电路的电源供应。
如图3所示，上述多条电源导线121可以平行地间隔设置，从而可以覆盖更多的区域，为第一导电金属层120的不同节点提供电源电压。这样，不同节点可以就近连接对应的金属线，不需要过多的跳线。
每条电源导线121都可以与上述导电线132通过通孔(图3中未示出)进行电连接，因此，每条电源导线121都可以包括提供相同的电源信号电源线。
在一些实施例中，多个所述电源焊盘用于提供不同电源电压；
每条所述电源导线包括多个电源线，多个所述电源线分别用于连接不同的电源焊盘；其中，所述电源线与对应电源的所述导电线通过多个连接孔电连接。
每条电源导线121，可以包括多个电源线，这些电源线也可以平行地间隔排布，如图4所示。不同的电源线用于连接不同的电源，不同的电源焊盘所连接的导电线132在上述第一导线区132a中与对应的电源线的投影重叠的位置则可以设置通孔122连接导电线132与一条电源线。
示例性地，如图4所示，上述电源导线121包括间隔排布的第一电源 线VDD2H、第二电源线VSS以及第三电源线VDD2L。
需要说明的是，图4仅示例性地示出3条电源线之间间隔排布的关系，并不用于限定这些电源线为直线，也并不表明电源线之间一定为平行分布。事实上，每条电源线都可以存在弯折，例如几条电源线之间也存在相互之间插指的形态。
此外，每条电源线上可以具有多个通孔122用于与导电线132连接，相邻两条电源线上的通孔122可以交错分布，同一条电源线上的相邻的通孔122也可以交错分布，从而减少各个通孔之间的信号干扰，并且可以便于在制造过程中提升结构的稳定性。
在一些实施例中，所述多个不同电源电压的电源焊盘所连接的导电线在所述第一导线区等间距分布。
如图1所示，多个用于提供不同电源电压的电源焊盘分别连接各自的导电线，并在第一导线区反复弯折。在第一导线区内，不同电源焊盘连接的导电线之间不能交叉，在发生弯折的位置也可以是有规律的交替分布。在第一导线区内，不同的导电线之间可以等间距分布，从而一方面便于分别连接至第一导电金属层120，另一方面，可以减少信号间的串扰。
在一些实施例中，如图5所示，所述多个不同电源电压的电源焊盘至少包括：沿第一方向依次排布的第一电源焊盘501、第二电源焊盘502和第三电源焊盘503；所述第一方向为所述电源导线121的延伸方向；
所述第一电源焊盘501连接的导电线为第一导电线511；
所述第二电源焊盘502连接的导电线为第二导电线512；
所述第三电源焊盘503连接的导电线为第三导电线513。
上述第一电源焊盘501可以为提供第一种高电源电压的焊盘VDD2H，第二电源焊盘502可以是用于提供低电源电压或者接地的焊盘VSS，第三电源焊盘503可以为提供第二种高电源电压的焊盘VDD2L。这里，VDD2H与VDD2L可以用于通过第一导电金属层120向高速电路模块提供不同的电源信号，以便实现更加灵活复杂的电路功能。以上设计仅为示例性的实施例，在实际应用中，上述电源焊盘还可以包括其他提供不同大小电源电压的焊盘，具体可以取决于高速电路模块的功能和需求。
此外，上述第一电源焊盘501、第二电源焊盘502以及第三电源焊盘503还可以分别包括一个或多个，即每种电源焊盘可以不限于一个，从而便于电路的布局和走线的设计。
在一些实施例中，所述第二导电线512在所述第一导线区132a内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域s1和第二凹陷区域s2；
其中，所述第一凹陷区域s1的凹口与所述第二凹陷区域s2的凹口的朝向相反；
所述第一导电线511沿所述第一方向包括多个延伸至所述第一凹陷区 域s1内的第一支线521；所述第三导电线513沿所述第一方向包括多个延伸至所述第二凹陷区域s2内的第二支线523。
如图5所示，第二电源焊盘502位于第一电源焊盘501以及第三电源焊盘503之间，第一电源焊盘501、第二电源焊盘502以及第三电源焊盘503所连接的第一导电线511、第二导电线512以及第三导电线513从各电源焊盘延伸至第一导线区132a并进行弯折为了使三条导电线尽可能等间距分布，位于三条导电线的中间的第二导电线512可以采用蛇形结构，向第一方向(X方向)延伸。第二导电线512弯折的形状在第二方向的两侧分别具有多个凹陷区域，第一导电线511与第三导电线513则可以分别设置有多个插指形状的支线延伸至开口中。第一导电线511的第一支线521可以延伸至一个方向上的第一凹陷区域s1，第三导电线513的第二支线523则可以延伸至与第一凹陷区域s1方向相反的第二凹陷区域s2。
这样，一方面三条导电线均可以通过弯折增大与第一导电金属层120的接触面积，另一方面也能够维持三个电源在各个位置的电压均衡，提升电路的稳定性。
在一些实施例中，如图6所示，所述半导体结构100还包括：
存储单元阵列区610，位于所述高速电路模块110远离所述电源焊盘131的一侧；所述存储单元阵列区610包括多个存储单元阵列611；所述电源焊盘131与所述存储单元阵列611通过所述重布线层130的导电线132连接。
上述电源焊盘131除了用于通过连接第一导电金属层120实现对高速电路模块110的电源供应，还可以用于向存储单元阵列611提供电源信号。
每个电源焊盘131连接的导电线132可以延伸至存储单元阵列区610，连接每个存储单元阵列。
在一些实施例中，所述重布线层130的导电线132还包括用于连接所述存储单元阵列611的第二导线区132b；其中，所述第二导线区132b的导电线132与所述高速电路模块110的投影区域不重叠；所述第一导线区132a与所述第二导线区132b的所述导电线132相互连接。
上述导电线132延伸至第一导线区132a反复弯折后，至少有一个端可以继续延伸至存储单元阵列区610。第二导线区132b的导电线可以是直线，也可以存在一些弯折以便连接至存储单元阵列611所需的位置。
在一些实施例中，如图7所示，所述半导体结构100包括并列设置的第一区710和第二区720；
所述第一区710的重布线层130和所述第二区720的重布线层130分别包括多个所述电源焊盘131；其中，所述第一区710的电源焊盘131通过第一区710的导电线132连接至第一区710的存储单元阵列611；所述第二区720的电源焊盘131通过第二区720的所述导电线132连接至第二区的所述存储单元阵列611。
在其他实施例中，上述半导体结构100还可以包括更多分区，每个分区都可以具有相同的电源焊盘以及导电线等结构，并分别连接至不同的存储单元阵列，从而便于扩展存储单元阵列的数量。
由于上述第一区710和第二区720在第一方向上并列排布，故上述第一导电金属层120中沿第一方向延伸的电源导线121可以直接贯穿第一区710和第二区720，并连接至对应的高速电路模块110。
在一些实施例中，所述第一区710的至少一个电源焊盘131与所述第二区720的至少一个电源焊盘131提供的电源电压相同。
示例性地，上述第一区710和第二区720中的电路结构、焊盘以及导电线等结构可以是相同。第一区710和第二区720中的电路结构、焊盘以及导电线等结构也可以存在不同，但可以具有一些相同的电源焊盘，用于提供相同的电源电压。如图7所示，第一区710和第二区720分别包括第一电源焊盘VDD2H、第二电源焊盘VSS以及第三电源焊盘VDD2L。
在一些实施例中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值之差小于预设阈值。
由于第一区和第二区的结构可能存在不同，相同的电源焊盘到对应的存储单元阵列之间的导电线的延伸路径也可能存在不同。即上述第一区和第二区中的电源焊盘与导电线等结构不是完全对称的，这样可能会导致提供至不同的存储单元阵列的电源电压存在差异。
因此，在本公开实施例中，需要使得第一区和第二区中用于提供相同电源电压的电源焊盘至不同存储单元阵列之间的导电线的电阻值具有较小的差异。这里，可以根据实际需求预设一个阈值，两条导电线的电阻值之差需要小于该预设阈值。
由于上述导电线存在反复弯折的第一导线区，因此，可以通过设计弯折的形状来调整导电线的总长度，进而设定相应的电阻值，使得两条导电线的电阻值尽可能相等。
在一些实施例中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值相同。
在一些实施例中，所述第一区中电源焊盘连接的导电线的所述第一导线区与所述第二区中电源焊盘连接的导电线的所述第一导线区呈轴对称分布。
也就是说，第一区和第二区中的相应的导电线在第一导线区内呈轴对称分布且具有相同的总长度与电阻值。如果第一区中电源焊盘的分布与第二区中电源焊盘的分布并不对称，则可以通过调整第一导线区以外的区域的导电线的长度和形状来实现两边的导电线电阻值的一致性。如图7所示，考虑到第一区710与第二区720中电源焊盘的位置并不完全对称，导致第一区710与第二区720中相同的电源焊盘131到各自要连接的存储单元阵列区610之间的距离不同。因此，可以通过灵活设计导电线的长度和形状， 例如，图7中第二区720的电源焊盘VDD2H所连接的导电线中额外延伸出的部分(图中虚线圈中的位置)就是用来保持与第一区710中的电源焊盘VDD2H所连接的导电线的电阻的一致性。同样的，第二区720中电源焊盘VSS额外弯折的部分(图中虚线圈中的位置)也是用来保持与第一区710中电源焊盘VSS所连接的导电线的电阻的一致性。
本公开实施例还提供一种存储器，包括：
如上述任一实施例所述的半导体结构。
该存储器可以为任意一种存储器，其电路结构及存储单元阵列的分布可以为上述半导体结构中的设计。
如图8所示，本公开实施例还提供一种版图结构200，包括：
高速电路模块版图210，至少包括用于表示包含有频率大于第一阈值的时钟信号；
第一导电金属层版图220，所述第一导电金属层版图220包括多条沿第一方向延伸的电源导线图形221，用于表示电连接所述高速电路模块版图210；
重布线层版图230，位于所述第一导电金属层版图220上，所述重布线层版图230包括：多个电源焊盘图形231，以及与所述电源焊盘图形231连接的导电线图形232；其中，所述电源焊盘图形231位于所述高速电路模块版图210的一侧，且所述电源焊盘图形231的投影区域与所述高速电路模块版图210不重叠；所述导电线图形232包括反复弯折形成的第一导线区232a，所述第一导线区232a至少部分覆盖所述高速电路模块版图210，所述导电线图形232连接所述电源导线图形221与所述电源焊盘图形231。
上述版图结构中导电线图形232在第一导线区232a的范围内反复弯折，可以与第一导电金属层版图220具有更多的重叠区域，从而便于设定更多的通孔图形240以表示导电线图形232与第一导电金属层版图220中电源导线图形221的连接关系。
在一些实施例中，多个所述电源焊盘图形至少包括：沿第一方向依次排布的第一电源焊盘图形、第二电源焊盘图形和第三电源焊盘图形；所述第一方向为所述电源导线图形的延伸方向；
所述第一电源焊盘图形连接的导电线图形为第一导电线图形；
所述第二电源焊盘图形连接的导电线图形为第二导电线图形；
所述第三电源焊盘图形连接的导电线图形为第三导电线图形。
在一些实施例中，所述第二导电线图形在所述第一导线区内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域和第二凹陷区域；
其中，所述第一凹陷区域的凹口与所述第二凹陷区域的凹口的朝向相反；
所述第一导电线图形沿所述第一方向包括多个延伸至所述第一凹陷区域内的第一支线图形；所述第三导电线图形沿所述第一方向包括多个延伸 至所述第二凹陷区域内的第二支线图形。
在一些实施例中，所述版图结构还包括：
存储单元阵列区版图，位于所述高速电路模块版图远离所述电源焊盘图形的一侧；所述存储单元阵列区版图包括多个存储单元阵列图形；所述电源焊盘图形与所述存储单元阵列图形通过所述重布线层版图的导电线图形连接。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本公开所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本公开各实施例中的各功能单元可以全部集成在一个处理单元中，也可以是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本公开的实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保 护范围应以所述权利要求的保护范围为准。
工业实用性
本公开实施例的技术方案中，多个电源焊盘位于重布线层，并通过重布线层上具有反复弯折形成的第一导线区的导电线与第一导电金属层连接，并电连接至高速电路模块。这样，可以有效增大导电线与高速电路模块的接触面积，使得电源可以直接对高速电路进行供电，便于降低功耗。同时，重布线层中的导电线也可以延伸并连接其他电路模块，且不会影响对高速电路的供电。

Claims (16)

  1. 一种半导体结构，包括：
    高速电路模块，包括时钟信号，所述时钟信号的频率大于第一阈值；
    第一导电金属层，所述第一导电金属层包括多条沿第一方向延伸且间隔排布的电源导线，电连接所述高速电路模块；
    重布线层，位于所述第一导电金属层上，所述重布线层包括：多个电源焊盘，以及与所述电源焊盘连接的导电线；其中，所述电源焊盘位于所述高速电路模块的一侧，且所述电源焊盘的投影区域与所述高速电路模块不重叠；所述导电线包括反复弯折形成的第一导线区，所述第一导线区至少部分覆盖所述高速电路模块，所述导电线用于电连接所述电源导线与所述电源焊盘。
  2. 根据权利要求1所述的半导体结构，其中，多个所述电源焊盘用于提供不同电源电压；
    每条所述电源导线包括多个电源线，多个所述电源线分别用于连接不同的电源焊盘；其中，所述电源线与对应电源的所述导电线通过多个连接孔电连接。
  3. 根据权利要求2所述的半导体结构，其中，多个所述电源焊盘所连接的导电线在所述第一导线区等间距分布。
  4. 根据权利要求3所述的半导体结构，其中，多个所述电源焊盘至少包括：沿第一方向依次排布的第一电源焊盘、第二电源焊盘和第三电源焊盘；所述第一方向为所述电源导线的延伸方向；
    所述第一电源焊盘连接的导电线为第一导电线；
    所述第二电源焊盘连接的导电线为第二导电线；
    所述第三电源焊盘连接的导电线为第三导电线。
  5. 根据权利要求4所述的半导体结构，其中，所述第二导电线在所述第一导线区内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域和第二凹陷区域；
    其中，所述第一凹陷区域的凹口与所述第二凹陷区域的凹口的朝向相反；
    所述第一导电线沿所述第一方向包括多个延伸至所述第一凹陷区域内的第一支线；所述第三导电线沿所述第一方向包括多个延伸至所述第二凹陷区域内的第二支线。
  6. 根据权利要求1至5任一所述的半导体结构，其中，还包括：
    存储单元阵列区，位于所述高速电路模块远离所述电源焊盘的一侧；所述存储单元阵列区包括多个存储单元阵列；所述电源焊盘与所述存储单元阵列通过所述重布线层的导电线连接。
  7. 根据权利要求6所述的半导体结构，其中，所述重布线层的导电线 还包括用于连接所述存储单元阵列的第二导线区；其中，所述第二导线区的导电线与所述高速电路模块的投影区域不重叠；所述第一导线区与所述第二导线区的所述导电线相互连接。
  8. 根据权利要求6所述的半导体结构，其中，所述半导体结构包括并列设置的第一区和第二区；
    所述第一区的重布线层和所述第二区的重布线层分别包括多个所述电源焊盘；其中，所述第一区的电源焊盘通过所述第一区的所述导电线连接至所述第一区的存储单元阵列；所述第二区的电源焊盘通过所述第二区的所述导电线连接至所述第二区的存储单元阵列。
  9. 根据权利要求8所述的半导体结构，其中，所述第一区的至少一个电源焊盘与所述第二区的至少一个电源焊盘提供的电源电压相同。
  10. 根据权利要求9所述的半导体结构，其中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值之差小于预设阈值。
  11. 根据权利要求10所述半导体结构，其中，所述第一区和所述第二区中用于提供相同电源电压的所述电源焊盘所连接的导电线的电阻值相同。
  12. 根据权利要求8所述的半导体结构，其中，所述第一区中电源焊盘连接的导电线的所述第一导线区与所述第二区中电源焊盘连接的导电线的所述第一导线区呈轴对称分布。
  13. 一种版图结构，包括：
    高速电路模块版图，至少包括用于表示包含有频率大于第一阈值的时钟信号；
    第一导电金属层版图，所述第一导电金属层版图包括多条沿第一方向延伸的电源导线图形，用于表示电连接所述高速电路模块版图；
    重布线层版图，位于所述第一导电金属层版图上，所述重布线层版图包括：多个电源焊盘图形，以及与所述电源焊盘图形连接的导电线图形；其中，所述电源焊盘图形位于所述高速电路模块版图的一侧，且所述电源焊盘图形的投影区域与所述高速电路模块版图不重叠；所述导电线图形包括反复弯折形成的第一导线区，所述第一导线区至少部分覆盖所述高速电路模块版图，所述导电线图形连接所述电源导线图形与所述电源焊盘图形。
  14. 根据权利要求13所述的版图结构，其中，多个所述电源焊盘图形至少包括：沿第一方向依次排布的第一电源焊盘图形、第二电源焊盘图形和第三电源焊盘图形；所述第一方向为所述电源导线图形的延伸方向；
    所述第一电源焊盘图形连接的导电线图形为第一导电线图形；
    所述第二电源焊盘图形连接的导电线图形为第二导电线图形；
    所述第三电源焊盘图形连接的导电线图形为第三导电线图形。
  15. 根据权利要求14所述的版图结构，其中，所述第二导电线图形在 所述第一导线区内弯折形成有：沿第一方向延伸的多个交替排布的第一凹陷区域和第二凹陷区域；
    其中，所述第一凹陷区域的凹口与所述第二凹陷区域的凹口的朝向相反；
    所述第一导电线图形沿所述第一方向包括多个延伸至所述第一凹陷区域内的第一支线图形；所述第三导电线图形沿所述第一方向包括多个延伸至所述第二凹陷区域内的第二支线图形。
  16. 根据权利要求13所述的版图结构，其中，还包括：
    存储单元阵列区版图，位于所述高速电路模块版图远离所述电源焊盘图形的一侧；所述存储单元阵列区版图包括多个存储单元阵列图形；所述电源焊盘图形与所述存储单元阵列图形通过所述重布线层版图的导电线图形连接。
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CN114121883A (zh) * 2020-08-26 2022-03-01 三星电子株式会社 半导体装置

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US20060220215A1 (en) * 2005-03-18 2006-10-05 Jong-Joo Lee Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same
CN110858572A (zh) * 2018-08-22 2020-03-03 美光科技公司 具有外部端子的布线
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