WO2024045758A1 - 一种三维堆叠的扇出型封装结构及其制备方法 - Google Patents

一种三维堆叠的扇出型封装结构及其制备方法 Download PDF

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Publication number
WO2024045758A1
WO2024045758A1 PCT/CN2023/099289 CN2023099289W WO2024045758A1 WO 2024045758 A1 WO2024045758 A1 WO 2024045758A1 CN 2023099289 W CN2023099289 W CN 2023099289W WO 2024045758 A1 WO2024045758 A1 WO 2024045758A1
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layer
substrate
chip
silicon transfer
electrically connected
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PCT/CN2023/099289
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English (en)
French (fr)
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陈彦亨
林正忠
杨进
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盛合晶微半导体(江阴)有限公司
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Publication of WO2024045758A1 publication Critical patent/WO2024045758A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device

Definitions

  • the present invention relates to the field of semiconductor packaging technology, and in particular to a three-dimensional stacked fan-out packaging structure and a preparation method thereof.
  • Flip-chip fan-out packaging structures include a variety of chip types, including core chips (core die), IO chips (IO die), cache/SRAM chips, structural chips, etc. As the core count and functional complexity of such high-performance chips increases, more and more chips need to be integrated onto a single substrate. As shown in Figures 1 and 2, in the prior art, a transmission chip 122 and a first chip 201 are formed on a substrate 302.
  • the transmission chip 122 and the first chip 201 are laid out on the surface of the substrate 302 in sequence.
  • the chip is bound to increase the area of the substrate, which also prompts the substrate size to rapidly increase from 50 ⁇ 50mm 2 to 100 ⁇ 100mm 2 .
  • the size of the substrate increases, its cost and defective rate also increase, which hinders the application of large-size substrates.
  • the fan-out packaging structure includes:
  • a silicon transfer layer with a transmission chip bonded to the lower surface of the silicon transfer layer
  • a coating layer covers the side wall of the transmission chip, and the coating layer is provided with a first conductive pillar penetrating the coating layer;
  • a chip stack the chip stack is bonded to the upper surface of the silicon transfer layer, the chip stack includes more than two chips stacked in a vertical direction, and adjacent chip stacks are connected by the The transmission chip performs signal transmission;
  • a substrate, the substrate is disposed below the cladding layer
  • a rewiring layer or a metal solder ball electrically connected to the first conductive pillar is also provided between the cladding layer and the substrate, so that the substrate and the silicon transfer layer are electrically connected.
  • the rewiring layer includes a wiring dielectric layer and a metal wiring layer located within the wiring dielectric layer.
  • the rewiring layer is bonded to the substrate through a bonding glue layer; a second conductive pillar is provided in the bonding glue layer, and the substrate passes through the second conductive pillar, the metal wiring layer, and the first The conductive pillar is electrically connected to the silicon transfer layer.
  • the transmission chip is electrically connected to the substrate through the rewiring layer and the second conductive pillar.
  • the cladding layer when the cladding layer and the substrate are connected through metal solder balls, the cladding layer also covers the lower surface of the transmission chip, and the substrate is connected to the substrate through metal solder balls, the first conductive pillar and the first conductive pillar in sequence.
  • a silicon transfer layer makes the electrical connection.
  • the invention also provides a method for preparing a three-dimensional stacked fan-out packaging structure, which includes the following steps:
  • S1 Provide a silicon transfer layer, with a transmission chip bonded to the lower surface of the silicon transfer layer;
  • S2 Form a coating layer on the lower surface of the silicon transfer layer, the coating layer covers the side wall of the transmission chip, and the coating layer is provided with a first hole penetrating the coating layer.
  • conductive pillar
  • S3 Bond a chip stack on the upper surface of the silicon transfer layer.
  • the chip stack includes two or more chips stacked in the vertical direction. Signals are transmitted between adjacent chip stacks through the transmission chip. transmission;
  • a rewiring layer or a metal solder ball electrically connected to the first conductive pillar is also formed between the cladding layer and the substrate, so that the substrate and the silicon transfer layer are electrically connected.
  • the rewiring layer is formed on the lower surface of the cladding layer, and the rewiring layer includes a wiring dielectric layer and a metal wiring layer located in the wiring dielectric layer.
  • the rewiring layer is bonded to the substrate through a bonding glue layer; a second conductive pillar is provided in the bonding glue layer, and the substrate passes through the second conductive post in turn.
  • the pillar, the metal wiring layer, the first conductive pillar and the silicon transfer layer are electrically connected.
  • the transmission chip is electrically connected to the substrate through the rewiring layer and the second conductive pillar.
  • the coating layer also covers the lower surface of the transmission chip; the coating layer and the substrate are connected through metal solder balls, and the substrate is connected through metal solder balls and the first conductive pillar in sequence. An electrical connection is made with the silicon transfer layer.
  • the present invention provides a three-dimensional stacked fan-out packaging structure and a preparation method thereof.
  • the fan-out packaging structure includes, from top to bottom, a chip stack, a silicon transfer layer, a transmission chip, a cladding layer and
  • the substrate is electrically connected to the substrate by providing a rewiring layer or a metal solder ball for signal transmission.
  • the transmission chip is arranged on the lower surface of the silicon transfer layer, and the chip stack containing multiple chips is arranged on the upper surface of the silicon transfer layer, thereby improving the integration of the entire structure, reducing the packaging volume, and saving substrates.
  • the area allows a larger number of chips to be accommodated on a small-area substrate; the stacked design allows overlap between chips, which is also conducive to heat transfer, thus improving the heat dissipation effect. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
  • Figure 1 shows a schematic top view of the chip arrangement in the prior art.
  • FIG. 2 shows a schematic side view of the chip arrangement in the prior art.
  • Figure 3 shows a schematic structural diagram of the silicon transfer layer.
  • Figure 4 shows a schematic structural diagram of forming a coating layer.
  • FIG. 5 shows a schematic structural diagram of the first chip bonded to the wafer.
  • Figure 6 shows a schematic structural diagram of a chip stack formed by cutting a wafer.
  • Figure 7 shows a schematic structural diagram of forming a rewiring layer.
  • Figure 8 shows a schematic diagram of the structure after cutting.
  • Figure 9 shows a schematic diagram of the structure bonded to the substrate.
  • Figure 10 shows a schematic diagram of the arrangement of metal solder balls.
  • FIG. 11 shows a schematic top view of the fan-out packaging structure of the present invention.
  • spatial relationship words such as “below”, “below”, “below”, “below”, “above”, “on”, etc. may be used herein to describe an element or element shown in the drawings.
  • a layer when referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • “between” means including both endpoint values.
  • structures described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, as well as may include additional features formed between the first and second features. Embodiments between second features such that the first and second features may not be in direct contact.
  • illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complex.
  • This embodiment provides a method for preparing a three-dimensional stacked fan-out packaging structure, which includes the following steps:
  • S1 Provide a silicon transfer layer 101, with a transmission chip 122 bonded to the lower surface of the silicon transfer layer 101, as shown in Figure 3;
  • S2 Form a cladding layer 102 on the lower surface of the silicon transfer layer 101.
  • the cladding layer 102 covers the side wall of the transmission chip 122, and the cladding layer 102 has an internal structure that penetrates the package.
  • the first conductive pillar 121 of the coating 102 is as shown in Figure 4;
  • S3 Bond a chip stack on the upper surface of the silicon transfer layer 101.
  • the chip stack includes two or more chips stacked in the vertical direction.
  • the transmission chip 122 is between adjacent chip stacks. Perform signal transmission, as shown in Figure 7;
  • a rewiring layer 103 or a metal solder ball 311 electrically connected to the first conductive pillar 121 is also formed between the cladding layer 102 and the substrate 302, so that the substrate 302 and the silicon transfer layer 101 realizes electrical connection.
  • the silicon interposer layer 101 is a silicon interposer, which has a TSV through hole inside the silicon layer as a conductive channel between the upper chip stack and the lower device.
  • the transmission chip 122 can be an IO chip for connecting the upper adjacent cores. Transmission of IO signals between chip stacks.
  • the chip stack in this embodiment includes a first chip 201 and a second chip 202.
  • the first chip 201 may be a core processing chip (core die)
  • the second chip 202 may be a cache chip (cache die). It should be understood that the types of the first chip 201 and the second chip 202 are not limited to this, and the chips in the chip stack are not limited to 2 layers, and may also be 3 layers, 4 layers...
  • Each chip in the chip stack is electrically connected for signal transmission, for example, the first chip 201 and the second chip 202 are electrically connected.
  • the transmission chip 122 can be used for signal transmission between two adjacent chip stacks, or for signal transmission between four or more adjacent chip stacks.
  • the substrate 302 may be a glass substrate, a ceramic substrate, a metal substrate, an organic polymer substrate, or other materials.
  • a cutting process ie, Singulation
  • the present invention improves the overall structure by arranging the transmission chip 122 on the lower surface of the silicon transfer layer 101 and at the same time arranging a chip stack including multiple chips on the upper surface of the silicon transfer layer 101.
  • the integration level allows a larger number of chips to be accommodated on a small-area substrate.
  • the stacked design allows overlap between chips, which is also conducive to heat transfer and thus improves heat dissipation.
  • the first chip 201 is bonded to the wafer 2021 , and then the wafer 2021 is cut (ie, Singulation) to remove unnecessary parts. Cutting and separation are performed to finally form the chip stack.
  • step S4 in addition to being electrically connected through the first conductive pillar 121, the substrate 302 and the silicon transfer layer 101 are also connected through the rewiring layer 103 or the metal solder ball 311, such as As shown in Figure 9- Figure 10.
  • the rewiring layer 103 is formed on the lower surface of the cladding layer 102 .
  • the rewiring layer 103 includes a wiring dielectric layer 132 and a wiring dielectric layer 132 located on the wiring dielectric layer.
  • the material of the wiring dielectric layer 132 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring
  • the material of layer 131 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium.
  • the materials, number of layers, and distribution morphology of the wiring dielectric layer 132 and the metal wiring layer 131 can be set according to the specific conditions of the semiconductor chip, and are not limited here.
  • the rewiring layer 103 is bonded to the substrate 302 through the bonding glue layer 301 .
  • the bonding adhesive layer 301 is provided with a second conductive pillar 312 , and the substrate 302 is electrically connected to the silicon transfer layer 101 through the second conductive pillar 312 , the metal wiring layer 131 , and the first conductive pillar 121 .
  • the transmission chip 122 can also be electrically connected to the substrate 302 through the rewiring layer 103 and the second conductive pillar 312 .
  • the material of the first conductive pillar 121 and the second conductive pillar 312 may be one metal material or two or more alloy materials among copper, aluminum, nickel, gold, silver, tin, and titanium.
  • the layer 102 and the bonding glue layer 301 may be one or any combination of polyimide, silicone, and epoxy resin.
  • the coating layer 102 also covers the lower surface of the transmission chip 122 to form protection, that is, the thickness of the coating layer 102 is greater than the thickness of the transmission chip 122 .
  • the cladding layer 102 and the substrate 302 are connected through the metal solder ball 311, and the substrate 302 is connected to the silicon through the metal solder ball 311 and the first conductive pillar 121 in turn.
  • Layer 101 implements electrical connections.
  • the metal solder ball 311 can also ensure a certain gap between the cladding layer 102 and the substrate 302 .
  • the material of the metal solder ball 311 may be one material selected from copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.
  • this embodiment also provides a three-dimensional stacked fan-out packaging structure, as shown in Figures 9-10.
  • the fan-out packaging structure includes:
  • Silicon transfer layer 101, the transmission chip 122 is bonded to the lower surface of the silicon transfer layer 101;
  • Covering layer 102 covers the side wall of the transmission chip 122, and the covering layer 102 is provided with a first conductive pillar 121 penetrating the covering layer 102;
  • the chip stack is bonded to the upper surface of the silicon transfer layer 101.
  • the chip stack includes two or more chips stacked in the vertical direction. Adjacent chip stacks are separated by The transmission chip 122 performs signal transmission;
  • Substrate 302 the substrate 302 is disposed below the cladding layer 102;
  • a rewiring layer or a metal solder ball electrically connected to the first conductive pillar is also provided between the cladding layer and the substrate, so that the substrate and the silicon transfer layer are electrically connected.
  • the silicon interposer layer 101 is a silicon interposer, which has a TSV through hole inside the silicon layer as a conductive channel between the upper chip stack and the lower device.
  • the transmission chip 122 can be an IO chip for the upper adjacent chip stack. Transmission of IO signals between bodies.
  • the chip stack in this embodiment includes a first chip 201 and a second chip 202.
  • the first chip 201 may be a core processing chip (core die)
  • the second chip 202 may be a cache chip (cache die). It should be understood that the types of the first chip 201 and the second chip 202 are not limited to this, and the chips in the chip stack are not limited to 2 layers, and may also be 3 layers, 4 layers...
  • Each chip in the chip stack is electrically connected for signal transmission, for example, the first chip 201 and the second chip 202 are electrically connected.
  • the transmission chip 122 can be used for signal transmission between two adjacent chip stacks, or for signal transmission between four or more adjacent chip stacks.
  • the substrate 302 may be a glass substrate, a ceramic substrate, a metal substrate, an organic polymer substrate, or other materials.
  • the present invention improves the overall structure by arranging the transmission chip 122 on the lower surface of the silicon transfer layer 101 and at the same time arranging a chip stack including multiple chips on the upper surface of the silicon transfer layer 101.
  • the integration level allows a larger number of chips to be accommodated on a small-area substrate.
  • the stacked design allows overlap between chips, which is also conducive to heat transfer and thus improves heat dissipation.
  • the substrate 302 and the silicon transfer layer 101 are also connected through the rewiring layer 103 or the metal solder ball 311 .
  • a rewiring layer 103 is formed on the lower surface of the cladding layer 102 .
  • the rewiring layer 103 includes a wiring dielectric layer 132 and a metal wiring layer 131 located in the wiring dielectric layer 132 .
  • the material of the wiring dielectric layer 132 includes one or a combination of two or more from the group consisting of epoxy resin, silicone, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass; the metal wiring
  • the material of layer 131 includes one or a combination of two or more from the group consisting of copper, aluminum, nickel, gold, silver and titanium.
  • the materials, number of layers, and distribution morphology of the wiring dielectric layer 132 and the metal wiring layer 131 can be set according to the specific conditions of the semiconductor chip, and are not limited here.
  • the rewiring layer 103 is bonded to the substrate 302 through a bonding adhesive layer 301 .
  • the bonding adhesive layer 301 is provided with a second conductive pillar 312 , and the substrate 302 is electrically connected to the silicon transfer layer 101 through the second conductive pillar 312 , the metal wiring layer 131 , and the first conductive pillar 121 .
  • the transmission chip 122 can also be electrically connected to the substrate 302 through the rewiring layer 103 and the second conductive pillar 312 .
  • the material of the first conductive pillar 121 and the second conductive pillar 312 may be one metal material or two or more alloy materials among copper, aluminum, nickel, gold, silver, tin, and titanium.
  • the layer 102 and the bonding glue layer 301 may be one or any combination of polyimide, silicone, and epoxy resin.
  • the coating layer 102 also covers the lower surface of the transmission chip 122 to form a protective layer. protection, that is, the thickness of the coating layer 102 is greater than the thickness of the transmission chip 122 .
  • the cladding layer 102 and the substrate 302 are connected through metal solder balls 311 , and the substrate 302 is electrically connected to the silicon transfer layer 101 through the metal solder balls 311 and the first conductive pillar 121 .
  • the metal solder ball 311 can also ensure a certain gap between the cladding layer 102 and the substrate 302 .
  • the material of the metal solder ball 311 may be one material selected from copper, aluminum, nickel, gold, silver, and titanium, or a combination of two or more materials.
  • the present invention provides a three-dimensional stacked fan-out packaging structure and a preparation method thereof.
  • the fan-out packaging structure includes a chip stack, a silicon transfer layer, a transmission chip, and a cladding layer from top to bottom. and the substrate, and achieves electrical connection between the silicon transfer layer and the substrate by setting a rewiring layer or metal solder balls for signal transmission.
  • the transmission chip is arranged on the lower surface of the silicon transfer layer, and the chip stack containing multiple chips is arranged on the upper surface of the silicon transfer layer, thereby improving the integration of the entire structure, reducing the packaging volume, and saving substrates.
  • the area allows a larger number of chips to be accommodated on a small-area substrate; the stacked design allows overlap between chips, which is also conducive to heat transfer, thus improving the heat dissipation effect. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

一种三维堆叠的扇出型封装结构及其制备方法，扇出型封装结构从上至下依次包括芯片堆叠体、硅转接层（101）、传输芯片（122）、包覆层（102）及基板（302），通过设置重新布线层（103）或金属焊球（311）实现硅转接层（101）与基板（302）的电连接从而进行信号传输。其中，传输芯片（122）设置于硅转接层（101）的下表面，包含多个芯片的芯片堆叠体则设置于硅转接层（101）的上表面。

Description

一种三维堆叠的扇出型封装结构及其制备方法 技术领域
本发明涉及半导体封装技术领域，特别是涉及一种三维堆叠的扇出型封装结构及其制备方法。
背景技术
封装近年来发展迅速，倒装芯片电子封装作为主流封装形式占据了60-70％的IC封装市场。对于高端倒装芯片封装，例如用于服务器、AI和HPC的CPU，需要多芯片集成，这就需要将多个芯片放置在一个基板上。倒装扇出型封装结构包括有多种芯片类型，包括有核心芯片(core die)、IO芯片(IO die)、高速缓存/SRAM芯片、结构芯片等。随着这种高性能芯片的核心数量和功能复杂性的增加，越来越多的芯片需要集成到一个单一的基板上。如图1、2所示，现有技术中，基板302上形成有传输芯片122及第一芯片201，传输芯片122及第一芯片201依序平铺于基板302的表面，为了容纳更多数量的芯片，势必要增加基板的面积，这也催使基板尺寸正在从50×50mm2迅速增加到100×100mm2。然而随着基板尺寸的增加，其成本和残品率也随之增加，这给大尺寸基板的应用带来阻碍。
因此需要提出一种封装结构，以在现有小尺寸基板的条件下，也能容纳较多数量的芯片。
发明内容
鉴于以上所述现有技术的缺点，本发明提供一种三维堆叠的扇出型封装结构，所述扇出型封装结构包括：
硅转接层，所述硅转接层的下表面键合有传输芯片；
包覆层，所述包覆层包覆所述传输芯片的侧壁，且所述包覆层内设有贯穿所述包覆层的第一导电柱；
芯片堆叠体，所述芯片堆叠体键合于所述硅转接层的上表面，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片进行信号传输；
基板，所述基板设置于所述包覆层下方；
所述包覆层与所述基板之间还设有与所述第一导电柱电连接的重新布线层或金属焊球，以使所述基板与硅转接层实现电连接。
优选地，所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。
优选地，所述重新布线层通过键合胶层与所述基板键合；所述键合胶层内设有第二导电柱，所述基板依次通过第二导电柱、金属布线层、第一导电柱与所述硅转接层实现电连接。
优选地，所述传输芯片通过所述重新布线层及第二导电柱与所述基板实现电连接。
优选地，所述包覆层与基板通过金属焊球进行连接时，所述包覆层还包覆所述传输芯片的下表面，所述基板依次通过金属焊球、第一导电柱与所述硅转接层实现电连接。
本发明还提供一种三维堆叠的扇出型封装结构的制备方法，包括如下步骤：
S1：提供硅转接层，所述硅转接层的下表面键合有传输芯片；
S2：于所述硅转接层的下表面形成包覆层，所述包覆层包覆所述传输芯片的侧壁，且所述包覆层内设有贯穿所述包覆层的第一导电柱；
S3：于所述硅转接层的上表面键合芯片堆叠体，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片进行信号传输；
S4：于所述包覆层的下方连接基板；
其中，所述包覆层与所述基板之间还形成有与所述第一导电柱电连接的重新布线层或金属焊球，以使所述基板与硅转接层实现电连接。
优选地，在步骤S3之后，于所述包覆层下表面形成所述重新布线层，所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。
优选地，形成所述重新布线层之后，所述重新布线层通过键合胶层与所述基板键合；所述键合胶层内设有第二导电柱，所述基板依次通过第二导电柱、金属布线层、第一导电柱与所述硅转接层实现电连接。
优选地，所述传输芯片通过所述重新布线层及第二导电柱与所述基板实现电连接。
优选地，步骤S2中，所述包覆层还包覆所述传输芯片的下表面；所述包覆层与基板通过金属焊球进行连接，所述基板依次通过金属焊球、第一导电柱与所述硅转接层实现电连接。
如上所述，本发明提供一种三维堆叠的扇出型封装结构及其制备方法，该扇出型封装结构从上至下依次包括芯片堆叠体、硅转接层、传输芯片、包覆层及基板，并通过设置重新布线层或金属焊球实现硅转接层与基板的电连接从而进行信号传输。其中，传输芯片设置于硅转接层的下表面，包含多个芯片的芯片堆叠体则设置于硅转接层的上表面，从而提高了整个结构的集成度，减小封装体积，节省了基板面积，使得在小面积的基板上也能容纳较多数量的芯片；采用堆叠式的设计使得芯片之间产生交叠，这也有利于热传递，从而提升散热效果。因此本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
附图说明
图1显示为现有技术中芯片排布的俯视结构示意图。
图2显示为现有技术中芯片排布的侧视结构示意图。
图3显示为硅转接层的结构示意图。
图4显示为形成包覆层的结构示意图。
图5显示为第一芯片键合至晶圆的结构示意图。
图6显示为切割晶圆形成的芯片堆叠体结构示意图。
图7显示为形成重新布线层的结构示意图。
图8显示为切割后的结构示意图。
图9显示为与基板键合的结构示意图。
图10显示为金属焊球的设置示意图。
图11显示为本发明扇出型封装结构的俯视结构示意图。
元件标号说明：101硅转接层；102包覆层；121第一导电柱；122传输芯片；302基板；201第一芯片；202第二芯片；103重新布线层；311金属焊球；131金属布线层；132布线介质层；301键合胶层；312第二导电柱；2021晶圆。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
为了方便描述，此处可能使用诸如“之下”、“下方”、“低于”、“下面”、“上方”、“上”等的空间关系词语来描述附图中所示的一个元件或特征与其他元件或特征的关系。将理解到，这些空间关系词语意图包含使用中或操作中的器件的、除了附图中描绘的方向之外的其他方向。此外，当一层被称为在两层“之间”时，它可以是所述两层之间仅有的层，或者也可以存在一个或多个介于其间的层。本文使用的“介于……之间”表示包括两端点值。
在本申请的上下文中，所描述的第一特征在第二特征“之上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，其组件布局型态也可能更为复杂。
本实施例提供一种三维堆叠的扇出型封装结构的制备方法，包括如下步骤：
S1：提供硅转接层101，所述硅转接层101的下表面键合有传输芯片122，如图3所示；
S2：于所述硅转接层101的下表面形成包覆层102，所述包覆层102包覆所述传输芯片122的侧壁，且所述包覆层102内设有贯穿所述包覆层102的第一导电柱121，如图4所示；
S3：于所述硅转接层101的上表面键合芯片堆叠体，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片122进行信号传输，如图7所示；
S4：于所述包覆层102的下方设置基板302，如图9、图10所示。
其中，所述包覆层102与所述基板302之间还形成有与所述第一导电柱121电连接的重新布线层103或金属焊球311，以使所述基板302与硅转接层101实现电连接。
具体地，所述硅转接层101即silicon interposer，其在硅层内部设有TSV通孔作为上方芯片堆叠体与下方器件的导电通道，传输芯片122可以是IO芯片，用以上方相邻的芯 片堆叠体之间IO信号的传输。本实施例中的芯片堆叠体包括第一芯片201及第二芯片202，所述第一芯片201可以是核心处理芯片(core die)，所述第二芯片202可以是缓存芯片(cache die)，应当理解的是，所述第一芯片201及第二芯片202的类型不限于此，且芯片堆叠体中芯片也不局限于2层，也可以是3层、4层……。所述芯片堆叠体中的各个芯片之间具有电连接以进行信号传输，例如所述第一芯片201及第二芯片202之间具有电连接。如图11所示，所述传输芯片122可以用于相邻2个芯片堆叠体之间的信号传输，也可以是对相邻的4个或多个芯片堆叠体之间的信号传输，此处不作过多限制。所述基板302可以是玻璃基板、陶瓷基板、金属基板、有机聚合物基板等材料。此外，在步骤S3之后，还可以包括切割的工艺过程(即Singulation)，以对不需要的部分进行切割分离，如图8所示。
本发明通过将所述传输芯片122设置于所述硅转接层101的下表面，同时将包含多个芯片的芯片堆叠体设置于所述硅转接层101的上表面，从而提高了整个结构的集成度，使得在小面积的基板上也能容纳较多数量的芯片。此外，采用堆叠式的设计使得芯片之间产生交叠，这也有利于热传递，从而提升散热效果。
具体地，如图5-图6所示，将所述第一芯片201键合至所述晶圆2021上，然后对所述晶圆2021进行切割(即Singulation)，以对不需要的部分进行切割分离，最终形成所述芯片堆叠体。
可选地，步骤S4中，所述基板302与所述硅转接层101之间除了通过所述第一导电柱121电连接，还通过重新布线层103连接或金属焊球311进行连接，如图9-图10所示。
可选地，如图7所示，在步骤S3之后，于所述包覆层102下表面形成所述重新布线层103，所述重新布线层103包括布线介质层132及位于所述布线介质层132内的金属布线层131。所述布线介质层132的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合；所述金属布线层131的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。所述布线介质层132及金属布线层131的材料、层数及分布形貌，可根据半导体芯片的具体情况进行设置，在此不作限制。
进一步地，如图9所示，形成所述重新布线层103之后，所述重新布线层103通过键合胶层301与所述基板302键合。所述键合胶层301内设有第二导电柱312，所述基板302依次通过第二导电柱312、金属布线层131、第一导电柱121与所述硅转接层101实现电连接。可选地，所述传输芯片122也可通过所述重新布线层103及第二导电柱312与所述基板302实现电连接。其中，所述第一导电柱121及第二导电柱312的材料可以是铜、铝、镍、金、银、锡、钛中的一种金属材料或两种以上的合金材料，所述包覆层102及键合胶层301可以是聚酰亚胺、硅胶以及环氧树脂中的一种或任意种的组合。
可选地，步骤S2中，所述包覆层102还包覆所述传输芯片122的下表面以形成保护，即所述包覆层102的厚度大于所述传输芯片122的厚度。如图10所示，在步骤S3之后，所述包覆层102与基板302通过金属焊球311进行连接，所述基板302依次通过金属焊球311、第一导电柱121与所述硅转接层101实现电连接。其中，所述金属焊球311除了用于实现电连接，还能够保证所述包覆层102与基板302之间具有一定的间隙。所述金属焊球311的材料可以是铜、铝、镍、金、银、钛中的一种材料或两种以上材料的组合材料。
基于上述制备方法，本实施例还提供一种三维堆叠的扇出型封装结构，如图9-图10所示，所述扇出型封装结构包括：
硅转接层101，所述硅转接层101的下表面键合有传输芯片122；
包覆层102，所述包覆层102包覆所述传输芯片122的侧壁，且所述包覆层102内设有贯穿所述包覆层102的第一导电柱121；
芯片堆叠体，所述芯片堆叠体键合于所述硅转接层101的上表面，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片122进行信号传输；
基板302，所述基板302设置于所述包覆层102下方；
所述包覆层与所述基板之间还设有与所述第一导电柱电连接的重新布线层或金属焊球，以使所述基板与硅转接层实现电连接。
具体地，所述硅转接层101即silicon interposer，其在硅层内部设有TSV通孔作为上方芯片堆叠体与下方器件的导电通道，传输芯片122可以是IO芯片，用以上方相邻的芯片堆叠体之间IO信号的传输。本实施例中的芯片堆叠体包括第一芯片201及第二芯片202，所述第一芯片201可以是核心处理芯片(core die)，所述第二芯片202可以是缓存芯片(cache die)，应当理解的是，所述第一芯片201及第二芯片202的类型不限于此，且芯片堆叠体中芯片也不局限于2层，也可以是3层、4层……。所述芯片堆叠体中的各个芯片之间具有电连接以进行信号传输，例如所述第一芯片201及第二芯片202之间具有电连接。如图11所示，所述传输芯片122可以用于相邻2个芯片堆叠体之间的信号传输，也可以是对相邻的4个或多个芯片堆叠体之间的信号传输，此处不作过多限制。所述基板302可以是玻璃基板、陶瓷基板、金属基板、有机聚合物基板等材料。
本发明通过将所述传输芯片122设置于所述硅转接层101的下表面，同时将包含多个芯片的芯片堆叠体设置于所述硅转接层101的上表面，从而提高了整个结构的集成度，使得在小面积的基板上也能容纳较多数量的芯片。此外，采用堆叠式的设计使得芯片之间产生交叠，这也有利于热传递，从而提升散热效果。
可选地，所述基板302与所述硅转接层101之间除了通过所述第一导电柱121电连接，还通过重新布线层103连接或金属焊球311进行连接。
可选地，如图9所示，所述包覆层102下表面形成有重新布线层103，所述重新布线层103包括布线介质层132及位于所述布线介质层132内的金属布线层131。所述布线介质层132的材料包括由环氧树脂、硅胶、PI、PBO、BCB、氧化硅、磷硅玻璃及含氟玻璃组成的群组中的一种或两种以上组合；所述金属布线层131的材料包括由铜、铝、镍、金、银及钛组成的群组中的一种或两种以上组合。所述布线介质层132及金属布线层131的材料、层数及分布形貌，可根据半导体芯片的具体情况进行设置，在此不作限制。
进一步地，所述重新布线层103通过键合胶层301与所述基板302键合。所述键合胶层301内设有第二导电柱312，所述基板302依次通过第二导电柱312、金属布线层131、第一导电柱121与所述硅转接层101实现电连接。可选地，所述传输芯片122也可通过所述重新布线层103及第二导电柱312与所述基板302实现电连接。其中，所述第一导电柱121及第二导电柱312的材料可以是铜、铝、镍、金、银、锡、钛中的一种金属材料或两种以上的合金材料，所述包覆层102及键合胶层301可以是聚酰亚胺、硅胶以及环氧树脂中的一种或任意种的组合。
可选地，如图10所示，所述包覆层102还包覆所述传输芯片122的下表面以形成保 护，即所述包覆层102的厚度大于所述传输芯片122的厚度。所述包覆层102与基板302通过金属焊球311进行连接，所述基板302依次通过金属焊球311、第一导电柱121与所述硅转接层101实现电连接。其中，所述金属焊球311除了用于实现电连接，还能够保证所述包覆层102与基板302之间具有一定的间隙。所述金属焊球311的材料可以是铜、铝、镍、金、银、钛中的一种材料或两种以上材料的组合材料。
综上所述，本发明提供一种三维堆叠的扇出型封装结构及其制备方法，该扇出型封装结构从上至下依次包括芯片堆叠体、硅转接层、传输芯片、包覆层及基板，并通过设置重新布线层或金属焊球实现硅转接层与基板的电连接从而进行信号传输。其中，传输芯片设置于硅转接层的下表面，包含多个芯片的芯片堆叠体则设置于硅转接层的上表面，从而提高了整个结构的集成度，减小封装体积，节省了基板面积，使得在小面积的基板上也能容纳较多数量的芯片；采用堆叠式的设计使得芯片之间产生交叠，这也有利于热传递，从而提升散热效果。因此本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种三维堆叠的扇出型封装结构，其特征在于，所述扇出型封装结构包括：
    硅转接层，所述硅转接层的下表面键合有传输芯片；
    包覆层，所述包覆层包覆所述传输芯片的侧壁，且所述包覆层内设有贯穿所述包覆层的第一导电柱；
    芯片堆叠体，所述芯片堆叠体键合于所述硅转接层的上表面，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片进行信号传输；
    基板，所述基板设置于所述包覆层下方；
    所述包覆层与所述基板之间还设有与所述第一导电柱电连接的重新布线层或金属焊球，以使所述基板与硅转接层实现电连接。
  2. 根据权利要求1所述的扇出型封装结构，其特征在于，所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。
  3. 根据权利要求2所述的扇出型封装结构，其特征在于，所述重新布线层通过键合胶层与所述基板键合；所述键合胶层内设有第二导电柱，所述基板依次通过第二导电柱、金属布线层、第一导电柱与所述硅转接层实现电连接。
  4. 根据权利要求3所述的扇出型封装结构，其特征在于，所述传输芯片通过所述重新布线层及第二导电柱与所述基板实现电连接。
  5. 根据权利要求1所述的扇出型封装结构，其特征在于，所述包覆层与基板通过金属焊球进行连接时，所述包覆层还包覆所述传输芯片的下表面，所述基板依次通过金属焊球、第一导电柱与所述硅转接层实现电连接。
  6. 一种三维堆叠的扇出型封装结构的制备方法，其特征在于，包括如下步骤：
    S1：提供硅转接层，所述硅转接层的下表面键合有传输芯片；
    S2：于所述硅转接层的下表面形成包覆层，所述包覆层包覆所述传输芯片的侧壁，且所述包覆层内设有贯穿所述包覆层的第一导电柱；
    S3：于所述硅转接层的上表面键合芯片堆叠体，所述芯片堆叠体包括2个以上沿竖直方向堆叠的芯片，相邻的芯片堆叠体之间通过所述传输芯片进行信号传输；
    S4：于所述包覆层的下方连接基板；
    其中，所述包覆层与所述基板之间还形成有与所述第一导电柱电连接的重新布线层或金属焊球，以使所述基板与硅转接层实现电连接。
  7. 根据权利要求6所述的制备方法，其特征在于，在步骤S3之后，于所述包覆层下表面形成所述重新布线层，所述重新布线层包括布线介质层及位于所述布线介质层内的金属布线层。
  8. 根据权利要求7所述的制备方法，其特征在于，形成所述重新布线层之后，所述重新布线层通过键合胶层与所述基板键合；所述键合胶层内设有第二导电柱，所述基板依次通过第二导电柱、金属布线层、第一导电柱与所述硅转接层实现电连接。
  9. 根据权利要求8所述的制备方法，其特征在于，所述传输芯片通过所述重新布线层及第二导电柱与所述基板实现电连接。
  10. 根据权利要求6所述的制备方法，其特征在于，步骤S2中，所述包覆层还包覆所述传输芯片的下表面；所述包覆层与基板通过金属焊球进行连接，所述基板依次通过金属焊球、第一导电柱与所述硅转接层实现电连接。
PCT/CN2023/099289 2022-08-29 2023-06-09 一种三维堆叠的扇出型封装结构及其制备方法 WO2024045758A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107564825A (zh) * 2017-08-29 2018-01-09 睿力集成电路有限公司 一种芯片双面封装结构及其制造方法
US20180190635A1 (en) * 2016-12-30 2018-07-05 Samsung Electronics Co., Ltd. Electronic device package
CN114171469A (zh) * 2021-12-30 2022-03-11 长电集成电路(绍兴)有限公司 晶圆级扇出的多芯片封装结构及其制备方法
CN216413054U (zh) * 2021-12-30 2022-04-29 长电集成电路(绍兴)有限公司 一种多芯片晶圆级扇出封装结构
CN115101519A (zh) * 2022-08-29 2022-09-23 盛合晶微半导体(江阴)有限公司 一种三维堆叠的扇出型封装结构及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2016099523A1 (en) * 2014-12-19 2016-06-23 Intel IP Corporation Stacked semiconductor device package with improved interconnect bandwidth

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180190635A1 (en) * 2016-12-30 2018-07-05 Samsung Electronics Co., Ltd. Electronic device package
CN107564825A (zh) * 2017-08-29 2018-01-09 睿力集成电路有限公司 一种芯片双面封装结构及其制造方法
CN114171469A (zh) * 2021-12-30 2022-03-11 长电集成电路(绍兴)有限公司 晶圆级扇出的多芯片封装结构及其制备方法
CN216413054U (zh) * 2021-12-30 2022-04-29 长电集成电路(绍兴)有限公司 一种多芯片晶圆级扇出封装结构
CN115101519A (zh) * 2022-08-29 2022-09-23 盛合晶微半导体(江阴)有限公司 一种三维堆叠的扇出型封装结构及其制备方法

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