WO2024045211A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2024045211A1
WO2024045211A1 PCT/CN2022/118313 CN2022118313W WO2024045211A1 WO 2024045211 A1 WO2024045211 A1 WO 2024045211A1 CN 2022118313 W CN2022118313 W CN 2022118313W WO 2024045211 A1 WO2024045211 A1 WO 2024045211A1
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WIPO (PCT)
Prior art keywords
layer
isolation
capacitor
mask
capacitive contact
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PCT/CN2022/118313
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English (en)
French (fr)
Inventor
周刘涛
潘烁
Original Assignee
长鑫存储技术有限公司
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Priority to US18/511,875 priority Critical patent/US20240090196A1/en
Publication of WO2024045211A1 publication Critical patent/WO2024045211A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • Embodiments of the present disclosure claim priority to a Chinese patent with application number 202211065549. incorporated in embodiments of the present disclosure.
  • Embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then passes through the bit line. Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • the capacitor of the dynamic random access memory is electrically connected to the capacitor landing pad through its lower electrode and forms an access path with the drain of the transistor.
  • the size of capacitors continues to shrink, and the size of the corresponding capacitor connection pads also shrinks.
  • by-products of the capacitor connection pad materials during dry etching and pickling remain between adjacent capacitor connection pads, causing adjacent capacitor connection pads to interact with each other and cause short circuits.
  • the subsequent capacitances formed on this will also interfere with each other, resulting in a reduction in the production yield of the memory device and affecting the reliability and electrical performance of the memory device.
  • a semiconductor structure and a method of manufacturing the same are provided.
  • embodiments of the present disclosure provide a semiconductor structure according to some embodiments, including:
  • a substrate a plurality of capacitive contact structures arranged at intervals are formed on the substrate;
  • the isolation structure is located on the substrate and between adjacent capacitive contact structures; the top surface of the isolation structure is not higher than the top surface of the capacitive contact structure;
  • the isolation groove extends from the top surface of the isolation structure into the isolation structure, and there is a distance between the isolation groove and the capacitive contact structure.
  • a plurality of the capacitive contact structures are distributed in an array of multiple rows and multiple columns.
  • a plurality of the capacitive contact structures located in the same column are arranged at intervals along the first direction.
  • a plurality of the capacitor contact structures located in the same row are arranged at intervals.
  • the contact structures are arranged at intervals along a second direction, and the second direction intersects the first direction;
  • the isolation grooves include a plurality of first isolation grooves arranged at intervals.
  • the first isolation grooves extend along the first direction and are located between two adjacent columns of the capacitive contact structures.
  • the isolation grooves include a plurality of second isolation grooves arranged at intervals, the second isolation grooves extend along the second direction and are located in two adjacent rows of the capacitive contact structures. between them, and penetrate a plurality of first isolation grooves.
  • the semiconductor structure further includes a plurality of capacitive structures, the capacitive structures are located on the substrate and are in one-to-one contact with the capacitive contact structures.
  • the semiconductor structure further includes a support structure.
  • the support structure includes a first support layer, a second support layer, and a third support layer stacked in sequence from bottom to top; the support structure has a A plurality of capacitor holes penetrating the first support layer, the second support layer and the third support layer, the capacitor holes are arranged in one-to-one correspondence with the capacitor contact structure, and the capacitor holes expose all The capacitive contact structure;
  • the isolation groove also penetrates the first support layer along the thickness direction
  • the capacitor structure includes:
  • the lower electrode is located on the side wall and bottom of the capacitor hole, is connected to the first support layer, the second support layer and the third support layer, and is connected to the capacitor contact structure contact;
  • the capacitive dielectric layer is located on the surface of the lower electrode and in the isolation groove;
  • the upper electrode is located on the surface of the capacitive dielectric layer.
  • the capacitor structure further includes:
  • the filling conductive layer fills the gap.
  • embodiments of the present disclosure also provide a method for preparing a semiconductor structure according to some embodiments, including:
  • a plurality of spaced-apart capacitive contact structures are formed in the base; the capacitive contact structures include an upper surface protruding from the base;
  • An isolation groove is formed; the isolation groove extends from the top surface of the isolation structure into the isolation structure and has a distance from the capacitive contact structure.
  • a plurality of the capacitive contact structures are distributed in multiple rows and multiple columns, a plurality of the capacitive contact structures located in the same column are arranged at intervals along the first direction, and a plurality of the capacitive contact structures located in the same row are arranged at intervals along the first direction. Arranged at intervals along a second direction, the second direction intersecting the first direction;
  • isolation grooves includes:
  • a first patterned mask layer is formed on the capacitive contact structure and the isolation structure; the first patterned mask layer includes a plurality of first mask patterns arranged in parallel and spaced apart, and the first mask layer The pattern extends along the first direction, and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate is located between two adjacent columns of the capacitive contact structures;
  • the isolation structure is etched based on the first patterned mask layer to form a plurality of first isolation grooves arranged at intervals; the first isolation grooves extend along the first direction and are located adjacent to between two columns of said capacitive contact structures.
  • forming a first patterned mask layer on the substrate includes:
  • first sub-mask patterns Forming a plurality of first sub-mask patterns arranged in parallel and spaced apart and extending along the first direction on the upper surface of the first mask layer;
  • first filling mask layer Form a first filling mask layer; the first filling mask layer fills the gaps between adjacent first sacrificial patterns, and the upper surface of the first filling mask layer is not higher than the first Sacrifice the upper surface of the figure;
  • the first mask layer is etched along the first initial trench to obtain the first patterned mask layer.
  • forming a first sacrificial pattern on the sidewall of the first sub-mask pattern includes:
  • the upper surface of the first mask layer exposed between the adjacent first sub-mask patterns, the sidewalls of the first sub-mask pattern and the top of the first sub-mask pattern form a third a layer of sacrificial material
  • forming the first filling mask layer includes:
  • first filling material layer Forming a first filling material layer on the first mask layer; the first filling material layer fills the gaps between adjacent first sacrificial patterns and covers the first sacrificial patterns;
  • forming the isolation groove further includes:
  • a second patterned mask layer is formed on the capacitive contact structure and the isolation structure;
  • the second patterned mask layer includes a plurality of second mask patterns arranged in parallel and spaced apart, and the second mask layer The pattern extends along a second direction, the second direction intersects the first direction, and the orthographic projection of the gap between adjacent second mask patterns on the upper surface of the substrate is located in two adjacent rows of the capacitors. between contact structures;
  • the isolation structure is etched based on the second patterned mask layer to form a plurality of second isolation grooves arranged at intervals; the second isolation grooves extend along the second direction and are located adjacent to Between two rows of the capacitive contact structures, a plurality of first isolation grooves pass through.
  • forming the isolation groove, before forming the first patterned mask layer and the second patterned mask layer on the capacitive contact structure and the isolation structure further includes: forming a pattern transfer material layer;
  • the isolation structure is etched based on the first patterned mask layer, the second patterned mask layer and the pattern transfer layer to form a plurality of first isolation grooves and second isolations arranged at intervals. groove.
  • the method further includes:
  • a plurality of capacitor structures are formed on the substrate, and the capacitor structures are in one-to-one contact with the capacitor contact structures.
  • forming multiple capacitor structures on the substrate includes:
  • a first support layer is formed on the upper surface of the isolation structure; the first support layer covers the top surface of the capacitive contact structure, and the isolation groove penetrates the first support layer along the thickness direction;
  • a first capacitor sacrificial layer is formed on the first support layer; the first capacitor sacrificial layer fills the isolation groove;
  • a plurality of capacitor holes are formed; the capacitor holes penetrate the third support layer, the second capacitor sacrificial layer, the second support layer, the first capacitor sacrificial layer and the first support layer to expose Produce the capacitive contact structure;
  • An upper electrode is formed on the surface of the capacitive dielectric layer.
  • the method further includes:
  • a filling conductive layer is formed that fills at least the gap.
  • Embodiments of the present disclosure may/at least have the following advantages:
  • the semiconductor structure provided by the embodiment of the present disclosure by arranging an isolation structure between adjacent capacitive contact structures, the problem of short circuit between adjacent capacitive contact structures is avoided.
  • the capacitive contact material used to form the capacitive contact structure is easily oxidized and remains between adjacent capacitive contact structures, causing adjacent capacitive contact structures to interfere with each other and cause a short circuit.
  • the semiconductor structure provided by the embodiment of the present disclosure also avoids the adjacent capacitance caused by the capacitance contact material being oxidized and remaining between the adjacent capacitance contact structures by providing an isolation groove extending from the top surface of the isolation structure into the isolation structure.
  • the contact structures interfere with each other and cause short circuit problems. Subsequent capacitors formed on top of this will not interfere with each other. Therefore, the semiconductor structure provided by the embodiment of the present disclosure can improve the production yield and use reliability of the capacitor, thereby improving the production yield and electrical performance of the semiconductor structure.
  • the method for manufacturing a semiconductor structure avoids the problem of short circuit between adjacent capacitive contact structures by filling the gaps between adjacent capacitive contact structures with isolation structures.
  • the capacitive contact material used to form the capacitive contact structure is easily oxidized, and by-products remain between adjacent capacitive contact structures, causing adjacent capacitive contact structures to interfere with each other and cause a short circuit.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure also avoids the problem caused by the by-products of the capacitive contact material remaining between the adjacent capacitive contact structures by forming an isolation groove extending from the top surface of the isolation structure into the isolation structure.
  • Adjacent capacitor contact structures interfere with each other, causing short circuit problems. Subsequent capacitors formed on top of this will not interfere with each other. Therefore, the preparation method of the semiconductor structure provided by the embodiment of the present disclosure can improve the production yield and use reliability of the capacitor, thereby improving the production yield and electrical performance of the semiconductor structure. .
  • 1 to 5 are schematic flow diagrams of a method for preparing a semiconductor structure provided in some embodiments of the present disclosure
  • Figure 6 is a schematic cross-sectional structural diagram of the structure obtained in step S300 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • FIG. 7 and FIG 8 are schematic cross-sectional structural diagrams of the structure obtained in step S413 in the preparation method of a semiconductor structure provided by some embodiments of the present disclosure
  • Figure (b) in Figure 7 and Figure 8(b) is a schematic top view of the structure obtained in step S413 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • Figure 9 and Figure 10 are schematic cross-sectional structural diagrams of the structure obtained in step S414 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure;
  • Figure (b) of Figure 10 is provided by some embodiments of the present disclosure.
  • Figure 11 (a) is a schematic cross-sectional view of the structure obtained in step S415 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • Figure (b) of Figure 11 is a semiconductor structure provided by some embodiments of the present disclosure.
  • Figure 12 is a schematic cross-sectional structural diagram of the structure obtained in step S416 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • Figure 13 (a) is a schematic cross-sectional view of the structure obtained in step S400 in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • Figure (b) of Figure 13 is a semiconductor structure provided by some embodiments of the present disclosure.
  • FIG. 14 to 22 are schematic cross-sectional structural diagrams of the structure obtained in the method for preparing a semiconductor structure provided by some embodiments of the present disclosure
  • FIG. 22 is also a schematic cross-sectional structural diagram of the semiconductor structure provided by some embodiments of the present disclosure.
  • first isolation groove may be called a second isolation groove
  • second isolation groove may be called a first isolation groove
  • first isolation groove and the second isolation groove are different isolation grooves. groove.
  • the spatially relative terms encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, what is described as “upper surface” would then be oriented “lower surface.” Thus, the exemplary term “upper” may include both upper and lower orientations. Additionally, the device may be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Inventive embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the disclosed embodiments, such that variations in the illustrated shapes are contemplated due, for example, to manufacturing techniques and/or tolerances.
  • embodiments of the present disclosure should not be limited to the particular shapes of regions shown herein but are to include deviations in shapes due, for example, to manufacturing techniques.
  • the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of embodiments of the present disclosure.
  • embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • the method for preparing a semiconductor structure may include the following steps:
  • S200 Form a plurality of spaced-apart capacitive contact structures in the substrate; the capacitive contact structures include protruding from the upper surface of the substrate.
  • S300 Form an isolation structure to fill the gap between adjacent capacitive contact structures, and the top surface of the isolation structure is not higher than the top surface of the capacitive contact structure.
  • S400 Form an isolation groove; the isolation groove extends from the top surface of the isolation structure into the isolation structure, and is spaced apart from the capacitive contact structure.
  • the method for preparing a semiconductor structure avoids the problem of short circuit between adjacent capacitive contact structures by designing a gap-filling isolation structure between adjacent capacitive contact structures.
  • the capacitive contact material used to form the capacitive contact structure is easily oxidized, and by-products remain between adjacent capacitive contact structures, causing adjacent capacitive contact structures to interfere with each other and cause a short circuit.
  • the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure also avoids the problem caused by the by-products of the capacitive contact material remaining between adjacent capacitive contact structures by forming an isolation groove extending from the top surface of the isolation structure into the isolation structure.
  • Adjacent capacitor contact structures interfere with each other, causing short circuit problems. Subsequent capacitors formed on top of this will not interfere with each other. Therefore, the preparation method of the semiconductor structure provided by the embodiment of the present disclosure can improve the production yield and use reliability of the capacitor, thereby improving the production yield and electrical performance of the semiconductor structure. .
  • multiple capacitive contact structures are distributed in multiple rows and multiple columns, multiple capacitive contact structures located in the same column are spaced apart along the first direction, and multiple capacitive contact structures located in the same row are spaced apart along the second direction. cloth, the second direction intersects the first direction.
  • step S400 forms an isolation groove, which may include the following steps:
  • S410 Form a first patterned mask layer on the capacitive contact structure and the isolation structure; the first patterned mask layer includes a plurality of first mask patterns arranged in parallel and spaced apart, and the first mask patterns extend along the first direction. , and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate is located between two adjacent columns of capacitive contact structures.
  • S420 Etch the isolation structure based on the first patterned mask layer to form a plurality of first isolation grooves arranged at intervals; the first isolation grooves extend along the first direction and are located between two adjacent columns of capacitive contact structures. between.
  • step S410 forms a first patterned mask layer on the substrate, which may include the following steps:
  • S411 Form a first mask layer on the capacitive contact structure and isolation structure.
  • S412 Form a plurality of first sub-mask patterns arranged in parallel and spaced apart and extending along the first direction on the upper surface of the first mask layer.
  • S413 Form a first sacrificial pattern on the sidewall of the first sub-mask pattern, and remove the first sub-mask pattern to retain a plurality of first sacrificial patterns arranged in parallel and spaced apart and extending along the first direction.
  • S414 Form a first filling mask layer; the first filling mask layer fills the gaps between adjacent first sacrificial patterns, and the upper surface of the first filling mask layer is not higher than the upper surface of the first sacrificial pattern.
  • S415 Remove the first sacrificial pattern to form a first initial trench between adjacent first filling mask layers.
  • S416 Etch the first mask layer along the first initial trench to obtain a first patterned mask layer.
  • step S400 forms an isolation groove, and may also include the following steps:
  • S430 Form a second patterned mask layer on the capacitive contact structure and the isolation structure; the second patterned mask layer includes a plurality of second mask patterns arranged in parallel and spaced apart, and the second mask pattern extends along the second direction. , the second direction intersects the first direction, and the orthographic projection of the gap between adjacent second mask patterns on the upper surface of the substrate is located between two adjacent rows of capacitive contact structures.
  • S440 Etch the isolation structure based on the second patterned mask layer to form a plurality of second isolation grooves arranged at intervals; the second isolation grooves extend along the second direction and are located between two adjacent rows of capacitive contact structures. space, and penetrates a plurality of first isolation grooves.
  • a step of forming a plurality of capacitor structures on the substrate is further included.
  • the capacitor structure and the capacitor contact structure are in one-to-one contact.
  • a step of forming a first support layer on the upper surface of the isolation structure is further included.
  • the following steps can be used to form multiple capacitor structures, including:
  • S511 Form a first support layer on the upper surface of the isolation structure; the first support layer covers the top surface of the capacitive contact structure, and the isolation groove penetrates the first support layer along the thickness direction.
  • S513 Form a second support layer on the upper surface of the first capacitor sacrificial layer.
  • S514 Form a second capacitor sacrificial layer on the upper surface of the second support layer.
  • S515 Form a third support layer on the upper surface of the second capacitor sacrificial layer.
  • S516 Form a plurality of capacitor holes; the capacitor holes penetrate the third support layer, the second capacitor sacrificial layer, the second support layer, the first capacitor sacrificial layer and the first support layer to expose the capacitor contact structure.
  • S517 Form a lower electrode on the side wall and bottom of the capacitor hole.
  • S520 Form an upper electrode on the surface of the capacitor dielectric layer.
  • step S100 a substrate is provided.
  • the material of the substrate may include but is not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), etc. or combinations thereof.
  • step S200 a plurality of spaced-apart capacitive contact structures 100 are formed in a substrate (not shown in FIG. 6 ). As shown in FIG. 6 , the upper surface of the capacitive contact structure 100 may protrude from the upper surface of the substrate.
  • the embodiment of the disclosure does not specifically limit the material of the capacitive contact structure 100 .
  • the material of the capacitive contact structure 100 may include, but is not limited to, related semiconductor conductive materials such as tungsten (W) or copper (Cu).
  • the sidewall dielectric layer 110 may be formed on at least one sidewall of the capacitive contact structure 100 .
  • the sidewall dielectric layer 110 can be formed to prevent the capacitive contact structure 100 from diffusing in a high temperature environment, causing mutual interference between adjacent capacitive contact structures 100 and causing a short circuit, and to avoid subsequent occurrence of a short circuit.
  • a short circuit occurs between the adjacent capacitors formed, further improving the production yield and use reliability of the products obtained by the preparation method.
  • the embodiment of the present disclosure does not specifically limit the material of the sidewall dielectric layer 110 .
  • the material of the sidewall dielectric layer 110 may include, but is not limited to, metal suicide.
  • step S300 an isolation structure 200 is formed to fill the gap between adjacent capacitive contact structures 100 .
  • the top surface of the isolation structure 200 is not higher than the top surface of the capacitive contact structure 100 so that the top surface of the capacitive contact structure 100 is exposed.
  • the isolation structure 200 can be filled in the gap between the adjacent capacitive contact structures 100 to insulate the adjacent capacitive contact structures 100 to avoid short circuit.
  • the embodiment of the disclosure does not specifically limit the material of the isolation structure 200 .
  • the material of the isolation structure 200 may include, but is not limited to, insulating materials such as monocrystalline silicon, polycrystalline silicon, silicon dioxide (SiO 2 ), or silicon nitride (SiN).
  • an isolation groove 300 is formed.
  • the isolation groove 300 extends from the top surface of the isolation structure 200 into the isolation structure 200 and is spaced apart from the capacitive contact structure 100 .
  • the isolation groove 300 can effectively cut off the remaining capacitive contact material 100 a between adjacent capacitive contact structures 100 .
  • the remaining capacitive contact material 100a will not cause adjacent capacitive contact structures 100 to interfere with each other and cause a short circuit. Subsequent capacitors formed on top of this will not interfere with each other.
  • the multiple capacitive contact structures 100 are distributed in multiple rows and multiple columns.
  • the multiple capacitive contact structures 100 located in the same column are spaced apart along the first direction, and the multiple capacitive contact structures 100 located in the same row are arranged along the second direction.
  • Directionally spaced arrangement is possible.
  • the second direction intersects the first direction.
  • the isolation groove 300 formed in step S400 may include a plurality of first isolation grooves arranged at intervals.
  • step S400 may specifically include the following steps S410 to S420 to form a first isolation groove.
  • step S410 referring to FIGS. 7 to 12 , a first patterned mask layer 310 is formed on the capacitive contact structure 100 and the isolation structure 200 .
  • the first patterned mask layer 310 may include a plurality of first mask patterns arranged in parallel and spaced apart.
  • the first mask patterns extend along the first direction, and the orthographic projection of the gap between adjacent first mask patterns on the upper surface of the substrate should be located between two adjacent columns of capacitive contact structures 100 .
  • step S420 please continue to refer to FIGS. 7 to 12 , the isolation structure 200 is etched based on the first patterned mask layer 310 to form a plurality of first isolation grooves arranged at intervals.
  • the first isolation groove extends along the first direction and is located between two adjacent columns of capacitive contact structures 100 .
  • the isolation groove 300 formed in step S400 may further include a plurality of second isolation grooves arranged at intervals.
  • step S400 may further include the following steps S430 to S440 to form a second isolation groove.
  • step S430 a second patterned mask layer is formed on the capacitive contact structure 100 and the isolation structure 200.
  • the second patterned mask layer may include a plurality of second mask patterns arranged in parallel and spaced apart.
  • the second mask patterns extend along a second direction, and the second direction intersects the first direction. Between adjacent second mask patterns, The orthographic projection of the gap on the upper surface of the substrate is located between two adjacent rows of capacitive contact structures 100 .
  • step S440 the isolation structure 200 is etched based on the second patterned mask layer to form a plurality of second isolation grooves arranged at intervals.
  • the second isolation groove extends along the second direction, is located between two adjacent rows of capacitive contact structures 100, and penetrates the plurality of first isolation grooves.
  • the second patterned mask layer may be formed after the first patterned mask layer 310 is formed.
  • the materials of the first patterned mask layer 310 and the second patterned mask layer may include, but are not limited to, silicon oxynitride (SiO 2 ).
  • the first isolation groove and the second isolation groove can be formed in the following manner. for example:
  • a pattern transfer material layer is formed. Before etching the isolation structure 200, the first mask pattern and the second mask pattern are transferred to the pattern transfer material layer to form a pattern transfer layer.
  • the isolation structure 200 is etched based on the first patterned mask layer 310, the second patterned mask layer and the pattern transfer layer to form a plurality of first isolation grooves and second isolation grooves arranged at intervals.
  • step S410 may specifically include the following steps S411 to S416.
  • step S411 as shown in Figure 7 (a) and Figure 7 (b), a first mask layer 311 is formed on the capacitive contact structure 100 and the isolation structure 200.
  • step S412 as shown in Figure 7(a) and Figure 7(b), a plurality of parallel and spaced-apart patterns are formed on the upper surface of the first mask layer 311 and extending in the first direction.
  • a first sacrificial pattern 314 is formed on the sidewall of the first sub-mask pattern 312; the first sub-mask pattern 312 is removed, as shown in (a) of Figure 8 and (b) of Figure 8 As shown, a plurality of first sacrificial patterns 314 arranged in parallel and spaced apart and extending along the first direction remain.
  • step S414 as shown in Figures 9 to 10, a first filling mask layer 316 is formed; the first filling mask layer 316 fills the gaps between adjacent first sacrificial patterns 314, and the first filling mask layer 316 is The upper surface of layer 316 is no higher than the upper surface of first sacrificial pattern 314 .
  • step S415 as shown in (a) of FIG. 11 and (b) of FIG. 11 , the first sacrificial pattern 314 is removed to form a first initial filling mask layer 316 between adjacent first filling mask layers 316 . Groove 317.
  • step S416 as shown in FIG. 12, the first mask layer 311 is etched along the first initial trench 317 to obtain the first patterned mask layer 310.
  • the embodiment of the present disclosure does not specifically limit the material of the first sub-mask pattern 312 formed in step S412.
  • the material of the first sub-mask pattern 312 may include but is not limited to photoresist.
  • step S413 in some embodiments, the following steps may be used to form the first sacrificial pattern 314. include:
  • the upper surface of the first mask layer 311 , the sidewalls of the first sub-mask pattern 312 and the first sub-mask layer are exposed between adjacent first sub-mask patterns 312 .
  • a first sacrificial material layer 313 is formed on top of the mask pattern 312 .
  • the material of the first sacrificial pattern 314 may include but is not limited to oxide.
  • the embodiment of the present disclosure does not specifically limit the method of removing part of the first sacrificial material layer 313 in the above steps.
  • carbon tetrafluoride also known as tetrafluoromethane, chemical formula is CF 4
  • perfluorobutadiene (C 4 F 6 ) gas may be used to etch and remove part of the first sacrificial material layer 313 .
  • step S413 and step S414 a step of removing the first sub-mask pattern 312 may also be included.
  • the first sub-mask pattern 312 may be removed by dry cleaning using oxygen (O 2 ) plasma or silicon dioxide, but is not limited thereto.
  • step S4144 in some embodiments, the following steps may be used to form the first filling mask layer 316. include:
  • a first filling material layer 315 is formed on the first mask layer 311 .
  • the first filling material layer 315 should at least fill the gaps between adjacent first sacrificial patterns 314.
  • the first filling material layer 315 can also cover the first sacrificial pattern 314.
  • the first filling material layer 315 is etched back to remove the first filling material layer 315 on top of the first sacrificial pattern 314 and retain the first filling material layer 315 on the top of the first sacrificial pattern 314.
  • the first filling material layer 315 adjacent to the first sacrificial pattern 314 is the first filling mask layer 316.
  • the embodiment of the present disclosure does not specifically limit the method of removing the first sacrificial pattern 314 in step S415.
  • a wet etching process may be used to remove the first sacrificial pattern 314 .
  • the embodiment of the present disclosure does not specifically limit the material of the first filling mask layer 316 formed in the above steps.
  • the material of the first filling mask layer 316 may include but is not limited to carbide (Carbon).
  • the method of forming the second patterned mask layer in step S430 may refer to the aforementioned step of forming the first patterned mask layer 310, which will not be described again here.
  • the first patterned mask layer 310 and the first filling mask layer can be removed after the isolation groove 300 is formed. 316.
  • a plurality of capacitor structures 400 can be formed on the substrate.
  • the capacitor structure 400 can be in one-to-one contact with the capacitor contact structure 100 .
  • forming the capacitor structure 400 may specifically include the following steps S511 to S520.
  • a first support layer 411 is formed on the upper surface of the isolation structure 200.
  • the first support layer 411 covers the top surface of the capacitive contact structure 100, and the isolation groove 300 penetrates the first support layer 411.
  • step S512 please refer to FIG. 14, a first capacitor sacrificial layer 421 is formed on the first support layer 411, and the first capacitor sacrificial layer 421 fills the isolation groove 300.
  • step S513 please continue to refer to FIG. 14 to form a second support layer 412 on the upper surface of the first capacitor sacrificial layer 421.
  • step S514 please continue to refer to FIG. 14 to form a second capacitor sacrificial layer 422 on the upper surface of the second support layer 412.
  • step S515 please continue to refer to FIG. 14 to form a third support layer 413 on the upper surface of the second capacitor sacrificial layer 422.
  • a plurality of capacitor holes 430 are formed.
  • the capacitor hole 430 penetrates the third support layer 413 , the second capacitor sacrificial layer 422 , the second support layer 412 , the first capacitor sacrificial layer 421 and the first support layer 411 to expose the capacitor contact structure 100 .
  • step S517 please refer to FIG. 16, a lower electrode 440 is formed on the side wall and bottom of the capacitor hole 430.
  • step S518, please refer to FIGS. 17 to 21 to remove the first capacitor sacrificial layer 421 and the second capacitor sacrificial layer 422.
  • a capacitive dielectric layer 450 is formed on the surface of the lower electrode 440 and in the isolation groove 300.
  • step S520 referring to FIG. 22, an upper electrode 460 is formed on the surface of the capacitive dielectric layer 450.
  • the surface of the lower electrode 440 located above the third support layer 413 is called the top surface of the lower electrode 440 .
  • step S511 may specifically include the following steps. for example:
  • a first support material layer 411 a is formed on the upper surface of the isolation structure 200 .
  • the first support material layer 411a covers the top surface of the capacitive contact structure 100.
  • the isolation groove 300 penetrates the first support material layer 411 a.
  • the remaining first support material layer 411a serves as the first support layer 411.
  • the embodiment of the present disclosure does not specifically limit the materials of the first support layer 411 formed in step S511 and the second support layer 412 formed in step S513.
  • the material of the first support layer 411 and the material of the second support layer 412 both include silicon nitride.
  • the embodiment of the present disclosure does not specifically limit the materials of the first capacitor sacrificial layer 421 formed in step S512 and the second capacitor sacrificial layer 422 formed in step S514.
  • the material of the first capacitor sacrificial layer 421 may include, but is not limited to, phosphosilicate glass (PSG for short) or borophosphosilicate glass (BPSG for short), and the like.
  • the material of the second capacitor sacrificial layer 422 may include but is not limited to oxide.
  • the embodiment of the present disclosure does not specifically limit the materials of the lower electrode 440, the capacitive dielectric layer 450, and the upper electrode 460 formed in the above steps.
  • the material of the lower electrode 440 may include, but is not limited to, a compound formed of one or two of metal nitride and metal silicide.
  • the material of the capacitive dielectric layer 450 may include, but is not limited to, zirconium oxide (ZrO x ), hafnium oxide (HfO x ), zirconium titanium oxide (ZrTiO x ), ruthenium oxide (RuO x ), antimony oxide (SbO x ), Aluminum oxide ( AlOx ) or combinations thereof.
  • the material of the upper electrode 460 may include but is not limited to polysilicon.
  • step S518 may specifically include the following steps. for example:
  • a mask stack 510 is formed.
  • the mask stack 510 covers the top surface of the lower electrode 440 and seals the capacitor hole 430 .
  • a photoresist layer 520 is formed on the upper surface of the mask stack 510, and the photoresist layer 520 is patterned to form a photoresist pattern 520a on the photoresist layer 520.
  • the resist pattern 520a exposes a portion of the upper surface of the mask stack 510.
  • the mask stack 510 is etched based on the photoresist layer 520 to form a plurality of openings in the mask stack 510 , and the openings expose part of the third support layer 413 .
  • the top surface of the lower electrode 440 is removed, and the pattern of the opening is transferred to the third support layer 413 to form a capacitor opening hole 530 .
  • the capacitor opening hole 530 exposes a portion of the second capacitor sacrificial layer 422 .
  • the second capacitor sacrificial layer 422 is removed to expose the second support layer 412 .
  • the pattern of the capacitor opening hole 530 is transferred to the second support layer 412 to expose part of the first capacitor sacrificial layer 421 .
  • the first capacitor sacrificial layer 421 is removed to expose the first support layer 411 .
  • the embodiment of the present disclosure does not specifically limit the structure of the mask stack 510 .
  • the mask stack 510 may include a first mask material layer 511 , a second mask material layer 512 , and a third mask material layer 513 sequentially stacked from bottom to top.
  • the first mask material layer 511 may include but is not limited to a silicon dioxide layer; the second mask material layer 512 may include but is not limited to a crystalline carbon layer or an amorphous carbon layer, etc.; the third mask material layer 513 May include, but are not limited to, silicon oxynitride layers.
  • the embodiment of the disclosure does not specifically limit the method of removing the second capacitor sacrificial layer 422 and the first capacitor sacrificial layer 421 .
  • the following steps can be used to remove the second capacitor sacrificial layer 422, such as:
  • an acid solution is injected into the second capacitor sacrificial layer 422 through the capacitor opening hole 530, and the second capacitor sacrificial layer 422 is removed by dissolving the acid solution.
  • the following steps can be used to remove the first capacitor sacrificial layer 421, such as:
  • an acid solution is injected into the first capacitor sacrificial layer 421, and the first capacitor sacrificial layer 421 is removed by dissolving the acid solution.
  • a step of forming the filling conductive layer 470 may also be included.
  • the filling conductive layer 470 can at least fill the gap between the upper electrodes 460 in the embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a semiconductor structure according to some embodiments.
  • the semiconductor structure may include a substrate, an isolation structure 200 and an isolation groove 300 .
  • a plurality of capacitive contact structures 100 arranged at intervals are formed on the substrate.
  • the isolation structure 200 is located on the substrate and between adjacent capacitive contact structures 100; the top surface of the isolation structure 200 should be no higher than the top surface of the capacitive contact structure 100.
  • the isolation groove 300 extends from the top surface of the isolation structure 200 into the isolation structure 200 , and there is a gap between the isolation groove 300 and the capacitive contact structure 100 .
  • the semiconductor structure provided by the above embodiments by disposing the isolation structure 200 between adjacent capacitive contact structures 100, the problem of short circuit between adjacent capacitive contact structures 100 is avoided.
  • the capacitive contact material used to form the capacitive contact structure 100 is easily oxidized, and by-products remain between adjacent capacitive contact structures 100, causing the adjacent capacitive contact structures 100 to interfere with each other. causing a short circuit.
  • the semiconductor structure provided by the embodiment of the present disclosure also avoids failure due to by-products of the capacitive contact material remaining between adjacent capacitive contact structures 100 by arranging the isolation groove 300 extending from the top surface of the isolation structure 200 into the isolation structure 200 .
  • the semiconductor structure provided by the embodiment of the present disclosure can improve the production yield and use reliability of the capacitor, thereby improving the production yield and electrical performance of the semiconductor structure.
  • the isolation groove 300 may include a plurality of first isolation grooves arranged at intervals.
  • the first isolation groove extends along the first direction and is located between two adjacent columns of capacitive contact structures 100 .
  • the isolation groove 300 may further include a plurality of second isolation grooves arranged at intervals.
  • the second isolation groove extends along the second direction, is located between two adjacent rows of capacitive contact structures 100, and penetrates the plurality of first isolation grooves.
  • the semiconductor structure may also include a plurality of capacitor structures 400 .
  • the capacitor structure 400 is located on the substrate and contacts the capacitor contact structure 100 one-to-one.
  • the semiconductor structure may further include a support structure.
  • the support structure may include a first support layer 411 , a second support layer 412 and a third support layer 413 that are stacked in sequence from bottom to top (not shown in FIG. 22 ).
  • the support structure is provided with a plurality of capacitor holes 430 penetrating the first support layer 411, the second support layer 412 and the third support layer 413.
  • the capacitor holes 430 are arranged in one-to-one correspondence with the capacitor contact structure 100, and the capacitor holes 430 expose the capacitor. Contact structure 100.
  • the isolation groove 300 also penetrates the first support layer 411 along the thickness direction.
  • the capacitive structure 400 may include a lower electrode 440 , a capacitive dielectric layer 450 and an upper electrode 460 .
  • the lower electrode 440 is located on the sidewall and bottom of the capacitor hole 430 , is connected to the first support layer 411 , the second support layer 412 and the third support layer 413 , and is in contact with the capacitor contact structure 100 .
  • the capacitive dielectric layer 450 is located on the surface of the lower electrode 440 and within the isolation groove 300 .
  • the upper electrode 460 is located on the surface of the capacitive dielectric layer 450 .
  • the capacitor structure 400 may further include a filled conductive layer 470 .
  • the filling conductive layer 470 may be filled in the gaps between the upper electrodes 460 .
  • the filled conductive layer 470 is electrically connected to the upper electrode 460 to achieve connection with the metal interconnect lines on the capacitor structure 400 .

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Abstract

本公开实施例涉及一种半导体结构及其制备方法。该半导体结构包括：基底；基底上形成有多个间隔排布的电容接触结构；隔离结构；隔离结构位于基底上，且位于相邻电容接触结构之间；隔离结构的顶面不高于电容接触结构的顶面；隔离凹槽；隔离凹槽由隔离结构顶面延伸至隔离结构内，且隔离凹槽与电容接触结构之间具有间距。

Description

半导体结构及其制备方法
相关申请的交叉引用
本公开实施例要求于2022年9月1日提交中国专利局、申请号为202211065549.X、名称为“半导体结构及其制备方法”的中国专利的优先权，所述专利申请的全部内容通过引用结合在本公开实施例中。
技术领域
本公开实施例涉及半导体制造技术领域，特别是涉及一种半导体结构及其制备方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，简称DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
动态随机存取存储器的电容通过其下电极来与电容连接垫(landing pad)电连接并与晶体管的漏极形成存取通路。随着存储器件集成度的不断微缩，电容尺寸不断缩小，相应的电容连接垫尺寸也在缩小。但是，电容连接垫在制备过程中，干法刻蚀和酸洗时电容连接垫材料的副产物残留在相邻电容连接垫之间，使相邻电容连接垫相互影响，造成短路。后续在此之上形成的电容也会相互干扰，从而造成存储器件生产良率降低，影响存储器件的使用可靠性及电学性能。
发明内容
根据本公开实施例的各种实施例，提供一种半导体结构及其制备方法。
一方面，本公开实施例根据一些实施例，提供一种半导体结构，包括：
基底；所述基底上形成有多个间隔排布的电容接触结构；
隔离结构；所述隔离结构位于所述基底上，且位于相邻所述电容接触结构之间；所述隔离结构的顶面不高于所述电容接触结构的顶面；
隔离凹槽；所述隔离凹槽由所述隔离结构顶面延伸至所述隔离结构内，且所述隔离凹槽与所述电容接触结构之间具有间距。
在一些实施例中，多个所述电容接触结构呈多行多列的阵列分布，位于同一列的多个所述电容接触结构沿第一方向间隔排布，位于同一行的多个所述电容接触结构沿第二方向间隔排布，所述第二方向与所述第一方向相交；
所述隔离凹槽包括多个间隔排布的第一隔离凹槽，所述第一隔离凹槽沿所述第一方向延伸，且位于相邻两列所述电容接触结构之间。
在一些实施例中，所述隔离凹槽包括多个间隔排布的第二隔离凹槽，所述第二隔离凹槽沿所述第二方向延伸，且位于相邻两行所述电容接触结构之间，并贯通多个所述第一隔离凹槽。
在一些实施例中，所述半导体结构还包括多个电容结构，所述电容结构位于所述基底上，且 与所述电容接触结构一一对应接触。
在一些实施例中，所述半导体结构还包括支撑结构，所述支撑结构包括由下至上依次间隔叠置的第一支撑层、第二支撑层及第三支撑层；所述支撑结构内设有多个贯穿所述第一支撑层、所述第二支撑层及所述第三支撑层的电容孔，所述电容孔与所述电容接触结构一一对应设置，且所述电容孔暴露出所述电容接触结构；
所述隔离凹槽还沿厚度方向贯穿所述第一支撑层；
所述电容结构包括：
下电极；所述下电极位于所述电容孔的侧壁及底部，与所述第一支撑层、所述第二支撑层及所述第三支撑层均相连接，并与所述电容接触结构相接触；
电容介质层；所述电容介质层位于所述下电极的表面及所述隔离凹槽内；
上电极；所述上电极位于所述电容介质层的表面。
在一些实施例中，所述上电极之间还具有间隙；所述电容结构还包括：
填充导电层；所述填充导电层填充于所述间隙内。
另一方面，本公开实施例还根据一些实施例，提供一种半导体结构的制备方法，包括：
提供基底；
于所述基底内形成多个间隔排布的电容接触结构；所述电容接触结构包括凸出于所述基底的上表面；
形成隔离结构填充相邻所述电容接触结构之间的间隙，所述隔离结构的顶面不高于所述电容接触结构的顶面；
形成隔离凹槽；所述隔离凹槽由所述隔离结构的顶面延伸至所述隔离结构内，且与所述电容接触结构具有间距。
在一些实施例中，多个所述电容接触结构呈多行多列分布，位于同一列的多个所述电容接触结构沿第一方向间隔排布，位于同一行的多个所述电容接触结构沿第二方向间隔排布，所述第二方向与所述第一方向相交；
所述形成隔离凹槽，包括：
于所述电容接触结构及所述隔离结构上形成第一图形化掩膜层；所述第一图形化掩膜层包括多个平行间隔排布的第一掩膜图形，所述第一掩膜图形沿第一方向延伸，且相邻所述第一掩膜图形之间的间隙于所述基底上表面的正投影位于相邻两列所述电容接触结构之间；
基于所述第一图形化掩膜层刻蚀所述隔离结构，以形成多个间隔排布的第一隔离凹槽；所述第一隔离凹槽沿所述第一方向延伸，且位于相邻两列所述电容接触结构之间。
在一些实施例中，所述于所述基底上形成第一图形化掩膜层，包括：
于所述电容接触结构及所述隔离结构上形成第一掩膜层；
于所述第一掩膜层的上表面形成多个平行间隔排布且沿所述第一方向延伸的第一子掩膜图形；
于所述第一子掩膜图形的侧壁形成第一牺牲图形，去除所述第一子掩膜图形，以保留多个平行间隔排布且沿所述第一方向延伸的所述第一牺牲图形；
形成第一填充掩膜层；所述第一填充掩膜层填充满相邻所述第一牺牲图形之间的间隙，且所述第一填充掩膜层的上表面不高于所述第一牺牲图形的上表面；
去除所述第一牺牲图形，以在相邻所述第一填充掩膜层之间形成第一初始沟槽；
沿所述第一初始沟槽刻蚀所述第一掩膜层，以得到所述第一图形化掩膜层。
在一些实施例中，所述于所述第一子掩膜图形的侧壁形成第一牺牲图形，包括：
于相邻所述第一子掩膜图形之间暴露的所述第一掩膜层的上表面、所述第一子掩膜图形的侧壁及所述第一子掩膜图形的顶部形成第一牺牲材料层；
去除位于相邻所述第一子掩膜图形之间暴露的所述第一掩膜层的上表面及位于所述第一子掩膜图形的顶部的所述第一牺牲材料层，保留于所述第一子掩膜图形的侧壁的所述第一牺牲材料层即为所述第一牺牲图形。
在一些实施例中，所述形成第一填充掩膜层，包括：
于所述第一掩膜层上形成第一填充材料层；所述第一填充材料层填充满相邻所述第一牺牲图形之间的间隙，并覆盖所述第一牺牲图形；
回刻所述第一填充材料层，以去除所述第一牺牲图形顶部的所述第一填充材料层，并保留位于相邻所述第一牺牲图形之间的所述第一填充材料层即为所述第一填充掩膜层。
在一些实施例中，所述形成隔离凹槽，还包括：
于所述电容接触结构及所述隔离结构上形成第二图形化掩膜层；所述第二图形化掩膜层包括多个平行间隔排布的第二掩膜图形，所述第二掩膜图形沿第二方向延伸，所述第二方向与所述第一方向相交，相邻所述第二掩膜图形之间的间隙于所述基底上表面的正投影位于相邻两行所述电容接触结构之间；
基于所述第二图形化掩膜层刻蚀所述隔离结构，以形成多个间隔排布的第二隔离凹槽；所述第二隔离凹槽沿所述第二方向延伸，且位于相邻两行所述电容接触结构之间，并贯通多个所述第一隔离凹槽。
在一些实施例中，所述形成隔离凹槽，在所述电容接触结构及所述隔离结构上形成所述第一图形化掩膜层及所述第二图形化掩膜层之前，还包括：形成图形转移材料层；
在刻蚀所述隔离结构之前，将所述第一掩膜图形及所述第二掩膜图形转移至所述图形转移材料层，以形成图形转移层；
基于所述第一图形化掩膜层、所述第二图形化掩膜层及所述图形转移层刻蚀所述隔离结构，以形成多个间隔排布的第一隔离凹槽及第二隔离凹槽。
在一些实施例中，所述形成隔离凹槽之后，还包括：
于所述基底上形成多个电容结构，所述电容结构与所述电容接触结构一一对应接触。
在一些实施例中，于所述基底上形成多个电容结构包括：
于所述隔离结构的上表面形成第一支撑层；所述第一支撑层覆盖所述电容接触结构的顶面，且所述隔离凹槽沿厚度方向贯穿所述第一支撑层；
在形成所述隔离凹槽之后，于所述第一支撑层上形成第一电容牺牲层；所述第一电容牺牲层填满所述隔离凹槽；
于所述第一电容牺牲层的上表面形成第二支撑层；
于所述第二支撑层的上表面形成第二电容牺牲层；
于所述第二电容牺牲层的上表面形成第三支撑层；
形成多个电容孔；所述电容孔贯穿所述第三支撑层、所述第二电容牺牲层、所述第二支撑层、所述第一电容牺牲层及所述第一支撑层，以暴露出所述电容接触结构；
于所述电容孔的侧壁及底部形成下电极；
去除所述第一电容牺牲层及所述第二电容牺牲层；
于所述下电极的表面及所述隔离凹槽内形成电容介质层；
于所述电容介质层的表面形成上电极。
在一些实施例中，所述上电极之间具有间隙；所述形成上电极之后，还包括：
形成填充导电层，所述填充导电层至少填满所述间隙。
本公开实施例可以/至少具有以下优点：
在本公开实施例提供的半导体结构中，通过在相邻电容接触结构之间设置隔离结构，避免相邻电容接触结构之间发生短路的问题。在电容接触结构的制备过程中，用于形成电容接触结构的电容接触材料很容易被氧化，并在相邻电容接触结构之间残留，使相邻电容接触结构相互干扰，造成短路。然而，本公开实施例提供的半导体结构还通过设置由隔离结构顶面延伸至隔离结构内的隔离凹槽，避免由于电容接触材料被氧化后残留在相邻电容接触结构之间而导致相邻电容接触结构相互干扰，造成短路的问题。后续在此之上形成的电容也不会相互干扰，因此，本公开实施例提供的半导体结构能够提升电容的生产良率及使用可靠性，从而提升半导体结构的生产良率及电学性能。
本公开实施例提供的半导体结构的制备方法，通过在相邻电容接触结构之间的间隙填充隔离结构，避免相邻电容接触结构之间发生短路的问题。在电容接触结构的制备过程中，用于形成电容接触结构的电容接触材料很容易被氧化，并在相邻电容接触结构之间残留副产物，使相邻电容接触结构相互干扰，造成短路。然而，本公开实施例提供的半导体结构的制备方法还通过形成由隔离结构顶面延伸至隔离结构内的隔离凹槽，避免由于电容接触材料的副产物残留在相邻电容接触结构之间而导致相邻电容接触结构相互干扰，造成短路的问题。后续在此之上形成的电容也不会相互干扰，因此，本公开实施例提供的半导体结构的制备方法能够提升电容的生产良率及使用可靠性，从而提升半导体结构的生产良率及电学性能。
本公开实施例的一个或多个实施例的细节在下面的附图和描述中提出。本公开实施例的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1至图5为本公开一些实施例中提供的半导体结构的制备方法的流程示意图；
图6为本公开一些实施例提供的半导体结构的制备方法中，步骤S300所得结构的截面结构示意图；
图7中的(a)图及图8中的(a)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S413所得结构的截面结构示意图；图7中的(b)图及图8中的(b)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S413所得结构的俯视结构示意图；
图9及图10中的(a)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S414所得结构的截面结构示意图；图10中的(b)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S414所得结构的俯视结构示意图；
图11中的(a)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S415所得结构的截面结构示意图；图11中的(b)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S415 所得结构的俯视结构示意图；
图12为本公开一些实施例提供的半导体结构的制备方法中，步骤S416所得结构的截面结构示意图；
图13中的(a)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S400所得结构的截面结构示意图；图13中的(b)图为本公开一些实施例提供的半导体结构的制备方法中，步骤S400所得结构的俯视结构示意图；
图14至图22为本公开一些实施例提供的半导体结构的制备方法中所得结构的截面结构示意图；其中，图22亦为本公开一些实施例提供的半导体结构的截面结构示意图。
具体实施方式
为了便于理解本公开实施例，下面将参照相关附图对本公开实施例进行更全面的描述。附图中给出了本公开实施例的首选实施例。但是，本公开实施例可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开实施例的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开实施例的技术领域的技术人员通常理解的含义相同。本文中在本公开实施例的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开实施例。
应当明白，当元件或层被称为“位于…上”、“相邻…之间”或“与…相连接”时，其可以直接地位于其他元件或层上、相邻元件或层之间或与元件或层相连接，或者可以存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开实施例教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一隔离凹槽称为第二隔离凹槽，且类似地，可以将第二隔离凹槽称为第一隔离凹槽；第一隔离凹槽与第二隔离凹槽为不同的隔离凹槽。
还应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“上表面”将取向为“下表面”。因此，示例性术语“上”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开实施例的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开实施例的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开实施例的范围。
请参阅图1至图22。需要说明的是，本公开实施例中所提供的图示仅以示意方式说明本公开实施例的基本构想，虽图示中仅显示与本公开实施例中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
本公开实施例根据一些实施例，提供一种半导体结构的制备方法。
请参阅图1，在一些实施例中，所述半导体结构的制备方法可以包括如下的步骤：
S100：提供基底。
S200：于基底内形成多个间隔排布的电容接触结构；电容接触结构包括凸出于基底的上表面。
S300：形成隔离结构填充相邻电容接触结构之间的间隙，隔离结构的顶面不高于电容接触结构的顶面。
S400：形成隔离凹槽；隔离凹槽由隔离结构的顶面延伸至隔离结构内，且与电容接触结构具有间距。
上述实施例提供的半导体结构的制备方法，通过在相邻电容接触结构之间的间隙填充隔离结构的设计，避免相邻电容接触结构之间发生短路的问题。在电容接触结构的制备过程中，用于形成电容接触结构的电容接触材料很容易被氧化，并在相邻电容接触结构之间残留副产物，使相邻电容接触结构相互干扰，造成短路。然而，本公开实施例提供的半导体结构的制备方法还通过形成由隔离结构顶面延伸至隔离结构内的隔离凹槽，避免由于电容接触材料的副产物残留在相邻电容接触结构之间而导致相邻电容接触结构相互干扰，造成短路的问题。后续在此之上形成的电容也不会相互干扰，因此，本公开实施例提供的半导体结构的制备方法能够提升电容的生产良率及使用可靠性，从而提升半导体结构的生产良率及电学性能。
在一些实施例中，多个电容接触结构呈多行多列分布，位于同一列的多个电容接触结构沿第一方向间隔排布，位于同一行的多个电容接触结构沿第二方向间隔排布，第二方向与第一方向相交。
请参阅图2，在一些实施例中，步骤S400形成隔离凹槽，可以包括如下的步骤：
S410：于电容接触结构及隔离结构上形成第一图形化掩膜层；第一图形化掩膜层包括多个平行间隔排布的第一掩膜图形，第一掩膜图形沿第一方向延伸，且相邻第一掩膜图形之间的间隙于基底上表面的正投影位于相邻两列电容接触结构之间。
S420：基于第一图形化掩膜层刻蚀隔离结构，以形成多个间隔排布的第一隔离凹槽；第一隔离凹槽沿第一方向延伸，且位于相邻两列电容接触结构之间。
请参阅图3，在一些实施例中，步骤S410于基底上形成第一图形化掩膜层，可以包括如下的步骤：
S411：于电容接触结构及隔离结构上形成第一掩膜层。
S412：于第一掩膜层的上表面形成多个平行间隔排布且沿第一方向延伸的第一子掩膜图形。
S413：于第一子掩膜图形的侧壁形成第一牺牲图形，去除第一子掩膜图形，以保留多个平行间隔排布且沿第一方向延伸的第一牺牲图形。
S414：形成第一填充掩膜层；第一填充掩膜层填充满相邻第一牺牲图形之间的间隙，且第一填充掩膜层的上表面不高于第一牺牲图形的上表面。
S415：去除第一牺牲图形，以在相邻第一填充掩膜层之间形成第一初始沟槽。
S416：沿第一初始沟槽刻蚀第一掩膜层，以得到第一图形化掩膜层。
请参阅图4，在一些实施例中，步骤S400形成隔离凹槽，还可以包括如下的步骤：
S430：于电容接触结构及隔离结构上形成第二图形化掩膜层；第二图形化掩膜层包括多个平行间隔排布的第二掩膜图形，第二掩膜图形沿第二方向延伸，第二方向与第一方向相交，相邻第二掩膜图形之间的间隙于基底上表面的正投影位于相邻两行电容接触结构之间。
S440：基于第二图形化掩膜层刻蚀隔离结构，以形成多个间隔排布的第二隔离凹槽；第二隔离凹槽沿第二方向延伸，且位于相邻两行电容接触结构之间，并贯通多个第一隔离凹槽。
在一些实施例中，在步骤S400形成隔离凹槽之后，还包括于基底上形成多个电容结构的步骤。电容结构与电容接触结构一一对应接触。
在一些实施例中，在步骤S400形成隔离凹槽之前，还包括在隔离结构的上表面形成第一支撑层的步骤。
请参阅图5，在一些实施例中，在步骤S400形成隔离凹槽之后，可以采用如下的步骤形成多个电容结构，包括：
S511：于隔离结构的上表面形成第一支撑层；第一支撑层覆盖电容接触结构的顶面，且隔离凹槽沿厚度方向贯穿第一支撑层。
S512：在形成隔离凹槽之后，于第一支撑层上形成第一电容牺牲层；第一电容牺牲层填满隔离凹槽。
S513：于第一电容牺牲层的上表面形成第二支撑层。
S514：于第二支撑层的上表面形成第二电容牺牲层。
S515：于第二电容牺牲层的上表面形成第三支撑层。
S516：形成多个电容孔；电容孔贯穿第三支撑层、第二电容牺牲层、第二支撑层、第一电容牺牲层及第一支撑层，以暴露出电容接触结构。
S517：于电容孔的侧壁及底部形成下电极。
S518：去除第一电容牺牲层及第二电容牺牲层。
S519：于下电极的表面及隔离凹槽内形成电容介质层。
S520：于电容介质层的表面形成上电极。
为了更清楚的说明本公开实施例中的制备方法，以下请结合图6至图22解本公开实施例的一些实施例。
在步骤S100中，提供基底。
本公开实施例对于基底的材质并不做具体限定。作为示例，基底的材质可以包括但不仅限于硅(Si)、锗(Ge)、锗硅(SiGe)或碳化硅(SiC)等或其组合。
请参阅图6，在步骤S200中，于基底(图6中未示出)内形成多个间隔排布的电容接触结构100。如图6所示，电容接触结构100的上表面可以凸出于基底的上表面。
本公开实施例对于电容接触结构100的材质并不做具体限定。作为示例，电容接触结构100的材质可以包括但不限于钨(W)或铜(Cu)等相关半导体导电材料。
在一些实施例中，可以在电容接触结构100至少一侧的侧壁上形成侧壁介质层110。
在上述实施例提供的制备方法中，可以通过形成侧壁介质层110阻止电容接触结构100在高温环境中扩散而导致相邻电容接触结构100之间相互干扰，出现短路，避免后续在此之上形成的相邻电容之间出现短路，进一步提升制备方法所得产品的生产良率及使用可靠性。
本公开实施例对于侧壁介质层110的材质并不做具体限定。作为示例，侧壁介质层110的材 质可以包括但不仅限于金属硅化物。
请继续参阅图6，在步骤S300中，形成隔离结构200填充相邻电容接触结构100之间的间隙。如图6所示，隔离结构200的顶面不高于电容接触结构100的顶面，以使得电容接触结构100的顶面得以露出。
在本公开实施例中，可以通过在相邻电容接触结构100之间的间隙填充隔离结构200，使相邻电容接触结构100之间绝缘以避免发生短路。
本公开实施例对于隔离结构200的材质并不做具体限定。作为示例，隔离结构200的材质可以包括但不限于单晶硅、多晶硅、二氧化硅(SiO 2)或氮化硅(SiN)等绝缘材料。
请参阅图7至图12，在步骤S400中，形成隔离凹槽300。隔离凹槽300由隔离结构200的顶面延伸至隔离结构200内，且与电容接触结构100具有间距。
根据图12，可见在本公开实施例中，隔离凹槽300能够有效地截断相邻电容接触结构100之间残留的电容接触材料100a。如此，残留的电容接触材料100a则不会导致相邻电容接触结构100相互干扰，造成短路。后续在此之上形成的电容也不会相互干扰。
在一些实施例中，多个电容接触结构100呈多行多列分布，位于同一列的多个电容接触结构100沿第一方向间隔排布，位于同一行的多个电容接触结构100沿第二方向间隔排布。
在本公开实施例中，第二方向与第一方向相交。
在一些实施例中，步骤S400形成的隔离凹槽300可以包括多个间隔排布的第一隔离凹槽。
作为示例，步骤S400具体可以包括如下的步骤S410至S420，以形成第一隔离凹槽。
在步骤S410中，请参阅图7至图12，于电容接触结构100及隔离结构200上形成第一图形化掩膜层310。
第一图形化掩膜层310可以包括多个平行间隔排布的第一掩膜图形。第一掩膜图形沿第一方向延伸，且相邻第一掩膜图形之间的间隙于基底上表面的正投影应当位于相邻两列电容接触结构100之间。
在步骤S420中，请继续参阅图7至图12，基于第一图形化掩膜层310刻蚀隔离结构200，以形成多个间隔排布的第一隔离凹槽。
第一隔离凹槽沿第一方向延伸，且位于相邻两列电容接触结构100之间。
在一些实施例中，步骤S400形成的隔离凹槽300还可以包括多个间隔排布的第二隔离凹槽。
在一些实施例中，步骤S400具体还可以包括如下的步骤S430至S440，以形成第二隔离凹槽。
在步骤S430中，于电容接触结构100及隔离结构200上形成第二图形化掩膜层。
第二图形化掩膜层可以包括多个平行间隔排布的第二掩膜图形，第二掩膜图形沿第二方向延伸，第二方向与第一方向相交，相邻第二掩膜图形之间的间隙于基底上表面的正投影位于相邻两行电容接触结构100之间。
在步骤S440中，基于第二图形化掩膜层刻蚀隔离结构200，以形成多个间隔排布的第二隔离凹槽。
第二隔离凹槽沿第二方向延伸，且位于相邻两行电容接触结构100之间，并贯通多个第一隔离凹槽。
在一些实施例中，可以在形成第一图形化掩膜层310之后，形成第二图形化掩膜层。
需要说明的是，在本公开实施例中，形成第一隔离凹槽的步骤与形成第二隔离凹槽的步骤并无顺序上的限制，也即二者任一在先执行或同时执行，均是允许的。
作为示例，第一图形化掩膜层310及第二图形化掩膜层的材质均可以包括但不仅限于氮氧化硅(SiO 2)。
在一些实施例中，可以采用如下的方式形成第一隔离凹槽及第二隔离凹槽。比如：
在形成第一图形化掩膜层310及第二图形化掩膜层之前，形成图形转移材料层。在刻蚀隔离结构200之前，将第一掩膜图形及第二掩膜图形转移至所述图形转移材料层，以形成图形转移层。
基于第一图形化掩膜层310、第二图形化掩膜层及所述图形转移层刻蚀隔离结构200，以形成多个间隔排布的第一隔离凹槽及第二隔离凹槽。
作为示例，步骤S410具体可以包括如下的步骤S411至S416。
在步骤S411中，如图7中的(a)图及图7中的(b)图所示，于电容接触结构100及隔离结构200上形成第一掩膜层311。
在步骤S412中，如图7中的(a)图及图7中的(b)图所示，于第一掩膜层311的上表面形成多个平行间隔排布且沿第一方向延伸的第一子掩膜图形312。
在步骤S413中，于第一子掩膜图形312的侧壁形成第一牺牲图形314；去除第一子掩膜图形312，如图8中的(a)图及图8中的(b)图所示，保留多个平行间隔排布且沿第一方向延伸的第一牺牲图形314。
在步骤S414中，如图9至图10所示，形成第一填充掩膜层316；第一填充掩膜层316填充满相邻第一牺牲图形314之间的间隙，且第一填充掩膜层316的上表面不高于第一牺牲图形314的上表面。
在步骤S415中，如图11中的(a)图及图11中的(b)图所示，去除第一牺牲图形314，以在相邻第一填充掩膜层316之间形成第一初始沟槽317。
在步骤S416中，如图12所示，沿第一初始沟槽317刻蚀第一掩膜层311，以得到第一图形化掩膜层310。
本公开实施例对于步骤S412中形成的第一子掩膜图形312的材质并不做具体限定。作为示例，第一子掩膜图形312的材质可以包括但不仅限于光刻胶。
对于步骤S413，在一些实施例中，可以采用如下的步骤形成第一牺牲图形314。包括：
如图7中的(a)图所示，于相邻第一子掩膜图形312之间暴露的第一掩膜层311的上表面、第一子掩膜图形312的侧壁及第一子掩膜图形312的顶部形成第一牺牲材料层313。
如图7中的(b)图所示，去除位于相邻第一子掩膜图形312之间暴露的第一掩膜层311的上表面及位于第一子掩膜图形312的顶部的第一牺牲材料层313，保留于第一子掩膜图形312的侧壁的第一牺牲材料层313即为第一牺牲图形314。
作为示例，第一牺牲图形314的材质可以包括但不仅限于氧化物。
本公开实施例对于上述步骤中去除部分的第一牺牲材料层313的方式并不做具体限定。作为示例，可以采用四氟化碳(又称四氟甲烷，化学式为CF 4)气体或全氟丁二烯(C 4F 6)气体刻蚀去除部分的第一牺牲材料层313。
在步骤S413与步骤S414之间，还可以包括去除第一子掩膜图形312的步骤。
作为示例，可以但不仅限于采用氧气(O 2)等离子体或二氧化硅进行干洗的方式去除第一子掩膜图形312。
对于步骤S414，在一些实施例中，可以采用如下的步骤形成第一填充掩膜层316。包括：
如图9所示，于第一掩膜层311上形成第一填充材料层315。第一填充材料层315至少应当填 充满相邻第一牺牲图形314之间的间隙。可选的，第一填充材料层315还可以覆盖第一牺牲图形314。
如图10中的(a)图及图10中的(b)图所示，回刻第一填充材料层315，以去除第一牺牲图形314顶部的第一填充材料层315，并保留位于相邻第一牺牲图形314之间的第一填充材料层315即为第一填充掩膜层316。
本公开实施例对于步骤S415中去除第一牺牲图形314的方式并不做具体限定。作为示例，可以采用湿法刻蚀工艺去除第一牺牲图形314。
本公开实施例对于上述步骤中形成的第一填充掩膜层316的材质并不做具体限定。作为示例，第一填充掩膜层316的材质可以包括但不仅限于碳化物(Carbon)。
可以理解，在本公开实施例中，步骤S430形成第二图形化掩膜层的方式可以参照前述形成第一图形化掩膜层310的步骤，此处不再赘述。
请参阅图13中的(a)图及图13中的(b)图，在一些实施例中，可以在形成隔离凹槽300之后去除第一图形化掩膜层310和第一填充掩膜层316。
请参阅图14至图22，在一些实施例中，可以在步骤S400形成隔离凹槽300之后，于基底上形成多个电容结构400。
如图22所示，电容结构400可以与电容接触结构100一一对应接触。
作为示例，形成电容结构400具体可以包括如下的步骤S511至S520。
在步骤S511中，请参阅图13，于隔离结构200的上表面形成第一支撑层411，第一支撑层411覆盖电容接触结构100的顶面，且隔离凹槽300贯穿第一支撑层411。
在步骤S512中，请参阅图14，于第一支撑层411上形成第一电容牺牲层421，第一电容牺牲层421填满隔离凹槽300。
在步骤S513中，请继续参阅图14，于第一电容牺牲层421的上表面形成第二支撑层412。
在步骤S514中，请继续参阅图14，于第二支撑层412的上表面形成第二电容牺牲层422。
在步骤S515中，请继续参阅图14，于第二电容牺牲层422的上表面形成第三支撑层413。
在步骤S516中，请参阅图15，形成多个电容孔430。电容孔430贯穿第三支撑层413、第二电容牺牲层422、第二支撑层412、第一电容牺牲层421及第一支撑层411，以暴露出电容接触结构100。
在步骤S517中，请参阅图16，于电容孔430的侧壁及底部形成下电极440。
在步骤S518中，请参阅图17至图21，去除第一电容牺牲层421及第二电容牺牲层422。
在步骤S519中，请参阅图22，于下电极440的表面及隔离凹槽300内形成电容介质层450。
在步骤S520中，请参阅图22，于电容介质层450的表面形成上电极460。
为了便于描述，在本公开实施例中，将下电极440位于第三支撑层413上方的表面称为下电极440的顶面。
在一些实施例中，步骤S511具体可以包括如下的步骤。比如：
如图6至图11所示，在形成隔离凹槽300之前，在隔离结构200的上表面形成第一支撑材料层411a。第一支撑材料层411a覆盖电容接触结构100的顶面。
如图12至图13所示，在形成隔离凹槽300的过程中，隔离凹槽300贯穿第一支撑材料层411a。保留的第一支撑材料层411a作为第一支撑层411。
本公开实施例对于步骤S511中形成的第一支撑层411及步骤S513中形成的第二支撑层412 的材质均不做具体限定。
在一些实施例中，第一支撑层411的材质及第二支撑层412的材质均包括氮化硅。
本公开实施例对于步骤S512中形成的第一电容牺牲层421及步骤S514中形成的第二电容牺牲层422的材质均不做具体限定。
作为示例，第一电容牺牲层421的材质可以包括但不限于磷硅玻璃(简称PSG)或硼磷硅玻璃(简称BPSG)等等。
作为示例，第二电容牺牲层422的材质可以包括但不限于氧化物。
本公开实施例对于上述步骤中形成的下电极440、电容介质层450及上电极460的材质均不做具体限定。
作为示例，下电极440的材质可以包括但不限于金属氮化物及金属硅化物中的一种或两种所形成的化合物。
作为示例，电容介质层450的材质可以包括但不限于氧化锆(ZrO x)、氧化铪(HfO x)、氧化钛锆(ZrTiO x)、氧化钌(RuO x)、氧化锑(SbO x)、氧化铝(AlO x)或其组合。
作为示例，上电极460的材质可以包括但不仅限于多晶硅。
在一些实施例中，步骤S518具体可以包括如下的步骤。比如：
如图17所示，形成掩膜叠层510。掩膜叠层510覆盖下电极440的顶面，且封闭电容孔430。
请继续参阅图17，在掩膜叠层510的上表面形成光刻胶层520，并对光刻胶层520进行图形化处理，以于光刻胶层520上形成光刻胶图案520a，光刻胶图案520a暴露出部分掩膜叠层510的上表面。
基于光刻胶层520刻蚀掩膜叠层510，使掩膜叠层510内形成多个开口，所述开口暴露出部分的第三支撑层413。如图18所示，去除下电极440的顶面，并将所述开口的图案转移至第三支撑层413中，形成电容打开孔530。电容打开孔530暴露出部分第二电容牺牲层422。
如图19所示，去除第二电容牺牲层422，以露出第二支撑层412。
如图20所示，将电容打开孔530的图案转移至第二支撑层412，以暴露出部分第一电容牺牲层421。
如图21所示，去除第一电容牺牲层421，以露出第一支撑层411。
本公开实施例对于掩膜叠层510的结构并不做具体限定。
请继续参阅图17，在一些实施例中，掩膜叠层510可以包括由下至上依次叠置的第一掩膜材料层511、第二掩膜材料层512及第三掩膜材料层513。
作为示例，第一掩膜材料层511可以包括但不仅限于二氧化硅层；第二掩膜材料层512可以包括但不限于晶体碳层或非晶碳层等等；第三掩膜材料层513可以包括但不仅限于氮氧化硅层。
本公开实施例对于去除第二电容牺牲层422及去除第一电容牺牲层421的方式亦不做具体限定。
作为示例，可以采用如下的步骤去除第二电容牺牲层422，比如：
在电容打开孔530暴露出部分第二电容牺牲层422之后，通过电容打开孔530向第二电容牺牲层422注入酸液，采用酸液溶解去除第二电容牺牲层422。
作为示例，可以采用如下的步骤去除第一电容牺牲层421，比如：
在电容打开孔530的图案转移至第二支撑层412，暴露出部分第一电容牺牲层421之后，向第一电容牺牲层421注入酸液，采用酸液溶解去除第一电容牺牲层421。
在一些实施例中，上电极460之间具有间隙。
作为示例，请继续参阅图22，在步骤S520形成上电极460之后，还可以包括形成填充导电层470的步骤。
填充导电层470至少可以填满上电极460之间，在本公开实施例的间隙。
应该理解的是，虽然图1至图5的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图1至图5中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
本公开实施例还根据一些实施例，提供一种半导体结构。
请继续参阅图22，在一些实施例中，所述半导体结构可以包括基底、隔离结构200及隔离凹槽300。
其中，基底上形成有多个间隔排布的电容接触结构100。隔离结构200位于基底上，且位于相邻电容接触结构100之间；隔离结构200的顶面应当不高于电容接触结构100的顶面。隔离凹槽300由隔离结构200顶面延伸至隔离结构200内，且隔离凹槽300与电容接触结构100之间具有间距。
在上述实施例提供的半导体结构中，通过在相邻电容接触结构100之间设置隔离结构200，避免相邻电容接触结构100之间发生短路的问题。在电容接触结构100的制备过程中，用于形成电容接触结构100的电容接触材料很容易被氧化，并在相邻电容接触结构100之间残留副产物，使相邻电容接触结构100相互干扰，造成短路。然而，本公开实施例提供的半导体结构还通过设置由隔离结构200顶面延伸至隔离结构200内的隔离凹槽300，避免由于电容接触材料的副产物残留在相邻电容接触结构100之间而导致相邻电容接触结构100相互干扰，造成短路的问题。后续在此之上形成的电容也不会相互干扰，因此，本公开实施例提供的半导体结构能够提升电容的生产良率及使用可靠性，从而提升半导体结构的生产良率及电学性能。
在一些实施例中，隔离凹槽300可以包括多个间隔排布的第一隔离凹槽。第一隔离凹槽沿第一方向延伸，且位于相邻两列电容接触结构100之间。
在一些实施例中，隔离凹槽300还可以包括多个间隔排布的第二隔离凹槽。第二隔离凹槽沿第二方向延伸，且位于相邻两行电容接触结构100之间，并贯通多个第一隔离凹槽。
在一些实施例中，所述半导体结构还可以包括多个电容结构400。电容结构400位于基底上，且与电容接触结构100一一对应接触。
在一些实施例中，所述半导体结构还可以还包括支撑结构。
请继续参阅图22，支撑结构可以包括由下至上依次间隔叠置的第一支撑层411、第二支撑层412及第三支撑层413(图22中未示出)。支撑结构内设有多个贯穿第一支撑层411、第二支撑层412及第三支撑层413的电容孔430，电容孔430与电容接触结构100一一对应设置，且电容孔430暴露出电容接触结构100。
此时，隔离凹槽300还沿厚度方向贯穿第一支撑层411。
在一些实施例中，请继续参阅图22，电容结构400可以包括下电极440、电容介质层450及上电极460。
其中，下电极440位于电容孔430的侧壁及底部，与第一支撑层411、第二支撑层412及第三支撑层413均相连接，并与电容接触结构100相接触。电容介质层450位于下电极440的表面及隔离凹槽300内。上电极460位于电容介质层450的表面。
在一些实施例中，请继续参阅图22，上电极460之间还具有间隙。
在一些实施例中，请继续参阅图22，电容结构400还可以包括填充导电层470。填充导电层470可以填充于上电极460之间的间隙内。
作为示例，填充导电层470与上电极460电连接，以与电容结构400上面的金属互连线实现连接。
需要说明的是，本公开实施例中的半导体结构的制备方法均可用于制备对应的半导体结构，故而方法实施例与结构实施例之间的技术特征，在不产生冲突的前提下可以相互替换及补充，以使得本领域技术人员能够获悉本公开实施例的技术内容。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开实施例的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开实施例构思的前提下，还可以做出若干变形和改进，这些都属于本公开实施例的保护范围。因此，本公开实施例专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种半导体结构，包括：
    基底；所述基底上形成有多个间隔排布的电容接触结构；
    隔离结构；所述隔离结构位于所述基底上，且位于相邻所述电容接触结构之间；所述隔离结构的顶面不高于所述电容接触结构的顶面；
    隔离凹槽；所述隔离凹槽由所述隔离结构顶面延伸至所述隔离结构内，且所述隔离凹槽与所述电容接触结构之间具有间距。
  2. 根据权利要求1所述的半导体结构，其中，多个所述电容接触结构呈多行多列的阵列分布，位于同一列的多个所述电容接触结构沿第一方向间隔排布，位于同一行的多个所述电容接触结构沿第二方向间隔排布，所述第二方向与所述第一方向相交；
    所述隔离凹槽包括多个间隔排布的第一隔离凹槽，所述第一隔离凹槽沿所述第一方向延伸，且位于相邻两列所述电容接触结构之间。
  3. 根据权利要求2所述的半导体结构，其中，所述隔离凹槽包括多个间隔排布的第二隔离凹槽，所述第二隔离凹槽沿所述第二方向延伸，且位于相邻两行所述电容接触结构之间，并贯通多个所述第一隔离凹槽。
  4. 根据权利要求1至3中任一项所述的半导体结构，其中，还包括多个电容结构，所述电容结构位于所述基底上，且与所述电容接触结构一一对应接触。
  5. 根据权利要求4所述的半导体结构，其中，还包括支撑结构，所述支撑结构包括由下至上依次间隔叠置的第一支撑层、第二支撑层及第三支撑层；所述支撑结构内设有多个贯穿所述第一支撑层、所述第二支撑层及所述第三支撑层的电容孔，所述电容孔与所述电容接触结构一一对应设置，且所述电容孔暴露出所述电容接触结构；
    所述隔离凹槽还沿厚度方向贯穿所述第一支撑层；
    所述电容结构包括：
    下电极；所述下电极位于所述电容孔的侧壁及底部，与所述第一支撑层、所述第二支撑层及所述第三支撑层均相连接，并与所述电容接触结构相接触；
    电容介质层；所述电容介质层位于所述下电极的表面及所述隔离凹槽内；
    上电极；所述上电极位于所述电容介质层的表面。
  6. 根据权利要求5所述的半导体结构，其中，所述上电极之间还具有间隙；所述电容结构还包括：
    填充导电层；所述填充导电层填充于所述间隙内。
  7. 一种半导体结构的制备方法，其中，包括：
    提供基底；
    于所述基底内形成多个间隔排布的电容接触结构；所述电容接触结构包括凸出于所述基底的上表面；
    形成隔离结构填充相邻所述电容接触结构之间的间隙，所述隔离结构的顶面不高于所述电容接触结构的顶面；
    形成隔离凹槽；所述隔离凹槽由所述隔离结构的顶面延伸至所述隔离结构内，且与所述电容接触结构具有间距。
  8. 根据权利要求7所述的半导体结构的制备方法，其中，多个所述电容接触结构呈多行多列分 布，位于同一列的多个所述电容接触结构沿第一方向间隔排布，位于同一行的多个所述电容接触结构沿第二方向间隔排布，所述第二方向与所述第一方向相交；
    所述形成隔离凹槽，包括：
    于所述电容接触结构及所述隔离结构上形成第一图形化掩膜层；所述第一图形化掩膜层包括多个平行间隔排布的第一掩膜图形，所述第一掩膜图形沿第一方向延伸，且相邻所述第一掩膜图形之间的间隙于所述基底上表面的正投影位于相邻两列所述电容接触结构之间；
    基于所述第一图形化掩膜层刻蚀所述隔离结构，以形成多个间隔排布的第一隔离凹槽；所述第一隔离凹槽沿所述第一方向延伸，且位于相邻两列所述电容接触结构之间。
  9. 根据权利要求8所述的半导体结构的制备方法，其中，所述于所述基底上形成第一图形化掩膜层，包括：
    于所述电容接触结构及所述隔离结构上形成第一掩膜层；
    于所述第一掩膜层的上表面形成多个平行间隔排布且沿所述第一方向延伸的第一子掩膜图形；
    于所述第一子掩膜图形的侧壁形成第一牺牲图形，去除所述第一子掩膜图形，以保留多个平行间隔排布且沿所述第一方向延伸的所述第一牺牲图形；
    形成第一填充掩膜层；所述第一填充掩膜层填充满相邻所述第一牺牲图形之间的间隙，且所述第一填充掩膜层的上表面不高于所述第一牺牲图形的上表面；
    去除所述第一牺牲图形，以在相邻所述第一填充掩膜层之间形成第一初始沟槽；
    沿所述第一初始沟槽刻蚀所述第一掩膜层，以得到所述第一图形化掩膜层。
  10. 根据权利要求9所述的半导体结构的制备方法，其中，所述于所述第一子掩膜图形的侧壁形成第一牺牲图形，包括：
    于相邻所述第一子掩膜图形之间暴露的所述第一掩膜层的上表面、所述第一子掩膜图形的侧壁及所述第一子掩膜图形的顶部形成第一牺牲材料层；
    去除位于相邻所述第一子掩膜图形之间暴露的所述第一掩膜层的上表面及位于所述第一子掩膜图形的顶部的所述第一牺牲材料层，保留于所述第一子掩膜图形的侧壁的所述第一牺牲材料层即为所述第一牺牲图形。
  11. 根据权利要求9所述的半导体结构的制备方法，其中，所述形成第一填充掩膜层，包括：
    于所述第一掩膜层上形成第一填充材料层；所述第一填充材料层填充满相邻所述第一牺牲图形之间的间隙，并覆盖所述第一牺牲图形；
    回刻所述第一填充材料层，以去除所述第一牺牲图形顶部的所述第一填充材料层，并保留位于相邻所述第一牺牲图形之间的所述第一填充材料层即为所述第一填充掩膜层。
  12. 根据权利要求8所述的半导体结构的制备方法，其中，所述形成隔离凹槽，还包括：
    于所述电容接触结构及所述隔离结构上形成第二图形化掩膜层；所述第二图形化掩膜层包括多个平行间隔排布的第二掩膜图形，所述第二掩膜图形沿第二方向延伸，所述第二方向与所述第一方向相交，相邻所述第二掩膜图形之间的间隙于所述基底上表面的正投影位于相邻两行所述电容接触结构之间；
    基于所述第二图形化掩膜层刻蚀所述隔离结构，以形成多个间隔排布的第二隔离凹槽；所述第二隔离凹槽沿所述第二方向延伸，且位于相邻两行所述电容接触结构之间，并贯通多个所述第一隔离凹槽。
  13. 根据权利要求12所述的半导体结构的制备方法，其中，所述形成隔离凹槽，在所述电容接触结构及所述隔离结构上形成所述第一图形化掩膜层及所述第二图形化掩膜层之前，还包括：形成图形转移材料层；
    在刻蚀所述隔离结构之前，将所述第一掩膜图形及所述第二掩膜图形转移至所述图形转移材料层，以形成图形转移层；
    基于所述第一图形化掩膜层、所述第二图形化掩膜层及所述图形转移层刻蚀所述隔离结构，以形成多个间隔排布的第一隔离凹槽及第二隔离凹槽。
  14. 根据权利要求7至13中任一项所述的半导体结构的制备方法，其中，所述形成隔离凹槽之后，还包括：
    于所述基底上形成多个电容结构，所述电容结构与所述电容接触结构一一对应接触。
  15. 根据权利要求14所述的半导体结构的制备方法，其中，于所述基底上形成多个电容结构包括：
    于所述隔离结构的上表面形成第一支撑层；所述第一支撑层覆盖所述电容接触结构的顶面，且所述隔离凹槽沿厚度方向贯穿所述第一支撑层；
    在形成所述隔离凹槽之后，于所述第一支撑层上形成第一电容牺牲层；所述第一电容牺牲层填满所述隔离凹槽；
    于所述第一电容牺牲层的上表面形成第二支撑层；
    于所述第二支撑层的上表面形成第二电容牺牲层；
    于所述第二电容牺牲层的上表面形成第三支撑层；
    形成多个电容孔；所述电容孔贯穿所述第三支撑层、所述第二电容牺牲层、所述第二支撑层、所述第一电容牺牲层及所述第一支撑层，以暴露出所述电容接触结构；
    于所述电容孔的侧壁及底部形成下电极；
    去除所述第一电容牺牲层及所述第二电容牺牲层；
    于所述下电极的表面及所述隔离凹槽内形成电容介质层；
    于所述电容介质层的表面形成上电极。
  16. 根据权利要求15所述的半导体结构的制备方法，其中，所述上电极之间具有间隙；所述形成上电极之后，还包括：
    形成填充导电层，所述填充导电层至少填满所述间隙。
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CN209029380U (zh) * 2018-09-30 2019-06-25 长鑫存储技术有限公司 一种半导体结构
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CN113394162A (zh) * 2020-03-12 2021-09-14 长鑫存储技术有限公司 电容阵列结构及其形成方法
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CN209029380U (zh) * 2018-09-30 2019-06-25 长鑫存储技术有限公司 一种半导体结构
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