WO2024040701A1 - 图案化方法 - Google Patents
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- WO2024040701A1 WO2024040701A1 PCT/CN2022/124238 CN2022124238W WO2024040701A1 WO 2024040701 A1 WO2024040701 A1 WO 2024040701A1 CN 2022124238 W CN2022124238 W CN 2022124238W WO 2024040701 A1 WO2024040701 A1 WO 2024040701A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/696—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
- H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
- H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
- H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
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- H—ELECTRICITY
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- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/0698—Local interconnections
Definitions
- the embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a patterning method.
- a target pattern on a substrate, for example, etching a trench into the substrate to define an active area.
- a multi-patterning process is usually used to form the target pattern.
- the above-mentioned multiple patterning processes include but are not limited to Self-Aligned Double Patterning (SADP) process, Reverse Self-Aligned Double Patterning (R-SADP) process and Self-Aligned Quadruple Patterning (SAQP) process, etc.
- the formed target pattern is prone to odd-even effects, thereby affecting the performance of the formed semiconductor device.
- An embodiment of the present disclosure provides a patterning method, which includes:
- the first mask layer includes a compensation material layer and a first hard mask material layer located on the compensation material layer;
- first mask layer Patterning the first mask layer to form a plurality of first mandrel structures spaced apart along a first direction, wherein a first groove is formed between two adjacent first mandrel structures, each The first mandrel structure includes a compensation layer and a first hard mask layer;
- a sacrificial material layer Forming a sacrificial material layer, wherein the sacrificial material layer conformally covers the top surface and sidewalls of the plurality of first mandrel structures and the portion of the substrate exposed by the first trench; the sacrificial material layer forming a second trench within the first trench;
- the plurality of second mandrel structures are connected to the plurality of second mandrel structures.
- the first mandrel structures are alternately arranged at intervals along the first direction; wherein the remaining second hard mask material layer constitutes a second hard mask layer, and the remaining sacrificial material layer includes a a first sacrificial layer on the sidewall of a mandrel and a second sacrificial layer located below the second hard mask layer; the second mandrel structure includes a second sacrificial layer and a second hard mask layer;
- the thickness of the first mandrel structure and the thickness of the second mandrel structure are equal in a direction perpendicular to the plane of the substrate.
- the etching time used to completely etch away the first mandrel structure is equal to the etching time used to completely etch away the second mandrel structure. Time is equal.
- the second sacrificial layer and the compensation layer are made of the same material, and the thicknesses of the second sacrificial layer and the compensation layer are equal;
- the second hard mask layer and the first hard mask layer are made of the same material, and the second hard mask layer and the first hard mask layer have the same thickness.
- the second sacrificial layer and the compensation layer are made of the same material, and the thicknesses of the second sacrificial layer and the compensation layer are unequal;
- the second hard mask layer and the first hard mask layer are made of the same material, and the thicknesses of the second hard mask layer and the first hard mask layer are not equal.
- the materials of the second sacrificial layer and the compensation layer are different, and the thicknesses of the second sacrificial layer and the compensation layer are equal;
- the materials of the second hard mask layer and the first hard mask layer are different, and the thicknesses of the second hard mask layer and the first hard mask layer are equal.
- the second sacrificial layer and the compensation layer are made of the same material, and the thicknesses of the second sacrificial layer and the compensation layer are unequal;
- the second hard mask layer and the first hard mask layer are made of different materials, and the thicknesses of the second hard mask layer and the first hard mask layer are not equal.
- the second sacrificial layer and the compensation layer are made of different materials, and the thicknesses of the second sacrificial layer and the compensation layer are not equal;
- the second hard mask layer and the first hard mask layer are made of the same material, and the thicknesses of the second hard mask layer and the first hard mask layer are not equal.
- the widths of the first mandrel structure and the second mandrel structure are equal in the first direction.
- the center distance of two adjacent first mandrel structures is twice the center distance of the adjacent first mandrel structure and the second mandrel structure.
- the step of providing a substrate includes:
- a layer to be patterned and an etching stop layer are sequentially stacked on the substrate to obtain the substrate.
- patterning the first mask layer includes:
- the step of removing the first sacrificial layer between the adjacent first mandrel structure and the second mandrel structure includes:
- the remaining etching stop layer is removed to form a plurality of third mandrel structures spaced apart along the first direction in the remaining substrate.
- the thicknesses of the plurality of third mandrel structures are equal in a direction perpendicular to the plane of the substrate.
- the widths of adjacent third mandrel structures are equal, and the center distances of adjacent third mandrel structures are equal.
- the first mandrel structure includes a stacked compensation layer and a first hard mask layer; compared with the first mandrel structure in the related art, the first hard mask layer A compensation layer is added on the basis of the second layer, and the compensation layer is used to compensate for the difference in etching time used to etch the first mandrel structure and the second mandrel structure, so as to ensure that the first mandrel structure is completely etched away.
- the time is equal to the etching time used to completely etch away the second mandrel structure.
- the target pattern formed when patterning the substrate will basically not appear. Odd-even effect.
- Figure 1 is a process flow diagram of a patterning method provided by an embodiment of the present disclosure
- Figure 2 is a schematic diagram of forming a first mask layer in the patterning method provided by an embodiment of the present disclosure
- Figure 3 is a schematic diagram after patterning the first mask layer in the patterning method provided by the embodiment of the present disclosure
- Figure 4 is a schematic diagram after forming a sacrificial material layer in the patterning method provided by an embodiment of the present disclosure
- Figure 5 is a schematic diagram after forming a second hard mask material layer in the patterning method provided by an embodiment of the present disclosure
- Figure 6 is a schematic diagram after etching back the sacrificial material layer and the second hard mask material layer in the patterning method provided by the embodiment of the present disclosure
- Figure 7 is a schematic diagram after forming the first mandrel structure and the second mandrel structure in the patterning method provided by the embodiment of the present disclosure
- FIG. 8 is a schematic diagram after patterning the substrate in the patterning method provided by the embodiment of the present disclosure.
- 100 Base; 110: Substrate; 120: Layer to be patterned; 130: Etching stop layer;
- 200 first mask layer; 210: compensation material layer; 220: first hard mask material layer;
- 500 first mandrel structure
- 510 compensation layer
- 520 first hard mask layer
- 530 anti-reflection layer
- 540 first trench
- 610 sacrificial material layer
- 620 second trench
- 630 first sacrificial layer
- 640 second sacrificial layer
- 700 second hard mask layer
- 710 second hard mask material layer
- 800 Second mandrel structure
- 810 Third groove
- the formed target pattern is prone to odd-even effects.
- the target pattern is an active pillar and the thickness (that is, the height) of the formed active pillar has an odd-even effect.
- a first material layer is formed on the layer to be patterned, and the mask layer is patterned to form a first mandrel structure.
- a sacrificial layer is formed covering the sidewalls and top surface of the first mandrel structure and the unobstructed base.
- the sacrificial layer located on the sidewall and top surface of the first mandrel structure is etched, so that the retained sacrificial layer and The second material layer serves as a second mandrel structure. Since the film layer of the second mandrel structure is different from the film layer of the first mandrel structure, there is an odd-even effect in the formed target pattern. That is, the thickness of all active pillars located at odd-numbered positions is equal, and the thickness of all active pillars located at even-numbered positions is equal, but the thickness of the active pillars located at odd-numbered positions is not equal to the thickness of the active pillars located at even-numbered positions.
- embodiments of the present disclosure provide a patterning method by designing the first mandrel structure so that the first mandrel structure includes a stacked compensation layer and a first hard mask layer; and related technologies Compared with the first mandrel structure in the method, a compensation layer is added on the basis of the first hard mask layer, and the compensation layer is used to compensate for the difference in etching time used to etch the first mandrel structure and the second mandrel structure.
- the target pattern formed when patterning the substrate is essentially free of odd-even effects.
- the first mandrel structure and the second mandrel structure are used as masks to form multiple active pillars in the substrate, the thicknesses of the multiple active pillars are equal, and there is basically no parity effect.
- Embodiments of the present disclosure provide a patterning method, which can be used to form active pillars in a memory.
- a patterning method provided by an embodiment of the present disclosure includes the following steps:
- Step S100 Provide a substrate.
- the substrate 100 can be a semiconductor substrate.
- a patterning method can be used to form active pillars in the substrate 100, and shallow trenches are formed between adjacent active pillars to facilitate the formation of shallow trenches.
- a shallow trench isolation structure (STI) is formed in the trench.
- the substrate 100 can also have other structures.
- the substrate 100 may further include a substrate 110 , a layer to be patterned 120 and an etching stop layer 130 .
- the substrate 110 is used to support the layer to be patterned 120 and the etching stop layer 130 thereon.
- the substrate 110 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, Silicon carbide (SiC) substrate, Silicon on Insulator (SOI) substrate or Germanium on Insulator (GOI) substrate, etc.
- the layer 120 to be patterned is formed on the substrate 110, where the layer 120 to be patterned can be any film layer used to form a target pattern.
- the etching stop layer 130 is formed on the surface of the layer to be patterned 120 facing away from the substrate 110 .
- an etching process with a high etching selectivity ratio can be used to pattern the first mask layer 200, which can reduce or avoid damage to the layer to be patterned 120, ensuring the accuracy of the target pattern formed by the patterning method.
- the material of the etching stop layer 130 includes silicon oxynitride, but is not limited thereto.
- both the layer to be patterned 120 and the etching stop layer 130 can be formed using, for example, a deposition process.
- a deposition process such as Chemical Vapor Deposition (CVD for short), Physical Vapor Deposition (PVD for short) or Atomic Layer Deposition (ALD for short), the layers are sequentially formed on the substrate 110
- CVD Chemical Vapor Deposition
- PVD Physical Vapor Deposition
- ALD Atomic Layer Deposition
- Step S200 Form a first mask layer on the substrate, where the first mask layer includes a compensation material layer and a first hard mask material layer located on the compensation material layer.
- a deposition process is used to form the compensation material layer 210 on the etching stop layer 130 .
- a first hard mask material layer 220 is formed on the compensation material layer 210 .
- Step S300 Pattern the first mask layer to form a plurality of first mandrel structures spaced apart along the first direction, wherein there is a first groove between two adjacent first mandrels, and each first mandrel structure
- a mandrel structure includes a compensation layer and a first hard mask layer.
- an anti-reflective material layer 300 and a photoresist layer 400 are formed on the first mask layer 200 .
- the photoresist layer 400 is patterned.
- the photoresist layer 400 is exposed using a mask plate (not shown in the figure) with a mask pattern, so as to transfer the mask pattern on the mask plate to the photoresist layer 400 .
- the photoresist layer 400 is developed and part of the photoresist layer 400 is removed to form a plurality of openings 410 in the photoresist layer 400 .
- the plurality of openings 410 are spaced apart along the first direction.
- the first direction may be the X direction in FIG. 2 .
- the material of the anti-reflective material layer 300 may include nitride.
- the material of the anti-reflective material layer 300 includes silicon nitride or silicon oxynitride, but is not limited thereto.
- the anti-reflective material layer 300 can alleviate or eliminate the standing wave effect of the photoresist layer 400, thereby increasing the accuracy of transferring the mask pattern from the mask plate to the photoresist layer 400, thereby improving the accuracy of the pattern transfer process. .
- the remaining compensation material layer 210 constitutes the compensation layer 510 .
- the retained first hard mask material layer 220 constitutes the first hard mask layer 520 .
- the retained anti-reflective material layer 300 constitutes the anti-reflective layer 530 .
- the photoresist layer 400 is removed.
- the photoresist layer 400 can be removed by cleaning with a cleaning solution or by an ashing process, so that the formed anti-reflective layer 530 is no longer covered by the photoresist layer.
- the first mandrel structure 500 includes a compensation layer 510 and a first hard mask layer stacked in a vertical direction. 520 and anti-reflective layer 530.
- the vertical direction is a direction perpendicular to the plane where the base 100 is located. That is, the Z direction in Figure 3.
- the first mandrel structure 500 includes a compensation layer 510 and a third layer 510 stacked in a vertical direction.
- a hard mask layer 520 is another example, in the step of removing at least the photoresist layer 400, the photoresist layer 400 and the anti-reflection layer 530 are removed simultaneously, then the first mandrel structure 500 includes a compensation layer 510 and a third layer 510 stacked in a vertical direction.
- a hard mask layer 520 is another example, in the step of removing at least the photoresist layer 400, the photoresist layer 400 and the anti-reflection layer 530 are removed simultaneously, then the first mandrel structure 500 includes a compensation layer 510 and a third layer 510 stacked in a vertical direction.
- a hard mask layer 520 is another example, in the step of removing at least the photoresist layer 400, the photoresist layer 400 and the anti-reflection layer 530 are removed simultaneously, then the first mandrel structure 500 includes a compensation layer
- a first groove 540 is formed between adjacent first mandrel structures 500, and the first groove 540 is used to provide an installation space for the subsequently formed second mandrel structure.
- Step S300 Form a sacrificial material layer, wherein the sacrificial material layer conformally covers the top surfaces and sidewalls of the plurality of first mandrel structures and the portions of the substrate exposed by the first trenches; the sacrificial material layer is formed around the first trenches. into the second trench.
- an atomic layer deposition process is used to form a sacrificial material layer 610 of a certain thickness on the inner wall of the first trench 540 .
- the sacrificial material layer 610 extends to the outside of the first trench 540 and covers the first mandrel.
- the sacrificial material layer 610 is not filled with the first trench 540 , so that the sacrificial material layer 610 surrounds the second trench 620 within the first trench 540 .
- Step S400 Form a second hard mask material layer, where the second hard mask material layer at least fills the second trench.
- the second hard mask material layer 710 can fill the second trench so that the top surface of the second hard mask material layer 710 is flush with the top surface of the sacrificial material layer 610 .
- the second hard mask material layer 710 can also extend outside the second trench, so that the top surface of the second hard mask material layer 710 is higher than the top surface of the sacrificial material layer 610 .
- Step S500 Etch back the second hard mask material layer and the sacrificial material layer to form a plurality of second mandrel structures spaced apart along the first direction, the plurality of second mandrel structures and the plurality of first cores
- the shaft structures are alternately arranged along the first direction; wherein, the remaining second hard mask material layer constitutes the second hard mask layer, and the remaining sacrificial material layer includes the first sacrificial layer located on the side wall of the first mandrel. layer and a second sacrificial layer located below the second hard mask layer; the second mandrel structure includes a second sacrificial layer and a second hard mask layer.
- CMP chemical mechanical polishing
- the remaining second hard mask material layer 710 constitutes the second hard mask layer 700 .
- the retained sacrificial material layer 610 constitutes a sacrificial layer, wherein the sacrificial layer includes a first sacrificial layer 630 and a second sacrificial layer 640.
- the first sacrificial layer 630 conformally covers the side wall of the first mandrel structure 500
- the second sacrificial layer 630 covers the side wall of the first mandrel structure 500.
- the sacrificial layer 640 is located between the second hard mask layer 700 and the substrate 100 .
- the second sacrificial layer 640 and the second hard mask layer 700 are stacked in the vertical direction to form a second mandrel structure 800 .
- There are multiple second mandrel structures 800 and the plurality of second mandrel structures 800 and the plurality of first mandrel structures 500 are alternately arranged at intervals along the first direction.
- the thickness of the first core structure 500 is equal to the thickness of the second core structure 800 . That is, the top surface of the first mandrel structure 500 is flush with the top surface of the second mandrel structure 800 . In this way, a theoretical basis can be provided for subsequent simultaneous removal of the first mandrel structure 500 and the second mandrel structure 800 . In addition, the manufacturing process of the first mandrel structure 500 and the second mandrel structure 800 can also be simplified.
- “equal” in the embodiment may refer to the fact that the thickness of the first core structure 500 and the thickness of the second core structure 800 are strictly equal; it may also refer to the thickness of the first core structure 500 and the thickness of the second core being strictly equal.
- the thickness of the shaft structure 800 is approximately equal.
- the thickness difference between the first mandrel structure 500 and the second mandrel structure 800 is within a process error, for example, the difference between the two is within 5%.
- the thickness of the first mandrel structure 500 is 10 nm; the thickness of the second mandrel structure 800 is between 9.5 nm and 10 nm.
- "unequal" in the embodiment may refer to other situations besides the "equal" situation.
- Step S600 Remove the first sacrificial layer between the adjacent first mandrel structure and the second mandrel structure, and pattern the substrate using the first mandrel structure and the second mandrel structure as masks.
- a dry etching, wet etching or plasma etching process is used to remove the first sacrificial layer 630 between the adjacent first mandrel structure 500 and the second mandrel structure 800 , so that A third groove 810 is formed between the first mandrel structure 500 and the second mandrel structure 800 .
- the first sacrificial layer 630 located between the adjacent first mandrel structure 500 and the second mandrel structure 800 can be completely removed, or only a part of the thickness of the first sacrificial layer 630 can be removed. Sacrificial layer 630.
- the remaining top surface of the first sacrificial layer 630 may be flush with or slightly higher than the top surface of the second sacrificial layer 640 , thereby avoiding damage to the second sacrificial layer in step S600 640.
- the first mandrel structure 500 and the second mandrel structure 800 are used as masks to remove part of the thickness of the substrate 100 exposed in the third trench 810 .
- the etching stop layer 130 and the to-be-patterned layer 120 that are not blocked by the first mandrel structure 500 and the second mandrel structure 800 are removed to form a plurality of third spaced apart arrangements in the substrate in the first direction.
- grooves 910 are formed between adjacent third mandrel structures.
- first mandrel structure 500 and the second mandrel structure 800 are used as masks to pattern the substrate 100, the first mandrel structure 500, the second mandrel structure 800 and the respective components will be simultaneously etched and consumed.
- An etch stop layer 130 located directly below the first mandrel structure 500 and the second mandrel structure 800 . If after completing the etching and forming a plurality of third mandrel structures 900, there is still a certain thickness of the etching stop layer 130 on the top surface of the third mandrel structure 900, at this time, the remaining etching can be selectively removed. Stop layer 130.
- the thicknesses of the plurality of third mandrel structures 900 are equal, that is, the depths of the plurality of grooves 910 are equal. It should be noted that in this embodiment, “equal" may refer to that the thicknesses of the plurality of third mandrel structures 900 are strictly equal, or may also refer to being approximately equal.
- the first mandrel structure 500 is designed such that the first mandrel structure 500 includes a stacked compensation layer 510 and a first hard mask layer 520 , and the second mandrel structure 800 includes a stacked second sacrificial layer 500 .
- a compensation layer 510 is added on the basis of the first hard mask layer 520, and the compensation layer 510 is used to compensate for etching the first
- the difference in etching time between the mandrel structure 500 and the second mandrel structure 800 is to ensure that the etching time used to completely etch away the first mandrel structure 500 is the same as the etching time used to completely etch away the second mandrel structure 800.
- the etching time is equal.
- the target pattern formed will basically not have an odd-even effect.
- the etching time used to completely etch away the first mandrel structure 500 is equal to the etching time used to completely etch away the second mandrel structure 800. equal. That is, the ratio of the thickness of the first mandrel structure 500 to the average etching rate (referred to as the etching rate) is equal to the ratio of the thickness of the second mandrel structure 800 to the average etching rate.
- the first mandrel structure 500 and the second mandrel structure 800 will be removed simultaneously. For example, if the time taken to completely etch away the first mandrel structure 500 is greater than the time used to completely etch away the second mandrel structure 800, then a third mandrel structure 900 located directly below the first mandrel structure 500 will be formed. The thickness is greater than the thickness of the third core structure 900 formed directly below the first core structure 500, so that there is an odd-even effect in the thickness of the plurality of third core structures 900.
- the etching time used to completely etch away the first mandrel structure 500 is equal to the etching time used to completely etch away the second mandrel structure 800.
- the first mandrel The structure 500 and the second mandrel structure 800 serve as masks, and the target pattern formed when patterning the substrate 100 will have substantially no parity effect.
- the thickness of the first hard mask layer 520 in the first mandrel structure 500 may be marked as H1 and the thickness of the compensation layer 510 may be marked as H2.
- the thickness of the second hard mask layer 700 is denoted as H3
- the thickness of the second sacrificial layer 640 is denoted as H4.
- the average etching rates of the first hard mask layer 520, the compensation layer 510, the second hard mask layer 700 and the second sacrificial layer 640 are R1, R2, R3 and R4 respectively; according to The ratio of the thickness of the first mandrel structure 500 to the etching rate is equal to the ratio of the thickness of the second mandrel structure 800 to the etching rate, and the following formula (1) can be obtained.
- the target pattern formed will basically not have parity effects.
- the materials of the second sacrificial layer 640 and the compensation layer 510 are the same (that is, the etching rates of the two are equal), and the thicknesses of the second sacrificial layer 640 and the compensation layer 510 are equal; the second hard mask The film layer 700 and the first hard mask layer 520 are made of the same material, and the second hard mask layer 700 and the first hard mask layer 520 have the same thickness.
- Equation (2) can make the values on both sides of the equal sign in equation (1) equal. Furthermore, it can be ensured that the etching time used to completely etch away the first mandrel structure 500 is equal to the etching time used to completely etch away the second mandrel structure 800, so that the first mandrel structure 500 and the second mandrel structure 800 are etched away.
- the two-mandrel structure 800 is used as a mask.
- the target pattern formed will basically not have an odd-even effect.
- the first mandrel structure and the second mandrel structure are used as masks to form a plurality of third-order patterns in the substrate.
- the mandrel structure 900 basically does not exhibit parity effects.
- the material of the compensation layer 510 and the second sacrificial layer 640 is silicon boride (SiB) or silicon oxide.
- the material of the first hard mask layer 520 and the material of the second hard mask layer 700 are both Spin on Hardmask (SOH).
- the material of the compensation layer 510 and the second sacrificial layer 640 are the same; the material of the first hard mask layer 520 and the second hard mask layer 700 are the same. In this way, the etching of the third hard mask layer can be more easily controlled.
- the etching parameters of the first mandrel structure 500 and the second mandrel structure 800 simplify the patterning method.
- the second sacrificial layer 640 and the compensation layer 510 are made of the same material, and the thicknesses of the second sacrificial layer 640 and the compensation layer 510 are unequal; the second hard mask layer 700 and the first hard mask layer 520 are made of the same material, and the thicknesses of the second hard mask layer 700 and the first hard mask layer 520 are not equal.
- the average etching rate R2 of the compensation layer 510 is equal to the average etching rate R4 of the second sacrificial layer 640.
- the average etching rate R1 of the second hard mask layer 700 is equal to the average etching rate R3 of the first hard mask layer 520 .
- Equation (3) can make the values on both sides of the equal sign in equation (1) equal. This ensures that the etching time used to completely etch away the first mandrel structure 500 is equal to the etching time used to completely etch away the second mandrel structure 800 .
- the materials of the second sacrificial layer 640 and the compensation layer 510 are different (for example, the average etching rates of the two are different), and the thicknesses of the second sacrificial layer 640 and the compensation layer 510 are equal; the second hard The materials of the mask layer 700 and the first hard mask layer 520 are different (for example, their average etching rates are different), and the thicknesses of the second hard mask layer 700 and the first hard mask layer 520 are equal.
- the average etching rate R4 of the second sacrificial layer 640 and the average etching rate R2 of the compensation layer 510 are generally not equal.
- the average etching rate R3 of the second hard mask layer 700 and the average etching rate R1 of the first hard mask layer 520 Usually not equal.
- the second sacrificial layer 640 and the compensation layer 510 are made of the same material. In this way, it can be ensured that the average etching rate R4 of the second sacrificial layer 640 is equal to the average etching rate R2 of the compensation layer 510 .
- the thickness H4 of the second sacrificial layer 640 is different from the thickness H2 of the compensation layer 510; the thickness H3 of the second hard mask layer 700 is different from the thickness H1 of the first hard mask layer 520, and the material of the second hard mask layer 700 is different from the thickness H1 of the first hard mask layer 520.
- the materials of the first hard mask layer 520 are different.
- the materials of the second sacrificial layer 640 and the compensation layer 510 are different, and the thickness of the second sacrificial layer 640 and the thickness of the compensation layer 510 are not equal.
- the second hard mask layer 700 and the first hard mask layer 520 are made of the same material, and the thicknesses of the second hard mask layer 700 and the first hard mask layer 520 are not equal.
- the average etching rate R3 of the second hard mask layer 700 and the average etching rate R1 of the first hard mask layer 520 Usually equal.
- the widths of the first mandrel structure 500 and the second mandrel structure 800 are equal.
- the width W1 of the first mandrel structure 500 is equal to the width W2 of the second mandrel structure 800.
- the third mandrel structure 900 is formed to have the same width as the second mandrel structure 800 as a mask. Furthermore, the uniformity of the target pattern formed within the substrate 100 can be improved.
- width W1 of the first mandrel structure 500 and the width W2 of the second mandrel structure 800 may not be equal. In this way, the first mandrel structure can be reasonably set according to the requirements of the subsequent target pattern formed. 500 and a width W2 of the second mandrel structure 800 .
- the center distance of two adjacent first core structures 500 is the center distance of the adjacent first core structure 500 and the second core structure 800 . 2 times.
- the center distance L1 of the two first core structures 500 is The center distance of the second mandrel structure 800 is twice the distance L2.
- This arrangement can make the pattern density of the first mandrel structure 500 and the second mandrel structure 800 be twice the pattern density of the first mandrel structure 500. While doubling the pattern density, it is also beneficial to the subsequent etching of the first sacrificial layer, greatly improving the window of the subsequent multi-patterning process, thereby improving the yield of the target pattern using the patterning method in the embodiment of the present disclosure.
- the center distances of adjacent third core structures 900 are equal.
- the center distance between the first and third core shaft structures 900 and the second and third core shaft structures 900 is L3, and the center distance of the second and third core shaft structures 900 is L3.
- the center distance from the third third mandrel structure 900 is L4.
- L3 is equal to L4.
- Such an arrangement can ensure that the widths of the grooves 910 formed between adjacent third mandrel structures 900 are equal.
- the groove 910 is used to deposit and form interconnection metal blocks, it can be ensured that the widths of the formed interconnection metal blocks are equal, thereby ensuring that the resistances of multiple interconnection metal blocks are equal, thereby improving the performance of the subsequently formed memory. performance.
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- Drying Of Semiconductors (AREA)
Abstract
本公开提供一种图案化方法,涉及半导体技术领域,用于改善多重图案化工艺中的奇偶效应问题。该图案化方法包括:提供基底;在基底上形成第一掩膜层;图案化第一掩膜层以形成多个第一芯轴结构,相邻的两个第一芯轴结构之间具有第一沟槽,每个第一芯轴结构包括补偿层和第一硬掩膜层;形成牺牲材料层;牺牲材料层在第一沟槽内围成第二沟槽;形成至少填充满第二沟槽的第二硬掩膜材料层;回刻蚀第二硬掩膜材料层和牺牲材料层,以形成多个第二芯轴结构,第二芯轴结构包括第二牺牲层和第二硬掩膜层;去除第一牺牲层,并以第一芯轴结构和第二芯轴结构为掩膜,图案化基底。本公开能够减轻或避免在基底内形成目标图案存在奇偶效应的问题。
Description
本公开要求于2022年8月22日提交中国专利局、申请号为202211007228.4、申请名称为“图案化方法”的中国专利申请的优先权,其全部内容通过引用结合在本公开中。
本公开实施例涉及半导体技术领域,尤其涉及一种图案化方法。
在半导体结构制作过程中,通常需要在基底上形成目标图案,例如,在基底内刻蚀出沟槽以定义有源区。
随着目标图案尺寸微缩,通常采用多重图案化(multi-patterning)工艺形成所述目标图案。上述多重图案化工艺包括但不限于自对准双重图案化(Self-Aligned Double Patterning,简称SADP)工艺、反向自对准双重图案化(Reverse Self-Aligned Double Patterning,简称R-SADP)工艺和自对准四重图案化(Self-Aligned Quadruple Patterning,简称SAQP)工艺等。
然而,采用上述多重图案化工艺图案化基底时,所形成的目标图案易出现奇偶效应,进而影响所形成的半导体器件性能。
发明内容
本公开实施例提供一种图案化方法,其包括:
提供基底;
在所述基底上形成第一掩膜层,其中,所述第一掩膜层包括补偿材料层和位于所述补偿材料层上的第一硬掩膜材料层;
图案化所述第一掩膜层以形成沿第一方向间隔排布的多个第一芯轴结构,其中,相邻的两个所述第一芯轴结构之间具有第一沟槽,每个所述第一芯轴结构包括补偿层和第一硬掩膜层;
形成牺牲材料层,其中,所述牺牲材料层共形覆盖所述多个第一芯轴 结构的顶面和侧壁以及所述基底被所述第一沟槽暴露的部分;所述牺牲材料层在所述第一沟槽内围成第二沟槽;
形成第二硬掩膜材料层,其中,所述第二硬掩膜材料层至少填充满所述第二沟槽;
回刻蚀所述第二硬掩膜材料层和所述牺牲材料层,以形成沿所述第一方向间隔排布的多个第二芯轴结构,多个所述第二芯轴结构与多个所述第一芯轴结构沿所述第一方向交替间隔排布;其中,保留下来的第二硬掩膜材料层构成第二硬掩膜层,保留下来的所述牺牲材料层包括位于第一芯轴侧壁上的第一牺牲层和位于所述第二硬掩膜层下方的第二牺牲层;所述第二芯轴结构包括第二牺牲层和第二硬掩膜层;
去除相邻的所述第一芯轴结构和所述第二芯轴结构之间的第一牺牲层,并以所述第一芯轴结构和所述第二芯轴结构为掩膜,图案化所述基底。
在一些实施例中,在垂直于所述基底所在平面的方向上,所述第一芯轴结构的厚度和所述第二芯轴结构的厚度相等。
在一些实施例中,在图案化所述基底的过程中,将所述第一芯轴结构全部刻蚀掉所用的刻蚀时间与将所述第二芯轴结构全部刻蚀掉所用的刻蚀时间相等。
在一些实施例中,所述第二牺牲层和所述补偿层的材料相同,且所述第二牺牲层和所述补偿层的厚度相等;
所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度相等。
在一些实施例中,所述第二牺牲层和所述补偿层的材料相同,所述第二牺牲层和所述补偿层的厚度不相等;
所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
在一些实施例中,所述第二牺牲层和所述补偿层的材料不同,所述第二牺牲层和所述补偿层的厚度相等;
所述第二硬掩膜层和所述第一硬掩膜层的材料不同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度相等。
在一些实施例中,所述第二牺牲层和所述补偿层的材料相同,所述第二牺牲层和所述补偿层的厚度不相等;
所述第二硬掩膜层和所述第一硬掩膜层的材料不同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
在一些实施例中,所述第二牺牲层和所述补偿层的材料不同,所述第二牺牲层和所述补偿层的厚度不相等;
所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
在一些实施例中,在所述第一方向上,所述第一芯轴结构和所述第二芯轴结构的宽度相等。
在一些实施例中,在所述第一方向上,相邻的两个所述第一芯轴结构的中心距离为相邻的第一芯轴结构和第二芯轴结构的中心距离的2倍。
在一些实施例中,提供基底的步骤,包括:
提供衬底;
在所述衬底上形成依次层叠设置的待图案化层和刻蚀停止层,以得到所述基底。
在一些实施例中,图案化所述第一掩膜层的步骤包括:
在所述第一掩膜层上形成抗反射材料层以及光刻胶层;
图案化所述光刻胶层以形成沿第一方向间隔排布的多个开口;
以图案化后的所述光刻胶层为掩膜,去除暴露在所述开口内的所述抗反射材料层和所述第一掩膜层;
去除所述光刻胶层。
在一些实施例中,去除相邻的所述第一芯轴结构和所述第二芯轴结构之间的第一牺牲层的步骤包括:
去除未被所述第一芯轴结构和所述第二芯轴结构遮挡的所述刻蚀停止层和所述待图案化层;
在图案化所述基底的步骤之后,
去除保留的刻蚀停止层,以在保留下来的所述基底内形成沿第一方向间隔排布的多个第三芯轴结构。
在一些实施例中,在垂直于所述基底所在平面的方向上,多个所述第三芯轴结构的厚度相等。
在一些实施例中,在所述第一方向上,相邻的所述第三芯轴结构的宽度相等,相邻的所述第三芯轴结构的中心距离相等。
本公开实施例所提供的图案化方法中,第一芯轴结构包括层叠设置的补偿层和第一硬掩膜层;与相关技术中的第一芯轴结构相比,在第一硬掩膜层的基础上增设补偿层,利用补偿层来补偿刻蚀第一芯轴结构和第二芯轴结构所用的刻蚀时间的差异,以保证将第一芯轴结构全部刻蚀掉所用的刻蚀时间与将第二芯轴结构全部刻蚀掉所用的刻蚀时间相等,进而,在以第一芯轴结构和第二芯轴结构作为掩膜,图形化基底时所形成目标图案基本不会出现奇偶效应。
图1为本公开实施例提供的图案化方法的工艺流程图;
图2为本公开实施例提供的图案化方法中形成第一掩膜层的示意图;
图3为本公开实施例提供的图案化方法中图案化第一掩膜层后的示意图;
图4为本公开实施例提供的图案化方法中形成牺牲材料层后的示意图;
图5为本公开实施例提供的图案化方法中形成第二硬掩膜材料层后的示意图;
图6为本公开实施例提供的图案化方法中回刻牺牲材料层和第二硬掩膜材料层后的示意图;
图7为本公开实施例提供的图案化方法中形成第一芯轴结构和第二芯轴结构后的示意图;
图8为本公开实施例提供的图案化方法中图案化基底后的示意图。
附图标记:
100:基底;110:衬底;120:待图案化层;130:刻蚀停止层;
200:第一掩膜层;210:补偿材料层;220:第一硬掩膜材料层;
300:抗反射材料层;
400:光刻胶层;410:开口;
500:第一芯轴结构;510:补偿层;520:第一硬掩膜层;530:抗反射层;540:第一沟槽;
610:牺牲材料层;620:第二沟槽;630:第一牺牲层;640:第二牺牲层;
700:第二硬掩膜层;710:第二硬掩膜材料层;
800:第二芯轴结构;810:第三沟槽;
900:第三芯轴结构;910:凹槽。
以R-SADP工艺为例,采用R-SADP工艺图案化待图案化层时,所形成目标图案易出现奇偶效应。以下将以目标图案为有源柱,且所形成的有源柱的厚度(也即,高度)存在奇偶效应为例进行详细地描述。通常,先在待图案化层上形成第一材料层,图案化掩膜层以形成第一芯轴结构。之后,形成牺牲层,该牺牲层覆盖第一芯轴结构的侧壁和顶面以及未被遮挡的基底。并在相邻的第一芯轴结构之间的剩余间隙中形成第二材料层后,刻蚀位于第一芯轴结构的侧壁和顶面上的牺牲层,使得被保留下来的牺牲层和第二材料层作为第二芯轴结构。鉴于第二芯轴结构的膜层与第一芯轴结构的膜层不同,致使所形成的目标图案存在奇偶效应。即,所有位于奇数位置的有源柱的厚度相等,所有位于偶数位置的有源柱的厚度相等,但是,位于奇数位置的有源柱的厚度与位于偶数位置的有源柱的厚度不相等。
针对上述技术问题,本公开实施例提供了一种图案化方法,通过对第一芯轴结构进行设计,使得第一芯轴结构包括层叠设置的补偿层和第一硬掩膜层;与相关技术中的第一芯轴结构相比,在第一硬掩膜层的基础上增设补偿层,利用补偿层来补偿刻蚀第一芯轴结构和第二芯轴结构所用的刻蚀时间的差异,以保证将第一芯轴结构全部刻蚀掉所用的刻蚀时间与将第二芯轴结构全部刻蚀掉所用的刻蚀时间相等,进而,在以第一芯轴结构和第二芯轴结构作为掩膜,图形化基底时所形成目标图案基本不会出现奇偶效应。例如,以第一芯轴结构和第二芯轴结构作为掩膜在基底内形成多个有源柱时,多个有源柱的厚度相等,基本不会出现奇偶效应。
为了使本公开实施例的上述目的、特征和优点能够更加明显易懂,下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本公开的一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例,均属于本公开保护的范 围。
本公开实施例提供的一种图案化方法,该图案化方法可以用于形成存储器中有源柱。
请参考附图1,本公开实施例提供的一种图案化方法,包括如下步骤:
步骤S100:提供基底。
需要说明的是,本实施例中基底100可以为半导体基底,如此,可以利用图案化方法在基底100内形成有源柱,相邻的有源柱之间形成浅沟槽,以便于在浅沟槽内形成浅沟槽隔离结构(STI)。
当然,基底100还可以为其他结构。示例性地,请参考附图2,基底100还可以包括衬底110、待图案化层120和刻蚀停止层130。
其中,衬底110用于支撑其上的待图案化层120和刻蚀停止层130,衬底110可以为硅(Si)衬底、锗(Ge)衬底、硅锗(GeSi)衬底、碳化硅(SiC)衬底、绝缘体上硅(Silicon on Insulator,简称SOI)衬底或者绝缘体上锗(Germanium on Insulator,简称GOI)衬底等。
待图案化层120形成在衬底110上,其中,待图案化层120可以为用于形成目标图案的任意膜层。
刻蚀停止层130形成在待图案化层120背离衬底110的表面上。在后续中可以利用高刻蚀选择比的刻蚀工艺,图案化第一掩膜层200时,可以减轻或避免对待图案化层120造成损伤,保证了图案化方法所形成目标图案的准确性。
其中,刻蚀停止层130的材质包括氮氧化硅,但不仅限于此。
需要说明的是,本实施例中待图案化层120和刻蚀停止层130均可以采用例如沉积工艺形成。示例性地,通过化学气相沉积(Chemical Vapor Deposition,简称CVD)、物理气相沉积(Physical Vapor Deposition,简称PVD)或者原子层沉积(Atomic Layer Deposition,简称ALD)等工艺,在衬底110上形成依次层叠设置的待图案化层120和刻蚀停止层130。
步骤S200:在基底上形成第一掩膜层,其中,第一掩膜层包括补偿材料层和位于补偿材料层上的第一硬掩膜材料层。
示例性地,采用沉积工艺在刻蚀停止层130上形成补偿材料层210。之后,在补偿材料层210上形成第一硬掩膜材料层220。
步骤S300:图案化第一掩膜层以形成沿第一方向间隔排布的多个第一芯轴结构,其中,相邻的两个第一芯轴之间具有第一沟槽,每个第一芯轴结构包括补偿层和第一硬掩膜层。
示例性地,请继续参考附图2,在第一掩膜层200上形成抗反射材料层300和光刻胶层400。
之后,图案化光刻胶层400。示例性地,利用具有掩膜图案的掩膜版(图中未示出)对光刻胶层400进行曝光,以将掩膜版上的掩膜图案转移到光刻胶层400上。随后,对光刻胶层400进行显影,去除部分光刻胶层400,以在光刻胶层400内形成多个开口410。多个开口410沿第一方向间隔排布。第一方向可以为附图2中X方向。
在本实施例中,抗反射材料层300的材质可以包括氮化物。例如,抗反射材料层300的材质包括氮化硅或者氮氧化硅,但不仅限于此。抗反射材料层300能够缓解或消除光刻胶层400的驻波效应,从而可以增加掩膜图案从掩膜版转移到光刻胶层400上的精准性,进而提高图形转移过程中的准确性。
请参考附图3,以图案化后的光刻胶层400为掩膜,利用干法刻蚀、湿法刻蚀或者等离子刻蚀工艺,去除暴露在开口410内的抗反射材料层300和第一掩膜层200。
其中,被保留下来的补偿材料层210构成补偿层510。被保留下来的第一硬掩膜材料层220构成第一硬掩膜层520。被保留下来的抗反射材料层300构成抗反射层530。
在完成图案化第一掩膜层200的步骤之后,至少去除光刻胶层400。示例性地,可通过清洗液清洗或者通过灰化处理工艺去除光刻胶层400,使得所形成的抗反射层530不再被光刻胶层覆盖。
在一示例中,在至少去除光刻胶层400的步骤中,仅去除了光刻胶层400,则第一芯轴结构500包括沿垂直方向层叠设置的补偿层510、第一硬掩膜层520和抗反射层530。其中,垂直方向为垂直于基底100所在平面的方向。即,附图3中的Z方向。
在另一示例中,在至少去除光刻胶层400的步骤中,同时去除光刻胶层400和抗反射层530,则第一芯轴结构500包括沿垂直方向层叠设置的补偿层510和第一硬掩膜层520。
相邻的第一芯轴结构500之间形成有第一沟槽540,该第一沟槽540用于为后续所形成第二芯轴结构提供设置空间。
步骤S300:形成牺牲材料层,其中,牺牲材料层共形覆盖多个第一芯轴结构的顶面和侧壁以及基底被第一沟槽暴露的部分;牺牲材料层在第一沟槽内围成第二沟槽。
请参考附图4,利用原子层沉积工艺在第一沟槽540的内壁上形成一定厚度的牺牲材料层610,该牺牲材料层610延伸至第一沟槽540的外部,并覆盖第一芯轴结构500的顶面上。
牺牲材料层610未填充满第一沟槽540,使得牺牲材料层610在第一沟槽540内围成第二沟槽620。
步骤S400:形成第二硬掩膜材料层,其中,第二硬掩膜材料层至少填充满第二沟槽。
请参考附图5,第二硬掩膜材料层710可以填充满第二沟槽,使得第二硬掩膜材料层710的顶面与牺牲材料层610的顶面平齐。
当然第二硬掩膜材料层710还可以延伸至第二沟槽外,以使得第二硬掩膜材料层710的顶面高于牺牲材料层610的顶面。
步骤S500:回刻蚀所第二硬掩膜材料层和牺牲材料层,以形成沿第一方向间隔排布的多个第二芯轴结构,多个第二芯轴结构与多个第一芯轴结构沿第一方向交替间隔排布;其中,保留下来的第二硬掩膜材料层构成第二硬掩膜层,保留下来的牺牲材料层包括位于第一芯轴侧壁上的第一牺牲层和位于第二硬掩膜层下方的第二牺牲层;第二芯轴结构包括第二牺牲层和第二硬掩膜层。
示例性地,请参考附图6,采用化学机械研磨(Chemical Mechanical Polishing,简称CMP)工艺去除位于第一硬掩膜层520的顶面上的牺牲材料层610和第二硬掩膜材料层710,以暴露出第一硬掩膜层520的顶面。需要理解的是,在至少去除光刻胶层的步骤中,仅是去除了光刻胶层,未去除抗反射层530;在此步骤中,还需要同步去除抗反射层530。
被保留下来的第二硬掩膜材料层710构成第二硬掩膜层700。被保留下来的牺牲材料层610构成牺牲层,其中,牺牲层包括第一牺牲层630和第二牺牲层640,第一牺牲层630随形覆盖在第一芯轴结构500侧壁上,第二牺牲层640位于第二硬掩膜层700与基底100之间。
沿垂直方向层叠设置的第二牺牲层640和第二硬掩膜层700构成一个第二芯轴结构800。其中,第二芯轴结构800的个数为多个,多个第二芯轴结构800与多个第一芯轴结构500沿第一方向交替间隔排布。
在垂直于基底100所在平面上,第一芯轴结构500的厚度与第二芯轴结构800的厚度相等。即,第一芯轴结构500的顶面与第二芯轴结构800的顶面平齐。如此,可以为后续同步去除第一芯轴结构500和第二芯轴结构800提供理论依据。此外,还可以简化第一芯轴结构500和第二芯轴结构800的制备工艺。
需要说明的是,实施例中“相等”可以指代第一芯轴结构500的厚度与第二芯轴结构800的厚度严格相等;也可以指代第一芯轴结构500的厚度和第二芯轴结构800的厚度大致相等,例如,第一芯轴结构500和第二芯轴结构800的厚度差值在工艺误差之内,例如二者相差5%以内。例如,第一芯轴结构500的厚度为10nm;第二芯轴结构800的厚度要在9.5nm-10nm之间。相应地,实施例中“不相等”则可以指代除了“相等”的情形之外的其他情形。
步骤S600:去除相邻的第一芯轴结构和第二芯轴结构之间的第一牺牲层,并以第一芯轴结构和第二芯轴结构为掩膜,图案化基底。
请参考附图7,利用干法刻蚀、湿法刻蚀或者等离子刻蚀工艺,去除位于相邻的第一芯轴结构500和第二芯轴结构800之间的第一牺牲层630,使得第一芯轴结构500和第二芯轴结构800之间形成第三沟槽810。
需要说明的是,本实施例中,可以将位于相邻的第一芯轴结构500和第二芯轴结构800之间的第一牺牲层630全部去除掉,也可以仅去除部分厚度的第一牺牲层630。例如,保留下来的第一牺牲层630的顶面可以与第二牺牲层640的顶面平齐或者略高于第二牺牲层640的顶面,从而可以避免在步骤S600中损伤第二牺牲层640。
请参考附图8,以第一芯轴结构500和第二芯轴结构800为掩膜,去除暴露在第三沟槽810内部分厚度的基底100。
示例性地,去除未被第一芯轴结构500和第二芯轴结构800遮挡的刻蚀停止层130和待图案化层120,以在基底内形成沿第一方向间隔排布的多个第三芯轴结构900,相邻的第三芯轴结构之间形成有凹槽910。
需要说明的是,在以第一芯轴结构500和第二芯轴结构800为掩膜, 图案化基底100时,会同步刻蚀消耗第一芯轴结构500、第二芯轴结构800以及分别位于第一芯轴结构500和第二芯轴结构800正下方的刻蚀停止层130。若在完成刻蚀并形成多个第三芯轴结构900之后,第三芯轴结构900的顶面上仍然存在一定厚度的刻蚀停止层130,此时,可以选择性地去除剩余的刻蚀停止层130。
在垂直于基底100所在的平面上,多个第三芯轴结构900的厚度相等,也就是说,多个凹槽910的深度相等。需要说明的是,本实施例中“相等”可以指代多个第三芯轴结构900的厚度严格相等,也可以指代大致相等。
本实施例通过对第一芯轴结构500进行设计,使得第一芯轴结构500包括层叠设置的补偿层510和第一硬掩膜层520,第二芯轴结构800包括层叠设置在第二牺牲层640和第二硬掩膜层700;与相关技术中的第一芯轴结构相比,在第一硬掩膜层520的基础上增设补偿层510,利用补偿层510来补偿刻蚀第一芯轴结构500和第二芯轴结构800所用的刻蚀时间的差异,以保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等,进而,在以第一芯轴结构500和第二芯轴结构800作为掩膜,图形化基底100时所形成目标图案基本不会出现奇偶效应。
在一种可能的实施方式中,在图案化基底的过程中,将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。即,第一芯轴结构500的厚度与平均刻蚀速率(简称刻蚀速率)的比值与第二芯轴结构800的厚度与平均刻蚀速率的比值相等。
以第一芯轴结构500和第二芯轴结构800为掩膜,图案化基底100时,会同步去除第一芯轴结构500和第二芯轴结构800。例如,若全部刻蚀掉第一芯轴结构500所用的时间大于全部刻蚀掉第二芯轴结构800所用的时间,则形成在位于第一芯轴结构500正下方的第三芯轴结构900的厚度,要大于形成在位于第一芯轴结构500正下方的第三芯轴结构900的厚度,使得多个第三芯轴结构900的厚度存在奇偶效应。
因此,本实施例通过使将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等,如此,在以第一芯轴结构500和第二芯轴结构800作为掩膜,图形化基底100时所形成目标图案基本不会出现奇偶效应。
请继续参考附图7,为了清晰地对上述的原理进行描述,不妨将第一芯轴结构500中的第一硬掩膜层520的厚度记为H1,补偿层510的厚度记为H2。在第二芯轴结构800中,将第二硬掩膜层700的厚度记为H3,第二牺牲层640的厚度记为H4。
在图案化基底100的过程中,第一硬掩膜层520、补偿层510、第二硬掩膜层700和第二牺牲层640的平均刻蚀速率分别为R1、R2、R3和R4;根据第一芯轴结构500的厚度与刻蚀速率的比值与第二芯轴结构800的厚度与刻蚀速率的比值相等,可以得到如下的式(1)。
式(1)H1/R1+H2/R2=H3/R3+H4/R4
如此设置,可以保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。如此,在以第一芯轴结构500和第二芯轴结构800作为掩膜,图形化基底100时所形成目标图案基本不会出现奇偶效应。
在一种可能的实施方式中,第二牺牲层640和补偿层510的材料相同(即二者的刻蚀速率相等),且第二牺牲层640和补偿层510的厚度相等;第二硬掩膜层700和第一硬掩膜层520的材料相同,且第二硬掩膜层700和第一硬掩膜层520的厚度相等。
如此,可以得到如下的式(2):H1=H3,R1=R3,H2=H4,R2=R4。
将式(2)代入式(1),能够使得式(1)的等号两侧的数值相等。进而能够保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等,从而,在以第一芯轴结构500和第二芯轴结构800作为掩膜,图形化基底100时所形成目标图案基本不会出现奇偶效应,例如,以第一芯轴结构和第二芯轴结构作为掩膜在基底内形成多个第三芯轴结构900基本不会出现奇偶效应。
在本实施例中,补偿层510的材料和第二牺牲层640的材料均为硼化硅(SiB)或者氧化硅等。第一硬掩膜层520的材料和第二硬掩膜层700的材料均为旋涂硬掩膜(Spin on Hardmask,简称SOH)。
本实施例中,补偿层510的材料和第二牺牲层640的材料相同;第一硬掩膜层520的材料和第二硬掩膜层700的材料相同,如此,可以更加容易调控刻蚀第一芯轴结构500和第二芯轴结构800的刻蚀参数,简化图案化方法。
在一种可能的实施方式中,第二牺牲层640和补偿层510的材料相同,第二牺牲层640和补偿层510的厚度不相等;第二硬掩膜层700和第一硬掩膜层520的材料相同,且第二硬掩膜层700和第一硬掩膜层520的厚度不相等。
在图案化基底100的过程中,补偿层510的平均刻蚀速率R2等于第二牺牲层640的平均刻蚀速率R4。第二硬掩膜层700的平均刻蚀速率R1等于第一硬掩膜层520的平均刻蚀速率R3。如此,只要保证第一硬掩膜层520的厚度H1与第二硬掩膜层700的厚度H3的差值,与第二牺牲层640的厚度H4与补偿层510的厚度H2的差值相等。可以得到式(3):(H1-H3)=(H4-H2)。
将式(3)代入式(1),能够使得式(1)的等号两侧的数值相等。进而保证能够保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。
在一种可能的实施方式中,第二牺牲层640和补偿层510的材料不同(例如,二者的平均刻蚀速率不同),第二牺牲层640和补偿层510的厚度相等;第二硬掩膜层700和第一硬掩膜层520的材料不同(例如,二者的平均刻蚀速率不同),且第二硬掩膜层700和第一硬掩膜层520的厚度相等。
在第二牺牲层640和补偿层510的材料不同的情况下,第二牺牲层640的平均刻蚀速率R4与补偿层510的平均刻蚀速率R2通常不相等。在第二硬掩膜层700和第一硬掩膜层520的材料不同的情况下,第二硬掩膜层700的平均刻蚀速率R3和第一硬掩膜层520的平均刻蚀速率R1通常不相等。但是,只要能够保证(1/R4-1/R2)=(1/R1-1/R3),也能够保证式(1)的等号两侧的数值相等。进而保证能够保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。
在一种可能的实施方式中,第二牺牲层640和补偿层510的材料相同,如此,可以保证第二牺牲层640的平均刻蚀速率R4,与补偿层510的平均刻蚀速率R2相等。
第二牺牲层640的厚度H4和补偿层510的厚度H2不同;第二硬掩膜层700的厚度H3和第一硬掩膜层520的厚度H1不同,第二硬掩膜层700的材料和第一硬掩膜层520的材料不同。
只要能够保证(H2-H4)=(H3/R3-H1/R1),也能够保证式(1)的等号两侧的数值相等。进而保证能够保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。
在一种可能的实施方式中,第二牺牲层640和补偿层510的材料不同,第二牺牲层640的厚度和补偿层510的厚度不相等。
第二硬掩膜层700和第一硬掩膜层520的材料相同,且第二硬掩膜层700和第一硬掩膜层520的厚度不相等。在第二硬掩膜层700和第一硬掩膜层520的材料相同的情况下,第二硬掩膜层700的平均刻蚀速率R3和第一硬掩膜层520的平均刻蚀速率R1通常相等。
只要能够保证(H1-H3)=(H4/R4-H2/R2),也能够保证式(1)的等号两侧的数值相等。进而保证能够保证将第一芯轴结构500全部刻蚀掉所用的刻蚀时间与将第二芯轴结构800全部刻蚀掉所用的刻蚀时间相等。
在一种可能的实施方式中,在第一方向上,第一芯轴结构500和第二芯轴结构800的宽度相等。
请继续参考附图7和附图8,在第一方向上,第一芯轴结构500的宽度W1与第二芯轴结构800的宽度W2相等,如此设置,可以保证以第一芯轴结构500和第二芯轴结构800作为掩膜,所形成第三芯轴结构900的宽度相等。进而,可以提高形成在基底100内目标图案的均匀性。
需要说明的是,第一芯轴结构500的宽度W1和第二芯轴结构800的宽度W2还可以不相等,如此,可以根据后续所形成的目标图案的要求,合理地设置第一芯轴结构500的宽度W1和第二芯轴结构800的宽度W2。
在一种可能的实施方式中,在第一方向上,相邻的两个第一芯轴结构500的中心距离为相邻的第一芯轴结构500和第二芯轴结构800的中心距离的2倍。
请继续参考附图7,在任意相邻的两个第一芯轴结构500和一个第二芯轴结构800中,两个第一芯轴结构500的中心距离L1为第一芯轴结构500和第二芯轴结构800的中心距离L2的2倍,如此设置,可以使第一芯轴结构500和第二芯轴结构800的图形密度是第一芯轴结构500的图形密度的2倍,实现图形密度的倍增的同时,也有利于后续第一牺牲层刻蚀,极大地改善了后续的多重图案化工艺的窗口,进而提高了采用本公开实施例中图案化方法的目标图案的良率。
在一种可能的实施方式中,在第一方向上,相邻的第三芯轴结构900的中心距离相等。
以附图8所示的方位为例,从左往右,第一个第三芯轴结构900与第二个第三芯轴结构900的中心距离为L3,第二个第三芯轴结构900与第三个第三芯轴结构900的中心距离为L4。其中,L3等于L4。如此设置,可以保证相邻的第三芯轴结构900之间所形成凹槽910的宽度相等。例如,当该凹槽910内用于沉积形成互连金属块时,可以保证所形成的互连金属块的宽度相等,进而保证多条互连金属块的电阻相等,提高后续所形成的存储器的性能。
本说明书中各实施例或实施方式采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中,参考术语“一个实施方式”、“一些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施方式或示例中。
在本说明书中,对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是:以上各实施例仅用以说明本公开的技术方案,而非对其限制;尽管参照前述各实施例对本公开进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
Claims (15)
- 一种图案化方法,包括:提供基底;在所述基底上形成第一掩膜层,其中,所述第一掩膜层包括补偿材料层和位于所述补偿材料层上的第一硬掩膜材料层;图案化所述第一掩膜层以形成沿第一方向间隔排布的多个第一芯轴结构,其中,相邻的两个所述第一芯轴结构之间具有第一沟槽,每个所述第一芯轴结构包括补偿层和第一硬掩膜层;形成牺牲材料层,其中,所述牺牲材料层共形覆盖所述多个第一芯轴结构的顶面和侧壁以及所述基底被所述第一沟槽暴露的部分;所述牺牲材料层在所述第一沟槽内围成第二沟槽;形成第二硬掩膜材料层,其中,所述第二硬掩膜材料层至少填充满所述第二沟槽;回刻蚀所述第二硬掩膜材料层和所述牺牲材料层,以形成沿所述第一方向间隔排布的多个第二芯轴结构,多个所述第二芯轴结构与多个所述第一芯轴结构沿所述第一方向交替间隔排布;其中,保留下来的第二硬掩膜材料层构成第二硬掩膜层,保留下来的所述牺牲材料层包括位于第一芯轴侧壁上的第一牺牲层和位于所述第二硬掩膜层下方的第二牺牲层;所述第二芯轴结构包括第二牺牲层和第二硬掩膜层;去除相邻的所述第一芯轴结构和所述第二芯轴结构之间的第一牺牲层,并以所述第一芯轴结构和所述第二芯轴结构为掩膜,图案化所述基底。
- 根据权利要求1所述的图案化方法,其中,在垂直于所述基底所在平面的方向上,所述第一芯轴结构的厚度和所述第二芯轴结构的厚度相等。
- 根据权利要求2所述的图案化方法,其中,在图案化所述基底的过程中,将所述第一芯轴结构全部刻蚀掉所用的刻蚀时间与将所述第二芯轴结构全部刻蚀掉所用的刻蚀时间相等。
- 根据权利要求3所述的图案化方法,其中,所述第二牺牲层和所述补偿层的材料相同,且所述第二牺牲层和所述补偿层的厚度相等;所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度相等。
- 根据权利要求3所述的图案化方法,其中,所述第二牺牲层和所述补偿层的材料相同,所述第二牺牲层和所述补偿层的厚度不相等;所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
- 根据权利要求3所述的图案化方法,其中,所述第二牺牲层和所述补偿层的材料不同,所述第二牺牲层和所述补偿层的厚度相等;所述第二硬掩膜层和所述第一硬掩膜层的材料不同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度相等。
- 根据权利要求3所述的图案化方法,其中,所述第二牺牲层和所述补偿层的材料相同,所述第二牺牲层和所述补偿层的厚度不相等;所述第二硬掩膜层和所述第一硬掩膜层的材料不同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
- 根据权利要求3所述的图案化方法,其中,所述第二牺牲层和所述补偿层的材料不同,所述第二牺牲层和所述补偿层的厚度不相等;所述第二硬掩膜层和所述第一硬掩膜层的材料相同,且所述第二硬掩膜层和所述第一硬掩膜层的厚度不相等。
- 根据权利要求1-8任一项所述的图案化方法,其中,在所述第一方向上,所述第一芯轴结构和所述第二芯轴结构的宽度相等。
- 根据权利要求9所述的图案化方法,其中,在所述第一方向上,相邻的两个所述第一芯轴结构的中心距离为相邻的第一芯轴结构和第二芯轴结构的中心距离的2倍。
- 根据权利要求1-8任一项所述的图案化方法,其中,提供基底的步骤,包括:提供衬底;在所述衬底上形成依次层叠设置的待图案化层和刻蚀停止层,以得到所述基底。
- 根据权利要求11所述的图案化方法,其中,图案化所述第一掩膜层的步骤包括:在所述第一掩膜层上形成抗反射材料层以及光刻胶层;图案化所述光刻胶层以形成沿第一方向间隔排布的多个开口;以图案化后的所述光刻胶层为掩膜,去除暴露在所述开口内的所述抗 反射材料层和所述第一掩膜层;去除所述光刻胶层。
- 根据权利要求12所述的图案化方法,其中,以所述第一芯轴结构和所述第二芯轴结构为掩膜,图案化所述基底的步骤包括:去除未被所述第一芯轴结构和所述第二芯轴结构遮挡的所述刻蚀停止层和所述待图案化层,以在所述基底内形成沿第一方向间隔排布的多个第三芯轴结构。
- 根据权利要求13所述的图案化方法,其中,在垂直于所述基底所在平面的方向上,多个所述第三芯轴结构的厚度相等。
- 根据权利要求14所述的图案化方法,其中,在所述第一方向上,相邻的所述第三芯轴结构的宽度相等,相邻的所述第三芯轴结构的中心距离相等。
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| KR100734464B1 (ko) * | 2006-07-11 | 2007-07-03 | 삼성전자주식회사 | 미세 피치의 하드마스크 패턴 형성 방법 및 이를 이용한반도체 소자의 미세 패턴 형성 방법 |
| KR100790998B1 (ko) * | 2006-10-02 | 2008-01-03 | 삼성전자주식회사 | 셀프 얼라인 더블 패터닝법을 사용한 패드 패턴 형성 방법 및 셀프 얼라인 더블 패터닝법을 사용한 콘택홀 형성방법 |
| CN103594336B (zh) * | 2012-08-13 | 2016-05-25 | 中芯国际集成电路制造(上海)有限公司 | 一种双重图形化方法 |
| TWI555082B (zh) * | 2015-05-15 | 2016-10-21 | 力晶科技股份有限公司 | 圖案化方法 |
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| US20140065812A1 (en) * | 2012-09-06 | 2014-03-06 | Kabushiki Kaisha Toshiba | Manufacturing method of semiconductor storage device |
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| US20190341252A1 (en) * | 2018-05-01 | 2019-11-07 | United Microelectronics Corp. | Method for patterning a semiconductor structure |
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