WO2024040622A1 - 一种半导体结构及存储器 - Google Patents

一种半导体结构及存储器 Download PDF

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Publication number
WO2024040622A1
WO2024040622A1 PCT/CN2022/115543 CN2022115543W WO2024040622A1 WO 2024040622 A1 WO2024040622 A1 WO 2024040622A1 CN 2022115543 W CN2022115543 W CN 2022115543W WO 2024040622 A1 WO2024040622 A1 WO 2024040622A1
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region
channel region
channel
sub
recess
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PCT/CN2022/115543
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English (en)
French (fr)
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曺奎锡
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长鑫科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a memory.
  • embodiments of the present disclosure provide a semiconductor structure and a memory.
  • a semiconductor structure including:
  • the gate electrode includes a main body portion extending along a first direction, the source region and the drain region are located on both sides of the main body portion in a second direction, and the second direction is perpendicular to the first direction. direction;
  • the channel region includes a first channel region located directly below the body portion, and the first channel region has a recess at an interface between the first channel region and the isolation structure.
  • the boundary segment there is a boundary segment between the source region and the channel region; the first channel region includes a first sub-region; in the case of translating the boundary segment along the second direction Below, the boundary line segment passes through the first sub-region and at least part of the depression.
  • the isolation structure includes a trench and a first oxide layer covering a bottom and sidewalls of the trench, the first oxide layer being in contact with the first channel region, and the The thickness of the first oxide layer in the recess is greater than the thickness of the first oxide layer at other locations except the recess.
  • the isolation structure further includes a nitride layer located in the trench and covering the first oxide layer and a second oxide layer located in the trench and covering the nitride layer. layer, the nitride layer and the second oxide layer are located outside the recess.
  • the width of the interior of the recess along the second direction is smaller than the width of the opening of the recess along the second direction.
  • the first channel region further includes a second sub-region, and the second sub-region is located on a side of the recess close to the drain region, wherein along the second direction When the boundary line segment between the source region and the channel region is translated, the boundary line segment does not pass through the second sub-region.
  • the first channel region further includes a third sub-region, the third sub-region is located on a side of the recess close to the source region, wherein along the second direction When the boundary line segment between the source region and the channel region is translated, the boundary line segment does not pass through the third sub-region.
  • the area of the orthographic projection of the second sub-region and/or the third sub-region on the substrate plane is smaller than the area of the orthographic projection of the recess on the substrate plane.
  • the extending length of the recess along the first direction is greater than the width of the opening of the recess along the second direction.
  • the first channel region and the isolation structure include two discrete interfaces, wherein at at least one of the interfaces, the first channel region includes a plurality of Describe the depression.
  • the first channel region further includes a fourth sub-region, the fourth sub-region is located between adjacent recesses, wherein when the source is translated along the second direction In the case of a boundary segment between a region and the channel region, the boundary segment does not pass through the fourth sub-region.
  • the gate further includes a first extension portion protruding from the main body portion, the first extension portion extending along the second direction, and the first extension portion is located near the main body portion.
  • the channel region On one side of the drain region, the channel region further includes a second channel region, and the second channel region is covered by the first extension.
  • the boundary line segment of the source region and the channel region when the boundary line segment of the source region and the channel region is translated along the second direction, the boundary line segment passes through at least part of the second channel region.
  • the gate further includes a second extension portion protruding from the main body portion, the second extension portion is located on a side of the main body portion close to the source region, and the channel The region also includes a third channel region covered by the second extension.
  • the boundary line segment of the source region and the first channel region when the boundary line segment of the source region and the first channel region is translated along the second direction, the boundary line segment passes through at least part of the third channel region .
  • a memory including the semiconductor structure described in any one of the above embodiments.
  • Embodiments of the present disclosure provide a semiconductor structure, including: a substrate and an isolation structure located in the substrate, the isolation structure defines an active region in the substrate, the active region includes a source electrode region, a drain region and a channel region; a gate covering the channel region; wherein the gate includes a body portion extending along a first direction, the source region and the drain Areas are located on both sides of the main body in a second direction, and the second direction is perpendicular to the first direction; the channel area includes a first channel area located directly below the main body, where At an interface between the first channel region and the isolation structure, the first channel region has a recess.
  • the present disclosure defines an active area through an isolation structure, the active area includes a channel area, the transistor gate covers the channel area, the gate includes a main body portion extending along the first direction, and the first channel is covered directly below the main body portion of the gate electrode.
  • the first channel region has a recess at an interface between the first channel region and the isolation structure.
  • the recessed design can extend the channel length at the interface between the isolation structure and the channel region to suppress hot electron-induced punch-through effects and avoid or mitigate device performance degradation caused by hot electron-induced punch-through effects.
  • FIG. 1 is a schematic top view of a semiconductor structure in which a boundary segment passes through a first sub-region and at least a partial region of a recess in an embodiment of the present disclosure
  • FIG. 2 is a schematic top view of a semiconductor structure in which a boundary segment passes through at least part of the first sub-region and does not pass through a recess in an embodiment of the present disclosure
  • FIG. 3 is a schematic top view of a semiconductor structure in which the recess is not filled with the first oxide layer in an embodiment of the present disclosure
  • FIG. 4 is a schematic top view of a semiconductor structure in which the nitride layer and the second oxide layer are located outside the recess in an embodiment of the present disclosure
  • FIG. 5 is a schematic top view of a semiconductor structure in which the first channel region includes a second sub-region in an embodiment of the present disclosure
  • FIG. 6 is a schematic top view of a semiconductor structure in which the first channel region also includes a third sub-region in an embodiment of the present disclosure
  • FIG. 7 is a schematic top view of a semiconductor structure in which the first channel region includes a plurality of recesses in an embodiment of the present disclosure
  • FIG. 8 is a schematic top view of a semiconductor structure in which the gate electrode includes a main body part and a first extension part in an embodiment of the present disclosure
  • Figure 9 is a schematic top view of a semiconductor structure in which the gate electrode includes a main body part and first extension parts and third extension parts in an embodiment of the present disclosure
  • FIG. 10 is a schematic top view of a semiconductor structure in which a gate electrode includes a main body part and first extension parts and second extension parts in an embodiment of the present disclosure.
  • 10-isolation structure 10a-first oxide layer; 10b-nitride layer; 10c-second oxide layer; 11-active region; 12-source region; 13-drain region; 14-channel region ; 141-first channel area; 141a-first sub-area; 141b-second sub-area; 141c-third sub-area; 141d-fourth sub-area; 142-second channel area; 143-third trench Track area; 15-gate; 151-main body; 152-first extension; 153-second extension; 154-third extension; 16-depression; 17-junction line segment; a-depression along the first direction The extended length; b-the width of the recessed opening along the second direction.
  • an isolation structure is usually formed on the substrate to define the active area.
  • the isolation structure is usually formed by sequentially depositing an oxide layer, a nitride layer and an oxide layer in a shallow trench.
  • Figure 1-10 is a schematic top view of the semiconductor structure. As shown in Figure 1-10, the semiconductor structure includes:
  • a substrate (not shown in the figure) and an isolation structure 10 located in the substrate, the isolation structure 10 defining an active region 11 in the substrate, the active region 11 including a source region 12 , drain region 13 and channel region 14;
  • Gate 15 the gate 15 covers the channel region 14; wherein,
  • the gate 15 includes a main body portion 151 extending along a first direction.
  • the source region 12 and the drain region 13 are located on both sides of the main body portion 151 in a second direction.
  • the second direction is vertical. in the first direction;
  • the channel region 14 includes a first channel region 141 located directly below the main body portion 151 .
  • the first channel region 141 is Zone 141 has depressions 16 .
  • the first channel region located directly below the main body of the gate has a recess.
  • the recess can extend the channel length at the interface between the isolation structure and the channel region to suppress the hot electron-induced punch-through effect and avoid or reduce the hot electron induction. Device performance degradation caused by punch-through effect.
  • the semiconductor structure provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM), but is not limited thereto, and the semiconductor structure may also be any other semiconductor device type.
  • DRAM dynamic random access memory
  • the substrate includes, for example, but is not limited to, a single semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.) , or silicon-on-insulator (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.
  • the substrate may be doped or undoped, or contain both doped and undoped regions therein.
  • the substrate may also include one or more doped ( n- or p- ) regions; if the substrate includes multiple doped regions, these regions may have the same or different conductivities and/or doping concentrations.
  • the substrate is a doped or undoped silicon substrate.
  • the preparation of the isolation structure 10 includes but is not limited to the following process: first, using a photolithography process to form a patterned photoresist layer on the substrate, and then using the patterned photoresist layer as a mask, A dry or wet etching process is used to etch the substrate to form a shallow trench, and then the shallow trench is filled with an isolation material to form an isolation structure 10 .
  • the isolation structure 10 is used to isolate adjacent active areas 11 .
  • the preparation of the source region 12 and the drain region 13 located in the active region 11 includes but is not limited to the following process: first, forming a patterned mask layer on the substrate; then, exposing the patterned mask layer The area of the active region 11 is subjected to a source/drain doping process to form a first doped region and a second doped region.
  • the first doped region can be used as the source region 12 of the transistor, and the second doped region can be used as the source region 12 of the transistor. Drain region 13 of the transistor.
  • the gate 15 may include a gate dielectric layer and a gate electrode layer covering the gate dielectric layer, wherein the gate dielectric layer may include silicon oxide, a high-k dielectric material, or a combination thereof.
  • the high-k dielectric material is defined as having a dielectric constant greater than A dielectric material of silicon oxide, the high-k dielectric layer includes metal oxide; the gate electrode layer may include a metal electrode and/or polysilicon.
  • the preparation of the gate 15 includes but is not limited to the following process: first, an in-situ water vapor oxidation method can be used to grow a gate oxide layer, such as a silicon oxide layer, and then a plasma nitridation method is used to dope the oxide layer interface to form SiON.
  • a post-nitridation annealing process is used to stabilize nitrogen doping and repair broken or missing bonds in the gate oxide region to form a gate dielectric layer; next, an atomic layer deposition, chemical vapor deposition or physical vapor deposition process is used to form a gate dielectric layer on the gate dielectric layer.
  • a gate electrode layer is deposited to cover the gate dielectric layer.
  • the gate electrode layer material may include a metal liner layer and a metal material located on the metal liner layer, wherein the material of the metal liner layer includes conductive metal-non-metal compounds, multi-component Compounds or alloys , such as TiN, TiSix , CoSix , NiSix or TiSixNy , metal materials include one of tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu) or their alloys wait.
  • the recess 16 in the first channel region 141 is recessed toward the center of the active region 11 along the first direction.
  • the boundary segment 17 between the source region 12 and the channel region 14; the first channel region 141 includes a first sub-region 141a; along the When the boundary line segment 17 is translated in the second direction, the boundary line segment 17 passes through the first sub-region 141 a and at least part of the recess 16 .
  • the boundary line segment 17 is a line segment where the interface between the source region 12 and the channel region 14 intersects with the upper surface of the active region 11
  • the first sub-region 141 a is the first channel region 141 along the first direction on both sides of the recess 16
  • the channel area does not exceed the opening of recess 16.
  • the extension length of the first channel region 141 along the first direction at the position of the recess 16 is smaller than the extension length of the source region 12 along the first direction. In this way, the translation of the boundary segment 17 along the second direction can pass through part or all of the depression 16 area.
  • the above embodiment further limits the overlap between the position of the recess 16 and the source region 12 in the second direction by arranging the boundary line segment 17 to translate along the second direction through the first sub-region 141a and at least part of the recess 16, which can Effectively isolate hot carriers, thereby suppressing hot electron-induced punch-through effects and avoiding or mitigating device performance degradation caused by hot electron-induced punch-through effects.
  • the manufacturing process of the semiconductor structure described in this embodiment is relatively simple and easy to manufacture.
  • the location of the recess 16 in the above embodiment is not the only limitation on the present disclosure.
  • the boundary line segment 17 when the boundary line segment 17 is parallelized along the second direction, the boundary line segment 17 passes through at least part of the first sub-region 141 a and does not pass through the depression 16 .
  • the extension length of the first channel region 141 along the first direction at the position of the recess 16 is greater than or equal to the extension length of the source region 12 along the first direction. In this way, the intersection line segment 17 will not pass through the depression 16 area when translated in the second direction.
  • the recess 16 is further away from the source region 12 and the drain region 13 in the first direction, This in turn can more effectively isolate hot carriers, thereby better suppressing hot electron-induced punch-through effects and avoiding or mitigating device performance degradation caused by hot electron-induced punch-through effects.
  • the isolation structure 10 includes a trench (not shown in the figures) and a first oxide layer 10 a covering the bottom and sidewalls of the trench, and the first oxide layer 10 a covers the bottom and sidewalls of the trench.
  • An oxide layer 10a is in contact with the first channel region 141, and the thickness of the first oxide layer 10a in the recess 16 is greater than that of the first oxide layer 10a except for the recess 16. thickness at other locations.
  • the ratio of the thickness of the first oxide layer 10a located in the recess 16 to the thickness of the first oxide layer 10a located outside the recess 16 is greater than 2, specifically, such as 2.5, 3 or 4, etc. .
  • the isolation structure of the transistor usually includes a first oxide layer, a nitride layer and a second oxide layer sequentially deposited on the sidewalls and bottom of the trench.
  • a nitride liner can regulate and improve the stress in the active area, thereby improving the characteristics of the transistor.
  • the electric field between the channels increases rapidly, which generates many hot electrons.
  • holes as carriers can collide with the lattice of the drain region to which a high electric field is applied, thereby generating electron-hole pairs and generating many hot electrons, which can be Trapped in the nitride layer in the isolation structure, the trapped electrons can attract holes with opposite types of charges due to electrical attraction.
  • the holes can be concentrated and charged to the edge of the channel region (also known as the "edge channel”). area”), resulting in a shorter effective channel length in the channel area, so hot electron-induced punch-through effects are prone to occur.
  • the thickness of the first oxide layer in the isolation structure at the recess is greater than the thickness at other locations except the recess, such that the recess is located at a position where the nitride layer on the outer layer of the first oxide layer is away from the edge of the channel region Further, therefore, the above-mentioned hot electron-induced punch-through caused by the capture of hot electrons by the nitride layer will be effectively improved, which can effectively avoid or reduce the device performance degradation caused by the hot electron-induced punch-through effect.
  • the first oxide layer 10a may include silicon oxide, and the preparation of the first oxide layer 10a includes using chemical vapor deposition, physical vapor deposition or thermal oxidation process. Due to the existence of the recess 16 in the first channel region 141, during the deposition process to form the first oxide layer 10a, a thicker first oxide layer 10a tends to be formed inside the recess 16.
  • the isolation structure 10 further includes a nitride layer 10b located in the trench and covering the first oxide layer 10a and a nitride layer 10b located in the trench and covering the first oxide layer 10a.
  • the second oxide layer 10c of the nitride layer 10b, the nitride layer 10b and the second oxide layer 10c are located outside the recess 16.
  • the nitride layer 10b includes but is not limited to silicon nitride material.
  • process parameters are controlled to completely fill the recess 16 with the first oxide layer 10 a , and then the preparation process of the nitride layer 10 b is performed, so that the nitride layer 10 b is located outside the recess 16 .
  • the isolation structure 10 may further include a second oxide layer 10c. The second oxide layer 10c covers the nitride layer 10b, and together with the nitride layer 10b and the first oxide layer 10a, forms the isolation structure 10.
  • the first oxide layer deposited at the recess completely covers the recess, and the nitride layer and the second oxide layer are located outside the recess, so that the nitride layer located outside the first oxide layer at the recess
  • the position is further away from the edge of the channel region, so the above-mentioned hot electron-induced punch-through caused by the capture of hot electrons by the nitride layer will be better improved, and thus the device performance degradation caused by the hot electron-induced punch-through effect can be better avoided or mitigated.
  • the nitride layer 10b may partially fill the recess 16.
  • the volume of the nitride layer 10b located in the recess 16 is equal to the volume of the nitride layer 10b located in the recess 16.
  • the volume ratio of the first oxide layer 10a should be less than 0.5.
  • the width of the interior of the recess 16 along the second direction is smaller than the width of the opening of the recess 16 along the second direction.
  • the width of the interior of the recess along the second direction is smaller than the width of the opening of the recess along the second direction, it is easier to completely complete the first oxide layer when depositing the first oxide layer of the isolation structure at the recess. Cover depressions.
  • the nitride layer located on the outer layer of the first oxide layer in the recess is further away from the edge of the channel region. Therefore, the above-mentioned hot electron-induced punch-through caused by the nitride layer capturing hot electrons will be better improved. Therefore, It can better avoid or mitigate device performance degradation caused by hot electron-induced punch-through effects.
  • the shape of the depression 16 may include but is not limited to a trapezoid, a triangle or a drop shape. It is understood that the depression 16 may also have other shapes, as long as the width of the interior of the depression 16 along the second direction is less than The width of the opening of the recess 16 along the second direction will not be exemplified one by one in this disclosure.
  • the first channel region 141 further includes a second sub-region 141 b located on a side of the recess 16 close to the drain region 13 , wherein, when the boundary line segment 17 of the source region 12 and the channel region 14 is translated along the second direction, the boundary line segment 17 does not pass through the second sub-region 141b.
  • the hot electron-induced punch-through effect is more likely to occur in the drain region.
  • a second sub-region is provided on the side of the first channel region located in the recess close to the drain region, so that the channel at the interface between the isolation structure and the channel region The length can be further increased to better suppress the hot electron-induced punch-through effect; in addition, the second sub-region is located outside the channel region between the source region and the drain region, which can isolate hot carriers to alleviate the problem.
  • the hot electron-induced punch-through effect can better avoid or alleviate the device performance degradation caused by the hot electron-induced punch-through effect.
  • the first channel region 141 further includes a third sub-region 141 c located on a side of the recess 16 close to the source region 12 , wherein when the boundary line segment 17 of the source region 12 and the channel region 14 is translated along the second direction, the boundary line segment 17 does not pass through the third sub-region 141c.
  • the above embodiment further forms a third sub-region in the first channel region on the side of the recess close to the source region, which further increases the channel length at the interface between the isolation structure and the channel region at the source region to further improve
  • the hot electron-induced punch-through effect at both ends of the source region and the drain region is well suppressed; in addition, the second sub-region and the third sub-region are located outside the channel region between the source region and the drain region. , can isolate hot carriers to alleviate the hot electron-induced punch-through effect, thereby better avoiding or mitigating the device performance degradation caused by the hot electron-induced punch-through effect.
  • the second sub-region 141b and the third sub-region 141c may have the same shape and area, so that the formation process is simpler.
  • the boundary line segment 17 between the source region 12 and the channel region 14 is translated in the second direction, and the boundary line segment 17 does not pass through the third sub-region 141c.
  • the second sub-region 141b and the third sub-region 141c can also have different shapes and areas.
  • the extension length of the second sub-region 141b near one end of the drain region 13 along the first direction is greater than the extension length of the third sub-region 141c near one end of the source region 12 along the first direction, thereby better protecting the heat that is more likely to occur.
  • the drain region 13 of the carrier punch-through effect takes into consideration the occupied area of the active region 11 .
  • the area of the orthographic projection of the second sub-region 141b and/or the third sub-region 141c on the plane of the substrate is smaller than the area of the orthographic projection of the depression 16 on the substrate plane.
  • the area of the orthographic projection of the second sub-region and/or the third sub-region on the substrate plane is smaller than the area of the orthographic projection of the recess on the substrate plane, that is, the area of the second sub-region and/or the third sub-region is relatively recessed.
  • the area is smaller, which can isolate hot carriers to alleviate the hot electron-induced punch-through effect, thereby avoiding or mitigating the device performance degradation caused by the hot electron-induced punch-through effect.
  • the extension length a of the recess 16 along the first direction is greater than the width b of the opening of the recess 16 along the second direction.
  • the extension length a of the recess along the first direction is greater than the width b of the opening of the recess along the second direction, that is, the channel region on both sides of the recess close to the source region and the drain region is elongated along the first direction.
  • Shape which can better isolate hot carriers and thus better alleviate hot electron-induced punch-through effects, thereby better avoiding or mitigating device performance degradation caused by hot electron-induced punch-through effects.
  • the recess 16 is too long and narrow.
  • the first oxide layer 10a and other layers of the isolation structure 10 it is difficult for the first oxide layer 10a and other layers of the isolation structure 10 to fill the recess 16. , it is easy to generate bubbles, voids and other problems, resulting in a decrease in the isolation effect of the isolation structure 10.
  • the ratio of a to b is too small, the opening of the recess 16 is too shallow, making it difficult to ensure that the first oxide formed in the recess 16
  • the ratio of the thickness of the layer 10a to the thickness of the first oxide layer 10a outside the recess 16 reduces the ability to mitigate the hot electron induced punch-through effect.
  • the ratio of the extension length a of the recess 16 along the first direction to the width b of the opening of the recess 16 along the second direction is preferably greater than 2 and less than 5, for example, 2.5, 3, 3.5, 4, 4.5, etc.
  • each independent interface between the first channel region 141 and the isolation structure 10 only includes one recess 16 .
  • a single interface may also include multiple depressions 16 .
  • the first channel region 141 and the isolation structure 10 include two separate interfaces, wherein at at least one of the interfaces, the third A channel region 141 includes a plurality of recesses 16 .
  • the size and shape of the plurality of recesses 16 can be the same, so that the formation process is relatively simple.
  • the plurality of recesses 16 may vary in size and shape.
  • the extension length of the recess 16 along the first direction gradually increases, thereby better protecting hot carriers that are more likely to pass through.
  • the effective drain region 13 can better avoid or alleviate device performance degradation caused by hot electron-induced punch-through effect.
  • the channel length at the interface between the isolation structure and the first channel region can be significantly increased to better suppress hot electron-induced punch-through. effect, thereby better avoiding or mitigating device performance degradation caused by hot electron-induced punch-through effects.
  • the first channel region 141 further includes a fourth sub-region 141d, and the fourth sub-region 141d is located between the adjacent recesses 16, wherein along the When the boundary line segment 17 of the source region 12 and the channel region 14 is translated in the second direction, the boundary line segment 17 does not pass through the fourth sub-region 141d.
  • the above embodiment further forms a fourth sub-region between adjacent recesses in the first channel region, which further increases the channel length at the interface between the isolation structure and the channel region to better suppress the hot electron-induced punch-through effect.
  • the fourth sub-region is located outside the channel area between the source region and the drain region, which can isolate hot carriers to alleviate the hot electron-induced punch-through effect, thereby better avoiding or mitigating hot electrons. Device performance degradation caused by induced punch-through effect.
  • the gate 15 further includes a first extension portion 152 protruding from the main body portion 151 , the first extension portion 152 extending along the second direction, and the first extension portion 152 extends along the second direction.
  • the extension part 152 is located on a side of the main body part 151 close to the drain region 13 .
  • the channel region 14 also includes a second channel region 142 .
  • the second channel region 142 is connected by the first extension part. 152 coverage.
  • the gate electrode has a first extension portion extending toward one side of the drain region along the second direction, and a second channel region is added to the channel region, so that the channel length at the interface between the isolation structure and the channel region is increased to suppress heat. Electron-induced punch-through effect. In addition, some hot electrons are guided to accumulate near the interface between the second channel region and the isolation structure, so the hot electron-induced punch-through effect can be further alleviated, thereby avoiding or mitigating device performance degradation caused by the hot electron-induced punch-through effect.
  • the boundary line segment 17 of the source region 12 and the channel region 14 when the boundary line segment 17 of the source region 12 and the channel region 14 is translated along the second direction, the boundary line segment 17 passes through the second trench. At least part of the track area 142.
  • the gate 15 further includes a third extension part 154 extending from the first extension part 152 , and the third extension part 154 may extend along the first direction.
  • the first extension part of the gate has a third extension part extending along the first direction, so that the channel length at the interface between the isolation structure and the channel region is further increased to better suppress the hot electron-induced punch-through effect.
  • some hot electrons are guided to accumulate near the interface between the channel area and the isolation structure under the third extension, so the hot electron-induced punch-through effect can be better alleviated, thereby avoiding or mitigating the device performance caused by the hot electron-induced punch-through effect. Degenerate.
  • the semiconductor structure in the above embodiment can be used in an integrated circuit.
  • one active area can have multiple transistor structures, such as two, because the above semiconductor structure has a transistor structure extending toward the drain along the second direction.
  • the first extension portion extending to one side of the region does not have an extension portion extending to one side of the source region along the first direction. Therefore, two transistor structures can share one source region, and two transistors located in one active region There is no need to reserve extra space for the distance between the gates of the structure, which can reduce the area occupied by the semiconductor structure, facilitate device shrinkage, and improve integration.
  • the gate 15 further includes a second extension 153 protruding from the main body 151 , and the second extension 153 is located near the source of the main body 151 .
  • the channel region 14 On one side of the region 12 , the channel region 14 further includes a third channel region 143 , and the third channel region 143 is covered by the second extension 153 .
  • the gate electrode has a second extension portion extending toward one side of the source region along the second direction, and a third channel region is added to the channel region, so that the channel length at the interface between the isolation structure and the channel region is further increased.
  • some hot electrons are guided to accumulate near the interface between the third channel region and the isolation structure, so the hot electron-induced punch-through effect can be better alleviated, thereby avoiding or mitigating the device performance degradation caused by the hot electron-induced punch-through effect.
  • the material of the first extension part 152 , the second extension part 153 and the third extension part 154 may be consistent with the material of the main body part 151 of the gate 15 .
  • the height of the third extension part 154 may also be consistent with the height of the main part 151 of the gate 15 , and the first extension part 152 and the second extension part 153 are electrically connected to the main part 151 of the gate 15 , and the third extension part 154 is electrically connected to the main part 151 of the gate 15 .
  • the first extension 152 is electrically connected.
  • the main body portion 151 , the first extension portion 152 , the second extension portion 153 and the third extension portion 154 of the gate 15 are integrally formed.
  • the material of the first extension part 152 , the second extension part 153 or the third extension part 154 may be different from the material of the main body part 151 of the gate 15 , for example, electrode materials with different work functions are used.
  • the gate 15 also includes a spacer structure covering the sidewalls of the gate 15 .
  • the spacer structure includes but is not limited to a stack composed of an oxide layer, a nitride layer, and an oxide layer.
  • the materials of the sidewall structures respectively covering the main body portion 151, the first extension portion 152, the second extension portion 153, and the third extension portion 154 may be different.
  • the second extension part 153 and the first extension part 152 may have the same shape and area, so that the formation process is simpler.
  • the width of the first extension 152 gradually decreases along the first direction
  • the width of the second extension portion 153 gradually decreases along the first direction
  • the first extension portion 152 and the second extension portion 153 cover at least part of the channel region 14 and At least part of the structure 10 is isolated, so that the first extension part 152 and the second extension part 153 increase the channel length at the edge of the channel region 14 to improve the hot electron-induced punch-through effect and avoid or mitigate the device performance caused by the hot electron-induced punch-through effect.
  • the conduction current will not be reduced too much, so it will have less impact on the conduction performance of the semiconductor device.
  • the second extension part 153 and the first extension part 152 may also have different shapes and areas.
  • the extension length of the first extension portion 152 near one end of the drain region 13 along the second direction is greater than the extension length of the second extension portion 153 near one end of the source region 12 along the second direction, thereby better protecting the heat that is more likely to occur.
  • the drain region 13 with carrier punch-through effect can better avoid or alleviate device performance degradation caused by hot electron-induced punch-through effect.
  • the boundary line segment 17 of the source region 12 and the first channel region 141 when the boundary line segment 17 of the source region 12 and the first channel region 141 is translated along the second direction, the boundary line segment 17 passes through the at least part of the third channel region 143 .
  • Embodiments of the present disclosure also provide a memory, which includes the semiconductor structure described in any one of the above embodiments.
  • the semiconductor structure provided by the embodiments of the present disclosure may be a dynamic random access memory (DRAM), but is not limited thereto, and the semiconductor structure may also be any other semiconductor device type.
  • DRAM dynamic random access memory
  • the present disclosure defines an active area through an isolation structure, wherein the active area includes a channel area, the transistor gate covers the channel area, the transistor gate includes a main body portion extending along the first direction, and the gate main body
  • the first channel region is covered directly below the first channel region, and the first channel region has a recess at the interface between the first channel region and the isolation structure.
  • the recessed design can extend the channel length at the interface between the isolation structure and the channel region to suppress hot electron-induced punch-through effects and avoid or mitigate device performance degradation caused by hot electron-induced punch-through effects.
  • the present disclosure defines an active area through an isolation structure, the active area includes a channel area, the transistor gate covers the channel area, the gate includes a main body portion extending along the first direction, and the first channel is covered directly below the main body portion of the gate electrode.
  • the first channel region has a recess at an interface between the first channel region and the isolation structure.
  • the recessed design can extend the channel length at the interface between the isolation structure and the channel region to suppress hot electron-induced punch-through effects and avoid or mitigate device performance degradation caused by hot electron-induced punch-through effects.

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Abstract

本公开实施例公开了一种半导体结构。所述半导体结构包括：衬底和位于所述衬底中的隔离结构，所述隔离结构在所述衬底中限定出有源区，所述有源区包括源极区、漏极区和沟道区；栅极，所述栅极覆盖所述沟道区；其中，所述栅极包括沿第一方向延伸的主体部，所述源极区和所述漏极区位于所述主体部在第二方向上的两侧，所述第二方向垂直于所述第一方向；所述沟道区包括位于所述主体部正下方的第一沟道区，在所述第一沟道区与所述隔离结构之间的界面处，所述第一沟道区具有凹陷。

Description

一种半导体结构及存储器
相关申请的交叉引用
本公开基于申请号为202211003680.3、申请日为2022年08月22日、发明名称为“一种半导体结构及存储器”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体结构及存储器。
背景技术
传统的场效应晶体管通常采用平面栅结构，其栅极结构与隔离结构具有交叉部分，随着半导体结构不断朝着小型化、高集成度的方向发展，晶体管沟道区之间的电场迅速增加，进而产生许多热电子。由于沟槽隔离结构具有俘获热电子的能力，电子积聚导致热电子诱导穿通(Hot Electron Induced Punch Through，HEIP)效应，使晶体管的关断特性劣化，降低半导体结构的性能。因此，如何改善热电子诱导穿通效应成为目前亟待解决的技术问题。
发明内容
有鉴于此，本公开实施例提供一种半导体结构及存储器。
根据本公开实施例的第一方面，提供了一种半导体结构，包括：
衬底和位于所述衬底中的隔离结构，所述隔离结构在所述衬底中限定出有源区，所述有源区包括源极区、漏极区和沟道区；
栅极，所述栅极覆盖所述沟道区；其中，
所述栅极包括沿第一方向延伸的主体部，所述源极区和所述漏极区位于所述主体部在第二方向上的两侧，所述第二方向垂直于所述第一方向；
所述沟道区包括位于所述主体部正下方的第一沟道区，在所述第一沟道区与所述隔离结构之间的界面处，所述第一沟道区具有凹陷。
在一些实施例中，所述源极区和所述沟道区之间具有交界线段；所述第一沟道区包括第一子区；在沿所述第二方向平移所述交界线段的情况下，所述交界线段经过所述第一子区以及所述凹陷的至少部分区域。
在一些实施例中，所述隔离结构包括沟槽以及覆盖所述沟槽的底部和侧壁的第一氧化物层，所述第一氧化物层与所述第一沟道区接触，且所述 第一氧化物层在所述凹陷中的厚度大于所述第一氧化物层在除所述凹陷之外的其他位置处的厚度。
在一些实施例中，所述隔离结构还包括位于所述沟槽中且覆盖所述第一氧化物层的氮化物层以及位于所述沟槽中且覆盖所述氮化物层的第二氧化物层，所述氮化物层与所述第二氧化物层位于所述凹陷之外。
在一些实施例中，所述凹陷的内部沿所述第二方向上的宽度小于所述凹陷的开口处沿所述第二方向上的宽度。
在一些实施例中，所述第一沟道区还包括第二子区，所述第二子区位于所述凹陷的靠近所述漏极区的一侧，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第二子区。
在一些实施例中，所述第一沟道区还包括第三子区，所述第三子区位于所述凹陷的靠近所述源极区的一侧，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第三子区。
在一些实施例中，所述第二子区和/或所述第三子区在所述衬底平面上的正投影的面积小于所述凹陷在所述衬底平面上的正投影的面积。
在一些实施例中，所述凹陷沿所述第一方向的延伸长度大于所述凹陷的开口处沿所述第二方向上的宽度。
在一些实施例中，所述第一沟道区与所述隔离结构之间包括两个分立的交界面，其中，在至少一个所述交界面处，所述第一沟道区包括多个所述凹陷。
在一些实施例中，所述第一沟道区还包括第四子区，所述第四子区位于相邻的所述凹陷之间，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第四子区。
在一些实施例中，所述栅极还包括从所述主体部突出的第一延伸部，所述第一延伸部沿所述第二方向延伸，所述第一延伸部位于所述主体部靠近所述漏极区的一侧，所述沟道区还包括第二沟道区，所述第二沟道区被所述第一延伸部覆盖。
在一些实施例中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段经过所述第二沟道区的至少部分区域。
在一些实施例中，所述栅极还包括从所述主体部突出的第二延伸部，所述第二延伸部位于所述主体部的靠近所述源极区的一侧，所述沟道区还包括第三沟道区，所述第三沟道区被所述第二延伸部覆盖。
在一些实施例中，在沿所述第二方向平移所述源极区与所述第一沟道区的交界线段的情况下，所述交界线段经过所述第三沟道区的至少部分区域。
根据本公开实施例的第二方面，提供了一种存储器，所述存储器包含 上述实施例中任一项所述的半导体结构。
本公开实施例提供了一种半导体结构，包括：衬底和位于所述衬底中的隔离结构，所述隔离结构在所述衬底中限定出有源区，所述有源区包括源极区、漏极区和沟道区；栅极，所述栅极覆盖所述沟道区；其中，所述栅极包括沿第一方向延伸的主体部，所述源极区和所述漏极区位于所述主体部在第二方向上的两侧，所述第二方向垂直于所述第一方向；所述沟道区包括位于所述主体部正下方的第一沟道区，在所述第一沟道区与所述隔离结构之间的界面处，所述第一沟道区具有凹陷。本公开通过隔离结构限定出有源区，有源区包括沟道区，晶体管栅极覆盖沟道区，栅极包括沿第一方向延伸的主体部，栅极主体部正下方覆盖第一沟道区，在第一沟道区与隔离结构之间的界面处，第一沟道区具有凹陷。凹陷设计可延长隔离结构与沟道区界面处的沟道长度，以抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。
本公开附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例中的一种交界线段经过第一子区以及凹陷的至少部分区域的半导体结构的俯视示意图；
图2为本公开实施例中的一种交界线段经过第一子区的至少部分区域，且不经过凹陷的半导体结构的俯视示意图；
图3为本公开实施例中的凹陷内未填充满第一氧化物层的半导体结构的俯视示意图；
图4为本公开实施例中的氮化物层与第二氧化物层位于凹陷之外的半导体结构的俯视示意图；
图5为本公开实施例中的第一沟道区包括第二子区的半导体结构的俯视示意图；
图6为本公开实施例中的第一沟道区还包括第三子区的半导体结构的俯视示意图；
图7为本公开实施例中的第一沟道区包括多个凹陷的半导体结构的俯视示意图；
图8为本公开实施例中的栅极包括主体部及第一延伸部的半导体结构的俯视示意图；
图9为本公开实施例中的栅极包括主体部及第一延伸部和第三延伸部 的半导体结构的俯视示意图；
图10为本公开实施例中的栅极包括主体部及第一延伸部和第二延伸部的半导体结构的俯视示意图。
附图标记：
10-隔离结构；10a-第一氧化物层；10b-氮化物层；10c-第二氧化物层；11-有源区；12-源极区；13-漏极区；14-沟道区；141-第一沟道区；141a-第一子区；141b-第二子区；141c-第三子区；141d-第四子区；142-第二沟道区；143-第三沟道区；15-栅极；151-主体部；152-第一延伸部；153-第二延伸部；154-第三延伸部；16-凹陷；17-交界线段；a-凹陷沿第一方向的延伸长度；b-凹陷的开口处沿第二方向上的宽度。
具体实施方式
下面将参照附图更详细地描述本公开公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开，而不应被这里阐述的具体实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开公开的范围完整的传达给本领域的技术人员。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了 图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
半导体结构制作中，通常在衬底上形成隔离结构以定义出有源区，隔离结构通常在浅沟槽内依次沉积氧化物层、氮化物层和氧化物层形成。随着半导体结构不断朝着小型化、高集成度的方向发展，晶体管沟道区之间的电场迅速增加，进而产生许多热电子，隔离结构中的氮化物层易俘获热电子，从而引起热电子诱导穿通效应，降低半导体结构的性能。
基于此，提出了本公开实施例的以下技术方案。下面结合附图对本公开的具体实施方式做详细的说明。本公开提供了一种半导体结构，图1-10是半导体结构的俯视示意图，结合图1-10所示，半导体结构包括：
衬底(图中未示出)和位于所述衬底中的隔离结构10，所述隔离结构10在所述衬底中限定出有源区11，所述有源区11包括源极区12、漏极区13和沟道区14；
栅极15，所述栅极15覆盖所述沟道区14；其中，
所述栅极15包括沿第一方向延伸的主体部151，所述源极区12和所述漏极区13位于所述主体部151在第二方向上的两侧，所述第二方向垂直于所述第一方向；
所述沟道区14包括位于所述主体部151正下方的第一沟道区141，在所述第一沟道区141与所述隔离结构10之间的界面处，所述第一沟道区141具有凹陷16。
本公开实施例位于栅极主体部正下方的第一沟道区具有凹陷，凹陷可延长隔离结构与沟道区界面处的沟道长度，以抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。
在实际操作中，本公开实施例提供的半导体结构可以是动态随机存取存储器(DRAM)，但不限于此，半导体结构还可以是任何其他半导体器件类型。
这里，衬底例如包括但不限于单质半导体材料衬底(例如为硅(Si)衬 底、锗(Ge)衬底等)、复合半导体材料衬底(例如为锗硅(SiGe)衬底等)，或绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底等。衬底可以是掺杂的或未掺杂的，或者在其中包含掺杂区域和未掺杂区域二者。衬底还可以包括一个或多个掺杂(n -或p -)区域；如果衬底包括多个掺杂区域，则这些区域可以具有相同或者不同的导电性和/或掺杂浓度。这些掺杂区域被称为“阱”，并且可以用于限定各个器件区域。在一具体实施例中，衬底为经掺杂或未经掺杂的硅衬底。在实际工艺中，隔离结构10的制备包括但不限于采用如下工艺：首先，采用光刻工艺在衬底上形成图形化的光刻胶层，而后以图形化的光刻胶层为掩膜，采用干法或湿法刻蚀工艺对衬底进行蚀刻形成浅沟槽，接着在浅沟槽中填充隔离材料形成隔离结构10，隔离结构10用于隔离相邻的有源区11。位于有源区11内的源极区12及漏极区13的制备包括但不限于采用如下工艺：首先，在衬底上形成图案化的掩膜层；然后，对图案化的掩膜层暴露出的有源区11的区域进行源/漏掺杂工艺，形成第一掺杂区与第二掺杂区，第一掺杂区可作为晶体管的源极区12，第二掺杂区可作为晶体管的漏极区13。
栅极15可以包括栅介质层和覆盖栅介质层的栅电极层，其中，栅介质层可以包括氧化硅、高k介电材料或它们的组合，高k介电材料被定义为介电常数大于氧化硅的介电材料，高k介质层包含金属氧化物；栅电极层可以包括金属电极和/或多晶硅。栅极15的制备包括但不限于采用如下工艺：首先，可采用原位水蒸气氧化方法生长栅氧化层，例如氧化硅层，而后，采用等离子氮化法对氧化层界面进行掺杂形成SiON，接着，利用氮化后退火工艺稳定氮掺杂以及修复栅氧区的断裂键或缺失键形成栅介质层；接下来，采用原子层沉积、化学气相沉积或物理气相沉积工艺，在栅介质层上沉积形成栅电极层覆盖栅介质层，栅电极层材料可包括金属衬垫层和位于金属衬垫层上的金属材料，其中金属衬垫层的材料包括具有导电性能的金属-非金属化合物、多元化合物或合金，例如TiN、TiSi x、CoSi x、NiSi x或TiSi xN y，金属材料包括钨(W)、钛(Ti)、钽(Ta)、铜(Cu)中的一种或其合金等。
在上述实施例中，参见图1和图2，第一沟道区141中的凹陷16沿第一方向向有源区11的中心位置处凹进。
在一些具体实施例中，如图1所示，所述源极区12和所述沟道区14之间具有交界线段17；所述第一沟道区141包括第一子区141a；在沿所述第二方向平移所述交界线段17的情况下，所述交界线段17经过所述第一子区141a以及所述凹陷16的至少部分区域。
这里，交界线段17为源极区12和沟道区14的交界面与有源区11上表面相交的线段，第一子区141a为第一沟道区141在凹陷16两侧沿第一方向不超过凹陷16开口的沟道区域。如图1所示，第一沟道区141在凹陷16的位置处，沿第一方向的延伸长度小于所述源极区12沿第一方向的延伸 长度。如此，交界线段17沿第二方向平移能够经过部分或者全部的凹陷16区域。
上述实施例通过设置交界线段17沿第二方向平移经过第一子区141a和凹陷16的至少部分区域，进一步限定凹陷16所在的位置与源极区12在第二方向上存在一定交叠，能够有效地隔离热载流子，从而抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。此外，这一实施例中所述的半导体结构制作工艺较为简单，便于生产制造。
应当理解的是，上述实施例中凹陷16的位置并非对本公开的唯一限制。在一些其他实施例中，如图2所示，在沿第二方向平移交界线段17的情况下，交界线段17经过第一子区141a的至少部分区域，且不经过凹陷16。
在该实施方式中，第一沟道区141在凹陷16的位置处，沿第一方向的延伸长度大于或等于源极区12沿第一方向的延伸长度。如此，交界线段17沿第二方向平移不会经过凹陷16区域。
通过设置交界线段17沿第二方向平移经过第一子区141a的至少部分区域，且不经过凹陷16，使得凹陷16在第一方向上距离源极区12及漏极区13的距离更远，进而能够更有效地隔离热载流子，因此可更好地抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些实施例中，参见图3和图4，所述隔离结构10包括沟槽(图中未示出)以及覆盖所述沟槽的底部和侧壁的第一氧化物层10a，所述第一氧化物层10a与所述第一沟道区141接触，且所述第一氧化物层10a在所述凹陷16中的厚度大于所述第一氧化物层10a在除所述凹陷16之外的其他位置处的厚度。
在一些具体实施例中，位于凹陷16中的第一氧化物层10a的厚度与位于凹陷16之外的第一氧化物层10a的厚度的比值大于2，具体的，例如2.5、3或4等。
晶体管的隔离结构通常包括在沟槽侧壁和底部依次沉积形成的第一氧化物层、氮化物层及第二氧化物层。使用氮化物衬垫能够调节改善有源区的应力，从而改善晶体管的特性。但随着半导体器件急剧缩小，沟道之间的电场迅速增加，会产生许多热电子。例如，在P沟道型场效应晶体管中，作为载流子的空穴可与施加了高电场的漏区的晶格碰撞，从而产生电子-空穴对而产生许多热电子，热电子可被捕获在隔离结构中的氮化物层中，被捕获的电子由于电吸引而可以吸引具有相反类型电荷的空穴，空穴可以集中并充入到沟道区边缘(也可称为“边缘沟道区”)，导致沟道区的有效沟道长度变短，因此很容易发生热电子诱导穿通效应。隔离结构中的第一氧化物层在凹陷处的厚度大于在除凹陷之外的其他位置处的厚度，进而使得凹陷处位于第一氧化物层外层的氮化物层距沟道区边缘的位置更远，因此上述因氮化物层捕获热电子导致的热电子诱导穿通会被有效地改善，即可有效避免或减轻热电子诱导穿通效应导致的器件性能退化。
在实际操作中，第一氧化物层10a可包括氧化硅，第一氧化物层10a的制备包括采用化学气相沉积、物理气相沉积或热氧化工艺。由于第一沟道区141中凹陷16的存在，在沉积形成第一氧化物层10a过程中，凹陷16内部倾向于形成更厚的第一氧化物层10a。
在一些具体实施例中，参见图4，所述隔离结构10还包括位于所述沟槽中且覆盖所述第一氧化物层10a的氮化物层10b以及位于所述沟槽中且覆盖所述氮化物层10b的第二氧化物层10c，所述氮化物层10b与所述第二氧化物层10c位于所述凹陷16之外。
在实际操作中，氮化物层10b包括但不限于氮化硅材料。在隔离结构10的制备工艺中，控制工艺参数将第一氧化物层10a完全填充凹陷16之后，再进行氮化物层10b的制备工艺，以使得氮化物层10b位于凹陷16之外。这里，隔离结构10还可以包括第二氧化物层10c，第二氧化物层10c覆盖氮化物层10b，与氮化物层10b及第一氧化物层10a共同构成隔离结构10。
在上述实施例中，凹陷处沉积的第一氧化物层完全覆盖凹陷，氮化物层与第二氧化物层位于凹陷之外，这使得在凹陷处位于第一氧化物层外层的氮化物层距沟道区边缘的位置更远，因此上述因氮化物层捕获热电子导致的热电子诱导穿通会得到更好地改善，因而能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
应当理解的是，该实施方式并非是对本公开的唯一限制，氮化物层10b可以部分填充凹陷16，在一些优选实施方式中，位于凹陷16中的氮化物层10b的体积与位于凹陷16中的第一氧化物层10a的体积比值应当小于0.5。
在一些实施例中，所述凹陷16的内部沿所述第二方向上的宽度小于所述凹陷16的开口处沿所述第二方向上的宽度。
通过将凹陷内部沿第二方向上的宽度设置为小于凹陷的开口处沿第二方向上的宽度，使得在凹陷处沉积隔离结构的第一氧化物层时，更容易使第一氧化物层完全覆盖凹陷。继而使得在凹陷处位于第一氧化物层外层的氮化物层距沟道区边缘的位置更远，因此上述因氮化物层捕获热电子导致的热电子诱导穿通会得到更好地改善，因而能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在实际操作中，凹陷16的形状可以包括但不限于梯形、三角形或者水滴形，可以理解的是，所述凹陷16还可以呈其他的形状，只要使凹陷16内部沿第二方向上的宽度小于凹陷16的开口处沿第二方向上的宽度，本公开不再一一举例。
在一些实施例中，参见图5，所述第一沟道区141还包括第二子区141b，所述第二子区141b位于所述凹陷16的靠近所述漏极区13的一侧，其中，在沿所述第二方向平移所述源极区12与所述沟道区14的交界线段17的情况下，所述交界线段17不经过所述第二子区141b。
热电子诱导穿通效应更易在漏极区发生，上述实施方式通过在第一沟 道区位于凹陷的靠近漏极区的一侧设置第二子区，使得隔离结构与沟道区界面处的沟道长度能够进一步增加，以更好地抑制热电子诱导穿通效应；此外，第二子区所在位置位于源极区与漏极区之间的沟道区域之外，能够隔离热载流子，以缓解热电子诱导穿通效应，进而能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些其他实施例中，参见图6，所述第一沟道区141还包括第三子区141c，所述第三子区141c位于所述凹陷16的靠近所述源极区12的一侧，其中，在沿所述第二方向平移所述源极区12与所述沟道区14的交界线段17的情况下，所述交界线段17不经过所述第三子区141c。
上述实施方式进一步在第一沟道区位于凹陷的靠近源极区的一侧形成第三子区，这使得源极区位置处隔离结构与沟道区界面处的沟道长度进一步增加，以更好地抑制源极区和漏极区两个端部的热电子诱导穿通效应；此外，第二子区与第三子区所在位置位于源极区与漏极区之间的沟道区域之外，能够隔离热载流子以缓解热电子诱导穿通效应，进而能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在实际操作中，第二子区141b与第三子区141c可以是相同的形状和面积，这样形成工艺较为简单。沿第二方向平移源极区12与沟道区14的交界线段17，交界线段17不经过第三子区141c。
可以理解的是，第二子区141b与第三子区141c也可以是不同的形状和面积。例如，靠近漏极区13一端的第二子区141b沿第一方向的延伸长度大于靠近源极区12一端的第三子区141c沿第一方向的延伸长度，从而更好地保护更易发生热载流子穿通效应的漏极区13，同时兼顾有源区11的占用面积。
在一些具体实施例中，参见图5和图6，所述第二子区141b和/或所述第三子区141c在所述衬底(图中未示出)平面上的正投影的面积小于所述凹陷16在所述衬底平面上的正投影的面积。
第二子区和/或第三子区在衬底平面上的正投影的面积小于凹陷在衬底平面上的正投影的面积，即第二子区和/或第三子区的面积相对凹陷的面积较小，这样能够隔离热载流子以缓解热电子诱导穿通效应，进而能够避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些具体实施例中，参见图6，所述凹陷16沿所述第一方向的延伸长度a大于所述凹陷16的开口处沿所述第二方向上的宽度b。
凹陷沿第一方向的延伸长度a大于凹陷的开口处沿第二方向上的宽度b，即沟道区在凹陷两侧靠近源极区与漏极区的沟道区域沿第一方向呈细长形状，这样能够更好地隔离热载流子因此可更好地缓解热电子诱导穿通效应，进而更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
当a与b的比值过大时，凹陷16太过狭长，在沉积第一氧化物层10a及隔离结构10的其他层时，第一氧化物层10a和隔离结构10的其他层难 以充满凹陷16，容易产生气泡、空隙等问题，导致隔离结构10的隔离效果下降，另一方面，当a与b的比值过小时，凹陷16的开口过浅，难以保证形成在凹陷16中的第一氧化物层10a的厚度与凹陷16之外的第一氧化物层10a的厚度比例，缓解热电子诱导穿通效应的能力下降。因此，在一些更具体的实施方式中，凹陷16沿所述第一方向的延伸长度a与凹陷16的开口处沿所述第二方向上的宽度b的比值优选为大于2小于5，例如，2.5、3、3.5、4、4.5等。
为方便对本公开实施例进行诠释，以上实施方式中涉及的附图中，第一沟道区141与隔离结构10的每一个独立的交界面仅包括一个凹陷16，然而，本公开实施方式中，一个独立的交界面也可以包括多个凹陷16。
例如，在一些实施例中，参见图7，所述第一沟道区141与所述隔离结构10之间包括两个分立的交界面，其中，在至少一个所述交界面处，所述第一沟道区141包括多个所述凹陷16。
在实际操作中，多个所述凹陷16的大小和形状可以相同，这样形成工艺较为简单。在一些其他实施例中，多个所述凹陷16的大小和形状可以不同。例如，在一具体实施例中，沿从源极区12指向漏极区13的方向，所述凹陷16沿第一方向的延伸长度逐渐增大，从而更好地保护更易发生热载流子穿通效应的漏极区13，能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
通过在第一沟道区与隔离结构之间的一个独立交界面设置多个凹陷，可以使得隔离结构与第一沟道区界面处的沟道长度显著增加，以更好地抑制热电子诱导穿通效应，进而更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些具体实施例中，参见图7，所述第一沟道区141还包括第四子区141d，所述第四子区141d位于相邻的所述凹陷16之间，其中，在沿所述第二方向平移所述源极区12与所述沟道区14的交界线段17的情况下，所述交界线段17不经过所述第四子区141d。
上述实施方式进一步在第一沟道区位于相邻的凹陷之间形成第四子区，这使得隔离结构与沟道区界面处的沟道长度进一步增加，以更好地抑制热电子诱导穿通效应；此外，第四子区所在位置位于源极区与漏极区之间的沟道区域之外，能够隔离热载流子以缓解热电子诱导穿通效应，进而能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些实施例中，参见图8，所述栅极15还包括从所述主体部151突出的第一延伸部152，所述第一延伸部152沿所述第二方向延伸，所述第一延伸部152位于所述主体部151靠近所述漏极区13的一侧，所述沟道区14还包括第二沟道区142，所述第二沟道区142被所述第一延伸部152覆盖。
栅极具有沿第二方向向漏极区一侧延伸的第一延伸部，沟道区增加了第二沟道区，这样使得隔离结构与沟道区界面处的沟道长度增加，以抑制 热电子诱导穿通效应。此外，部分热电子被引导在第二沟道区与隔离结构界面附近聚集，因此可进一步缓解热电子诱导穿通效应，进而避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些实施例中，参见图8，在沿所述第二方向平移所述源极区12与所述沟道区14的交界线段17的情况下，所述交界线段17经过所述第二沟道区142的至少部分区域。
在一些具体实施例中，参见图9，栅极15还包括从第一延伸部152延伸出的第三延伸部154，第三延伸部154可以沿第一方向进行延伸。
栅极的第一延伸部具有沿第一方向延伸的第三延伸部，这样使得隔离结构与沟道区界面处的沟道长度进一步增加，以更好地抑制热电子诱导穿通效应。此外，部分热电子被引导在第三延伸部下方的沟道区域与隔离结构的界面附近聚集，因此可更好地缓解热电子诱导穿通效应，进而避免或减轻热电子诱导穿通效应导致的器件性能退化。
上述实施例中的半导体结构，可用于集成电路中，为了提高集成电路的集成度，一个有源区中可具有多个晶体管结构，比如两个，由于上述半导体结构具有沿第二方向向漏极区一侧延伸的第一延伸部，不具有沿第一方向向源极区一侧延伸的延伸部，因此，两个晶体管结构可共用一个源极区，位于一个有源区中的两个晶体管结构的栅极之间的距离不用预留多余的位置，进而可减小半导体结构的占用面积，有利于器件的微缩，提高集成度。
在一些实施例中，参见图10，所述栅极15还包括从所述主体部151突出的第二延伸部153，所述第二延伸部153位于所述主体部151的靠近所述源极区12的一侧，所述沟道区14还包括第三沟道区143，所述第三沟道区143被所述第二延伸部153覆盖。
栅极具有沿第二方向向源极区一侧延伸的第二延伸部，沟道区增加了第三沟道区，这样使得隔离结构与沟道区界面处的沟道长度进一步增加，以更好地抑制热电子诱导穿通效应。此外，部分热电子被引导在第三沟道区与隔离结构界面附近聚集，因此可更好地缓解热电子诱导穿通效应，进而避免或减轻热电子诱导穿通效应导致的器件性能退化。
在上述实施例中，第一延伸部152、第二延伸部153和第三延伸部154的材料与栅极15的主体部151的材料可以一致，第一延伸部152、第二延伸部153和第三延伸部154的高度与栅极15的主体部151的高度也可以一致，并且第一延伸部152和第二延伸部153与栅极15的主体部151电连接，第三延伸部154与第一延伸部152电连接。可选的，栅极15的主体部151、第一延伸部152、第二延伸部153和第三延伸部154是一体形成的。
在一些其他实施例中，第一延伸部152、第二延伸部153或第三延伸部154的材料可以与栅极15的主体部151的材料不相同，例如采用不同功函数的电极材料。
在实际操作中，所述栅极15还包括覆盖栅极15侧壁的侧墙结构，侧墙结构包括但不限于氧化层、氮化层和氧化层构成的叠层。在一些实施方式中，分别覆盖主体部151、第一延伸部152、第二延伸部153和第三延伸部154的侧墙结构的材料可以不同。
在一些其他实施例中，第二延伸部153与第一延伸部152可以是相同的形状和面积，这样形成工艺较为简单。
在一些具体的实施例中，与第二方向平行且从源极区12指向漏极区13的方向上，第一延伸部152沿第一方向上的宽度逐渐减小，与第二方向平行且从漏极区13指向源极区12的方向上，第二延伸部153沿第一方向上的宽度逐渐减小，且第一延伸部152和第二延伸部153覆盖至少部分沟道区14及至少部分隔离结构10，从而使得第一延伸部152和第二延伸部153在增加沟道区14边缘的沟道长度以改善热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化的同时，不至于将导通电流下降的太多，因此对半导体器件的导通性能影响更小。
可以理解的是，第二延伸部153与第一延伸部152也可以是不同的形状和面积。例如，靠近漏极区13一端的第一延伸部152沿第二方向的延伸长度大于靠近源极区12一端的第二延伸部153沿第二方向的延伸长度，从而更好地保护更易发生热载流子穿通效应的漏极区13，能够更好地避免或减轻热电子诱导穿通效应导致的器件性能退化。
在一些具体实施例中，参见图10，在沿所述第二方向平移所述源极区12与所述第一沟道区141的交界线段17的情况下，所述交界线段17经过所述第三沟道区143的至少部分区域。
本公开实施例还提供了一种存储器，所述存储器包含上述实施例中任一项所述的半导体结构。
在实际操作中，本公开实施例提供的半导体结构可以是动态随机存取存储器(DRAM)，但不限于此，半导体结构还可以是任何其他半导体器件类型。
综上所述，本公开通过隔离结构限定出有源区，其中，有源区包括沟道区，晶体管栅极覆盖沟道区，晶体管栅极包括沿第一方向延伸的主体部，栅极主体部的正下方覆盖第一沟道区，在第一沟道区与隔离结构之间的界面处，第一沟道区具有凹陷。凹陷设计可延长隔离结构与沟道区界面处的沟道长度，以抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。
需要说明的是，本公开实施例提供的半导体结构可以应用于任何包括该结构的集成电路中。各实施例所记载的技术方案中各技术特征之间，在不冲突的情况下，可以任意组合。
以上所述，仅为本公开的较佳实施例而已，并非用于限定本公开的保护范围，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进 等，均应包含在本公开的保护范围之内。
工业实用性
本公开通过隔离结构限定出有源区，有源区包括沟道区，晶体管栅极覆盖沟道区，栅极包括沿第一方向延伸的主体部，栅极主体部正下方覆盖第一沟道区，在第一沟道区与隔离结构之间的界面处，第一沟道区具有凹陷。凹陷设计可延长隔离结构与沟道区界面处的沟道长度，以抑制热电子诱导穿通效应，避免或减轻热电子诱导穿通效应导致的器件性能退化。

Claims (16)

  1. 一种半导体结构，包括：
    衬底和位于所述衬底中的隔离结构，所述隔离结构在所述衬底中限定出有源区，所述有源区包括源极区、漏极区和沟道区；
    栅极，所述栅极覆盖所述沟道区；其中，
    所述栅极包括沿第一方向延伸的主体部，所述源极区和所述漏极区位于所述主体部在第二方向上的两侧，所述第二方向垂直于所述第一方向；
    所述沟道区包括位于所述主体部正下方的第一沟道区，在所述第一沟道区与所述隔离结构之间的界面处，所述第一沟道区具有凹陷。
  2. 根据权利要求1所述的半导体结构，其中，
    所述源极区和所述沟道区之间具有交界线段；
    所述第一沟道区包括第一子区；
    在沿所述第二方向平移所述交界线段的情况下，所述交界线段经过所述第一子区以及所述凹陷的至少部分区域。
  3. 根据权利要求1所述的半导体结构，其中，
    所述隔离结构包括沟槽以及覆盖所述沟槽的底部和侧壁的第一氧化物层，所述第一氧化物层与所述第一沟道区接触，且所述第一氧化物层在所述凹陷中的厚度大于所述第一氧化物层在除所述凹陷之外的其他位置处的厚度。
  4. 根据权利要求3所述的半导体结构，其中，
    所述隔离结构还包括位于所述沟槽中且覆盖所述第一氧化物层的氮化物层以及位于所述沟槽中且覆盖所述氮化物层的第二氧化物层，所述氮化物层与所述第二氧化物层位于所述凹陷之外。
  5. 根据权利要求1所述的半导体结构，其中，
    所述凹陷的内部沿所述第二方向上的宽度小于所述凹陷的开口处沿所述第二方向上的宽度。
  6. 根据权利要求2所述的半导体结构，其中，
    所述第一沟道区还包括第二子区，所述第二子区位于所述凹陷的靠近所述漏极区的一侧，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第二子区。
  7. 根据权利要求6所述的半导体结构，其中，
    所述第一沟道区还包括第三子区，所述第三子区位于所述凹陷的靠近所述源极区的一侧，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第三子区。
  8. 根据权利要求7所述的半导体结构，其中，
    所述第二子区和/或所述第三子区在所述衬底平面上的正投影的面积小于所述凹陷在所述衬底平面上的正投影的面积。
  9. 根据权利要求8所述的半导体结构，其中，
    所述凹陷沿所述第一方向的延伸长度大于所述凹陷的开口处沿所述第二方向上的宽度。
  10. 根据权利要求9所述的半导体结构，其中，
    所述第一沟道区与所述隔离结构之间包括两个分立的交界面，其中，在至少一个所述交界面处，所述第一沟道区包括多个所述凹陷。
  11. 根据权利要求10所述的半导体结构，其中，
    所述第一沟道区还包括第四子区，所述第四子区位于相邻的所述凹陷之间，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段不经过所述第四子区。
  12. 根据权利要求1所述的半导体结构，其中，
    所述栅极还包括从所述主体部突出的第一延伸部，所述第一延伸部沿所述第二方向延伸，所述第一延伸部位于所述主体部靠近所述漏极区的一侧，所述沟道区还包括第二沟道区，所述第二沟道区被所述第一延伸部覆盖。
  13. 根据权利要求12所述的半导体结构，其中，在沿所述第二方向平移所述源极区与所述沟道区的交界线段的情况下，所述交界线段经过所述第二沟道区的至少部分区域。
  14. 根据权利要求13所述的半导体结构，其中，
    所述栅极还包括从所述主体部突出的第二延伸部，所述第二延伸部位于所述主体部的靠近所述源极区的一侧，所述沟道区还包括第三沟道区，所述第三沟道区被所述第二延伸部覆盖。
  15. 根据权利要求14所述的半导体结构，其中，在沿所述第二方向平移所述源极区与所述第一沟道区的交界线段的情况下，所述交界线段经过所述第三沟道区的至少部分区域。
  16. 一种存储器，包括如权利要求1-15中任一项所述的半导体结构。
PCT/CN2022/115543 2022-08-22 2022-08-29 一种半导体结构及存储器 WO2024040622A1 (zh)

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