WO2024036747A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2024036747A1
WO2024036747A1 PCT/CN2022/126965 CN2022126965W WO2024036747A1 WO 2024036747 A1 WO2024036747 A1 WO 2024036747A1 CN 2022126965 W CN2022126965 W CN 2022126965W WO 2024036747 A1 WO2024036747 A1 WO 2024036747A1
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WIPO (PCT)
Prior art keywords
substrate
along
trench
semiconductor structure
bit line
Prior art date
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Ceased
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PCT/CN2022/126965
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English (en)
French (fr)
Inventor
蒋懿
韩清华
肖德元
邱云松
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US18/536,586 priority Critical patent/US20240155834A1/en
Publication of WO2024036747A1 publication Critical patent/WO2024036747A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the present disclosure relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method of forming the same.
  • DRAM Dynamic Random Access Memory
  • each storage unit usually includes a transistor and a capacitor.
  • the gate of the transistor is electrically connected to the word line
  • the source is electrically connected to the bit line
  • the drain is electrically connected to the capacitor.
  • the word line voltage on the word line can control the turning on and off of the transistor, so that the memory can be read through the bit line. Data information in the capacitor, or writing data information into the capacitor.
  • Buried bit line structures are often used in semiconductor structures such as DRAM.
  • the formation rate of the bit line structure in the horizontal direction is greater than the formation rate in the vertical direction, resulting in the formation of
  • the thickness of the buried bit line structure is thin, and the thin buried bit line structure has a large resistance, thereby reducing the electrical performance of semiconductor structures such as DRAM.
  • the semiconductor structure and its formation provided by some embodiments of the present disclosure are used to reduce the resistance of the buried bit line, thereby improving the electrical performance of the semiconductor structure.
  • the present disclosure provides a method for forming a semiconductor structure, including the following steps:
  • the substrate under the active area is modified from a side surface of the substrate to form a plurality of active areas extending along the first direction and arranged at intervals along the first direction.
  • the bit line to which the source region is electrically connected is modified from a side surface of the substrate to form a plurality of active areas extending along the first direction and arranged at intervals along the first direction.
  • the specific steps of forming a substrate and a plurality of active regions located above the substrate and spaced along the first direction include:
  • the specific steps of forming a plurality of first trenches spaced apart along the first direction include:
  • the initial substrate remaining under the trench and the semiconductor layer serves as the substrate, wherein the second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction.
  • the following steps are further included:
  • a first protective layer covering the first trench sidewall in the semiconductor layer is formed.
  • the specific steps of modifying the substrate below the active area from the side of the substrate include:
  • the substrate under the active area is modified along a second direction.
  • the specific steps of modifying the substrate under the active area along the second direction include:
  • the substrate under the active area is modified simultaneously from two opposite sides of the substrate along the second direction.
  • the depth of the second trench is greater than the depth of the first trench along a third direction, wherein the third direction is perpendicular to the top surface of the substrate; from the The specific steps of modifying the side surface of the substrate below the active area include:
  • the substrate under the active area is modified along the etching groove.
  • the following steps are further included:
  • a second protective layer covering the first trench sidewall in the isolation layer is formed.
  • the specific steps of forming an etching trench located under the first trench in the isolation layer include:
  • the etching rate is to form the etching groove extending along the first direction in the isolation layer and continuously connecting a plurality of the first trenches spaced apart along the first direction.
  • the specific steps of forming an etching trench located under the first trench in the isolation layer include:
  • a selective etching process is used to etch the isolation layer below the first trench along the first trench to form a continuous connection along the first direction in the isolation layer.
  • the etching grooves include a plurality of first trenches arranged at intervals in the first direction.
  • the specific steps of forming an etching trench located under the first trench in the isolation layer include:
  • a wet etching process is used to etch the isolation layer below the first trench along the first trench to form a layer extending along the first direction in the isolation layer and having a continuous connection along all directions.
  • the etching grooves include a plurality of first trenches arranged at intervals in the first direction.
  • the modification process is a metal silicidation process or a doping ion implantation process.
  • the substrate under the active region is modified along the etching groove:
  • the substrate is annealed to form the bit line.
  • the metal material is one or more of Ti, Co, Mo, Ni or Sn.
  • the specific steps of annealing the substrate below the active region include:
  • the following steps are further included:
  • a dielectric layer is formed that fills the first trench in the isolation layer, and the etching trench remaining under the dielectric layer serves as an air gap between adjacent bit lines.
  • the following steps are further included:
  • a dielectric layer filling the first trench and the etching trench in the isolation layer is formed.
  • the present disclosure also provides a semiconductor structure, including:
  • a bit line is located on the substrate and extends along a first direction, wherein the first direction is parallel to the top surface of the substrate;
  • a plurality of active areas are located above the bit line, and a plurality of the active areas are arranged at intervals along the first direction.
  • the bit line is continuously connected to the plurality of active areas arranged at intervals along the first direction.
  • the source area is electrically connected, and the thickness of the bit line is evenly distributed in the first direction.
  • a plurality of the bit lines are spaced apart along a second direction, wherein the second direction is parallel to the top surface of the substrate, and the first direction intersects the second direction;
  • the semiconductor structure also includes:
  • An isolation layer is located between the bit lines spaced apart along the second direction, and in the third direction, the bottom surface of the isolation layer is located below the bottom surface of the bit lines, wherein the third The direction is perpendicular to the top surface of the substrate.
  • it also includes:
  • the air gap is located in the isolation layer and extends along the first direction.
  • the air gap is aligned with the bit line.
  • the top surface of the air gap is flush with the top surface of the bit line, and the bottom surface of the air gap is flush with the bottom surface of the bit line;
  • the length of the air gap is equal to the length of the bit line.
  • it also includes:
  • a dielectric layer is located in the isolation layer and extends along the first direction.
  • the dielectric layer is aligned with the bit line.
  • the top surface of the dielectric layer is flush with the top surface of the bit line, and the bottom surface of the dielectric layer is flush with the bottom surface of the bit line;
  • the length of the dielectric layer is equal to the length of the bit line.
  • the bit line is made of a metal suicide material or a silicon material including doped ions.
  • the bit line has a thickness of 5 nm to 50 nm.
  • the semiconductor structure and its formation method provided by some embodiments of the present disclosure form bit lines by modifying the substrate below the active area from the side of the substrate, which can make the thickness distribution of the formed bit lines uniform, and can Forming a thicker bit line can effectively reduce the resistance of the bit line and make the thickness of the bit line uniform in its extension direction, thereby improving the electrical performance of the semiconductor structure.
  • Other embodiments of the present disclosure simultaneously modify the substrate below the active area from opposite sides of the active area along the second direction, which can not only improve the formation efficiency of the bit lines, but also The uniformity of the bit line thickness distribution is further improved, thereby further improving the electrical performance of the semiconductor structure.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure
  • FIG. 2 is a schematic top view of a semiconductor structure formed according to specific embodiments of the present disclosure.
  • 3-6 are schematic cross-sectional views of main processes in the process of forming a semiconductor structure according to specific embodiments of the present disclosure.
  • FIG. 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure.
  • FIG. 2 is a top structural schematic diagram of a semiconductor structure formed in a specific embodiment of the present disclosure.
  • FIG. 3- is a schematic cross-sectional view of the main process in the process of forming a semiconductor structure according to the specific embodiment of the present disclosure.
  • 3 to 6 are main process cross-sectional schematic diagrams of the four positions a-a, b-b, c-c and d-d in the formation process of the semiconductor structure in FIG. 2 to clearly illustrate the formation process of the semiconductor structure. .
  • the method for forming the semiconductor structure includes the following steps:
  • Step S11 forming a substrate 22 and a plurality of active regions 20 located above the substrate 22 and arranged at intervals along a first direction D1 , wherein the first direction D1 is in contact with the top surface of the substrate 22 parallel;
  • Step S12 Modify the substrate 22 below the active area 20 from the side of the substrate 22 to form a shape extending along the first direction D1 and spaced apart from the substrate 22 along the first direction D1.
  • a plurality of arranged active areas 20 are electrically connected to bit lines 21, as shown in FIGS. 2 and 6 .
  • the specific steps of forming the substrate 22 and a plurality of active regions 20 located above the substrate 22 and arranged at intervals along the first direction D1 include:
  • the initial substrate is etched to form a plurality of first trenches 31 spaced apart along the first direction D1, and the remaining initial substrate between adjacent first trenches 31 serves as the active area. 20.
  • the initial substrate remaining under the first trench 31 and the active area 20 serves as the substrate 22.
  • the semiconductor structure formed in this specific embodiment may be, but is not limited to, a DRAM.
  • the initial substrate may be, but is not limited to, a silicon substrate.
  • This specific embodiment will be described by taking the initial substrate as a silicon substrate as an example.
  • the initial substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI.
  • the specific steps of forming a plurality of first trenches 31 spaced apart along the first direction D1 include:
  • the initial substrate is etched to form a plurality of second trenches arranged at intervals along the second direction D2, and the initial substrate remaining between adjacent second trenches serves as a semiconductor layer.
  • the initial substrate remaining under the trench and the semiconductor layer serves as the substrate 22 , wherein the second direction D2 is parallel to the top surface of the substrate 22 , and the first direction D1 is parallel to the top surface of the substrate 22 .
  • the second direction D2 intersects;
  • the semiconductor layer and the isolation layer 24 are etched to form a plurality of first trenches 31 spaced apart along the first direction D1.
  • the semiconductor layer serves as the active region 20, as shown in Figures 2 and 3.
  • a photolithography process may be used to first etch the initial substrate along the first direction D1 to form a plurality of holes extending along the first direction D1 and not penetrating the initial substrate along the third direction.
  • the second grooves, and a plurality of the second grooves are arranged at intervals along the second direction D2.
  • the initial substrate remaining between adjacent second trenches serves as a semiconductor layer, and the initial substrate remaining under the second trench and the semiconductor layer as the substrate 22.
  • the third direction D3 is perpendicular to the top surface of the substrate 22 .
  • the top surface of the substrate 22 mentioned in this specific embodiment refers to the surface of the substrate 22 facing the active area 20 .
  • the intersection described in this specific embodiment may be a vertical intersection (that is, an orthogonal intersection) or a horizontal intersection.
  • a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process may be used to deposit an insulating dielectric material such as an oxide material (such as silicon dioxide) in the second trench to form a process that fills the second trench. of the isolation layer 24.
  • an insulating dielectric material such as an oxide material (such as silicon dioxide)
  • a patterned mask layer is formed on the initial substrate.
  • the patterned mask layer is located on the semiconductor layer and the isolation layer 24 , and the mask layer 24 has an exposed portion of the The semiconductor layer and part of the isolation layer 24 are etched windows.
  • the semiconductor layer and the isolation layer 24 are etched downward along the etching window in the mask layer 24 to form a plurality of first trenches spaced apart along the first direction D1 Groove 31, the first groove 31 extends along the second direction D2, and the remaining semiconductor layer between adjacent first grooves 31 serves as the active region 20, as shown in Figures 2 and 3 shown.
  • the depth of the first trench 31 is less than the depth of the isolation layer 24, that is, the top surface of the first trench 31 is located above the top surface of the isolation layer 24. .
  • those skilled in the art can set the specific value of the depth difference between the first trench 31 and the isolation layer 24 along the third direction D3 according to actual needs, for example, according to the subsequent need to form the bit line.
  • the thickness of 21 is determined.
  • the material of the mask layer 24 is a nitride material (such as silicon nitride).
  • a first protective layer 40 covering the sidewalls of the first trench 31 in the semiconductor layer is formed, as shown in FIG. 4 .
  • a nitride material such as silicon nitride
  • a nitride material may be first deposited on the entire inner wall of the first trench 31 in the semiconductor layer (including the sides of the first trench 31 in the semiconductor layer). wall and bottom wall) to form the first protective layer 40.
  • the first semiconductor layer 40 on the bottom wall of the first trench 31 in the semiconductor layer is etched back to expose the substrate 22 below the first trench 31 .
  • the first protective layer 40 covering the sidewalls of the first trench 31 is used to protect the sidewalls of the active area 20 and avoid damage to the active area 20 during the subsequent process of forming the bit line 21 . damage, thereby further ensuring the electrical performance of the semiconductor structure.
  • the material of the first protective layer 40 is a nitride material (such as silicon nitride).
  • the material of the first protective layer 40 can also be other insulating dielectric materials, as long as a high etching selectivity ratio between the first protective layer 40 and the substrate 22 is ensured. Can. In an example, the etching selectivity ratio between the first protective layer 40 and the substrate 22 is greater than 3.
  • the specific steps of modifying the substrate 22 below the active area 20 from the side of the substrate 22 include:
  • the substrate 22 under the active area 20 is modified along the second direction D2.
  • the pre-formed bit line 21 extends along the first direction D1, and the second direction D2 modifies the substrate 22 below the active area 20. This process can not only improve the formation efficiency of the bit line 21, but also further improve the thickness uniformity of the bit line 21 along the second direction D2.
  • the specific steps of modifying the substrate 22 under the active area 20 along the second direction D2 include:
  • the substrate 22 below the active area 20 is modified simultaneously from two opposite sides of the substrate 22 along the second direction D2.
  • the depth of the second trench is greater than the depth of the first trench 31 along the third direction D3, where the third direction D3 is in contact with the top surface of the substrate 22 Vertically; the specific steps of modifying the substrate 22 below the active area 20 from the side of the substrate 22 include:
  • the isolation layer 24 below the first trench 31 is etched along the first trench 31 to form an etching groove 50 below the first trench 31 in the isolation layer 24 , as shown in FIG. As shown in 5;
  • the substrate 22 under the active area 20 is modified along the etching groove 50 .
  • the following steps are further included:
  • a second protective layer 41 covering the sidewalls of the first trench 31 in the isolation layer 24 is formed, as shown in FIG. 4 .
  • the first protective layer 40 covering the sidewalls of the first trench 31 in the semiconductor layer may be formed at the same time as forming the first protective layer 40 covering the sidewalls of the first trench 31 in the semiconductor layer.
  • the second protective layer 41 on the sidewall of the first trench 31 in the isolation layer 24 may be deposited on the entire inner walls of all first trenches 31 (including the sidewalls and bottom walls of the first trench 31).
  • the nitride material located on the bottom wall of the first trench 31 is etched back, and the nitride material remaining on the side wall of the first trench 31 in the semiconductor layer is used as the In the first protective layer 40 , the nitride material remaining on the sidewall of the first trench 31 in the isolation layer 24 serves as the second protective layer 41 .
  • the second protective layer 41 protects the sidewalls of the first trench 31 and prevents damage to the sidewalls of the first trench 31 during the subsequent process of forming the etching trench 50 .
  • the specific steps of forming the etching trench 50 below the first trench 31 in the isolation layer 24 include:
  • the isolation layer 24 below the first trench 31 is anisotropically etched along the first trench 31 , so that the etching rate of the isolation layer 24 along the first direction D1 is greater than that along the first direction D1 .
  • the etching rate in the third direction D3 forms a plurality of first trenches 31 extending along the first direction D1 and continuously connected in the isolation layer 24 and arranged at intervals along the first direction D1.
  • the etching groove 50 is
  • the etching rate of the isolation layer 24 along the first direction D1 can be adjusted by selecting a suitable etchant or adjusting etching parameters (such as etching temperature, etching pressure, plasma concentration, etc.) is greater than the etching rate along the third direction D3, so that the formed etching groove 50 can continuously communicate with the plurality of first trenches 31 spaced apart along the first direction D1. It will penetrate the isolation layer 24 along the third direction D3 to avoid damage to the substrate 22 below the isolation layer 24 .
  • Those skilled in the art can control the depth of the etching groove 50 along the third direction according to actual needs, for example, by controlling etching time, etchant dosage and other etching parameters, so that the subsequently formed bits can be flexibly adjusted.
  • the specific steps of forming the etching trench 50 located under the first trench 31 in the isolation layer 24 include:
  • a selective etching process is used to etch the isolation layer 24 below the first trench 31 along the first trench 31 to form in the isolation layer 24 extending along the first direction D1. And the etching grooves 50 of the plurality of first trenches 31 arranged at intervals along the first direction D1 are continuously connected.
  • the isolation layer 24 below the first trench 31 along the first trench 31 in order to use a selective etching process to etch the isolation layer 24 below the first trench 31 along the first trench 31, so that all the isolation layers 24 below the first trench 31 are etched.
  • the etching amount of the isolation layer 24 along the first direction D1 is greater than the etching amount of the isolation layer 24 along the third direction D3, so that the formed etching groove 50 can be continuously connected along the
  • the plurality of first trenches 31 spaced apart in the first direction D1 will not penetrate the isolation layer 24 along the third direction D3 to avoid damaging the substrate 22 below the isolation layer 24 cause damage.
  • the specific steps of forming the etching trench 50 located under the first trench 31 in the isolation layer 24 include:
  • a wet etching process is used to etch the isolation layer 24 below the first trench 31 along the first trench 31 to form in the isolation layer 24 extending along the first direction D1. And the etching grooves 50 of the plurality of first trenches 31 arranged at intervals along the first direction D1 are continuously connected.
  • a wet etching process may be used to etch the first trench 31 along the first trench 31 .
  • the isolation layer 24 below the first trench 31 is etched to simplify the formation process of the etching trench 50 .
  • the etching groove 50 formed can continuously connect multiple plurality of spaces arranged at intervals along the first direction D1.
  • the first trench 31 will not penetrate the isolation layer 24 along the third direction D3 to avoid damage to the substrate 22 below the isolation layer 24 .
  • the length of the etching groove 50 along the first direction D1 is greater than or equal to the length of the semiconductor layer along the first direction D1 , thereby ensuring that all the holes formed by the etching groove 50 are equal to the length of the semiconductor layer along the first direction D1 .
  • the bit line 21 can be electrically connected to a plurality of active areas 20 arranged at intervals along the first direction D1.
  • the width of the etching groove 50 along the second direction D2 may be less than or equal to the width of the isolation layer 24 along the second direction D2, so as to avoid damage to the active region 20 while increasing the Large process window for the modification treatment.
  • the modification process is to modify a portion of the substrate 22 below the active area 20, thereby enhancing the conductivity of the modified portion of the substrate 22 to form a conductor along the first
  • a plurality of the active areas 20 arranged at intervals in the direction D1 are electrically connected to the bit lines 21 .
  • the modification process is a metal silicidation process or a doping ion implantation process.
  • the substrate 22 under the active region 20 is modified along the etching groove 50:
  • the substrate 22 is annealed to form the bit line 21 .
  • the metal material is one or more of Ti, Co, Mo, Ni or Sn.
  • the metal material when the metal material is Ti, it can be deposited using a chemical vapor deposition process; when the metal material is Co, it can be deposited using an atomic layer deposition process.
  • the specific steps of annealing the substrate 22 below the active region 20 include:
  • the initial bit line is annealed for a second time at a second temperature to form the bit line 21 , wherein the second temperature is higher than the first temperature.
  • the modification process is a metal silicide formation process and the annealing process is rapid thermal annealing (Rapid Thermal Processing, RTP).
  • RTP Rapid Thermal Processing
  • the etching groove 50 exposes opposite side walls of the substrate 22 below the active region 20 along the second direction D2.
  • a chemical vapor deposition process may be used to deposit metal Ti along the etching trench 50 on the opposite side of the substrate 22 below the active region 20 along the second direction D2. on both side walls.
  • an atomic layer deposition process is used to deposit metal Co along the etching trench 50 on the opposite side walls of the substrate 22 below the active area 20 along the second direction D2.
  • the substrate 22 is subjected to a first annealing process at a lower first temperature, so that the metal material reacts with the silicon material in the substrate 22 to form a high-resistance metal silicide material. , and use high-resistance metal silicide material as the initial bit line.
  • the metal material that does not participate in the reaction is etched to remove, and the initial bit line is annealed for a second time at a higher second temperature to form the bit line 21 with low resistance.
  • the first temperature is 500°C-700°C
  • the second temperature is 850°C-100°C.
  • This specific embodiment is described by taking two low-temperature and high-temperature annealing treatments as an example. In other specific implementations, only one annealing process may be performed to simplify the formation process of the semiconductor structure.
  • bit line 21 After forming the bit line 21, the following steps are also included:
  • a dielectric layer is formed that fills the first trench 31 in the isolation layer 24 , and the etching groove 50 remaining under the dielectric layer serves as an air gap between adjacent bit lines 21 .
  • the dielectric layer only fills the first trench 31 in the isolation layer 24 , and the etching trench serves as the air gap between adjacent bit lines 21 , so that air can be utilized.
  • the low dielectric constant further enhances the electrical isolation effect between adjacent bit lines 21 .
  • the material of the dielectric layer may be an oxide material (such as silicon dioxide).
  • a dielectric layer filling the first trench 31 and the etching trench 50 in the isolation layer 24 is formed.
  • a channel region may be defined in the active region 20 , and sources distributed on opposite sides of the channel region along the third direction D3 may be defined. electrode region and drain region, and the source region is electrically connected to the bit line 21 .
  • conductive material such as TiN or metal tungsten is deposited along the first trench 21 to form a word line 30 covering the channel region.
  • the word line 30 extends along the second direction D2 and continuously covers the channel areas in the plurality of active areas 20 that are spaced along the second direction D2. And the plurality of word lines 30 are arranged at intervals along the first direction D1.
  • a capacitor electrically connected to the drain region may be formed above the drain region.
  • This embodiment also provides a semiconductor structure.
  • the semiconductor structure provided by this embodiment can be formed using the semiconductor structure forming method shown in FIGS. 1 to 6 .
  • the schematic diagrams of the semiconductor structure provided in this specific embodiment can be seen in FIG. 2 and FIG. 6 .
  • the semiconductor structure includes:
  • the bit line 21 is located on the substrate 22 and extends along the first direction D1, where the first direction D1 is parallel to the top surface of the substrate 22;
  • a plurality of active areas 20 are located above the bit lines 21, and the plurality of active areas 20 are arranged at intervals along the first direction D1.
  • the bit lines 21 are continuously arranged and at intervals along the first direction D1.
  • a plurality of active areas 20 are electrically connected, and the thickness of the bit lines 21 is evenly distributed in the first direction D1.
  • the semiconductor structure formed in this specific embodiment may be, but is not limited to, a DRAM.
  • the following description takes the semiconductor structure as a DRAM as an example.
  • the substrate 22 may be, but is not limited to, a silicon substrate. This specific embodiment will be described by taking the substrate 22 as a silicon substrate as an example.
  • the substrate 22 may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI.
  • the top surface of the substrate 22 refers to the surface of the substrate 22 facing the active area 20 .
  • the thickness of the bit line 21 in this specific embodiment refers to the thickness of the bit line 21 along the third direction D3.
  • the third direction D3 is perpendicular to the top surface of the substrate 22 .
  • electrical signals can be stably transmitted along the bit line 21 , thereby ensuring that multiple electrical signals electrically connected to the bit line 21
  • the uniformity of the electrical signal obtained by the active area; on the other hand, the resistance of the bit line 21 can also be reduced, thereby improving the electrical performance of the semiconductor structure.
  • a plurality of bit lines 21 are arranged at intervals along a second direction D2, where the second direction D2 is parallel to the top surface of the substrate 22, and the first direction D1 is parallel to the top surface of the substrate 22.
  • the second direction D2 intersects; the semiconductor structure further includes:
  • the isolation layer 24 is located between the bit lines 21 arranged at intervals along the second direction D2, and along the third direction D3, the bottom surface of the isolation layer 24 is located under the bottom surface of the bit lines 21 , wherein the third direction D3 is perpendicular to the top surface of the substrate 22 .
  • a plurality of the active regions 20 are arranged in a two-dimensional array along the first direction D1 and the second direction D2 above the substrate 22 to form an active array structure.
  • the isolation layer 24 extends along the first direction D1, and a plurality of the isolation layers 24 is spaced apart along the second direction D2.
  • the isolation layer 24 is located between the bit lines 21 spaced apart along the second direction D2 and between the two rows of active areas 20 spaced apart along the second direction D2, for The bit lines 21 adjacent along the second direction D2 and the active regions 20 adjacent along the second direction D2 are electrically isolated.
  • the depth of the isolation layer 24 is set deeper in order to form the bit line 21 with a thicker thickness and a uniform thickness distribution, that is, it can face all the bit lines 21 from the side of the substrate 22.
  • the substrate 22 under the active area 20 is modified to form the bit lines 21 with uniform thickness distribution.
  • the material of the isolation layer 24 is an oxide material (such as silicon dioxide).
  • the semiconductor structure further includes:
  • the air gap is located in the isolation layer 24 and extends along the first direction D1.
  • the air gap is aligned with the bit line 21.
  • the top surface of the air gap is flush with the top surface of the bit line 21, and the bottom surface of the air gap is flush with the bottom surface of the bit line 21. flush; flush;
  • the length of the air gap is equal to the length of the bit line 21.
  • the air gaps and the bit lines 21 are alternately arranged.
  • the setting of the air gap can, on the one hand, utilize the low dielectric constant of air to further enhance the electrical isolation effect between adjacent bit lines 21; on the other hand, the location of the air gap is also used to The silicon material under the active area 20 is modified laterally to form the bit line 21 .
  • the semiconductor structure further includes:
  • a dielectric layer is located in the isolation layer 24 and extends along the first direction D1.
  • the dielectric layer is aligned with the bit line 21.
  • the top surface of the dielectric layer is flush with the top surface of the bit line 21, and the bottom surface of the dielectric layer is flush with the bottom surface of the bit line 21. flush; flush;
  • the length of the dielectric layer is equal to the length of the bit line 21.
  • the material of the bit line 21 is a metal suicide material or a silicon material including doped ions.
  • the material of the bit line 21 is titanium silicon compound or cobalt silicon compound.
  • the thickness of the bit line 21 is 5 nm to 50 nm.
  • the semiconductor structure and its formation method provided by some embodiments of this specific embodiment form bit lines by modifying the substrate below the active area from the side of the substrate, which can make the thickness distribution of the formed bit lines uniform. And a thicker bit line can be formed, thereby effectively reducing the resistance of the bit line, and making the thickness of the bit line uniform in its extension direction, so as to improve the electrical performance of the semiconductor structure.
  • Other embodiments of this specific implementation mode simultaneously modify the substrate below the active area from opposite sides of the active area along the second direction, which can not only improve the formation efficiency of the bit lines, but also The uniformity of the thickness distribution of the bit line can also be further improved, thereby further improving the electrical performance of the semiconductor structure.

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Abstract

本公开涉及一种半导体结构及其形成方法所述半导体结构的形成方法包括如下步骤：形成衬底、以及位于所述衬底上方且沿第一方向间隔排布的多个有源区，其中，所述第一方向与所述衬底的顶面平行；自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理，形成沿所述第一方向延伸、且与沿所述第一方向间隔排布的多个所述有源区电连接的位线。本公开能够形成厚度较厚的位线，从而能够有效降低位线的电阻，并提高所述半导体结构的电性能。

Description

半导体结构及其形成方法
相关申请引用说明
本申请要求于2022年08月15日递交的中国专利申请号202210976358.2、申请名为“半导体结构及其形成方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本公开涉及半导体制造技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
动态随机存储器(Dynamic Random Access Memory，DRAM)是计算机等电子设备中常用的半导体装置，其由多个存储单元构成，每个存储单元通常包括晶体管和电容器。所述晶体管的栅极与字线电连接、源极与位线电连接、漏极与电容器电连接，字线上的字线电压能够控制晶体管的开启和关闭，从而通过位线能够读取存储在电容器中的数据信息，或者将数据信息写入到电容器中。
DRAM等半导体结构中多采用埋入式位线结构，然而，在形成埋入式位线结构的过程中，所述位线结构在水平方向的形成速率大于垂直方向的形成速率，从而导致形成的埋入式位线结构的厚度较薄，厚度较薄的埋入式位线结构具有较大的电阻，从而降低了DRAM等半导体结构的电性能。
因此，如何降低埋入式位线的电阻，从而改善半导体结构的电性能，是当前亟待解决的技术问题。
发明内容
本公开一些实施例提供的半导体结构及其形成，用于降低埋入式位线的电阻，从而改善半导体结构的电性能。
根据一些实施例，本公开提供了一种半导体结构的形成方法，包括如下步骤：
形成衬底、以及位于所述衬底上方且沿第一方向间隔排布的多个有源区，其中，所述第一方向与所述衬底的顶面平行；
自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理，形成沿所述第一方向延伸、且与沿所述第一方向间隔排布的多个所述有源区电连接的位线。
在一些实施例中，形成衬底、以及位于所述衬底上方且沿第一方向间隔排布的多个有源区的具体步骤包括：
提供初始衬底；
刻蚀所述初始衬底，形成沿第一方向间隔排布的多个第一沟槽，相邻所述第一沟槽之间残留的所述初始衬底作为所述有源区，所述第一沟槽和所述有源区下方残留的所述初始衬底作为所述衬底。
在一些实施例中，形成沿第一方向间隔排布的多个第一沟槽的具体步骤包括：
刻蚀所述初始衬底，形成沿第二方向间隔排布的多个第二沟槽，相邻所述第二沟槽之间残留的所述初始衬底作为半导体层，所述第二沟槽和所述半导体层下方残留的所述初始衬底作为所述衬底，其中，所述第二方向与所述衬底的顶面平行，且所述第一方向与所述第二方向相交；
于所述第二沟槽内形成隔离层；
刻蚀所述半导体层和所述隔离层，形成沿所述第一方向间隔排布的多个所述第一沟槽，相邻所述第一沟槽之间残留的所述半导体层作为所述有源区。
在一些实施例中，自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理之前，还包括如下步骤：
形成覆盖所述半导体层内的所述第一沟槽侧壁的第一保护层。
在一些实施例中，自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理的具体步骤包括：
沿第二方向对所述有源区下方的所述衬底进行改性处理。
在一些实施例中，沿第二方向对所述有源区下方的所述衬底进行改性处理的具体步骤包括：
自所述衬底沿所述第二方向的相对两侧面同时对所述有源区下方的所述衬底进行改性处理。
在一些实施例中，在沿第三方向上，所述第二沟槽的深度大于所述第一沟槽的深度，其中，所述第三方向与所述衬底的顶面垂直；自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理的具体步骤包括：
沿所述第一沟槽刻蚀所述第一沟槽下方的所述隔离层，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽；
沿所述刻蚀槽对所述有源区下方的所述衬底进行改性处理。
在一些实施例中，沿所述第一沟槽刻蚀所述第一沟槽下方的所述隔离层之前，还包括如下步骤：
形成覆盖所述隔离层内的所述第一沟槽侧壁的第二保护层。
在一些实施例中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行各项异性刻蚀，使得所述隔离层沿所述第一方向的刻蚀速率大于沿所述第三方向的刻蚀速率，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
在一些实施例中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
采用选择性刻蚀工艺沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行刻蚀，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
在一些实施例中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
采用湿法刻蚀工艺沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行刻蚀，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
在一些实施例中，所述改性处理为形成金属硅化处理或者掺杂离子注入处理。
在一些实施例中，沿所述刻蚀槽对所述有源区下方的所述衬底进行改性处理：
沿所述刻蚀槽沉积金属材料于所述有源区下方的所述衬底侧面；
对所述衬底进行退火处理，形成所述位线。
在一些实施例中，所述金属材料为Ti、Co、Mo、Ni或Sn的一种或多种。
在一些实施例中，对所述有源区下方的所述衬底进行退火处理的具体步骤包括：
在第一温度下对所述衬底进行第一次退火处理，形成初始位线；
去除没有参与反应的所述金属材料；
在第二温度下对所述初始位线进行第二次退火处理，形成所述位线，其中，所述第二温度高于所述第一温度。
在一些实施例中，形成所述位线之后，还包括如下步骤：
形成填充满所述隔离层中的所述第一沟槽的介质层，所述介质层下方保留的所述刻蚀槽作为相邻所述位线之间的空气隙。
在一些实施例中，形成所述位线之后，还包括如下步骤：
形成填充满所述隔离层中的所述第一沟槽和所述刻蚀槽的介质层。
根据另一些实施例，本公开还提供了一种半导体结构，包括：
衬底；
位线，位于所述衬底上，且沿第一方向延伸，其中，所述第一方向与所述衬底的顶面平行；
多个有源区，位于所述位线上方，且多个所述有源区沿第一方向间隔排布，所述位线连续与沿所述第一方向间隔排布的多个所述有源区电连接，在所述第一方向上，所述位线的厚度均匀分布。
在一些实施例中，多条所述位线沿第二方向间隔排布，其中，所述第二方向与所述衬底的顶面平行，所述第一方向与所述第二方向相交；所述半导体结构还包括：
隔离层，位于沿所述第二方向间隔排布的所述位线之间，且在沿第三方向上，所述隔离层的底面位于所述位线的底面之下，其中，所述第三方向与所述衬底的顶面垂直。
在一些实施例中，还包括：
空气隙，位于所述隔离层内，且沿所述第一方向延伸，所述空气隙与所述位线对准排布。
在一些实施例中，在沿所述第三方向上，所述空气隙的顶面与所述位线的顶面平齐、且所述空气隙的底面与所述位线的底面平齐；
在沿所述第一方向上，所述空气隙的长度与所述位线的长度相等。
在一些实施例中，还包括：
介质层，位于所述隔离层内，且沿所述第一方向延伸，所述介质层与所述位线对准排布。
在一些实施例中，在沿所述第三方向上，所述介质层的顶面与所述位线的顶面平齐、且所述介质层的底面与所述位线的底面平齐；
在沿所述第一方向上，所述介质层的长度与所述位线的长度相等。
在一些实施例中，所述位线的材料为金属硅化物材料或者包括掺杂离子的硅材料。
在一些实施例中，所述位线的厚度为5nm～50nm。
本公开一些实施例提供的半导体结构及其形成方法，通过自衬底的侧面对有源区下方的衬底进行改性处理来形成位线，能够使得形成的位线的厚度分布均匀，且能够形成厚度 较厚的位线，从而能够有效降低位线的电阻，且使得位线在其延伸方向上厚度分布均匀，以提高所述半导体结构的电性能。本公开另一些实施例自有源区沿第二方向的相对两侧同时对所述有源区下方的所述衬底进行改性处理，不仅能提高所述位线的形成效率，而且还能进一步提高所述位线厚度分布的均匀性，从而进一步改善所述半导体结构的电性能。
附图说明
附图1是本公开具体实施方式中半导体结构的形成方法流程图；
附图2是本公开具体实施方式形成的半导体结构的俯视结构示意图；
附图3-附图6是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。
具体实施方式
下面结合附图对本公开提供的半导体结构及其形成方法的具体实施方式做详细说明。
本具体实施方式提供了半导体结构的形成方法，附图1是本公开具体实施方式中半导体结构的形成方法流程图，附图2是本公开具体实施方式形成的半导体结构的俯视结构示意图，附图3-附图6是本公开具体实施方式在形成半导体结构的过程中主要的工艺截面示意图。其中，图3-图6是图2中的a-a位置、b-b位置、c-c位置和d-d位置这四个位置在半导体结构形成过程中的主要工艺截面示意图，以清楚的说明所述半导体结构的形成工艺。如图1-图6所示，所述半导体结构的形成方法，包括如下步骤：
步骤S11，形成衬底22、以及位于所述衬底22上方且沿第一方向D1间隔排布的多个有源区20，其中，所述第一方向D1与所述衬底22的顶面平行；
步骤S12，自所述衬底22的侧面对所述有源区20下方的所述衬底22进行改性处理，形成沿所述第一方向D1延伸、且与沿所述第一方向D1间隔排布的多个所述有源区20电连接的位线21，如图2和图6所示。
在一些实施例中，形成衬底22、以及位于所述衬底22上方且沿第一方向D1间隔排布的多个有源区20的具体步骤包括：
提供初始衬底；
刻蚀所述初始衬底，形成沿第一方向D1间隔排布的多个第一沟槽31，相邻所述第一沟槽31之间残留的所述初始衬底作为所述有源区20，所述第一沟槽31和所述有源区20下方残留的所述初始衬底作为所述衬底22。
本具体实施方式形成的半导体结构可以是但不限于DRAM，以下以所述半导体结构为 DRAM为例进行说明。举例来说，所述初始衬底可以是但不限于硅衬底，本具体实施方式以所述初始衬底为硅衬底为例进行说明。在其他实施例中，所述初始衬底还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。
在一些实施例中，形成沿第一方向D1间隔排布的多个第一沟槽31的具体步骤包括：
刻蚀所述初始衬底，形成沿第二方向D2间隔排布的多个第二沟槽，相邻所述第二沟槽之间残留的所述初始衬底作为半导体层，所述第二沟槽和所述半导体层下方残留的所述初始衬底作为所述衬底22，其中，所述第二方向D2与所述衬底22的顶面平行，且所述第一方向D1与所述第二方向D2相交；
于所述第二沟槽内形成隔离层24；
刻蚀所述半导体层和所述隔离层24，形成沿所述第一方向D1间隔排布的多个所述第一沟槽31，相邻所述第一沟槽31之间残留的所述半导体层作为所述有源区20，如图2和图3所示。
具体来说，可以采用光刻工艺先沿所述第一方向D1刻蚀所述初始衬底，形成多个沿所述第一方向D1延伸、且未沿第三方向贯穿所述初始衬底的所述第二沟槽，且多个所述第二沟槽沿所述第二方向D2间隔排布。在形成所述第二沟槽之后，相邻所述第二沟槽之间残留的所述初始衬底作为半导体层，所述第二沟槽和所述半导体层下方残留的所述初始衬底作为所述衬底22。其中，所述第三方向D3与所述衬底22的顶面垂直。本具体实施方式中所述的衬底22的顶面是指所述衬底22朝向所述有源区20的表面。本具体实施方式中所述的相交可以是垂直相交(即正交)，也可以是水平相交。接着，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积氧化物材料(例如二氧化硅)等绝缘介质材料于所述第二沟槽内，形成填充满所述第二沟槽的所述隔离层24。之后，形成图案化的掩膜层于所述初始衬底上方，例如图案化的掩膜层位于所述半导体层和所述隔离层24上方，且所述掩膜层24中具有暴露部分所述半导体层和部分所述隔离层24的刻蚀窗口。然后，沿所述掩膜层24中的所述刻蚀窗口向下刻蚀所述半导体层和所述隔离层24，形成沿所述第一方向D1间隔排布的多个所述第一沟槽31，所述第一沟槽31沿所述第二方向D2延伸，相邻所述第一沟槽31之间残留的所述半导体层作为所述有源区20，如图2和图3所示。在沿所述第三方向D3上，所述第一沟槽31的深度小于所述隔离层24的深度，即所述第一沟槽31的顶面位于所述隔离层24的顶面的上方。其中，所述第一沟槽31与所述隔离层24沿所述第三方向D3的深度差异的具体数值，本领域技术人员可以根据实际需要进行设置，例如 根据后续需要形成的所述位线21的厚度确定。在一示例中，所述掩膜层24的材料为氮化物材料(例如氮化硅)。
在一些实施例中，自所述衬底22的侧面对所述有源区20下方的所述衬底22进行改性处理之前，还包括如下步骤：
形成覆盖所述半导体层内的所述第一沟槽31侧壁的第一保护层40，如图4所示。
具体来说，可以先沉积氮化物材料(例如氮化硅)于所述半导体层内的所述第一沟槽31的整个内壁(包括所述半导体层内的所述第一沟槽31的侧壁和底壁)，形成所述第一保护层40。之后，回刻蚀所述半导体层内的所述第一沟槽31底壁上的所述第一半导体层40，暴露所述第一沟槽31下方的所述衬底22。覆盖于所述第一沟槽31侧壁的所述第一保护层40用于保护所述有源区20的侧壁，避免后续形成所述位线21的工艺对所述有源区20造成损伤，从而进一步确保所述半导体结构的电性能。本具体实施方式是以所述第一保护层40的材料为氮化物材料(例如氮化硅)为例进行说明。在其他具体实施方式中，所述第一保护层40的材料也可以为其他绝缘介质材料，只要确保所述第一保护层40与所述衬底22之间具有较高的刻蚀选择比即可。在一示例中，所述第一保护层40与所述衬底22之间的刻蚀选择比大于3。
在一些实施例中，自所述衬底22的侧面对所述有源区20下方的所述衬底22进行改性处理的具体步骤包括：
沿第二方向D2对所述有源区20下方的所述衬底22进行改性处理。
具体来说，按照预先的版图设计，预形成的所述位线21沿所述第一方向D1延伸，所述第二方向D2对所述有源区20下方的所述衬底22进行改性处理，可以在提高所述位线21形成效率的同时，进一步提高所述位线21沿所述第二方向D2的厚度均匀性。
为了进一步提高所述位线21的形成效率，在一些实施例中，沿第二方向D2对所述有源区20下方的所述衬底22进行改性处理的具体步骤包括：
自所述衬底22沿所述第二方向D2的相对两侧面同时对所述有源区20下方的所述衬底22进行改性处理。
在一些实施例中，在沿第三方向D3上，所述第二沟槽的深度大于所述第一沟槽31的深度，其中，所述第三方向D3与所述衬底22的顶面垂直；自所述衬底22的侧面对所述有源区20下方的所述衬底22进行改性处理的具体步骤包括：
沿所述第一沟槽31刻蚀所述第一沟槽31下方的所述隔离层24，于所述隔离层24内形 成位于所述第一沟槽31下方的刻蚀槽50，如图5所示；
沿所述刻蚀槽50对所述有源区20下方的所述衬底22进行改性处理。
在一些实施例中，沿所述第一沟槽31刻蚀所述第一沟槽31下方的所述隔离层24之前，还包括如下步骤：
形成覆盖所述隔离层24内的所述第一沟槽31侧壁的第二保护层41，如图4所示。
具体来说，为了进一步简化所述半导体结构的形成工艺，可以在形成覆盖所述半导体层内的所述第一沟槽31的侧壁的所述第一保护层40的同时，形成覆盖所述隔离层24内的所述第一沟槽31侧壁的所述第二保护层41。举例来说，可以沉积氮化物材料(例如氮化硅)于所有的所述第一沟槽31的整个内壁(包括所述第一沟槽31的侧壁和底壁)。之后，回刻蚀掉位于所述第一沟槽31底壁上的所述氮化物材料，残留于所述半导体层内的所述第一沟槽31侧壁的所述氮化物材料作为所述第一保护层40，残留于所述隔离层24内的所述第一沟槽31侧壁的所述氮化物材料作为所述第二保护层41。所述第二保护层41保护所述第一沟槽31的侧壁，避免后续形成所述刻蚀槽50的工序对所述第一沟槽31的侧壁造成损伤。
在一些实施例中，于所述隔离层24内形成位于所述第一沟槽31下方的刻蚀槽50的具体步骤包括：
沿所述第一沟槽31对所述第一沟槽31下方的所述隔离层24进行各项异性刻蚀，使得所述隔离层24沿所述第一方向D1的刻蚀速率大于沿所述第三方向D3的刻蚀速率，于所述隔离层24内形成沿所述第一方向D1延伸、且连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31的所述刻蚀槽50。
具体来说，可以通过选用合适的刻蚀剂或者调整刻蚀参数(例如刻蚀温度、刻蚀压力、等离子体浓度等)，使得所述隔离层24沿所述第一方向D1的刻蚀速率大于沿所述第三方向D3的刻蚀速率，从而使得形成的所述刻蚀槽50即能连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31、也不会沿所述第三方向D3贯穿所述隔离层24，以避免对所述隔离层24下方的所述衬底22造成损伤。本领域技术人员可以根据实际需要控制所述刻蚀槽50沿所述第三方向的深度，例如通过控制刻蚀时间、刻蚀剂用量等刻蚀参数，从而可以灵活调整后续形成的所述位线21沿所述第三方向D3的厚度。
在另一些实施例中，于所述隔离层24内形成位于所述第一沟槽31下方的刻蚀槽50的具体步骤包括：
采用选择性刻蚀工艺沿所述第一沟槽31对所述第一沟槽31下方的所述隔离层24进行 刻蚀，于所述隔离层24内形成沿所述第一方向D1延伸、且连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31的所述刻蚀槽50。
具体来说，为了可以采用选择性刻蚀工艺沿所述第一沟槽31对所述第一沟槽31下方的所述隔离层24进行刻蚀，使得所述第一沟槽31下方的所述隔离层24沿所述第一方向D1的刻蚀量大于所述隔离层24沿所述第三方向D3的刻蚀量，从而使得形成的所述刻蚀槽50即能连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31、也不会沿所述第三方向D3贯穿所述隔离层24，以避免对所述隔离层24下方的所述衬底22造成损伤。
在另一些实施例中，于所述隔离层24内形成位于所述第一沟槽31下方的刻蚀槽50的具体步骤包括：
采用湿法刻蚀工艺沿所述第一沟槽31对所述第一沟槽31下方的所述隔离层24进行刻蚀，于所述隔离层24内形成沿所述第一方向D1延伸、且连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31的所述刻蚀槽50。
具体来说，在形成覆盖所述隔离层24内的所述第一沟槽31侧壁的所述第二保护层41之后，可以采用湿法刻蚀工艺沿所述第一沟槽31对所述第一沟槽31下方的所述隔离层24进行刻蚀，以简化所述刻蚀槽50的形成工艺。通过调整湿法刻蚀过程中的刻蚀参数，例如刻蚀剂的种类、刻蚀温度等，使得形成的所述刻蚀槽50即能连续连通沿所述第一方向D1间隔排布的多个所述第一沟槽31、也不会沿所述第三方向D3贯穿所述隔离层24，以避免对所述隔离层24下方的所述衬底22造成损伤。
在一示例中，所述刻蚀槽50沿所述第一方向D1的长度大于或者等于所述半导体层沿所述第一方向D1的长度相等，从而确保通过所述刻蚀槽50形成的所述位线21能够与沿所述第一方向D1间隔排布的多个所述有源区20电连接。所述刻蚀槽50沿所述第二方向D2的宽度可以小于或者等于所述隔离层24沿所述第二方向D2的宽度，以在避免对所述有源区20造成损伤的同时，增大所述改性处理的工艺窗口。
所述改性处理是对所述有源区20下方的部分所述衬底22进行改性，从而使得改性后的部分所述衬底22的导电性增强，以形成与沿所述第一方向D1间隔排布的多个所述有源区20电连接的所述位线21。在一些实施例中，所述改性处理为形成金属硅化处理或者掺杂离子注入处理。
在一些实施例中，沿所述刻蚀槽50对所述有源区20下方的所述衬底22进行改性处理：
沿所述刻蚀槽50沉积金属材料于所述有源区20下方的所述衬底22侧面；
对所述衬底22进行退火处理，形成所述位线21。
在一些实施例中，所述金属材料为Ti、Co、Mo、Ni或Sn的一种或多种。举例来说，当所述金属材料为Ti时，可以采用化学气相沉积工艺沉积；当所述金属材料为Co时，可以采用原子层沉积工艺沉积。
在一些实施例中，对所述有源区20下方的所述衬底22进行退火处理的具体步骤包括：
在第一温度下对所述衬底22进行第一次退火处理，形成初始位线；
去除没有参与反应的所述金属材料；
在第二温度下对所述初始位线进行第二次退火处理，形成所述位线21，其中，所述第二温度高于所述第一温度。
以下以所述改性处理为形成金属硅化物处理、所述退火处理为快速热退火(Rapid Thermal Processing，RTP)为例进行说明。举例来说，所述刻蚀槽50暴露所述有源区20下方的所述衬底22沿所述第二方向D2的相对两侧壁。在形成所述刻蚀槽50之后，可以采用化学气相沉积工艺、沿所述刻蚀槽50沉积金属Ti于所述有源区20下方的所述衬底22沿所述第二方向D2的相对两侧壁上。或者，采用原子层沉积工艺、沿所述刻蚀槽50沉积金属Co于所述有源区20下方的所述衬底22沿所述第二方向D2的相对两侧壁上。之后，在较低的所述第一温度下对所述衬底22进行第一次退火处理，使得所述金属材料与所述衬底22中的硅材料反应，形成高阻的金属硅化物材料，并以高阻的金属硅化物材料作为所述初始位线。接着，刻蚀去除没有参与反应的所述金属材料，在较高的所述第二温度下对所述初始位线进行第二次退火处理，形成低阻的所述位线21。在一示例中，所述第一温度为500℃-700℃，所述第二温度为850℃-100℃。
本具体实施方式是以进行低温和高温两次退火处理为例进行说明。在其他具体实施方式中，也可以仅进行一次退火处理，以简化所述半导体结构的形成工艺。
在一些实施例中，形成所述位线21之后，还包括如下步骤：
形成填充满所述隔离层24中的所述第一沟槽31的介质层，所述介质层下方保留的所述刻蚀槽50作为相邻所述位线21之间的空气隙。
具体来说，所述介质层仅填充所述隔离层24中的所述第一沟槽31，所述刻蚀槽作为相邻所述位线21之间的所述空气隙，从而能够利用空气的低介电常数进一步增强相邻所述位线21之间的电性隔离效果。在一实施例中，所述介质层的材料可以为氧化物材料(例如二氧化硅)。
为了进一步简化所述半导体结构的形成工艺，在一些实施例中，形成所述位线21之后，还包括如下步骤：
形成填充满所述隔离层24中的所述第一沟槽31和所述刻蚀槽50的介质层。
在一实施例中，在形成所述位线21之后，还可以在所述有源区20中定义沟道区、以及沿所述第三方向D3分布于所述沟道区相对两侧的源极区和漏极区，且所述源极区与所述位线21接触电连接。之后，沿所述第一沟槽21沉积TiN或者金属钨等导电材料，形成覆盖所述沟道区的字线30。如图2所示，所述字线30沿所述第二方向D2延伸，且连续覆盖沿所述第二方向D2间隔排布的多个所述有源区20中的所述沟道区，且多条所述字线30沿所述第一方向D1间隔排布。接着，还可以在所述漏极区的上方形成与所述漏极区电连接的电容器。
本具体实施方式还提供了一种半导体结构，本具体实施方式提供的所述半导体结构可以采用如图1-图6所示的半导体结构的形成方法形成。本具体实施方式提供的半导体结构的示意图可以参见图2和图6。如图1-图6所示，所述半导体结构，包括：
衬底22；
位线21，位于所述衬底22上，且沿第一方向D1延伸，其中，所述第一方向D1与所述衬底22的顶面平行；
多个有源区20，位于所述位线21上方，且多个所述有源区20沿第一方向D1间隔排布，所述位线21连续与沿所述第一方向D1间隔排布的多个所述有源区20电连接，在所述第一方向D1上，所述位线21的厚度均匀分布。
本具体实施方式形成的半导体结构可以是但不限于DRAM，以下以所述半导体结构为DRAM为例进行说明。举例来说，所述衬底22可以是但不限于硅衬底，本具体实施方式以所述衬底22为硅衬底为例进行说明。在其他实施例中，所述衬底22还可以为氮化镓、砷化镓、碳化镓、碳化硅或SOI等半导体衬底。所述衬底22的顶面是指所述衬底22朝向所述有源区20的表面。
本具体实施方式中所述位线21的厚度是指所述位线21沿第三方向D3的厚度。其中，所述第三方向D3与所述衬底22的顶面垂直。本具体实施方式通过使得所述位线21在其延伸方向上的厚度分布均匀，一方面，可以使得电信号沿所述位线21稳定传输，从而确保与所述位线21电连接的多个所述有源区获得的所述电信号的均匀性；另一方面，还能够降低所述位线21的电阻，从而改善所述半导体结构的电性能。
在一些实施例中，多条所述位线21沿第二方向D2间隔排布，其中，所述第二方向D2与所述衬底22的顶面平行，所述第一方向D1与所述第二方向D2相交；所述半导体结构还包括：
隔离层24，位于沿所述第二方向D2间隔排布的所述位线21之间，且在沿第三方向D3上，所述隔离层24的底面位于所述位线21的底面之下，其中，所述第三方向D3与所述衬底22的顶面垂直。
具体来说，多个所述有源区20在所述衬底22上方沿所述第一方向D1和所述第二方向D2呈二维阵列排布，形成有源阵列结构。所述隔离层24沿所述第一方向D1延伸，且多个所述隔离层24沿所述第二方向D2间隔排布。所述隔离层24位于沿所述第二方向D2间隔排布的所述位线21之间、以及沿所述第二方向D2间隔排布的两列所述有源区20之间，用于电性隔离沿所述第二方向D2相邻的所述位线21、以及沿所述第二方向D2相邻的所述有源区20。在沿第三方向D3上，所述隔离层24的深度设置的较深，是为了形成厚度较厚且厚度分布均匀的所述位线21，即能够通过自所述衬底22的侧面对所述有源区20下方的所述衬底22进行改性处理来形成厚度均匀分布的所述位线21。在一示例中，所述隔离层24的材料为氧化物材料(例如二氧化硅)。
在一些实施例中，所述半导体结构还包括：
空气隙，位于所述隔离层24内，且沿所述第一方向D1延伸，所述空气隙与所述位线21对准排布。
在一些实施例中，在沿所述第三方向D3上，所述空气隙的顶面与所述位线21的顶面平齐、且所述空气隙的底面与所述位线21的底面平齐；
在沿所述第一方向D1上，所述空气隙的长度与所述位线21的长度相等。
具体来说，在沿所述第二方向D2上，所述空气隙与所述位线21交替排布。所述空气隙的设置，一方面，能够利用空气的低介电常数进一步增强相邻所述位线21之间的电性隔离效果；另一方面，所述空气隙所在的位置还用于从侧面对所述有源区20下方的硅材料进行改性处理，从而形成所述位线21。
在一些实施例中，所述半导体结构还包括：
介质层，位于所述隔离层24内，且沿所述第一方向D1延伸，所述介质层与所述位线21对准排布。
在一些实施例中，在沿所述第三方向D3上，所述介质层的顶面与所述位线21的顶面 平齐、且所述介质层的底面与所述位线21的底面平齐；
在沿所述第一方向D1上，所述介质层的长度与所述位线21的长度相等。
在一些实施例中，所述位线21的材料为金属硅化物材料或者包括掺杂离子的硅材料。在一示例中，所述位线21的材料为钛硅化合物或者钴硅化合物。
为了进一步降低所述位线21的电阻，在一些实施例中，所述位线21的厚度为5nm～50nm。
本具体实施方式一些实施例提供的半导体结构及其形成方法，通过自衬底的侧面对有源区下方的衬底进行改性处理来形成位线，能够使得形成的位线的厚度分布均匀，且能够形成厚度较厚的位线，从而能够有效降低位线的电阻，且使得位线在其延伸方向上厚度分布均匀，以提高所述半导体结构的电性能。本具体实施方式另一些实施例自有源区沿第二方向的相对两侧同时对所述有源区下方的所述衬底进行改性处理，不仅能提高所述位线的形成效率，而且还能进一步提高所述位线厚度分布的均匀性，从而进一步改善所述半导体结构的电性能。
以上所述仅是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本公开原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (25)

  1. 一种半导体结构的形成方法，包括如下步骤：
    形成衬底、以及位于所述衬底上方且沿第一方向间隔排布的多个有源区，其中，所述第一方向与所述衬底的顶面平行；
    自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理，形成沿所述第一方向延伸、且与沿所述第一方向间隔排布的多个所述有源区电连接的位线。
  2. 根据权利要求1所述的半导体结构的形成方法，其中，形成衬底、以及位于所述衬底上方且沿第一方向间隔排布的多个有源区的具体步骤包括：
    提供初始衬底；
    刻蚀所述初始衬底，形成沿第一方向间隔排布的多个第一沟槽，相邻所述第一沟槽之间残留的所述初始衬底作为所述有源区，所述第一沟槽和所述有源区下方残留的所述初始衬底作为所述衬底。
  3. 根据权利要求2所述的半导体结构的形成方法，其中，形成沿第一方向间隔排布的多个第一沟槽的具体步骤包括：
    刻蚀所述初始衬底，形成沿第二方向间隔排布的多个第二沟槽，相邻所述第二沟槽之间残留的所述初始衬底作为半导体层，所述第二沟槽和所述半导体层下方残留的所述初始衬底作为所述衬底，其中，所述第二方向与所述衬底的顶面平行，且所述第一方向与所述第二方向相交；
    于所述第二沟槽内形成隔离层；
    刻蚀所述半导体层和所述隔离层，形成沿所述第一方向间隔排布的多个所述第一沟槽，相邻所述第一沟槽之间残留的所述半导体层作为所述有源区。
  4. 根据权利要求3所述的半导体结构的形成方法，其中，自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理之前，还包括如下步骤：
    形成覆盖所述半导体层内的所述第一沟槽侧壁的第一保护层。
  5. 根据权利要求3所述的半导体结构的形成方法，其中，自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理的具体步骤包括：
    沿第二方向对所述有源区下方的所述衬底进行改性处理。
  6. 根据权利要求5所述的半导体结构的形成方法，其中，沿第二方向对所述有源区下方的 所述衬底进行改性处理的具体步骤包括：
    自所述衬底沿所述第二方向的相对两侧面同时对所述有源区下方的所述衬底进行改性处理。
  7. 根据权利要求5所述的半导体结构的形成方法，其中，在沿第三方向上，所述第二沟槽的深度大于所述第一沟槽的深度，其中，所述第三方向与所述衬底的顶面垂直；自所述衬底的侧面对所述有源区下方的所述衬底进行改性处理的具体步骤包括：
    沿所述第一沟槽刻蚀所述第一沟槽下方的所述隔离层，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽；
    沿所述刻蚀槽对所述有源区下方的所述衬底进行改性处理。
  8. 根据权利要求7所述的半导体结构的形成方法，其中，沿所述第一沟槽刻蚀所述第一沟槽下方的所述隔离层之前，还包括如下步骤：
    形成覆盖所述隔离层内的所述第一沟槽侧壁的第二保护层。
  9. 根据权利要求7所述的半导体结构的形成方法，其中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
    沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行各项异性刻蚀，使得所述隔离层沿所述第一方向的刻蚀速率大于沿所述第三方向的刻蚀速率，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
  10. 根据权利要求7所述的半导体结构的形成方法，其中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
    采用选择性刻蚀工艺沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行刻蚀，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
  11. 根据权利要求7所述的半导体结构的形成方法，其中，于所述隔离层内形成位于所述第一沟槽下方的刻蚀槽的具体步骤包括：
    采用湿法刻蚀工艺沿所述第一沟槽对所述第一沟槽下方的所述隔离层进行刻蚀，于所述隔离层内形成沿所述第一方向延伸、且连续连通沿所述第一方向间隔排布的多个所述第一沟槽的所述刻蚀槽。
  12. 根据权利要求7所述的半导体结构的形成方法，其中，所述改性处理为形成金属硅化处理或者掺杂离子注入处理。
  13. 根据权利要求12所述的半导体结构的形成方法，其中，沿所述刻蚀槽对所述有源区下方的所述衬底进行改性处理：
    沿所述刻蚀槽沉积金属材料于所述有源区下方的所述衬底侧面；
    对所述衬底进行退火处理，形成所述位线。
  14. 根据权利要求13所述的半导体结构的形成方法，其中，所述金属材料为Ti、Co、Mo、Ni或Sn的一种或多种。
  15. 根据权利要求14所述的半导体结构的形成方法，其中，对所述有源区下方的所述衬底进行退火处理的具体步骤包括：
    在第一温度下对所述衬底进行第一次退火处理，形成初始位线；
    去除没有参与反应的所述金属材料；
    在第二温度下对所述初始位线进行第二次退火处理，形成所述位线，其中，所述第二温度高于所述第一温度。
  16. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述位线之后，还包括如下步骤：
    形成填充满所述隔离层中的所述第一沟槽的介质层，所述介质层下方保留的所述刻蚀槽作为相邻所述位线之间的空气隙。
  17. 根据权利要求13所述的半导体结构的形成方法，其中，形成所述位线之后，还包括如下步骤：
    形成填充满所述隔离层中的所述第一沟槽和所述刻蚀槽的介质层。
  18. 一种半导体结构，包括：
    衬底；
    位线，位于所述衬底上，且沿第一方向延伸，其中，所述第一方向与所述衬底的顶面平行；
    多个有源区，位于所述位线上方，且多个所述有源区沿第一方向间隔排布，所述位线连续与沿所述第一方向间隔排布的多个所述有源区电连接，在所述第一方向上，所述位线的厚度均匀分布。
  19. 根据权利要求18所述的半导体结构，其中，多条所述位线沿第二方向间隔排布，其中，所述第二方向与所述衬底的顶面平行，所述第一方向与所述第二方向相交；所述半导体结构还包括：
    隔离层，位于沿所述第二方向间隔排布的所述位线之间，且在沿第三方向上，所述隔离层的底面位于所述位线的底面之下，其中，所述第三方向与所述衬底的顶面垂直。
  20. 根据权利要求19所述的半导体结构，还包括：
    空气隙，位于所述隔离层内，且沿所述第一方向延伸，所述空气隙与所述位线对准排布。
  21. 根据权利要求20所述的半导体结构，其中，在沿所述第三方向上，所述空气隙的顶面与所述位线的顶面平齐、且所述空气隙的底面与所述位线的底面平齐；
    在沿所述第一方向上，所述空气隙的长度与所述位线的长度相等。
  22. 根据权利要求19所述的半导体结构，还包括：
    介质层，位于所述隔离层内，且沿所述第一方向延伸，所述介质层与所述位线对准排布。
  23. 根据权利要求22所述的半导体结构，其中，在沿所述第三方向上，所述介质层的顶面与所述位线的顶面平齐、且所述介质层的底面与所述位线的底面平齐；
    在沿所述第一方向上，所述介质层的长度与所述位线的长度相等。
  24. 根据权利要求18所述的半导体结构，其中，所述位线的材料为金属硅化物材料或者包括掺杂离子的硅材料。
  25. 根据权利要求18所述半导体结构，其中，所述位线的厚度为5nm～50nm。
PCT/CN2022/126965 2022-08-15 2022-10-24 半导体结构及其形成方法 Ceased WO2024036747A1 (zh)

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CN114121818A (zh) * 2021-11-15 2022-03-01 长鑫存储技术有限公司 半导体器件及其形成方法
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US20060113587A1 (en) * 2004-11-30 2006-06-01 Andreas Thies Transistor array for semiconductor memory devices and method for fabricating a vertical channel transistor array
CN103681510A (zh) * 2012-08-28 2014-03-26 爱思开海力士有限公司 具有掩埋位线的半导体器件及其制造方法
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