WO2024031773A1 - 半导体结构的制造方法、半导体结构和半导体器件 - Google Patents

半导体结构的制造方法、半导体结构和半导体器件 Download PDF

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Publication number
WO2024031773A1
WO2024031773A1 PCT/CN2022/118536 CN2022118536W WO2024031773A1 WO 2024031773 A1 WO2024031773 A1 WO 2024031773A1 CN 2022118536 W CN2022118536 W CN 2022118536W WO 2024031773 A1 WO2024031773 A1 WO 2024031773A1
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Prior art keywords
power supply
wiring layer
supply wiring
chips
chip
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PCT/CN2022/118536
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English (en)
French (fr)
Inventor
庄凌艺
吕开敏
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长鑫存储技术有限公司
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Priority to US18/155,721 priority Critical patent/US20240057350A1/en
Publication of WO2024031773A1 publication Critical patent/WO2024031773A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00

Definitions

  • the present disclosure belongs to the field of semiconductors, and specifically relates to a manufacturing method of a semiconductor structure, a semiconductor structure and a semiconductor device.
  • HBM High Bandwidth Memory
  • Chip stacking technology represented by HBM extends the original one-dimensional memory layout to three dimensions, that is, stacking many chips together and packaging them, thus greatly increasing the density of the chip and achieving large capacity and high bandwidth.
  • Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method of the semiconductor structure, and a semiconductor device, which are at least conducive to improving the performance of the semiconductor structure.
  • embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, wherein the method of manufacturing a semiconductor structure includes: providing a plurality of chips, the chips including element regions and partitions arranged in a first direction.
  • Chip track area at least one of the plurality of chips has a power supply wiring layer, and the power supply wiring layer extends from the component area to the dicing track area; a plurality of the chips are stacked to form a chip module; The stacking direction of the chips is a second direction, and the second direction is perpendicular to the first direction; the component areas of multiple chips overlap, and the dicing lane areas of multiple chips overlap ; After forming the chip module, planarize the sides of the plurality of dicing lane areas away from the component area to remove at least part of the dicing lane regions and expose the power supply wiring layer; in the flattening A bonding pad is formed on the chemically treated side surface, and the bonding pad is connected to the power supply wiring layer.
  • another aspect of the present disclosure further provides a semiconductor structure.
  • the semiconductor structure includes: a chip module, including a plurality of stacked chips, and the chip includes component regions arranged along a first direction, The stacking direction of the chips is a second direction, and the second direction is perpendicular to the first direction; wherein, at least one of the chips also has a power supply wiring layer, and the power supply wiring layer extends along the component area to all directions.
  • the edge of the chip extends; wherein, a welding pad is also provided on the side of the chip, and the welding pad is connected to the power supply wiring layer.
  • another aspect of the present disclosure further provides a semiconductor device.
  • the semiconductor device includes: a substrate; and a chip module, which is disposed on the substrate and includes a plurality of stacked chips, and the chip includes: The component areas are arranged along the first direction, the stacking direction of the chips is the second direction, and the second direction is perpendicular to the first direction; wherein, at least one of the chips also has a power supply wiring layer, and the power supply wiring layer is The wiring layer extends along the component area to the edge of the chip; wherein, a bonding pad is also provided on the side of the chip, and the bonding pad is connected to the power supply wiring layer.
  • the dicing track area is flattened to improve the flatness of the side of the chip module and avoid affecting the formation of the pads on the side of the chip module.
  • the extension of the power supply wiring layer to the dicing lane area makes it easier to expose the power supply wiring layer during the planarization process and avoids damage to the component area caused by excessive planarization process.
  • Total Thickness Variation TTV
  • TTV Total Thickness Variation
  • Embodiments of the present disclosure provide a manufacturing method of a semiconductor structure, which provides multiple chips.
  • the chips include component areas and dicing track areas; after forming the chip module, the sides of the multiple dicing track areas away from the component areas are planarized to at least Remove part of the scribing area. That is, the dicing track area is retained before the chip module is formed; the dicing track area is used for planarization after the chip module is formed, thereby improving the flatness of the side of the chip module.
  • the power supply wiring layer extends to the dicing lane area, making it easier to expose the power supply wiring layer during the planarization process and avoiding damage to the component area caused by excessive planarization.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the manufacturing method of the semiconductor structure will be described in detail below with reference to the accompanying drawings.
  • step 1 Provide multiple chips 1.
  • the chips 1 include component areas A and dicing track areas B arranged in the first direction X.
  • component area A includes transistors, capacitors, word lines, bit lines and other components.
  • the component area A also has a plurality of power supply signal lines 12 (refer to FIGS. 3 to 5 ).
  • the power supply signal lines 12 can provide various voltage signals, such as digital signals or analog signals, to the components.
  • the power supply signal line 12 may be a ground signal line 12G or a power signal line 12P. Different ground signal lines 12G have different voltage signals, and different power signal lines 12P have different voltage signals.
  • the plurality of chips 1 are formed by wafer cutting. That is, a laser is usually used to irradiate the centerline position of the scribing track area B to form a modified layer. Subsequently, the wafer is divided into multiple chips 1 along the modified layer. Therefore, components are usually not placed in the dicing lane area B.
  • At least one of the plurality of chips 1 has a power supply wiring layer 2 extending from the component area A to the scribing track area B.
  • the power supply wiring layer 2 is electrically connected to the power supply signal line 12 in the component area A, so as to provide voltage signals to the components in the component area A through the power supply wiring layer 2 .
  • the scribing track area B has a dielectric layer 43 covering the power supply wiring layer 2; the power supply wiring layer 2 has an end surface 14 away from the component area A; that is, the dielectric layer 43 also covers the end surface 14 of the power supply wiring layer 2.
  • the dielectric layer 43 can also cover the front or back of the chip 1 .
  • the extension of the power supply wiring layer 2 into the scribing track area B can set a certain process margin for subsequent planarization processing to avoid damage to the components in the component area A due to excessive planarization processing.
  • the planarization time needs to be correspondingly extended, which may cause wear and tear. Part of the component area A is removed, which may affect the yield and performance of the semiconductor structure.
  • the power supply wiring layer 2 may not be exposed when the degree of planarization is insufficient. If the length of the power supply wiring layer 2 extending into the scribing lane area B is too long, it may affect the laser cutting process, that is, the power supply wiring layer 2 will reflect the laser to the component area A, which may damage the devices in the component area A.
  • the ratio of the width of the dicing track area B to the length of the power supply wiring layer 2 of the dicing track area B is within the above range, it is beneficial to take into account the above two aspects.
  • the length L1 of the power supply wiring layer 2 of the scribing track area B in the first direction X is 30um ⁇ 50um, such as 40um; the width L2 of the scribing track area B in the first direction
  • the planarization process is beneficial to fully exposing the end surface of the power supply wiring layer 2 and reducing the impact on laser cutting.
  • each chip 1 includes a dicing track area B, whereby the bonding pad 5 can be subsequently formed on one side of the chip module 100 (refer to FIG. 11 ).
  • each chip 1 includes two dicing lane areas B, and the two dicing lane areas B are located on opposite sides of the component area A, and the power supply wiring layer 2 extends from the chip 1 area to both sides. A zoning area B.
  • the bonding pads 5 can be subsequently formed on opposite sides of the chip module 100 .
  • Figures 3 to 6 respectively show schematic diagrams of different active surfaces 13 of the chip 1.
  • the power supply wiring layer 2 can extend along the active surface 13 of the chip 1.
  • the power supply signal line 12 can also be led out from the chip 1 to the active surface 13 of the chip 1, thereby communicating with the active surface 13 of the chip 1.
  • the power supply wiring layer 2 on the source plane 13 is electrically connected.
  • the active surface 13 can also be understood as the front side of the chip 1. Therefore, after the components in the chip 1 are manufactured, the original back-end process can be used to manufacture the power supply wiring layer 2, which makes the process simpler.
  • the power supply wiring layer 2 can only extend near the upper or lower edge of the chip 1 without covering the entire active surface 13 of the chip 1. Therefore, the contact area between the power supply wiring layer 2 and the chip 1 is small, and the power supply The heat of wiring layer 2 has less impact on chip 1.
  • the power supply wiring layer 2 is a power wiring layer 2P, a ground wiring layer 2G or a hybrid wiring layer 2PG. That is, one power supply wiring layer 2 includes a plurality of mutually isolated power supply wirings 20. According to the type of the power supply wiring 20 of each power supply wiring layer 2, the power supply wiring layer 2 can be divided into the above three categories.
  • the power wiring layer 2P includes a plurality of power wirings 20P.
  • the plurality of power wirings 20P are arranged at intervals and have different voltage signals.
  • the ground wiring layer 2G includes a plurality of ground wirings 20G, and the plurality of ground wirings 20G have different voltage signals; the ground wiring 20G is electrically connected to the ground signal line 12G, and the power wiring 20P is electrically connected to the power signal line 12P.
  • the hybrid wiring layer 2PG includes a plurality of power wirings 20P and a plurality of ground wirings 20G.
  • the power wirings 20P and the ground wirings 20G are spaced apart, and different power wirings 20P have different voltage signals, and different ground wirings 20G have different voltage signals.
  • the ground wiring 20G and the power wiring 20P of the same hybrid wiring layer 2PG are alternately arranged in the third direction Z, and the third direction Z is perpendicular to the first direction X and the second direction Y. Since the ground wiring 20 and the power wiring 20P are arranged alternately, it is beneficial to reduce the electromagnetic interference of the adjacent power supply wiring 20 .
  • a chip 1 has its own power supply wiring layer 2, at least part of the power supply signal lines 12 of the chip 1 can be directly connected to its own power supply wiring layer 2, that is, led out through its own power supply wiring layer 2. If a chip 1 does not have a power supply wiring layer 2, the power supply signal line 12 of this chip 1 can be led out through the power supply wiring layer 2 of other chips 1. In other words, this chip 1 can be connected to the chip 1 through the conductive via 41 and the bonding portion 42. The other chips 1 establish an electrical connection relationship, thereby electrically connecting their own power supply signal lines 12 with the power supply signal lines 12 of other chips 1 , and then electrically connecting with the power supply wiring layers 2 of other chips 1 .
  • multiple chips 1 have power supply wiring layers 2 .
  • the position and quantity relationship between the chip 1 and the power supply wiring layer 2 will be described in detail below.
  • each chip 1 has one power supply wiring layer 2, that is, the number of chips 1 is the same as the number of power supply wiring layers 2. More power supply wiring layers 2 are conducive to improving the stability of the power supply, thereby improving the performance of the semiconductor structure; in addition, multiple power supply wiring layers 2 are evenly arranged in multiple chips 1, therefore, it is conducive to unifying the layout of different chips 1. manufacturing process to reduce production costs.
  • two adjacent chips 1 constitute a chipset 10, and there are two power supply wiring layers 2 between the two chips 1 of the same chipset 10.
  • the two power supply wiring layers 2 respectively located on the surfaces of the two chips 1.
  • the two chips 1 of the chipset 10 are bonded front to front, that is, active surface 13 to active surface 13 .
  • the conductive via 41 is a through-silicon via (TSV); there is a bonding portion 42 between the two chips 1 of the same chipset 10.
  • the portion 42 is connected to the conductive vias 41 of the two chips 1 so that the chips 1 are electrically connected.
  • each chip 1 has a plurality of conductive vias 41 arranged at intervals, and the plurality of conductive vias 41 are connected to the plurality of power supply signal lines 12 (refer to FIGS. 3-6 ) in the chip 1 in a one-to-one correspondence.
  • the voltage signals on the multiple power supply signal lines 12 in the same chip 1 are different.
  • the voltage signals on the multiple conductive vias 41 in the same chip 1 are also different.
  • the conductive vias 41 with the same voltage signal are electrically connected through the bonding portion 42 , so that the power supply signal lines 12 with the same voltage signal in the two chips 1 are electrically connected together. .
  • the conductive vias 41 include a plurality of ground vias 41G and a plurality of power vias 41P
  • the bonding portions 42 include a plurality of ground bonding portions 42G and a plurality of power bonding portions 42P.
  • the ground via hole 41G is connected to the ground bonding portion 42G
  • the power supply via hole 41P is connected to the power supply bonding portion 42P.
  • FIGS. 1 to 4 wherein FIGS. 3 to 4 respectively illustrate the active surfaces 13 of two chips 1 of the same chipset 10 and two power supply wirings in the same chipset 10 .
  • One of the layers 2 is a power wiring layer 2P
  • the other is a ground wiring layer 2G. That is, the power signal lines 12P of the two chips 1 are both led out through the power wiring layer 2P, and the ground signal lines 12G of the two chips 1 are both led out through the ground wiring 20G.
  • FIGS. 5-6 respectively show the active surfaces 13 of two chips 1 of the same chipset 10.
  • the two power supply wiring layers 2 are both hybrid wiring layers 2PG.
  • both chips 1 include a first power supply signal line group 121 and a second power supply signal line group 122.
  • the power supply signal lines 12 of the first power supply signal line group 121 and the second power supply signal line group 122 both include a power supply signal line 12P. and ground signal line 12G.
  • the first power supply signal line group 121 of the two chips 1 is led out through one hybrid wiring layer 2PG
  • the second power supply signal line group 122 of the two chips 1 is led out through another hybrid wiring layer 2PG.
  • the power supply signal lines 12 (refer to FIGS. 3 to 6 ) in the same chip 1 are connected to the power supply wiring layer 2 , and the power supply wiring layers 2 of different chips 1 are independent of each other.
  • the power supply signal lines 12 are independent of each other. That is to say, the power supply signal lines 12 of multiple chips 1 do not need to be electrically connected together through the conductive vias 41 and the bonding portions 42 .
  • the power supply signal lines 12 in each chip 1 can be led out through the power supply wiring layer 2 of the chip 1 itself. , without needing to borrow the power supply wiring layer 2 of other chips 1 to lead out.
  • the power supply signal line 12 of each chip 1 can be drawn out separately, it is beneficial to improve the stability of the power supply.
  • the preparation steps of the bonding portion 42 and the conductive via 41 can be omitted, thereby reducing the production cost; in addition, multiple power supply wiring layers 212 can also be located on the same side of the chip 1, so that adjacent power supply wiring layers 2 can The distance between them is the same, that is, the distribution of the power supply wiring layer 2 is more uniform. After the planarization process, the side surface of the chip module 100 is relatively flat.
  • Example 2 The number of power supply wiring layers 2 may be greater than the number of chips 1.
  • the chips 1 on the outermost sides of the chip module 100 have a power supply wiring layer 2; there is a power supply wiring layer 2 between two adjacent chips 1, and the power supply wiring layer 2 and the power supply signal lines of the chips 1 on both sides 12 electrical connections.
  • each chip 1 has power supply wiring layers 2 on opposite sides. Part of the power supply signal lines 12 in the chip 1 are led out from the power supply wiring layer 2 on one side, and another part of the power supply signal lines 12 in the chip 1 are led out from the other side.
  • the power supply wiring layer 2 is led out. That is, except for the power supply wiring layers 2 on the outermost two sides, the other power supply wiring layers 2 are shared by the two chips 1 .
  • the side surface of the chip module 100 is relatively flat.
  • the power supply wiring layer 2 includes a power wiring layer 2P and a ground wiring layer 2G.
  • the power wiring layer 2P and the ground wiring layer 2G are alternately arranged in the first direction X.
  • the power wiring layer 2P located on the first side of the chip module 100 may be directly connected to the power signal line 12P of the first chip 1a. Therefore, the first chip 1a may not have the power through hole 41P and the power bonding portion 42P.
  • the first chip 1a and the second chip 1b share the ground wiring layer 2G, that is, the ground signal lines 12G of the two are connected together through the ground through holes 41G and the ground bonding portion 42G, and are led out through the ground wiring layer 2G between them. .
  • the second chip 1b and the third chip 1c share the power wiring layer 2P, that is, the power signal lines 12P of the two are connected together through the power through hole 41P and the power bonding portion 42P, and are led out through the power wiring layer 2P between them. ; Since the second chip 1b and the third chip 1c do not share the ground wiring layer 2G, there is no electrical connection between the ground via holes 41G and the ground bonding portions 42G of the two chips.
  • the number of power supply wiring layers 2 can also be less than the number of chips 1.
  • the chip module 100 has a power supply wiring layer 2 on both sides of the chip module 100, and is electrically connected to the chipsets 10 on both sides of the chip module 100 respectively. That is to say, except for the two power supply wiring layers 2 on the first and last sides that are not shared by the chipset 101 , the remaining power supply wiring layers 2 in the middle are shared by the chipsets 10 on both sides.
  • the chipsets 10 on both sides of the chip module 100 can be understood as the chipsets 10 on the outermost sides of the chip module 100.
  • the first chipset 101 and the second chipset 102 share the ground wiring layer 2G, that is, the ground signal lines 12G of the two are connected together through the ground via 41G and the ground bonding portion 42G, and through the ground wiring layer between them 2G lead out.
  • the first chipset 101 and the second chipset 102 do not share the power wiring layer 2P, so there is no electrical connection between the power vias 41P and the power bonding portions 42P of the two.
  • the second chipset 102 and the third chipset 103 are connected together through the power wiring layer 2P, that is, the power signal lines 12P of the two are connected through the power through holes 41P and the power bonding portion 42P, and pass through the power wiring layer between them. 2P elicitation.
  • the position and quantity of the power supply wiring layer 2 can also be adjusted according to the packaging situation of the chip module 100 .
  • Step 2 Stack multiple chips 1 to form a chip module 100; the stacking direction of the chips 1 is the second direction Y, and the second direction Y is the same as the first direction X.
  • the aforementioned stacking direction can also be understood as the arrangement direction of multiple chips 1; the component areas A of multiple chips 1 overlap, and the dicing lane areas B of multiple chips 1 overlap.
  • the chips 1 are first placed along the horizontal direction, that is, multiple chips 1 are arranged in the vertical direction of the horizontal direction. After multiple chips 1 are stacked to form the chip module 100, the chip module 100 is rotated 90° so that the multiple chips 1 are arranged in the horizontal direction. Thereafter, the chip module 100 is planarized.
  • Hybrid bonding can be used to connect multiple chips 1 .
  • the dielectric layers 43 of adjacent chips 1 may be connected together through molecular force or other forces.
  • the bonding portions 42 of adjacent chips 1 are bonded and connected together. That is to say, the dielectric layer 43 is made of insulating material and can play an isolation role; the bonding portion 42 is made of conductive material and can play an electrical connection role.
  • Step 3 After the chip module 100 is formed, the sides of the plurality of scribe lane areas B away from the component area A are planarized to remove at least part of the scribe lane areas B and expose the power supply wiring layer 2 . That is to say, in some embodiments, the planarization process can remove all of the dicing lane area B and expose the power supply wiring layer 2 located in the component area A, thereby helping to reduce the size of the chip module 100 . In other embodiments, the planarization process can also remove part of the dicing track area B and expose the power supply wiring layer 2 located in the dicing track area B, thereby conducive to shortening the process time.
  • the power supply wiring layer 2 extends from the component area A to the power supply wiring layer 2. Therefore, the planarization process can not only improve the flatness of the side of the chip module 100, but also ensure that the power supply wiring layer 2 is exposed while avoiding damage to the components. Area A to ensure the performance of the semiconductor structure. After the planarization process, the total thickness deviation (TTV) of the side of the chip module 100 can be less than 1um.
  • the planarization process includes at least one of a back grinding process and a chemical mechanical polishing process.
  • the back grinding process can be performed first.
  • the back grinding process includes two steps: rough grinding and fine grinding. That is, a grinding wheel is first used for rapid and precise grinding, and then an etching liquid is used for micro-etching of the surface to remove the particles caused by grinding. Destroys the layer and releases the stress. After that, a chemical mechanical polishing process is performed.
  • the chemical mechanical polishing process can obtain a highly flat surface while ensuring material removal efficiency.
  • planarization process also removes the dielectric layer 43 located at the end surface of the power supply wiring layer 2 away from the component region A to expose the power supply wiring layer 2.
  • Figure 11 is a cross-sectional view
  • Figure 12 is a top view of the semiconductor structure.
  • Step 4 Form the pad 5 on the side of the planarization process.
  • the pad 5 is connected to the power supply wiring layer 2 .
  • each power wiring 20P is connected to the pad 5
  • each ground wiring 20G is connected to the pad 5 .
  • the planarization process removes all of the scribe line area B, so the pad 5 is formed on the side of the device area A. In other embodiments, if part of the scribe line area B is removed by the planarization process, the pad 5 is formed on the side of the scribe line area B.
  • each chip 1 has only one dicing track area B, the bonding pad 5 can be formed only on one side of the chip 1 . If each chip 1 has two scribing lane areas B, the bonding pads 5 can be formed on opposite sides of the chip 1 . In this way, multi-layer chip modules 100 stacked in the first direction X can be formed to increase the capacity of the semiconductor structure, and adjacent chip modules 100 are electrically connected through the pads 5 .
  • the bonding pad 5 includes a plurality of first bonding pads 51 and a plurality of second bonding pads 52 .
  • the first bonding pads 51 and the second bonding pads 52 are respectively connected to the two power supply wiring layers 2 of the chipset 10 .
  • the first bonding pad 51 is directly opposite the gap between the two adjacent second bonding pads 52
  • the gap between the second bonding pad 52 and the two adjacent first bonding pads 51 is directly opposite. Is on.
  • the first bonding pad 51 may be disposed facing the second bonding pad 52 in the second direction Y. That is to say, in the second direction Y, the first bonding pad 51 and the second bonding pad 52 are not in a direct relationship. In this way, it is beneficial to increase the distance between the first bonding pad 51 and the second bonding pad 52 , thereby avoiding incorrect electrical connection between the first bonding pad 51 and the second bonding pad 52 .
  • the side where the two chips 1 face each other in the chipset 10 is called the inner side
  • the side where the two chips 1 face each other is called the outer side.
  • the inner surface of the soldering pad 5 can be flush with the inner surface of the power supply wiring layer 2
  • the outer surface of the soldering pad 5 can be protruding relative to the outer surface of the power supply wiring layer 2 . In this way, it is helpful to ensure that the soldering pad 5 while having a larger size, increase the distance between adjacent pads 5 in the second direction Y to avoid incorrect electrical connection of adjacent pads 5 .
  • FIGS. 13 to 17 which are all partial cross-sections, the steps for forming the pad 5 will be described in detail below.
  • a passivation layer 81 is formed on the side of the planarization process.
  • the passivation layer 81 has a first opening 81 a , and the first opening 81 a exposes part of the surface of the power supply wiring layer 2 .
  • a chemical vapor deposition process is used to deposit passivation materials such as silicon oxide and silicon nitride on the side of the chip module 100 as the passivation layer 81, and the passivation layer 81 is patterned to form the first opening 81a, thereby Part of the surface of the power supply wiring layer 2 is exposed.
  • a seed layer 82 is formed, covering the exposed portion of the surface of the power supply wiring layer 2 and the passivation layer 81 ; for example, titanium or copper is deposited as the seed layer 82 .
  • the seed layer 82 is beneficial to reducing the contact resistance between the subsequently formed pad 5 and the power supply wiring layer 2 .
  • a mask layer 83 is formed on the side of the passivation layer 81 away from the device region A, and the mask layer 83 is also located on the seed layer 82 .
  • the mask layer 83 is patterned to form a second opening 83 a , the second opening 83 a is directly opposite to the first opening 81 a , and the second opening 83 a exposes part of the surface of the seed layer 82 .
  • the seed layer 82 may not be formed.
  • the second opening 83 a exposes part of the surface of the power supply wiring layer 2 .
  • the material of the mask layer 83 may be photoresist, and the photoresist is subjected to a photolithography process to form the second opening 83a.
  • the width of the second opening 83a may be greater than the width of the first opening 81a, which is beneficial to increasing the contact area between the seed layer 82 and the subsequently formed pad 5, thereby reducing the contact resistance; in addition, it is beneficial to increase The volume of the pad 5 is increased to reduce the resistance of the pad 5 itself and improve the welding strength between the pad 5 and peripheral devices such as the substrate 9 (refer to Figure 18).
  • the bonding pad 5 is formed in the second opening 83 a; the bonding pad 5 also covers the seed layer 82 located within the second opening 83 a.
  • an electroplating process is used to plate metal such as copper or nickel in the second opening 83a to serve as a bonding pad.
  • a solder paste layer 53 may also be formed on the pad 5 , and the material of the solder paste layer 53 may be tin silver.
  • the mask layer 83 is removed, thereby exposing part of the surface of the seed layer 82 .
  • the seed layer 82 not covered by the pads 5 is removed to prevent multiple pads 5 from being electrically connected through the seed layer 82 .
  • the width of the pad 5 in the second direction Y is greater than the width of the power supply wiring layer 2 . That is, in the second direction Y, the width of the second opening 83 a (refer to FIG. 14 ) is larger than the width of the power supply wiring layer 2 . In this way, it is beneficial to reduce the resistance of the bonding pad 5 and increase the contact area between the bonding pad 5 and the power supply wiring layer 2, thereby reducing the contact resistance.
  • the planarization process can improve the flatness of the side of the chip module 100, thereby avoiding affecting the manufacturing process of the pad 5, and thereby avoiding affecting the power supply of the chip module 100.
  • the planarization process is facilitated to expose the power supply wiring layer 2 to ensure that the power supply wiring layer 2 can be electrically connected to the pad 5, thereby improving the reliability of the power supply.
  • another embodiment of the present disclosure also provides a semiconductor structure.
  • This semiconductor structure can be manufactured using the manufacturing method of the semiconductor structure provided in the previous embodiment.
  • the semiconductor structure please refer to the previous implementation. example.
  • the semiconductor structure includes: a chip module 100, including a plurality of stacked chips 1.
  • the chip 1 includes component areas A arranged along a first direction X.
  • the stacking direction of the chips 1 is a second direction Y, and the second direction Y is perpendicular to the One direction Connect the power supply wiring layer 2.
  • the final semiconductor structure does not include the dicing track area B, and the power supply wiring layer 2 located in the component area A is connected to the pad 5; if the planarization process If only part of the dicing track area B is removed during the process, the final semiconductor structure also includes part of the dicing track area B, and the power supply wiring layer 2 located in the dicing track area B is connected to the pad 5 .
  • the semiconductor device may include the semiconductor structure provided in the foregoing embodiments.
  • the semiconductor structure may include the semiconductor structure provided in the foregoing embodiments.
  • the semiconductor device includes: a substrate 9; a chip module 100, which is disposed on the substrate 9 and includes a plurality of stacked chips 1.
  • the chip 1 includes element areas A arranged along the first direction X.
  • the stacking direction of 100 is the second direction Y, and the second direction Y is perpendicular to the first direction
  • the edge of 1 extends; wherein, a bonding pad 5 is also provided on the side of the chip 1, and the bonding pad 5 is connected to the power supply wiring layer 2.
  • the substrate 9 can provide functions such as electrical connection, protection, support, heat dissipation, and assembly for the chip module 100 .
  • a power supply may be provided on the substrate 9 , and the pad 5 may be electrically connected to the power supply (not shown in the figure) on the substrate 9 to provide power to the chip module 100 .
  • the chip 1 is a memory chip
  • the semiconductor device further includes: a logic chip 91 located between the chip module 100 and the substrate 9 ; the logic chip 91 has a first wireless communication part 92 ; the memory chip has a second Wireless communication unit 11; the first wireless communication unit 92 performs wireless communication with the second wireless communication unit 11.
  • the side of the memory chip faces the logic chip 91 , and the area on the side is smaller. If wireless communication is used to realize communication between the memory chip and the logic chip 91 , there is no need to set a wire between the memory chip and the logic chip 91 . Communication part, therefore, the spatial position between the memory chip and the logic chip 91 can only be used to arrange the power supply path of the memory chip, thereby reducing process difficulty.
  • the second wireless communication unit 11 is located on the side of the memory chip facing the logic chip 91 .
  • the distance between the first wireless communication unit 92 and the second wireless communication unit 11 can be reduced, thereby improving the quality of wireless communication.
  • the logic chip 91 has a power supply port
  • the chip module 100 has one side of the bonding pad 5 facing the logic chip 91
  • the bonding pad 5 is electrically connected to the power supply port of the logic chip 91 .
  • the upper surface of the logic chip 92 has a bonding pad 54
  • the bonding pad 54 serves as a power supply port of the logic chip 91
  • the bonding pad 54 is connected to the bonding pad 5 of the chip module 100 through the solder paste layer 53 .
  • the power supply port of the logic chip 91 is electrically connected to the power supply on the substrate 9 to provide power to the chip module 100 .
  • the bonding pad 5 can not only electrically connect the power supply wiring layer 2 and the power supply port of the logic chip 91 , but can also fix the memory chip on the logic chip 91 . Therefore, there is no need to provide other fixed structures between the memory chip and the logic chip 91, which is beneficial to reducing the size of the semiconductor structure.
  • the substrate 9 has a power supply port.
  • the power supply port of the substrate 9 is located on the power supply.
  • the chip module 100 has one side of the pad 5 facing away from the logic chip 91 , and the pad 5 is connected to the power supply.
  • the power supply port of the substrate 9 is electrically connected.
  • the pad 5 and the power supply port are connected through conductive structures such as leads 95 and lead frames 96 .
  • the logic chip 91 and the chip module 100 can be bonded together through an adhesive layer 94 , and the logic chip 91 is soldered to the substrate 9 through solder balls 93 . The bonding process is simple and the production cost is low.
  • the bonding pad 5 is only used to lead out the power supply wiring layer 2 and is not used to fix the memory chip on the logic chip 91 . Since the bonding pad 5 and the wireless communication path are located on the upper and lower sides of the chip module 100, the current in the bonding pad 5 can be prevented from causing electromagnetic interference to the wireless communication, thereby avoiding signal loss.
  • each chip 1 has a power supply wiring layer 2. More power supply wiring layers 2 are beneficial to improving the stability of the power supply, thereby improving the performance of the semiconductor structure.
  • the power supply signal lines 12 in the same chip 1 are connected to the power supply wiring layer 2; the power supply wiring layers 2 of different chips 1 are independent of each other, and the power supply signal lines 2 of different chips 1 are independent of each other.
  • At least two adjacent chips 1 are bonded and form a chipset 10; there is a power supply wiring layer 2 between the two adjacent chipsets 10, and the power supply wiring layer 2 is connected to the power supply wiring layer 2.
  • the memory chips 1 of the chipsets 10 on both sides are electrically connected; the chip module 100 has a power supply wiring layer 2 on both sides of the front and rear, and is electrically connected to the chipsets 10 on both sides of the chip module 100 respectively.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构的制造方法、半导体结构和半导体器件，半导体结构的制造方法包括：提供多个芯片，芯片包括在第一方向排列的元件区和划片道区；多个芯片中的至少一者具有供电布线层，供电布线层从元件区延伸至划片道区；将多个芯片堆叠设置，以形成芯片模块；芯片的堆叠方向为第二方向，第二方向与第一方向垂直；多个芯片的元件区相重叠，多个芯片的划片道区相重叠；形成芯片模块后，对多个划片道区远离元件区的侧面进行平坦化处理，以至少去除部分划片道区，并露出供电布线层；在平坦化处理的侧面形成焊盘，焊盘与供电布线层相连。本公开实施例至少可以提高半导体结构的性能。

Description

半导体结构的制造方法、半导体结构和半导体器件
交叉引用
本申请引用于2022年8月10日递交的名称为“半导体结构的制造方法、半导体结构和半导体器件”的第202210957848.8号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开属于半导体领域，具体涉及一种半导体结构的制造方法、半导体结构和半导体器件。
背景技术
为提高半导体结构的集成度，可以在同一封装结构内放置一个以上的芯片。HBM(High Bandwidth Memory，高带宽内存)是一款新型的内存。以HBM为代表的芯片堆叠技术，将原本一维的存储器布局扩展到三维，即将很多个芯片堆叠在一起并进行封装，从而大幅度提高了芯片的密度，并实现了大容量和高带宽。
然而，HBM的性能有待提升。
发明内容
本公开实施例提供一种半导体结构、半导体结构的制造方法和半导体器件，至少有利于提高半导体结构的性能。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，其中，半导体结构的制造方法包括：提供多个芯片，所述芯片包括在第一方向排列的元件区和划片道区；所述多个芯片中的至少一者具有供电布线层，所述供电布线层从所述元件区延伸至所述划片道区；将多个所述芯片堆叠设置，以形成芯片模块；所述芯片的堆叠方向为第二方向，所述第二方向与所述第一方向垂直；多个所述芯片的所述元件区相重叠，多个所述芯片的所述划片道区相重叠；形成所述芯片模块后，对多个所述划片道区远离所述元件区的侧面进行平坦化处理，以至少去除部分所述划片道区，并露 出所述供电布线层；在所述平坦化处理的侧面形成焊盘，所述焊盘与所述供电布线层相连。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构，半导体结构包括：芯片模块，包括多个堆叠设置的芯片，所述芯片上包括沿第一方向排列的元件区，所述芯片的堆叠方向为第二方向，所述第二方向垂直于所述第一方向；其中，至少一所述芯片还具有供电布线层，所述供电布线层沿着所述元件区向所述芯片的边缘延伸；其中，所述芯片的侧面上还设置有焊盘，所述焊盘连接所述供电布线层。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体器件，半导体器件包括：基板；芯片模块，设置在所述基板上，包括多个堆叠设置的芯片，所述芯片上包括沿第一方向排列的元件区，所述芯片的堆叠方向为第二方向，所述第二方向垂直于所述第一方向；其中，至少一所述芯片上还具有供电布线层，所述供电布线层沿着所述元件区向所述芯片的边缘延伸；其中，所述芯片的侧面上还设置有焊盘，所述焊盘连接所述供电布线层。
本公开实施例提供的技术方案至少具有以下优点：对划片道区进行平坦化处理，从而提高芯片模块侧面的平整程度，避免影响在芯片模块的侧面形成焊盘。此外，供电布线层延伸至划片道区使得平坦化处理更易露出供电布线层，并避免过度的平坦化处理对元件区造成损伤。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图17分别示出了本公开一实施例提供的半导体结构的制造方法中各步骤对应的结构示意图；
图18-图19示出了本公开又一实施例提供的不同半导体器件的示意图。
具体实施方式
由于工艺误差，多个芯片堆叠形成的芯片模块的侧面的总厚度偏差(Total Thickness Variation，TTV)较大。也就是说，多个芯片的侧面存在参差不齐的情况，从而会影响在芯片侧面制造焊盘的过程，进而降低焊盘与 外围器件的焊接强度，半导体结构的性能受到影响。
本公开实施例提供一种半导体结构的制造方法，提供多个芯片，芯片包括元件区和划片道区；形成芯片模块后，对多个划片道区远离元件区的侧面进行平坦化处理，以至少去除部分划片道区。即，在形成芯片模块前保留划片道区；在形成芯片模块后利用划片道区进行平坦化处理，从而提高芯片模块侧面的平整程度。相比于供电布线层只位于元件区，供电布线层延伸至划片道区使得平坦化处理更易露出供电布线层，并避免过度的平坦化处理对元件区造成损伤。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图1-图17所示，本公开一实施例提供一种半导体结构的制造方法。以下将结合附图对半导体结构的制造方法进行详细说明。
具体地，参考图1-图10，步骤一：提供多个芯片1，芯片1包括在第一方向X排列的元件区A和划片道区B。示例地，元件区A内具有晶体管、电容、字线和位线等元件。此外，元件区A内还具有多条供电信号线12(参考图3-图5)，供电信号线12可以为元件提供多种电压信号，比如，数字信号或模拟信号。供电信号线12可以为接地信号线12G或电源信号线12P。不同的接地信号线12G具有不同的电压信号，不同的电源信号线12P具有不同的电压信号。
需要说明的是，多个芯片1是由晶圆切割形成的。即，通常会采用激光照射划片道区B的中心线位置，以形成改质层。后续沿着改质层将晶圆分割成多个芯片1，因此，划片道区B内通常不会设置元件。
继续参考图1-图10，多个芯片1中的至少一者具有供电布线层2，供电布线层2从元件区A延伸至划片道区B。供电布线层2与元件区A内的供电信号线12电连接，以通过供电布线层2向元件区A的元件提供电压信号。
在一些实施例中，划片道区B具有覆盖供电布线层2的介质层43；供电布线层2具有远离元件区A的端面14；即介质层43还覆盖了供电布线层2的端面14。此外，介质层43还可以覆盖芯片1的正面或背面。
供电布线层2伸入划片道区B能够为后续平坦化处理设置一定的工艺余量，避免过度平坦化处理而损伤元件区A内的元件。换言之，若供电布线层2只位于元件区A内，或者供电布线层2的端面与元件区A的侧面齐平，则为了露出供电布线层2，需要相应延长平坦化处理的时间，从而可能磨掉部分元件区A，进而可能影响半导体结构的良率和性能。
在第一方向X上，划片道区B的宽度L2与位于划片道区B的供电布线层2的长度L1之比为10:3～2:1。值得注意的是，若供电布线层2伸入划 片道区B的长度过短，则在平坦化处理的程度不足时，供电布线层2可能不会露出。若供电布线层2伸入划片道区B的长度过长，则可能会影响激光切割的过程，即供电布线层2将激光反射至元件区A，进而可能损坏元件区A内的器件。当划片道区B的宽度与划片道区B的供电布线层2的长度之比处于上述范围时，有利于兼顾上述两方面的问题。
示例地，划片道区B的供电布线层2在第一方向X上的长度L1为30um～50um，比如40um；划片道区B在第一方向X上的宽度L2为90um～110um，比如100um。如此，有利于平坦化处理充分露出供电布线层2的端面，且降低对激光切割的影响。
在一些实施例中，参考图1和图7-图9，每个芯片1包括一个划片道区B，由此，后续可以在芯片模块100的一侧形成焊盘5(参考图11)。在另一些实施例中，参考图2，每个芯片1包括两个划片道区B，且两个划片道区B位于元件区A的相对两侧，供电布线层2从芯片1区延伸至两个划片道区B。由此，后续可以在芯片模块100的相对两侧形成焊盘5。
图3-图6分别示出了芯片1的不同有源面13的示意图。参考图3-图6，供电布线层2可以沿着芯片1的有源面13延伸，相应地，供电信号线12也可以由芯片1内被引出至芯片1的有源面13，从而与有源面13上的供电布线层2电连接。
有源面13也可以理解为芯片1的正面，因此，在芯片1内的元件制造完成后，可以利用原有的后段工艺制造供电布线层2，工艺更加简单。另外，供电布线层2可以只在靠近芯片1的上侧或下侧的边缘位置延伸，而无需覆盖整个芯片1的有源面13，因此，供电布线层2与芯片1的接触面积小，供电布线层2的热量对芯片1的影响较小。
供电布线层2为电源布线层2P、接地布线层2G或混合布线层2PG。即一个供电布线层2包括了多个相互隔离的供电布线20，根据每个供电布线层2的供电布线20的种类，可以将供电布线层2分成上述三类。
参考图3，电源布线层2P包括多条电源布线20P，多条电源布线20P间隔设置，且具有不同的电压信号。参考图4，接地布线层2G包括多条接地布线20G，多条接地布线20G具有不同的电压信号；接地布线20G与接地信号线12G对应电连接，电源布线20P与电源信号线12P对应电连接。
参考图5-图6，混合布线层2PG包括多条电源布线20P和多条接地布线20G，电源布线20P与接地布线20G间隔设置，且不同电源布线20P具有不同的电压信号，不同接地布线20G具有不同的电压信号。
在一实施例中，同一混合布线层2PG的接地布线20G与电源布线20P在第三方向Z上交替排布，第三方向Z与第一方向X和第二方向Y相垂直。由于接地布线20与电源布线20P交替排列有利于降低相邻供电布线20的电磁干扰。
若一个芯片1自身具有供电布线层2，则此芯片1的至少部分供电信号线12可以直接与自身的供电布线层2连接，即，通过自身的供电布线层 2引出。若一个芯片1自身不具有供电布线层2，则此芯片1的供电信号线12可以通过其他芯片1的供电布线层2引出，换言之，此芯片1可以通过导电通孔41以及键合部42与其他的芯片1建立电连接关系，从而将自身的供电信号线12与其他芯片1的供电信号线12电连接，进而与其他芯片1的供电布线层2电连接。
在一些实施例中，多个芯片1具有供电布线层2。以下将对芯片1与供电布线层2的位置及数量关系进行详细说明。
示例一，参考图1-图8，每个芯片1均具有一个供电布线层2，即芯片1的数量与供电布线层2的数量相同。较多的供电布线层2有利于提高供电的稳定性，进而提高半导体结构的性能；此外，多个供电布线层2是均匀设置在多个芯片1内的，因此，有利于统一不同芯片1的制造工艺，以降低生产成本。
在一些实施例中，参考图1-图2；两个相邻的芯片1构成芯片组10，同一芯片组10的两个芯片1之间具有两个供电布线层2，两个供电布线层2分别位于两个芯片1的表面。示例地，芯片组10的两个芯片1是正面对正面的键合，即有源面13对有源面13。
具体地，芯片1内具有导电通孔41，示例地，导电通孔41为硅穿孔(Through-Silicon Vias，TSV)；同一芯片组10的两个芯片1之间具有键合部42，键合部42与两个芯片1的导电通孔41连接，以使芯片1电连接。示例地，每个芯片1内均具有多个间隔设置导电通孔41，且多个导电通孔41与芯片1内的多个供电信号线12(参考图3-图6)一一对应连接。同一芯片1内的多个供电信号线12上的电压信号不同，相应地，同一芯片1内的多个导电通孔41上的电压信号也不相同。在同一芯片组10的两个芯片1中，具有相同电压信号的导电通孔41通过键合部42电连接，从而使得两个芯片1中具有相同电压信号的供电信号线12被电连接在一起。
举例而言，导电通孔41包括多个接地通孔41G和多个电源通孔41P，键合部42包括多个接地键合部42G和多个电源键合部42P。接地通孔41G与接地键合部42G相连，电源通孔41P与电源键合部42P相连。
在一些实施例中，结合参考图1-图4，其中，图3-图4分别示出了同一芯片组10的两个芯片1的有源面13，同一芯片组10内的两个供电布线层2中的一者为电源布线层2P，另一者为接地布线层2G。即两个芯片1的电源信号线12P均通过电源布线层2P引出，两个芯片1的接地信号线12G均通过接地布线20G引出。
在另一些实施例中，结合参考图1-图2和图5-图6，图5-图6分别示出了同一芯片组10的两个芯片1的有源面13，同一芯片组10内的两个供电布线层2均为混合布线层2PG。换言之，两个芯片1均包括第一供电信号线组121和第二供电信号线组122，第一供电信号线组121和第二供电信号线组122的供电信号线12均包括电源信号线12P和接地信号线12G。其中，两个芯片1的第一供电信号线组121通过一个混合布线层2PG引出，两个 芯片1的第二供电信号线组122通过另一个混合布线层2PG引出。
在另一些实施例中，参考图7，同一芯片1内的供电信号线12(参考图3-图6)与供电布线层2相连，不同芯片1的供电布线层2相互独立，不同芯片1的供电信号线12相互独立。也就是说，多个芯片1的供电信号线12无需通过导电通孔41和键合部42电连接在一起，每个芯片1内的供电信号线12可以通过芯片1自身的供电布线层2引出，而无需借用其他芯片1的供电布线层2引出。
由于每个芯片1的供电信号线12可以被单独引出，因此，有利于提高供电的稳定性。此外，还可以省去键合部42和导电通孔41的制备步骤，从而降低生产成本；此外，多个供电布线层212还可以位于芯片1的同一侧，从而使得相邻供电布线层2之间的距离相同，即供电布线层2分布更为均匀，在平坦化处理后，芯片模块100的侧面的平整程度较高。
示例二，供电布线层2的数量可以多于芯片1的数量。参考图8，芯片模块100最外两侧的芯片1具有供电布线层2；相邻两个芯片1之间具有一个供电布线层2，且供电布线层2与其两侧的芯片1的供电信号线12电连接。换言之，每个芯片1的相对两侧都具有供电布线层2，芯片1内的部分供电信号线12从一侧的供电布线层2引出，芯片1内的另一部分供电信号线12从另一侧的供电布线层2引出。即，除了最外两侧的供电布线层2，其余的供电布线层2均被两个芯片1所共用。
由于相邻供电布线层2之间的距离大致相同，供电布线层2的分布更为均匀，在平坦化处理后，芯片模块100的侧面的平整程度较高。
以下将对共用方式进行举例说明，供电布线层2包括电源布线层2P和接地布线层2G，电源布线层2P与接地布线层2G在第一方向X上交替排布。位于芯片模块100首侧的电源布线层2P可以直接与第一芯片1a的电源信号线12P相连，因此，第一芯片1a可以不具有电源通孔41P和电源键合部42P。第一芯片1a与第二芯片1b共用接地布线层2G，即二者的接地信号线12G通过接地通孔41G和接地键合部42G连接在一起，并通过二者之间的接地布线层2G引出。第二芯片1b与第三芯片1c共用电源布线层2P，即二者的电源信号线12P通过电源通孔41P和电源键合部42P连接在一起，并通过二者之间的电源布线层2P引出；由于第二芯片1b与第三芯片1c不共用接地布线层2G，因此二者的接地通孔41G和接地键合部42G不会产生电连接关系。
示例三，供电布线层2的数量也可以少于芯片1的数量。举例而言，参考图9；至少两个相邻的芯片1相键合，并构成芯片组10；相邻两个芯片组10之间具有一个供电布线层2，且供电布线层2与其两侧的芯片组10的芯片1电连接；芯片模块100首尾两侧具有一个供电布线层2，且分别与首尾两侧的芯片组10电连接。也就是说，除了首尾两侧的两个供电布线层2不被芯片组101共用外，其余中间位置的供电布线层2均被其两侧的芯片组10共用。芯片模块100首尾两侧的芯片组10可以理解为芯片模块100最外 两侧的芯片组10。
以下将对供电布线层2的共用方式进行举例说明。第一芯片组101与第二芯片组102共用接地布线层2G，即二者的接地信号线12G通过接地通孔41G和接地键合部42G连接在一起，并通过二者之间的接地布线层2G引出。第一芯片组101与第二芯片组102不共用电源布线层2P，因此二者的电源通孔41P和电源键合部42P不发生电连接关系。第二芯片组102与第三芯片组103用电源布线层2P，即二者的电源信号线12P通过电源通孔41P和电源键合部42P连接在一起，并通过二者之间的电源布线层2P引出。
需要注意的是，除上述几个示例外，还可以根据芯片模块100的封装情况对供电布线层2的位置和数量进行调整。
参考图1-图2和图7-图9，步骤二：将多个芯片1堆叠设置，以形成芯片模块100；芯片1的堆叠方向为第二方向Y，第二方向Y与第一方向X垂直，前述的堆叠方向也可以理解为多个芯片1的排列方向；多个芯片1的元件区A相重叠，多个芯片1的划片道区B相重叠。
具体地，先将芯片1沿着水平方向放置，即多个芯片1在水平方向的垂直方向上排列。多个芯片1堆叠并形成芯片模块100后，将芯片模块100旋转90°，使得多个芯片1在水平方向上排列。此后，再对芯片模块100进行平坦化处理。
可以采用混合键合的方式以连接多个芯片1。具体地，相邻芯片1的介质层43可以通过分子力等作用力连接在一起。此外，在升温条件下，相邻芯片1的键合部42发生键合连接在一起。也就是说，介质层43为绝缘材料，能够起到隔离作用；键合部42为导电材料，能够起到电气连接的作用。
参考图10，步骤三：形成芯片模块100后，对多个划片道区B远离元件区A的侧面进行平坦化处理，以至少去除部分划片道区B，并露出供电布线层2。也就是说，在一些实施例中，平坦化处理可以去除全部的划片道区B，并露出位于元件区A的供电布线层2，从而有利于减小芯片模块100的体积。在另一些实施例中，平坦化处理也可以去除部分的划片道区B，并露出位于划片道区B的供电布线层2，从而有利于缩短工艺时间。
由前述可知，供电布线层2从元件区A延伸至供电布线层2，因此，平坦化处理不仅能提高芯片模块100侧面的平整度，还能在保证露出供电布线层2的同时，避免损伤元件区A，以保证半导体结构的性能。经平坦化处理后，芯片模块100侧面的总厚度偏差(TTV)可以小于1um。
在一些实施例中，平坦化处理包括背面研磨工艺和化学机械研磨工艺至少一者。示例地，可以先进行背面研磨工艺，背面研磨工艺包括粗磨和细磨两个步骤，即先采用研磨轮进行快速而精密的研磨，再以蚀刻液进行表面微蚀刻，藉以去除因研磨产生的破坏层，并释放应力。此后，再进行化学机械研磨工艺，化学机械研磨工艺可以在保证材料去除效率的同时，获得平整度高的表面。
示例地，平坦化处理还去除位于供电布线层2远离元件区A的端面的 介质层43，以露出供电布线层2。
图11为剖面图，图12为半导体结构的俯视图，为更加直观，图12只示出半导体结构的部分结构；参考图11-图12，步骤四：在平坦化处理的侧面形成焊盘5，焊盘5与供电布线层2相连。具体地，每条电源布线20P均与焊盘5连接，每条接地布线20G均与焊盘5连接。
在一些实施例中，平坦化处理去除了全部的划片道区B，因此，焊盘5形成于元件区A的侧面。在另一些实施例中，若平坦化处理去除了部分的划片道区B，则焊盘5形成于划片道区B的侧面。
需要说明的是，若每个芯片1只具有一个划片道区B，则可以只在芯片1的一侧形成焊盘5。若每个芯片1具有两个划片道区B，则可以在芯片1的相对两侧形成焊盘5。如此，可以形成在第一方向X堆叠的多层芯片模块100以提高半导体结构的容量，且相邻芯片模块100之间通过焊盘5电连接。
参考图12，焊盘5包括多个第一焊盘51和多个第二焊盘52，第一焊盘51和第二焊盘52分别与芯片组10的两个供电布线层2相连。在第二方向Y上，第一焊盘51与两个相邻的第二焊盘52之间的间隙正对，第二焊盘52与两个相邻的第一焊盘51之间的间隙正对。在另一些实施例中，第一焊盘51可以与第二焊盘52在第二方向Y上正对设置。也就是说，在第二方向Y上，第一焊盘51与第二焊盘52不是正对关系。如此，有利于增大第一焊盘51和第二焊盘52之间的距离，从而避免第一焊盘51和第二焊盘52发生错误的电连接。
为便于理解，将芯片组10内两个芯片1相向的一侧称为内侧，将两个芯片1相背的一侧称为外侧。焊盘5在内侧的表面可以与供电布线层2在内侧的表面齐平，焊盘5在外侧的表面可以相对于供电布线层2在外侧的表面呈凸出设置，如此，有利于保证焊盘5在具有较大尺寸的同时，增加相邻焊盘5在第二方向Y上的距离，以避免相邻焊盘5发生错误的电连接。
参考图13-图17，图13-图17均为局部剖面，以下将对焊盘5的形成步骤进行详细说明。
参考图13，在平坦化处理的侧面形成钝化层81，钝化层81具有第一开口81a，第一开口81a露出供电布线层2的部分表面。示例地，采用化学气相沉积工艺在芯片模块100的侧面沉积氧化硅、氮化硅等钝化材料以作为钝化层81，并对钝化层81进行图形化处理以形成第一开口81a，从而露出供电布线层2的部分表面。
参考图14，形成种子层82，种子层82覆盖供电布线层2被露出的部分表面以及钝化层81；示例地，沉积钛或铜以作为种子层82。种子层82有利于减小后续形成的焊盘5与供电布线层2的接触电阻。
继续参考图14，在钝化层81远离元件区A的一侧形成掩膜层83，掩膜层83还位于种子层82上。对掩膜层83进行图形化处理，以形成第二开口83a，第二开口83a与第一开口81a正对，且第二开口83a露出种子层82 的部分表面。在另一些实施例中，也可以不形成种子层82，此时，第二开口83a露出供电布线层2的部分表面。
示例地，掩膜层83的材料可以为光刻胶，对光刻胶进行光刻处理以形成第二开口83a。
在一些实施例中，第二开口83a的宽度可以大于第一开口81a的宽度，从而有利于增大种子层82与后续形成的焊盘5的接触面积，进而降低接触电阻；此外还有利于增大焊盘5的体积，以降低焊盘5自身的电阻，并提高焊盘5与基板9(参考图18)等外围器件的焊接强度。
参考图15，在第二开口83a中形成焊盘5；焊盘5还覆盖位于第二开口83a内的种子层82。示例地，采用电镀工艺在第二开口83a中镀上铜或镍等金属以作为焊盘。此后，还可以在焊盘5上形成焊膏层53，焊膏层53的材料可以为锡银。
参考图16，去除掩膜层83，从而露出种子层82的部分表面。参考图18，去除未被焊盘5覆盖的种子层82，以避免多个焊盘5通过种子层82而电连接。
在一些实施例中，参考图11-图12，焊盘5在第二方向Y上的宽度大于供电布线层2的宽度。即，在第二方向Y上，第二开口83a(参考图14)的宽度大于供电布线层2的宽度。如此，有利于降低焊盘5的电阻，且增大焊盘5与供电布线层2的接触面积，进而降低接触电阻。
综上所述，平坦化处理可以提高芯片模块100的侧面的平整程度，从而避免影响焊盘5的制造过程，进而避免影响芯片模块100的供电。此外，由于供电布线层2伸入划片道区B，从而便于平坦化处理露出供电布线层2，以保证供电布线层2能够与焊盘5电连接，进而提高供电的可靠性。
参考图11-图12，本公开另一实施例还提供一种半导体结构，此半导体结构可以采用前述实施例所提供的半导体结构的制造方法进行制造，有关此半导体结构的详细说明可参考前述实施例。
半导体结构包括：芯片模块100，包括多个堆叠设置的芯片1，芯片1上包括沿第一方向X排列的元件区A，芯片1的堆叠方向为第二方向Y，第二方向Y垂直于第一方向X；其中，至少一芯片1还具有供电布线层2，供电布线层2沿着元件区A向芯片1的边缘延伸；其中，芯片1的侧面上还设置有焊盘5，焊盘5连接供电布线层2。
需要说明的是，若平坦化处理将芯片1的划片道区B完全去除，最终的半导体结构不包括划片道区B，且位于元件区A的供电布线层2与焊盘5相连；若平坦化处理只去除部分划片道区B，则最终的半导体结构还包括部分划片道区B，且位于划片道区B的供电布线层2连接焊盘5。
本公开又一实施例还提供一种半导体器件，半导体器件可以包括前述实施例提供的半导体结构，有关此半导体结构的详细说明可参考前述实施例。
参考图18-图19，半导体器件包括：基板9；芯片模块100，设置在基板9上，包括多个堆叠设置的芯片1，芯片1上包括沿第一方向X排列的 元件区A，芯片模块100的堆叠方向为第二方向Y，第二方向Y垂直于第一方向X；其中，至少一所述芯片1上还具有供电布线层2，供电布线层2沿着元件区A向所述芯片1的边缘延伸；其中，芯片1的侧面上还设置有焊盘5，焊盘5连接供电布线层2。
示例地，基板9可为芯片模块100提供电连接、保护、支撑、散热、组装等功效。基板9上可以设置有电源，焊盘5可以与基板9上的电源(图中未示出)电连接，从而为芯片模块100供电。
在一些实施例中，芯片1为存储芯片，半导体器件还包括：逻辑芯片91，逻辑芯片91位于芯片模块100与基板9之间；逻辑芯片91具有第一无线通信部92；存储芯片具有第二无线通信部11；第一无线通信部92与第二无线通信部11进行无线通信。
需要说明的是，存储芯片的侧面朝向逻辑芯片91设置，侧面的面积较小；而采用无线通信的方式实现存储芯片与逻辑芯片91的通信，则无需在存储芯片与逻辑芯片91之间设置有线通信部，因此，存储芯片与逻辑芯片91之间空间位置可以仅用于布置存储芯片的供电路径，从而降低工艺难度。
举例而言，第二无线通信部11位于存储芯片朝向逻辑芯片91的一侧。由此，可以减小第一无线通信部92与第二无线通信部11之间的距离，从而提升无线通信的质量。
在一些实施例中，参考图18，逻辑芯片91具有供电端口，芯片模块100具有焊盘5的一侧朝向逻辑芯片91，且焊盘5与逻辑芯片91的供电端口电连接。示例地，逻辑芯片92的上表面具有焊垫54，焊垫54作为逻辑芯片91的供电端口，焊垫54通过焊膏层53与芯片模块100的焊盘5连接。逻辑芯片91的供电端口与基板9上的电源电连接，从而为芯片模块100供电。
也就是说，焊盘5不仅可以将供电布线层2与逻辑芯片91的供电端口电连接，还能够将存储芯片固定在逻辑芯片91上。因此，无需在存储芯片与逻辑芯片91之间设置其他的固定结构，有利于缩小半导体结构的体积。
在另一些实施例中，参考图19，基板9具有供电端口，示例地，基板9的供电端口位于电源上，芯片模块100具有焊盘5的一侧背向逻辑芯片91，且焊盘5与基板9的供电端口电连接。示例地，通过引线95和引线框架96等导电结构连接焊盘5与供电端口。此外，逻辑芯片91与芯片模块100可以通过粘结层94粘接在一起，逻辑芯片91通过焊球93焊接在基板9上。粘结工艺简单，生产成本低。
也就是说，焊盘5只用于引出供电布线层2，而不用于将存储芯片固定在逻辑芯片91上。由于焊盘5和无线通信路径位于芯片模块100的上下两侧，从而可以避免焊盘5中的电流对无线通信造成电磁干扰，以避免信号损失。
在一些实施例中，参考图1、图2和图7，每个芯片1均具有一个供 电布线层2，较多的供电布线层2有利于提高供电的稳定性，进而提高半导体结构的性能。举例而言，同一芯片1内的供电信号线12与供电布线层2相连；不同芯片1的供电布线层2相互独立，不同芯片1的供电信号线2相互独立。
在一些实施例中，参考图9，至少两个相邻的芯片1相键合，并构成芯片组10；相邻两个芯片组10之间具有一个供电布线层2，且供电布线层2与其两侧的芯片组10的存储芯片1电连接；芯片模块100首尾两侧具有一个供电布线层2，且分别与首尾两侧的芯片组10电连接。
有关芯片1与供电布线层2的位置关系和数量关系的详细说明可参考前述实施例，在此不再赘述。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (24)

  1. 一种半导体结构的制造方法，包括：
    提供多个芯片，所述芯片包括在第一方向排列的元件区和划片道区；所述多个芯片中的至少一者具有供电布线层，所述供电布线层从所述元件区延伸至所述划片道区；
    将多个所述芯片堆叠设置，以形成芯片模块；所述芯片的堆叠方向为第二方向，所述第二方向与所述第一方向垂直；多个所述芯片的所述元件区相重叠，多个所述芯片的所述划片道区相重叠；
    形成所述芯片模块后，对多个所述划片道区远离所述元件区的侧面进行平坦化处理，以至少去除部分所述划片道区，并露出所述供电布线层；
    在所述平坦化处理的侧面形成焊盘，所述焊盘与所述供电布线层相连。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，
    所述平坦化处理去除全部的所述划片道区，并露出位于所述元件区的所述供电布线层；
    所述焊盘形成于所述元件区的侧面。
  3. 根据权利要求1所述的半导体结构的制造方法，其中，
    所述供电布线层具有远离所述元件区的端面；
    所述划片道区具有覆盖所述供电布线层的介质层；
    所述平坦化处理包括：去除位于所述端面的所述介质层，以露出所述供电布线层。
  4. 根据权利要求3所述的半导体结构的制造方法，其中，在所述第一方向上，所述划片道区的宽度与位于所述划片道区的所述供电布线层的长度之比为10:3～2:1。
  5. 根据权利要求4所述的半导体结构的制造方法，其中，所述划片道区的所述供电布线层在所述第一方向上的长度为30um～50um；
    所述划片道区在所述第一方向上的宽度为90um～110um。
  6. 根据权利要求1所述的半导体结构的制造方法，其中，所述平坦化处理包括背面研磨工艺和/或化学机械研磨工艺。
  7. 根据权利要求1所述的半导体结构的制造方法，其中，在所述平坦化处理后，在形成所述焊盘前，还包括：
    在所述平坦化处理的侧面形成钝化层，所述钝化层具有第一开口，所述第一开口露出所述供电布线层的部分表面；
    在所述钝化层远离所述元件区的一侧形成掩膜层；
    对所述掩膜层进行图形化处理，以形成第二开口，第二开口与第一开口正对；
    在所述第二开口中形成所述焊盘；
    形成所述焊盘后，去除所述掩膜层。
  8. 根据权利要求7所述的半导体结构的制造方法，其中，在形成所述掩膜层，还包括：
    形成种子层，所述种子层覆盖所述供电布线层被露出的部分表面以及所述钝化层；
    形成所述种子层后，形成所述掩膜层，且所述第二开口还露出所述种子层的部分表面；
    所述焊盘还覆盖位于所述第二开口内的所述种子层；
    形成所述焊盘后，去除未被所述焊盘覆盖的所述种子层。
  9. 根据权利要求7所述的半导体结构的制造方法，其中，在所述第二方向上，所述第二开口的宽度大于所述供电布线层的宽度。
  10. 根据权利要求1所述的半导体结构的制造方法，其中，多个所述芯片具有所述供电布线层；
    所述供电布线层为电源布线层、接地布线层或混合布线层；所述电源布线层包括多条电源布线，所述接地布线层包括多条接地布线，所述混合布线层包括多条电源布线和多条接地布线；每条所述电源布线均与所述焊盘连接，每条所述接地布线均与所述焊盘连接。
  11. 根据权利要求10所述的半导体结构的制造方法，其中，
    所述芯片内还具有导电通孔；
    两个相邻的所述芯片用于构成芯片组；
    同一所述芯片组的两个所述芯片之间具有键合部，所述键合部与两个所述芯片的所述导电通孔连接，以使两个所述芯片电连接；
    同一所述芯片组的两个所述芯片之间具有两个供电布线层，两个所述供电布线层分别位于两个所述芯片的表面，两个所述供电布线层中的一者为所述电源布线层，另一者为所述接地布线层；或者，两个所述供电布线层均为所述混合供电布线层；或者，所述第一供电布线层和所述第二供电布线均为混合布线层。
  12. 根据权利要求11所述的半导体结构的制造方法，其中，所述焊盘包括多个第一焊盘和多个第二焊盘，所述第一焊盘和所述第二焊盘分别与所述芯片组的两个所述供电布线层相连；
    在所述第二方向上，所述第一焊盘与两个相邻的所述第二焊盘之间的间隙正对，所述第二焊盘与两个相邻的所述第一焊盘之间的间隙正对。
  13. 根据权利要求10所述的半导体结构的制造方法，其中，所述芯片模块最外两侧的所述芯片具有所述供电布线层；
    相邻两个芯片之间具有一个所述供电布线层，且所述供电布线层与其两侧的所述芯片的所述供电信号线电连接。
  14. 根据权利要求10所述的半导体结构的制造方法，其中，
    同一所述混合布线层的所述接地布线与所述电源布线在第三方向上交替排布，所述第三方向与所述第一方向和所述第二方向相垂直。
  15. 根据权利要求1所述的半导体结构的制造方法，其中，每个所述芯片包括一个所述划片道区；
    或者，每个所述芯片包括两个划片道区，且两个所述划片道区位于所述元件区的相对两侧，所述供电布线层从所述芯片区延伸至两个所述划片道区。
  16. 一种半导体结构，包括：
    芯片模块，包括多个堆叠设置的芯片，所述芯片上包括沿第一方向排列的元件区，所述芯片的堆叠方向为第二方向，所述第二方向垂直于所述第一方向；
    其中，至少一所述芯片还具有供电布线层，所述供电布线层沿着所述元件区向所述芯片的边缘延伸；
    其中，所述芯片的侧面上还设置有焊盘，所述焊盘连接所述供电布线层。
  17. 一种半导体器件，包括：
    基板；
    芯片模块，设置在所述基板上，包括多个堆叠设置的芯片，所述芯片上包括沿第一方向排列的元件区，所述芯片的堆叠方向为第二方向，所述第二方向垂直于所述第一方向；
    其中，至少一所述芯片上还具有供电布线层，所述供电布线层沿着所述元件区向所述芯片的边缘延伸；
    其中，所述芯片的侧面上还设置有焊盘，所述焊盘连接所述供电布线层。
  18. 根据权利要求17所述的半导体器件，其中，所述芯片为存储芯片；
    半导体器件还包括：逻辑芯片，所述逻辑芯片位于所述芯片模块与所述基板之间；
    所述逻辑芯片具有第一无线通信部；所述存储芯片具有第二无线通信部；所述第一无线通信部与所述第二无线通信部进行无线通信。
  19. 根据权利要求18所述的半导体器件，其中，
    所述第二无线通信部位于所述存储芯片朝向所述逻辑芯片的一侧。
  20. 根据权利要求18所述的半导体器件，其中，所述逻辑芯片具有供电端口，所述芯片模块具有所述焊盘的一侧朝向所述逻辑芯片，且所述焊盘与所述逻辑芯片的供电端口电连接。
  21. 根据权利要求18所述的半导体器件，其中，所述基板具有供电端口，所述芯片模块具有所述焊盘的一侧背向所述逻辑芯片，且所述焊盘与所述基板的供电端口电连接。
  22. 根据权利要求17所述的半导体器件，其中，至少两个相邻的所述芯片相键合，并构成芯片组；
    相邻两个所述芯片组之间具有一个所述供电布线层，且所述供电布线层与其两侧的所述芯片组的所述芯片电连接；
    所述芯片模块首尾两侧具有一个所述供电布线层，且分别与首尾两侧的所述芯片组电连接。
  23. 根据权利要求17所述的半导体器件，其中，每个所述芯片均具 有一个所述供电布线层。
  24. 根据权利要求23所述的半导体器件，其中，同一所述芯片内的所述供电信号线与所述供电布线层相连；
    不同所述芯片的所述供电布线层相互独立，不同所述芯片的所述供电信号线相互独立。
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