CN114664671A - 一种多层高带宽内存芯片的封装方法 - Google Patents

一种多层高带宽内存芯片的封装方法 Download PDF

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CN114664671A
CN114664671A CN202210213847.2A CN202210213847A CN114664671A CN 114664671 A CN114664671 A CN 114664671A CN 202210213847 A CN202210213847 A CN 202210213847A CN 114664671 A CN114664671 A CN 114664671A
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wafer
packaging
memory chip
bandwidth memory
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吕锡明
曹立强
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明总的来说涉及高带宽内存芯片技术领域，提出一种多层高带宽内存芯片的封装方法，包括下列步骤：构造堆叠内存芯片，其中包括将多个高带宽内存晶圆通过微凸块连接，并且对所述高带宽内存晶圆进行晶圆切割；构造转接模块，其中包括构造晶圆级硅通孔转接板，其中在所述晶圆级硅通孔转接板的第一面上布置第一凸块；以及将所述堆叠内存芯片与所述转接模块连接，其中将所述微凸块与所述第一凸块连接。

Description

一种多层高带宽内存芯片的封装方法
技术领域
本发明总的来说涉及高带宽内存芯片技术领域。具体而言，本发明涉及一种多层高带宽内存芯片的封装方法。
背景技术
高带宽内存(HBM，High-Bandwidth Memory)芯片在高端显卡中被广泛应用。
传统上高带宽内存芯片通常基于3D硅通孔(TSV，Through Silicon Via)和2.5DTSV技术来进行堆叠和连接，其中通常通过3D TSV技术将多块高带宽内存芯片进行堆叠在一起形成堆叠内存芯片，并且通过2.5D TSV技术将所述堆叠内存芯片与图形处理器(GPU，Graphics processing unit)在载板上实现互连。然而，传统的基于硅通孔技术的技术方案在生产效率上仍存在不足。
发明内容
为至少部分解决现有技术中的上述问题，本发明提出一种多层高带宽内存芯片的封装方法，包括下列步骤：
构造堆叠内存芯片，其中包括将多个高带宽内存晶圆通过微凸块连接，并且对所述高带宽内存晶圆进行晶圆切割；
构造转接模块，其中包括构造晶圆级硅通孔转接板，所述晶圆级硅通孔转接板的第一面上具有第一基片，其中在所述第一基片上布置第一凸块；以及
将所述堆叠内存芯片与所述转接模块连接，其中将所述微凸块与所述第一凸块连接。
在本发明一个实施例中规定，所述晶圆级硅通孔转接板的第二面上具有第二基片，其中在所述第二基片上布置第二凸块。
在本发明一个实施例中规定，将所述晶圆级硅通孔转接板的第二面通过键合胶与载片键合以保护所述第二凸块。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
构造晶圆连接标记；
在所述第一基片上布置晶圆连接标记；以及
根据所述晶圆连接标记的位置将所述堆叠内存芯片布置在所述第一基片的对应位置上。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
通过填充料填充所述堆叠内存芯片与所述转接模块之间的空隙，其中通过所述填充料填充所述微凸块与所述第一凸块之间的空隙。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
通过塑封料对所述堆叠内存芯片和所述转接模块进行塑封。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
对所述塑封料进行减薄。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
通过解键合拆除所述键合胶以及载片，以使得所述第二凸块露出。
在本发明一个实施例中规定，所述多层高带宽内存芯片的封装方法还包括：
对解键合后的所述堆叠内存芯片和所述转接模块进行晶圆切割。
本发明至少具有如下有益效果：本发明提供一种晶圆级的技术方案，通过waferto wafer(W2W)晶圆键合的方式来构造多层的多高带宽内存晶圆结构，然后对其进行切割来形成特定尺寸的单颗芯片，生产效率较高；另外本发明中通过Die Bonding的形式实现堆叠内存芯片与转接模块精准连接，其中可以通过晶圆级芯片封装(WLCSP，Wafer-LevelChip Scale Packaging Technology)的方式来进行封装，极大地提高了封装效率。
附图说明
为进一步阐明本发明的各实施例中具有的及其它的优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出了本发明一个实施例中一个多层高带宽内存芯片的封装方法的流程示意图。
图2示出了本发明一个实施例中一个堆叠内存芯片的示意图
图3-9示出了本发明一个实施例中进行多层高带宽内存芯片的封装过程中的结构示意图
具体实施方式
应当指出，各附图中的各组件可能为了图解说明而被夸大地示出，而不一定是比例正确的。在各附图中，给相同或功能相同的组件配备了相同的附图标记。
在本发明中，除非特别指出，“布置在…上”、“布置在…上方”以及“布置在…之上”并未排除二者之间存在中间物的情况。此外，“布置在…上或上方”仅仅表示两个部件之间的相对位置关系，而在一定情况下、如在颠倒产品方向后，也可以转换为“布置在…下或下方”，反之亦然。
在本发明中，各实施例仅仅旨在说明本发明的方案，而不应被理解为限制性的。
在本发明中，除非特别指出，量词“一个”、“一”并未排除多个元素的场景。
在此还应当指出，在本发明的实施例中，为清楚、简单起见，可能示出了仅仅一部分部件或组件，但是本领域的普通技术人员能够理解，在本发明的教导下，可根据具体场景需要添加所需的部件或组件。另外，除非另行说明，本发明的不同实施例中的特征可以相互组合。例如，可以用第二实施例中的某特征替换第一实施例中相对应或功能相同或相似的特征，所得到的实施例同样落入本申请的公开范围或记载范围。
在此还应当指出，在本发明的范围内，“相同”、“相等”、“等于”等措辞并不意味着二者数值绝对相等，而是允许一定的合理误差，也就是说，所述措辞也涵盖了“基本上相同”、“基本上相等”、“基本上等于”。以此类推，在本发明中，表方向的术语“垂直于”、“平行于”等等同样涵盖了“基本上垂直于”、“基本上平行于”的含义。
另外，本发明的各方法的步骤的编号并未限定所述方法步骤的执行顺序。除非特别指出，各方法步骤可以以不同顺序执行。
下面结合具体实施方式参考附图进一步阐述本发明。
图1示出了本发明一个实施例中一个多层高带宽内存芯片的封装方法的流程示意图。如图1所示，该方法可以包括下列步骤：
步骤100、构造堆叠内存芯片200，其中可以包括：
将多个高带宽内存晶圆(HBM wafer)在垂直方向上通过微凸块(uBump)连接以实现多个高带宽内存晶圆之间的互联互通；以及
进行晶圆切割(wafer dicing)以获取特定尺寸的单颗堆叠内存芯片200。
图2示出了本发明一个实施例中一个堆叠内存芯片的示意图。如图2所示，通过本发明方法构造而成的堆叠内存芯片200可以包括多个高带宽内存存储区域201，所述多个高带宽内存存储区域201平行布置，并且通过微凸块202进行连接。
传统上的制造工艺通过3D TSV技术将多块单个的高带宽内存芯片进行堆叠在一起形成堆叠内存芯片，而本发明提供了一种晶圆级的技术方案，通过wafer to wafer(W2W)晶圆键合的方式来构造多层的多高带宽内存晶圆结构，然后对其进行切割来形成特定尺寸的单颗芯片，生产效率较高。
步骤200、构造转接模块300，如图3所示，其中可以包括：
构造晶圆级硅通孔(TSV)转接板301；
在所述晶圆级硅通孔转接板301的第一面上
布置第一凸块302(bump)，在所述晶圆级硅通孔转接板301的第二面上布置第二凸块303，其中所述第一凸块302和第二凸块303的高度和数量可以根据实际的生产需要进行选择，其中所述第一凸块302用于与所述堆叠内存芯片200连接；以及
将所述晶圆级硅通孔转接板301的第二面通过键合胶304与载片(carrier wafer)305键合以保护所述第二凸块303。在本发明的实施例中，载片一般为单晶硅片，载片还可选择其他材料，如玻璃载片、有机基板、金属基板、陶瓷基板、有机基板与金属基板复合的基板，或者其他类似材料也可以。本领域的技术人员应该理解，只要具有特定强度的平整表面，即可作为本发明的载片。
步骤300、在所述晶圆级硅通孔转接板301的第一面上构造管芯连接标记(DieAttach Mark)400，所述晶圆连接标记400用于标记位置实现所述堆叠内存芯片200的高精度晶圆级互联封装。
步骤400、在所述转接模块300上布置所述堆叠内存芯片200，如图4所示，其中将所述堆叠内存芯片200通过Die to Wafer(D2W)晶圆级封装的方式根据所述管芯连接标记400的位置贴装在所述第一基片302的对应位置上，其中所述第一基片302上的第一凸块302与所述堆叠内存芯片200上的微凸块202连接。
步骤500、通过填充料500填充所述堆叠内存芯片200与所述转接模块300之间的空隙，如图5所示，其中通过所述填充料500填充所述微凸块202与所述第一凸块302之间的互联空隙，以便保护所述微凸块202处的锡球和所述第一凸块302。
步骤600、通过塑封料600进行塑封，如图6所示，其中通过塑封料600对完成了所述堆叠内存芯片200贴装的晶圆进行塑封以保护整个封装产品。
步骤700、如图7所示，对塑封后的晶圆进行减薄以满足终端铲平的使用需求。
步骤800、如图8所示，通过解键合(Debonding)拆除所述键合胶304以及载片305，以使得所述第二凸块303露出以满足终端产品贴装需求。在本发明的具体实施例中，可以通过加热、机械、化学、激光、冷冻等方式进行解键合拆除。
步骤900、如图9所示，对完成解键合后的晶圆进行切割(dicing)以便获得符合设计尺寸的单颗芯片。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (9)

1.一种多层高带宽内存芯片的封装方法，其特征在于，包括下列步骤：
构造堆叠内存芯片，其中包括将多个高带宽内存晶圆通过微凸块连接，并且对所述高带宽内存晶圆进行晶圆切割；
构造转接模块，其中包括构造晶圆级硅通孔转接板，其中在所述晶圆级硅通孔转接板的第一面上布置第一凸块；以及
将所述堆叠内存芯片与所述转接模块连接，其中将所述微凸块与所述第一凸块连接。
2.根据权利要求1所述的多层高带宽内存芯片的封装方法，其特征在于，还包括在所述晶圆级硅通孔转接板的第二面上布置第二凸块。
3.根据权利要求2所述的多层高带宽内存芯片的封装方法，其特征在于，还包括将所述晶圆级硅通孔转接板的第二面通过键合胶与载片键合以保护所述第二凸块。
4.根据权利要求3所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
在所述晶圆级硅通孔转接板的第一面上构造管芯连接标记；
以及
根据所述晶圆连接标记的位置将所述堆叠内存芯片布置在所述第一基片的对应位置上。
5.根据权利要求4所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
通过填充料填充所述堆叠内存芯片与所述转接模块之间的空隙，其中通过所述填充料填充所述微凸块与所述第一凸块之间的空隙。
6.根据权利要求5所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
通过塑封料对所述堆叠内存芯片和所述转接模块进行塑封。
7.根据权利要求6所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
对所述塑封料进行减薄。
8.根据权利要求7所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
通过解键合拆除所述键合胶以及载片，以使得所述第二凸块露出。
9.根据权利要求8所述的多层高带宽内存芯片的封装方法，其特征在于，还包括：
对解键合后的所述堆叠内存芯片和所述转接模块进行晶圆切割。
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CN117276094A (zh) * 2023-10-12 2023-12-22 江苏柒捌玖电子科技有限公司 一种晶圆级封装方法及芯链封装结构
WO2024031775A1 (zh) * 2022-08-10 2024-02-15 长鑫存储技术有限公司 半导体结构、半导体结构的制造方法和半导体器件
WO2024031773A1 (zh) * 2022-08-10 2024-02-15 长鑫存储技术有限公司 半导体结构的制造方法、半导体结构和半导体器件

Cited By (3)

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Publication number Priority date Publication date Assignee Title
WO2024031775A1 (zh) * 2022-08-10 2024-02-15 长鑫存储技术有限公司 半导体结构、半导体结构的制造方法和半导体器件
WO2024031773A1 (zh) * 2022-08-10 2024-02-15 长鑫存储技术有限公司 半导体结构的制造方法、半导体结构和半导体器件
CN117276094A (zh) * 2023-10-12 2023-12-22 江苏柒捌玖电子科技有限公司 一种晶圆级封装方法及芯链封装结构

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