WO2024018695A1 - Dispositif à semi-conducteurs et son procédé de production - Google Patents

Dispositif à semi-conducteurs et son procédé de production Download PDF

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Publication number
WO2024018695A1
WO2024018695A1 PCT/JP2023/013896 JP2023013896W WO2024018695A1 WO 2024018695 A1 WO2024018695 A1 WO 2024018695A1 JP 2023013896 W JP2023013896 W JP 2023013896W WO 2024018695 A1 WO2024018695 A1 WO 2024018695A1
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WO
WIPO (PCT)
Prior art keywords
barrier metal
metal layer
semiconductor device
insulating film
semiconductor
Prior art date
Application number
PCT/JP2023/013896
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English (en)
Japanese (ja)
Inventor
正樹 白石
Original Assignee
株式会社日立パワーデバイス
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Publication of WO2024018695A1 publication Critical patent/WO2024018695A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same.
  • a semiconductor device such as a power semiconductor has an active region in which a semiconductor element is formed and a main current flows, and a termination region formed around the active region to maintain a breakdown voltage.
  • Patent Document 1 describes a structure including a guard ring (p layer) and an electrode (also called a field electrode or field plate) connected to the guard ring via a barrier metal layer. has been done.
  • FIGS. 1, 2, and the abstract of the patent document describe a "high breakdown voltage power semiconductor device having a termination region by a guard ring, in which an active region is connected to a first barrier metal layer via a first barrier metal layer.
  • the guard ring is connected to the second electrode through the second barrier metal layer, and the channel stopper is connected to the third electrode through the third barrier metal layer.
  • the barrier metal layers are arranged at intervals, and the width of each of the barrier metal layers (first to third barrier metal layers) is equal to the width of each of the electrodes (first to third barrier metal layers) to be connected in the direction crossing the termination region. to the third electrode), and a portion of each barrier metal layer protrudes from both sides of each electrode to be joined in the transverse direction. ⁇ Providing a semiconductor device that can achieve both high breakdown voltage and miniaturization of the semiconductor device.'''
  • a thin film for forming a barrier metal layer and electrodes such as field electrodes are formed.
  • a metal layer pattern the metal layer by over-etching using photoresist by wet etching to form an electrode, and pattern the thin film by anisotropic dry etching using the same photoresist to form a barrier metal layer. is forming.
  • the barrier metal layer under the electrodes such as field electrodes may not be etched sufficiently, and residue may remain between the electrodes. There is sex. If the barrier metal layer remains as a residue, the field electrodes are electrically connected, and the guard rings connected to the field electrodes have the same potential, causing a problem that sufficient breakdown voltage cannot be ensured in the termination region.
  • the problem to be solved by the present invention is to provide a semiconductor device that can suppress the residue of a barrier metal layer from remaining in a semiconductor device having a field plate connected to a guard ring formed in a termination region via a barrier metal layer.
  • An object of the present invention is to provide a manufacturing method thereof.
  • a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed and a termination region surrounding the active region, wherein the termination region is of a first conductivity type.
  • the method for manufacturing a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed, and a termination region surrounding the active region, and the termination region includes a semiconductor substrate of a first conductivity type; a plurality of guard rings of a second conductivity type formed on the semiconductor substrate; an insulating film contacting the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard rings; and an insulating film contacting the guard rings and spaced apart from each other.
  • the method is characterized in that the barrier metal layer is etched before the field plate is formed.
  • the outer shape of the barrier metal layer is inside the field plate, so even if a residue remains when patterning the barrier metal layer, the barrier metal layer outside the field plate can be etched again.
  • the residue can be removed by doing the following, and it is possible to suppress the residue of the barrier metal layer from remaining.
  • the barrier metal layer is etched before the field plate is formed, it is possible to suppress the residue of the barrier metal layer from remaining. Furthermore, even if a residue remains when patterning the barrier metal layer, the residue can be removed by etching the barrier metal layer again during or after etching the field plate, and the residue on the barrier metal layer can be removed. can be suppressed from remaining.
  • FIG. 1 is a cross-sectional view of a semiconductor device of Example 1.
  • FIG. 1 is a plan view of a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 3 is a cross-sectional view of a semiconductor device of Example 2.
  • FIG. 1 is a cross-sectional view of the semiconductor device of Example 1
  • FIG. 2 is a plan view of the semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view taken along line AA in FIG.
  • the semiconductor device 20 of Example 1 has an active region 21 in which a semiconductor element is formed, and a termination region 22 surrounding the active region 21.
  • the termination region 22 includes a semiconductor substrate 1 of a first conductivity type (n-type in FIG. 1), a plurality of guard rings 2 of a second conductivity type (p-type in FIG. 1) formed on the semiconductor substrate 1, and an insulating film. 3, a barrier metal layer 4, and a field plate 5.
  • the active region 21 includes a drift layer formed of the semiconductor substrate 1, a body layer 6 of the second conductivity type serving as a main bonding layer, a barrier metal layer 4 formed in contact with the body layer 6, and a barrier metal layer 4 formed in contact with the body layer 6.
  • a front side main electrode 7 formed in contact with the layer 4 , a first conductivity type buffer layer 8 formed on the back side of the semiconductor substrate 1 , a second conductivity type collector layer 9 , and a back side main electrode 10 It has Note that the buffer layer 8 may be omitted in some cases.
  • the active region 21 includes a gate electrode, a gate, and a gate insulating film, but these are not shown.
  • the impurity concentration of the semiconductor substrate 1 is low, it is expressed as n-.
  • the first conductivity type is n type and the second conductivity type is p type, but the first conductivity type may be p type and the second conductivity type may be n type.
  • the semiconductor element may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which case a drain layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the semiconductor element may be a diode element instead of a switching element such as an IGBT or MOSFET.
  • a cathode layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
  • a plurality of guard rings 2 are formed spaced apart from each other.
  • the insulating film 3 is in contact with the semiconductor substrate 1 and the guard ring 2 and has an opening at a position overlapping with the guard ring 2.
  • a plurality of barrier metal layers 4 are formed and are spaced apart from each other, and are formed at least within the opening of the insulating film 3 and are in contact with the guard ring 2.
  • the barrier metal layer 4 is also formed on the upper surface of the insulating film 3.
  • the barrier metal layer 4 can be formed of, for example, any one of Ti, TiN, TiW, and MoSi2 .
  • the barrier metal layer 4 has a role of preventing metal (for example, Al) contained in the field plate 5 from diffusing into the semiconductor layer (for example, Si) forming the guard ring 2 . Therefore, it is desirable that the barrier metal layer 4 be formed in the entire region overlapping the guard ring 2 within the opening of the insulating film 3.
  • a plurality of field plates 5 are formed, and are spaced apart from each other, and have an outer shape outside the outer shape of the barrier metal layer 4 when viewed from above, and are connected to the upper surface of the barrier metal layer 4 and the insulating film 3. It is in contact with the top surface.
  • the field plate 5 can be formed of, for example, any one of Al, AlSi, AlCu, and AlSiCu.
  • the barrier metal layer 4 is also formed on the upper surface of the insulating film 3, so the field plate 5 is also in contact with the side surface of the barrier metal layer 4 on the upper surface of the insulating film 3.
  • the distance between the plurality of field plates 5 is smaller than the distance between the plurality of barrier metal layers 4. Further, the end of the barrier metal layer 4 is located inside the end of the field plate 5. The barrier metal layer 4 is entirely covered by the field plate 5 and has a structure that it does not protrude.
  • the outer shape of the barrier metal layer 4 is inside the field plate 5, so even if a residue remains when patterning the barrier metal layer 4, it will not remain outside the field plate 5.
  • the residue can be removed by etching the barrier metal layer again, and it is possible to suppress the residue of the barrier metal layer 4 from remaining.
  • the barrier metal layer 4 remains as a residue, the field plates 5 are electrically connected, and the guard rings 2 connected to each field plate 5 have the same potential, making it impossible to ensure sufficient breakdown voltage in the termination region 22. A problem arises.
  • the outer shape of the barrier metal layer 4 is inside the field plate 5, and the residue of the barrier metal layer 4 can be suppressed from remaining. Problems can be prevented from occurring.
  • the semiconductor device 20 of Example 1 can be formed by etching the barrier metal layer 4 after the barrier metal layer 4 is formed and before the field plate 5 is formed.
  • 3 to 7 are cross-sectional views illustrating the method for manufacturing the semiconductor device of Example 1. Note that only the front side will be described here, and illustration and description of the back side will be omitted.
  • a second conductivity type impurity is implanted into the semiconductor substrate 1 to form the guard ring 2 and the body layer 6. Thereafter, after forming the insulating film 3, openings are formed at necessary locations.
  • a metal layer that will become the barrier metal layer 4 is formed by sputtering or vapor deposition.
  • the barrier metal layer 4 is processed by etching using the photoresist 11.
  • etching the barrier metal layer 4 before forming the field plate 5 it is possible to suppress the residue of the barrier metal layer 4 from remaining, and to change the outer shape of the barrier metal layer 4 to be inside the outer shape of the field plate 5. It becomes possible to process it as follows.
  • a metal layer that will become the field plate 5 is formed by sputtering or vapor deposition.
  • the field plate 5 is processed by etching using the photoresist 11. At this time, processing is performed so that the outer shape of the field plate 5 is located outside the outer shape of the barrier metal layer 4 when viewed from above. As a result, the distance between the plurality of field plates 5 becomes smaller than the distance between the plurality of barrier metal layers 4. Thereafter, by removing the photoresist 11, the structure shown in FIG. 1 can be formed.
  • the residue can be removed by etching the barrier metal layer 4 again during or after etching the field plate 5. It can also be removed. Thereby, it is possible to suppress the residue of the barrier metal layer 4 from remaining.
  • Example 2 is a modification of Example 1.
  • points different from the first embodiment will be mainly explained, and redundant explanations will be omitted.
  • FIG. 8 is a cross-sectional view of the semiconductor device of Example 2.
  • the barrier metal layer 4 of the semiconductor device 20 of Example 2 differs from Example 1 in that it is not formed on the upper surface of the insulating film 3. In other words, it is formed only within the opening of the insulating film 3.
  • the manufacturing method is almost the same as in Example 1, except that the patterning shape of the barrier metal layer 4 is different.
  • the second embodiment can also provide the same effects as the first embodiment.
  • SYMBOLS 1 Semiconductor substrate, 2... Guard ring, 3... Insulating film, 4... Barrier metal layer, 5... Field plate, 6... Body layer, 7... Surface side main electrode, 8... Buffer layer, 9... Collector layer, 10... Back side main electrode, 11... Photoresist, 12... Electrode layer, 20... Semiconductor device, 21... Active region, 22... Termination region

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteurs qui comprend une plaque de champ qui est connectée à un anneau de garde, qui est formé dans une région de terminaison, par l'intermédiaire d'une couche métallique barrière, le reste d'un résidu de la couche métallique barrière pouvant être supprimé. Selon la présente invention, une région de terminaison 22 comprend : un substrat semi-conducteur 1 d'un premier type de conductivité ; une pluralité d'anneaux de garde 2 d'un second type de conductivité, les anneaux de garde 2 étant formés sur le substrat semi-conducteur ; un film isolant 3 qui est en contact avec le substrat semi-conducteur et les anneaux de garde, tout en ayant des ouvertures à des positions qui correspondent aux anneaux de garde ; une pluralité de couches métalliques barrières 4 qui sont formées au moins dans les ouvertures du film isolant de façon à être en contact avec les anneaux de garde, tout en étant séparées les unes des autres ; et une pluralité de plaques de champ 5, dont les contours sont à l'extérieur des contours des couches métalliques barrières lorsqu'elles sont vues en plan, tout en étant agencées de façon à être séparées les unes des autres et étant en contact avec les surfaces supérieures des couches métalliques barrières et la surface supérieure du film isolant.
PCT/JP2023/013896 2022-07-20 2023-04-04 Dispositif à semi-conducteurs et son procédé de production WO2024018695A1 (fr)

Applications Claiming Priority (2)

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JP2022115369A JP2024013345A (ja) 2022-07-20 2022-07-20 半導体装置およびその製造方法
JP2022-115369 2022-07-20

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021526A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 電力用半導体装置及びその製造方法
JP2019169551A (ja) * 2018-03-22 2019-10-03 ローム株式会社 窒化物半導体装置
JP2021005657A (ja) * 2019-06-27 2021-01-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021526A (ja) * 2007-07-13 2009-01-29 Toshiba Corp 電力用半導体装置及びその製造方法
JP2019169551A (ja) * 2018-03-22 2019-10-03 ローム株式会社 窒化物半導体装置
JP2021005657A (ja) * 2019-06-27 2021-01-14 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

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TW202406150A (zh) 2024-02-01

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