WO2024018695A1 - Semiconductor device and method for producing same - Google Patents

Semiconductor device and method for producing same Download PDF

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WO2024018695A1
WO2024018695A1 PCT/JP2023/013896 JP2023013896W WO2024018695A1 WO 2024018695 A1 WO2024018695 A1 WO 2024018695A1 JP 2023013896 W JP2023013896 W JP 2023013896W WO 2024018695 A1 WO2024018695 A1 WO 2024018695A1
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barrier metal
metal layer
semiconductor device
insulating film
semiconductor
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PCT/JP2023/013896
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French (fr)
Japanese (ja)
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正樹 白石
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株式会社日立パワーデバイス
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same.
  • a semiconductor device such as a power semiconductor has an active region in which a semiconductor element is formed and a main current flows, and a termination region formed around the active region to maintain a breakdown voltage.
  • Patent Document 1 describes a structure including a guard ring (p layer) and an electrode (also called a field electrode or field plate) connected to the guard ring via a barrier metal layer. has been done.
  • FIGS. 1, 2, and the abstract of the patent document describe a "high breakdown voltage power semiconductor device having a termination region by a guard ring, in which an active region is connected to a first barrier metal layer via a first barrier metal layer.
  • the guard ring is connected to the second electrode through the second barrier metal layer, and the channel stopper is connected to the third electrode through the third barrier metal layer.
  • the barrier metal layers are arranged at intervals, and the width of each of the barrier metal layers (first to third barrier metal layers) is equal to the width of each of the electrodes (first to third barrier metal layers) to be connected in the direction crossing the termination region. to the third electrode), and a portion of each barrier metal layer protrudes from both sides of each electrode to be joined in the transverse direction. ⁇ Providing a semiconductor device that can achieve both high breakdown voltage and miniaturization of the semiconductor device.'''
  • a thin film for forming a barrier metal layer and electrodes such as field electrodes are formed.
  • a metal layer pattern the metal layer by over-etching using photoresist by wet etching to form an electrode, and pattern the thin film by anisotropic dry etching using the same photoresist to form a barrier metal layer. is forming.
  • the barrier metal layer under the electrodes such as field electrodes may not be etched sufficiently, and residue may remain between the electrodes. There is sex. If the barrier metal layer remains as a residue, the field electrodes are electrically connected, and the guard rings connected to the field electrodes have the same potential, causing a problem that sufficient breakdown voltage cannot be ensured in the termination region.
  • the problem to be solved by the present invention is to provide a semiconductor device that can suppress the residue of a barrier metal layer from remaining in a semiconductor device having a field plate connected to a guard ring formed in a termination region via a barrier metal layer.
  • An object of the present invention is to provide a manufacturing method thereof.
  • a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed and a termination region surrounding the active region, wherein the termination region is of a first conductivity type.
  • the method for manufacturing a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed, and a termination region surrounding the active region, and the termination region includes a semiconductor substrate of a first conductivity type; a plurality of guard rings of a second conductivity type formed on the semiconductor substrate; an insulating film contacting the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard rings; and an insulating film contacting the guard rings and spaced apart from each other.
  • the method is characterized in that the barrier metal layer is etched before the field plate is formed.
  • the outer shape of the barrier metal layer is inside the field plate, so even if a residue remains when patterning the barrier metal layer, the barrier metal layer outside the field plate can be etched again.
  • the residue can be removed by doing the following, and it is possible to suppress the residue of the barrier metal layer from remaining.
  • the barrier metal layer is etched before the field plate is formed, it is possible to suppress the residue of the barrier metal layer from remaining. Furthermore, even if a residue remains when patterning the barrier metal layer, the residue can be removed by etching the barrier metal layer again during or after etching the field plate, and the residue on the barrier metal layer can be removed. can be suppressed from remaining.
  • FIG. 1 is a cross-sectional view of a semiconductor device of Example 1.
  • FIG. 1 is a plan view of a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1.
  • FIG. 3 is a cross-sectional view of a semiconductor device of Example 2.
  • FIG. 1 is a cross-sectional view of the semiconductor device of Example 1
  • FIG. 2 is a plan view of the semiconductor device of Example 1.
  • FIG. 1 is a cross-sectional view taken along line AA in FIG.
  • the semiconductor device 20 of Example 1 has an active region 21 in which a semiconductor element is formed, and a termination region 22 surrounding the active region 21.
  • the termination region 22 includes a semiconductor substrate 1 of a first conductivity type (n-type in FIG. 1), a plurality of guard rings 2 of a second conductivity type (p-type in FIG. 1) formed on the semiconductor substrate 1, and an insulating film. 3, a barrier metal layer 4, and a field plate 5.
  • the active region 21 includes a drift layer formed of the semiconductor substrate 1, a body layer 6 of the second conductivity type serving as a main bonding layer, a barrier metal layer 4 formed in contact with the body layer 6, and a barrier metal layer 4 formed in contact with the body layer 6.
  • a front side main electrode 7 formed in contact with the layer 4 , a first conductivity type buffer layer 8 formed on the back side of the semiconductor substrate 1 , a second conductivity type collector layer 9 , and a back side main electrode 10 It has Note that the buffer layer 8 may be omitted in some cases.
  • the active region 21 includes a gate electrode, a gate, and a gate insulating film, but these are not shown.
  • the impurity concentration of the semiconductor substrate 1 is low, it is expressed as n-.
  • the first conductivity type is n type and the second conductivity type is p type, but the first conductivity type may be p type and the second conductivity type may be n type.
  • the semiconductor element may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which case a drain layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the semiconductor element may be a diode element instead of a switching element such as an IGBT or MOSFET.
  • a cathode layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
  • a plurality of guard rings 2 are formed spaced apart from each other.
  • the insulating film 3 is in contact with the semiconductor substrate 1 and the guard ring 2 and has an opening at a position overlapping with the guard ring 2.
  • a plurality of barrier metal layers 4 are formed and are spaced apart from each other, and are formed at least within the opening of the insulating film 3 and are in contact with the guard ring 2.
  • the barrier metal layer 4 is also formed on the upper surface of the insulating film 3.
  • the barrier metal layer 4 can be formed of, for example, any one of Ti, TiN, TiW, and MoSi2 .
  • the barrier metal layer 4 has a role of preventing metal (for example, Al) contained in the field plate 5 from diffusing into the semiconductor layer (for example, Si) forming the guard ring 2 . Therefore, it is desirable that the barrier metal layer 4 be formed in the entire region overlapping the guard ring 2 within the opening of the insulating film 3.
  • a plurality of field plates 5 are formed, and are spaced apart from each other, and have an outer shape outside the outer shape of the barrier metal layer 4 when viewed from above, and are connected to the upper surface of the barrier metal layer 4 and the insulating film 3. It is in contact with the top surface.
  • the field plate 5 can be formed of, for example, any one of Al, AlSi, AlCu, and AlSiCu.
  • the barrier metal layer 4 is also formed on the upper surface of the insulating film 3, so the field plate 5 is also in contact with the side surface of the barrier metal layer 4 on the upper surface of the insulating film 3.
  • the distance between the plurality of field plates 5 is smaller than the distance between the plurality of barrier metal layers 4. Further, the end of the barrier metal layer 4 is located inside the end of the field plate 5. The barrier metal layer 4 is entirely covered by the field plate 5 and has a structure that it does not protrude.
  • the outer shape of the barrier metal layer 4 is inside the field plate 5, so even if a residue remains when patterning the barrier metal layer 4, it will not remain outside the field plate 5.
  • the residue can be removed by etching the barrier metal layer again, and it is possible to suppress the residue of the barrier metal layer 4 from remaining.
  • the barrier metal layer 4 remains as a residue, the field plates 5 are electrically connected, and the guard rings 2 connected to each field plate 5 have the same potential, making it impossible to ensure sufficient breakdown voltage in the termination region 22. A problem arises.
  • the outer shape of the barrier metal layer 4 is inside the field plate 5, and the residue of the barrier metal layer 4 can be suppressed from remaining. Problems can be prevented from occurring.
  • the semiconductor device 20 of Example 1 can be formed by etching the barrier metal layer 4 after the barrier metal layer 4 is formed and before the field plate 5 is formed.
  • 3 to 7 are cross-sectional views illustrating the method for manufacturing the semiconductor device of Example 1. Note that only the front side will be described here, and illustration and description of the back side will be omitted.
  • a second conductivity type impurity is implanted into the semiconductor substrate 1 to form the guard ring 2 and the body layer 6. Thereafter, after forming the insulating film 3, openings are formed at necessary locations.
  • a metal layer that will become the barrier metal layer 4 is formed by sputtering or vapor deposition.
  • the barrier metal layer 4 is processed by etching using the photoresist 11.
  • etching the barrier metal layer 4 before forming the field plate 5 it is possible to suppress the residue of the barrier metal layer 4 from remaining, and to change the outer shape of the barrier metal layer 4 to be inside the outer shape of the field plate 5. It becomes possible to process it as follows.
  • a metal layer that will become the field plate 5 is formed by sputtering or vapor deposition.
  • the field plate 5 is processed by etching using the photoresist 11. At this time, processing is performed so that the outer shape of the field plate 5 is located outside the outer shape of the barrier metal layer 4 when viewed from above. As a result, the distance between the plurality of field plates 5 becomes smaller than the distance between the plurality of barrier metal layers 4. Thereafter, by removing the photoresist 11, the structure shown in FIG. 1 can be formed.
  • the residue can be removed by etching the barrier metal layer 4 again during or after etching the field plate 5. It can also be removed. Thereby, it is possible to suppress the residue of the barrier metal layer 4 from remaining.
  • Example 2 is a modification of Example 1.
  • points different from the first embodiment will be mainly explained, and redundant explanations will be omitted.
  • FIG. 8 is a cross-sectional view of the semiconductor device of Example 2.
  • the barrier metal layer 4 of the semiconductor device 20 of Example 2 differs from Example 1 in that it is not formed on the upper surface of the insulating film 3. In other words, it is formed only within the opening of the insulating film 3.
  • the manufacturing method is almost the same as in Example 1, except that the patterning shape of the barrier metal layer 4 is different.
  • the second embodiment can also provide the same effects as the first embodiment.
  • SYMBOLS 1 Semiconductor substrate, 2... Guard ring, 3... Insulating film, 4... Barrier metal layer, 5... Field plate, 6... Body layer, 7... Surface side main electrode, 8... Buffer layer, 9... Collector layer, 10... Back side main electrode, 11... Photoresist, 12... Electrode layer, 20... Semiconductor device, 21... Active region, 22... Termination region

Abstract

The present invention provides a semiconductor device which comprises a field plate that is connected to a guard ring, which is formed in a termination region, by the intermediary of a barrier metal layer, wherein it is possible to suppress the remaining of a residue of the barrier metal layer. According to the present invention, a termination region 22 comprises: a semiconductor substrate 1 of a first conductivity type; a plurality of guard rings 2 of a second conductivity type, the guard rings 2 being formed on the semiconductor substrate; an insulating film 3 which is in contact with the semiconductor substrate and the guard rings, while having openings at positions that correspond to the guard rings; a plurality of barrier metal layers 4 which are formed at least in the openings of the insulating film so as to be in contact with the guard rings, while being separated from each other; and a plurality of field plates 5, the outlines of which are outside the outlines of the barrier metal layers when viewed in plan, while being arranged so as to be separated from each other and being in contact with the upper surfaces of the barrier metal layers and the upper surface of the insulating film.

Description

半導体装置およびその製造方法Semiconductor device and its manufacturing method
　本発明は、半導体装置およびその製造方法に関する。 The present invention relates to a semiconductor device and a method for manufacturing the same.
　パワー半導体などの半導体装置には、半導体素子が形成され主電流が流れるアクティブ領域と、アクティブ領域の周辺に形成され耐圧を保持するためのターミネーション領域とが存在する。 A semiconductor device such as a power semiconductor has an active region in which a semiconductor element is formed and a main current flows, and a termination region formed around the active region to maintain a breakdown voltage.
　ターミネーション領域の構造として、例えば特許文献１には、ガードリング（ｐ層）と、ガードリングにバリアメタル層を介して接続された電極（フィールド電極、フィールドプレートとも呼ばれる）とを備えた構造が記載されている。 As a structure of the termination region, for example, Patent Document 1 describes a structure including a guard ring (p layer) and an electrode (also called a field electrode or field plate) connected to the guard ring via a barrier metal layer. has been done.
　より具体的には、特許文献の図１、図２、要約には、「ガードリングによるターミネーション領域を有する高耐圧パワー半導体装置であって、能動領域は第１のバリアメタル層を介して第１の電極と接合され、前記ガードリングは第２のバリアメタル層を介して第２の電極と接合され、チャネルストッパは第３のバリアメタル層を介して第３の電極と接合されている。前記バリアメタル層は各々に間隔をあけて配設され、前記ターミネーション領域を横断する方向において、前記各バリアメタル層（第１乃至第３のバリアメタル層）の幅は接合する前記各電極（第１乃至第３の電極）の幅よりも広く、かつ前記各バリアメタル層の一部が前記接合する各電極の前記横断する方向における両側からはみ出していることを特徴とする。」ことにより、「パワー半導体装置における高耐圧化と小型化とを両立できる半導体装置を提供する」ことが記載されている。 More specifically, FIGS. 1, 2, and the abstract of the patent document describe a "high breakdown voltage power semiconductor device having a termination region by a guard ring, in which an active region is connected to a first barrier metal layer via a first barrier metal layer. The guard ring is connected to the second electrode through the second barrier metal layer, and the channel stopper is connected to the third electrode through the third barrier metal layer. The barrier metal layers are arranged at intervals, and the width of each of the barrier metal layers (first to third barrier metal layers) is equal to the width of each of the electrodes (first to third barrier metal layers) to be connected in the direction crossing the termination region. to the third electrode), and a portion of each barrier metal layer protrudes from both sides of each electrode to be joined in the transverse direction. ``Providing a semiconductor device that can achieve both high breakdown voltage and miniaturization of the semiconductor device.''
特開２０１０－２５１４０４号公報Japanese Patent Application Publication No. 2010-251404
　しかしながら、特許文献１に記載された構造を実現するために、特許文献１では、特許文献１の図３に示すように、バリアメタル層を形成するための薄膜とフィールド電極などの電極を形成するための金属層を形成後、ホトレジストを用いてウェットエッチによってオーバーエッチングして金属層をパターニングして電極を形成し、同じホトレジストを用いて異方性ドライエッチによって薄膜をパターニングしてバリアメタル層を形成している。 However, in order to realize the structure described in Patent Document 1, as shown in FIG. 3 of Patent Document 1, a thin film for forming a barrier metal layer and electrodes such as field electrodes are formed. After forming a metal layer, pattern the metal layer by over-etching using photoresist by wet etching to form an electrode, and pattern the thin film by anisotropic dry etching using the same photoresist to form a barrier metal layer. is forming.
　したがって、異物等でホトマスクの開口が不十分な場合や、ウェットエッチが不十分な場合には、フィールド電極などの電極の下のバリアメタル層が十分にエッチングされず、電極間に残渣として残る可能性がある。バリアメタル層が残渣として残ると、各フィールド電極の間が電気的に接続され、各フィールド電極に接続されているガードリングが同電位となり、ターミネーション領域で十分な耐圧が確保できないという問題が生じる。 Therefore, if the opening in the photomask is insufficient due to foreign matter, or if wet etching is insufficient, the barrier metal layer under the electrodes such as field electrodes may not be etched sufficiently, and residue may remain between the electrodes. There is sex. If the barrier metal layer remains as a residue, the field electrodes are electrically connected, and the guard rings connected to the field electrodes have the same potential, causing a problem that sufficient breakdown voltage cannot be ensured in the termination region.
　本発明が解決しようとする課題は、ターミネーション領域に形成されたガードリングにバリアメタル層を介して接続されたフィールドプレートを有する半導体装置において、バリアメタル層の残渣が残るのを抑制できる半導体装置とその製造方法を提供することである。 The problem to be solved by the present invention is to provide a semiconductor device that can suppress the residue of a barrier metal layer from remaining in a semiconductor device having a field plate connected to a guard ring formed in a termination region via a barrier metal layer. An object of the present invention is to provide a manufacturing method thereof.
　上記課題を解決するために、本発明の半導体装置は、例えば、半導体素子が形成されたアクティブ領域と、前記アクティブ領域を囲むターミネーション領域とを有する半導体装置において、前記ターミネーション領域は、第１導電型の半導体基板と、前記半導体基板に形成された第２導電型の複数のガードリングと、前記半導体基板と前記ガードリングとに接し、前記ガードリングと重なる位置に開口部を有する絶縁膜と、少なくとも前記絶縁膜の前記開口部内に形成され、前記ガードリングに接し、互いに離間して配置された複数のバリアメタル層と、平面視したとき外形が前記バリアメタル層の外形よりも外側にあり、前記バリアメタル層の上面と前記絶縁膜の上面とに接し、互いに離間して配置された複数のフィールドプレートと、を有することを特徴とする。 In order to solve the above problems, a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed and a termination region surrounding the active region, wherein the termination region is of a first conductivity type. a semiconductor substrate, a plurality of second conductivity type guard rings formed on the semiconductor substrate, an insulating film contacting the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard rings; a plurality of barrier metal layers formed in the opening of the insulating film, in contact with the guard ring, and spaced apart from each other; It is characterized by comprising a plurality of field plates that are in contact with the upper surface of the barrier metal layer and the upper surface of the insulating film and are spaced apart from each other.
　また、本発明の半導体装置の製造方法は、例えば、半導体素子が形成されたアクティブ領域と、前記アクティブ領域を囲むターミネーション領域とを有し、前記ターミネーション領域は、第１導電型の半導体基板と、前記半導体基板に形成された第２導電型の複数のガードリングと、前記半導体基板と前記ガードリングとに接し前記ガードリングと重なる位置に開口部を有する絶縁膜と、前記ガードリングに接し互いに離間して配置された複数のバリアメタル層と、前記バリアメタル層に接し互いに離間して配置された複数のフィールドプレートとを有する半導体装置の製造方法において、前記バリアメタル層の成膜後、かつ、前記フィールドプレートの成膜前に、前記バリアメタル層をエッチングすることを特徴とする。 Further, the method for manufacturing a semiconductor device of the present invention includes, for example, an active region in which a semiconductor element is formed, and a termination region surrounding the active region, and the termination region includes a semiconductor substrate of a first conductivity type; a plurality of guard rings of a second conductivity type formed on the semiconductor substrate; an insulating film contacting the semiconductor substrate and the guard rings and having an opening at a position overlapping the guard rings; and an insulating film contacting the guard rings and spaced apart from each other. In the method of manufacturing a semiconductor device having a plurality of barrier metal layers disposed as a barrier metal layer and a plurality of field plates disposed in contact with the barrier metal layer and spaced apart from each other, after forming the barrier metal layer, and The method is characterized in that the barrier metal layer is etched before the field plate is formed.
　本発明の半導体装置によれば、バリアメタル層の外形はフィールドプレートよりも内側になるので、バリアメタル層をパターニングする際に残渣が残ったとしてもフィールドプレートよりも外側のバリアメタル層を再度エッチングするなどして残渣を除去することができ、バリアメタル層の残渣が残るのを抑制できる。 According to the semiconductor device of the present invention, the outer shape of the barrier metal layer is inside the field plate, so even if a residue remains when patterning the barrier metal layer, the barrier metal layer outside the field plate can be etched again. The residue can be removed by doing the following, and it is possible to suppress the residue of the barrier metal layer from remaining.
　また、本発明の半導体装置の製造方法によれば、フィールドプレートの成膜前にバリアメタル層をエッチングするので、バリアメタル層の残渣が残るのを抑制できる。また、仮にバリアメタル層をパターニングする際に残渣が残ったとしても、フィールドプレートのエッチング中またはエッチング後に、バリアメタル層を再度エッチングするなどして残渣を除去することもでき、バリアメタル層の残渣が残るのを抑制できる。 Furthermore, according to the method for manufacturing a semiconductor device of the present invention, since the barrier metal layer is etched before the field plate is formed, it is possible to suppress the residue of the barrier metal layer from remaining. Furthermore, even if a residue remains when patterning the barrier metal layer, the residue can be removed by etching the barrier metal layer again during or after etching the field plate, and the residue on the barrier metal layer can be removed. can be suppressed from remaining.
実施例１の半導体装置の断面図。1 is a cross-sectional view of a semiconductor device of Example 1. FIG. 実施例１の半導体装置の平面図。1 is a plan view of a semiconductor device of Example 1. FIG. 実施例１の半導体装置の製造方法を説明する断面図。1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1. FIG. 実施例１の半導体装置の製造方法を説明する断面図。1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1. FIG. 実施例１の半導体装置の製造方法を説明する断面図。1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1. FIG. 実施例１の半導体装置の製造方法を説明する断面図。1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1. FIG. 実施例１の半導体装置の製造方法を説明する断面図。1 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of Example 1. FIG. 実施例２の半導体装置の断面図。FIG. 3 is a cross-sectional view of a semiconductor device of Example 2.
　以下、図面を用いて本発明の実施例を説明する。各図、各実施例において、同一または類似の構成要素については同じ符号を付け、重複する説明は省略する。 Embodiments of the present invention will be described below with reference to the drawings. In each figure and each embodiment, the same or similar components are denoted by the same reference numerals, and overlapping explanations will be omitted.
　図１は、実施例１の半導体装置の断面図であり、図２は、実施例１の半導体装置の平面図である。図１は、図２のＡ－Ａにおける断面図である。 FIG. 1 is a cross-sectional view of the semiconductor device of Example 1, and FIG. 2 is a plan view of the semiconductor device of Example 1. FIG. 1 is a cross-sectional view taken along line AA in FIG.
　実施例１の半導体装置２０は、半導体素子が形成されたアクティブ領域２１と、アクティブ領域２１を囲むターミネーション領域２２とを有する。ターミネーション領域２２は、第１導電型（図１ではｎ型）の半導体基板１と、半導体基板１に形成された第２導電型（図１ではｐ型）の複数のガードリング２と、絶縁膜３と、バリアメタル層４と、フィールドプレート５とを有している。 The semiconductor device 20 of Example 1 has an active region 21 in which a semiconductor element is formed, and a termination region 22 surrounding the active region 21. The termination region 22 includes a semiconductor substrate 1 of a first conductivity type (n-type in FIG. 1), a plurality of guard rings 2 of a second conductivity type (p-type in FIG. 1) formed on the semiconductor substrate 1, and an insulating film. 3, a barrier metal layer 4, and a field plate 5.
　図１では、アクティブ領域２１に形成された半導体素子がＩＧＢＴ（Insulated Gate Bipolar Transistor）である場合を例に説明している。したがって、アクティブ領域２１は、半導体基板１で構成されたドリフト層と、主接合層となる第２導電型のボディ層６と、ボディ層６に接して形成されたバリアメタル層４と、バリアメタル層４に接して形成された表面側主電極７と、半導体基板１の裏面側に形成された第１導電型のバッファ層８と、第２導電型のコレクタ層９と、裏面側主電極１０とを有している。なお、バッファ層８は省略される場合もある。また、アクティブ領域２１は、ゲート電極とゲートとゲート絶縁膜とを有するが、図示省略している。図１では、半導体基板１の不純物濃度は低濃度であるため、ｎ－と表記した。図１では、第１導電型をｎ型とし、第２導電型をｐ型としているが、第１導電型をｐ型とし、第２導電型をｎ型としてもよい。 In FIG. 1, the case where the semiconductor element formed in the active region 21 is an IGBT (Insulated Gate Bipolar Transistor) is explained as an example. Therefore, the active region 21 includes a drift layer formed of the semiconductor substrate 1, a body layer 6 of the second conductivity type serving as a main bonding layer, a barrier metal layer 4 formed in contact with the body layer 6, and a barrier metal layer 4 formed in contact with the body layer 6. A front side main electrode 7 formed in contact with the layer 4 , a first conductivity type buffer layer 8 formed on the back side of the semiconductor substrate 1 , a second conductivity type collector layer 9 , and a back side main electrode 10 It has Note that the buffer layer 8 may be omitted in some cases. Further, the active region 21 includes a gate electrode, a gate, and a gate insulating film, but these are not shown. In FIG. 1, since the impurity concentration of the semiconductor substrate 1 is low, it is expressed as n-. In FIG. 1, the first conductivity type is n type and the second conductivity type is p type, but the first conductivity type may be p type and the second conductivity type may be n type.
　なお、半導体素子はＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）でもよく、その場合、第２導電型のコレクタ層９の代わりに第１導電型のドレイン層が形成される。 Note that the semiconductor element may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), in which case a drain layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
　また、半導体素子は、ＩＧＢＴやＭＯＳＦＥＴなどのスイッチング素子の代わりに、ダイオード素子でもよい。その場合、第２導電型のコレクタ層９の代わりに第１導電型のカソード層が形成される。 Furthermore, the semiconductor element may be a diode element instead of a switching element such as an IGBT or MOSFET. In that case, a cathode layer of the first conductivity type is formed instead of the collector layer 9 of the second conductivity type.
　次に、実施例１のターミネーション領域２２の構造の詳細を説明する。 Next, details of the structure of the termination region 22 of Example 1 will be explained.
　ガードリング２は、互いに離間して複数形成されている。 A plurality of guard rings 2 are formed spaced apart from each other.
　絶縁膜３は、半導体基板１とガードリング２とに接し、ガードリング２と重なる位置に開口部を有する。 The insulating film 3 is in contact with the semiconductor substrate 1 and the guard ring 2 and has an opening at a position overlapping with the guard ring 2.
　バリアメタル層４は、複数形成されており、互いに離間して配置されているとともに、少なくとも絶縁膜３の開口部内に形成され、ガードリング２に接している。実施例１では、バリアメタル層４は、絶縁膜３の上面にも形成されている。バリアメタル層４は、例えばＴｉ，ＴｉＮ，ＴｉＷ，ＭｏＳｉ２のうちの何れかにより形成することができる。バリアメタル層４は、フィールドプレート５に含有される金属（例えばＡｌ）がガードリング２を構成する半導体層（例えばＳｉ）に拡散するのを防止する役割を有する。したがって、バリアメタル層４は、絶縁膜３の開口部内において、ガードリング２と重なる領域のすべてに形成されていることが望ましい。 A plurality of barrier metal layers 4 are formed and are spaced apart from each other, and are formed at least within the opening of the insulating film 3 and are in contact with the guard ring 2. In Example 1, the barrier metal layer 4 is also formed on the upper surface of the insulating film 3. The barrier metal layer 4 can be formed of, for example, any one of Ti, TiN, TiW, and MoSi2 . The barrier metal layer 4 has a role of preventing metal (for example, Al) contained in the field plate 5 from diffusing into the semiconductor layer (for example, Si) forming the guard ring 2 . Therefore, it is desirable that the barrier metal layer 4 be formed in the entire region overlapping the guard ring 2 within the opening of the insulating film 3.
　フィールドプレート５は、複数形成されており、互いに離間して配置されているとともに、平面視したとき外形がバリアメタル層４の外形よりも外側にあり、バリアメタル層４の上面と絶縁膜３の上面とに接している。フィールドプレート５は、例えばＡｌ，ＡｌＳｉ，ＡｌＣｕ，ＡｌＳｉＣｕのうちの何れかにより形成することができる。実施例１では、バリアメタル層４は、絶縁膜３の上面にも形成されているので、フィールドプレート５は、絶縁膜３の上面においてバリアメタル層４の側面にも接している。 A plurality of field plates 5 are formed, and are spaced apart from each other, and have an outer shape outside the outer shape of the barrier metal layer 4 when viewed from above, and are connected to the upper surface of the barrier metal layer 4 and the insulating film 3. It is in contact with the top surface. The field plate 5 can be formed of, for example, any one of Al, AlSi, AlCu, and AlSiCu. In Example 1, the barrier metal layer 4 is also formed on the upper surface of the insulating film 3, so the field plate 5 is also in contact with the side surface of the barrier metal layer 4 on the upper surface of the insulating film 3.
　以上のような構成により、複数のフィールドプレート５の間隔は、複数のバリアメタル層４の間隔よりも小さくなっている。また、バリアメタル層４の端部は、フィールドプレート５の端部よりも内側に存在するようになっている。そして、バリアメタル層４は、全体がフィールドプレート５によって覆われ、はみ出さない構造になっている。 With the above configuration, the distance between the plurality of field plates 5 is smaller than the distance between the plurality of barrier metal layers 4. Further, the end of the barrier metal layer 4 is located inside the end of the field plate 5. The barrier metal layer 4 is entirely covered by the field plate 5 and has a structure that it does not protrude.
　実施例１の半導体装置２０によれば、バリアメタル層４の外形はフィールドプレート５よりも内側になるので、バリアメタル層４をパターニングする際に残渣が残ったとしてもフィールドプレート５よりも外側のバリアメタル層を再度エッチングするなどして残渣を除去することができ、バリアメタル層４の残渣が残るのを抑制できる。 According to the semiconductor device 20 of the first embodiment, the outer shape of the barrier metal layer 4 is inside the field plate 5, so even if a residue remains when patterning the barrier metal layer 4, it will not remain outside the field plate 5. The residue can be removed by etching the barrier metal layer again, and it is possible to suppress the residue of the barrier metal layer 4 from remaining.
　バリアメタル層４が残渣として残ると、フィールドプレート５の間が電気的に接続され、各フィールドプレート５に接続されているガードリング２が同電位となり、ターミネーション領域２２で十分な耐圧が確保できないという問題が生じる。これに対して、実施例１の半導体装置２０によれば、バリアメタル層４の外形はフィールドプレート５よりも内側になること、および、バリアメタル層４の残渣が残るのを抑制できることから、この問題が生じるのを抑制できる。 If the barrier metal layer 4 remains as a residue, the field plates 5 are electrically connected, and the guard rings 2 connected to each field plate 5 have the same potential, making it impossible to ensure sufficient breakdown voltage in the termination region 22. A problem arises. On the other hand, according to the semiconductor device 20 of Example 1, the outer shape of the barrier metal layer 4 is inside the field plate 5, and the residue of the barrier metal layer 4 can be suppressed from remaining. Problems can be prevented from occurring.
　次に、実施例１の半導体装置２０の製造方法を説明する。実施例１の半導体装置２０は、バリアメタル層４の成膜後、かつ、フィールドプレート５の成膜前に、バリアメタル層４をエッチングすることで形成することができる。 Next, a method for manufacturing the semiconductor device 20 of Example 1 will be described. The semiconductor device 20 of Example 1 can be formed by etching the barrier metal layer 4 after the barrier metal layer 4 is formed and before the field plate 5 is formed.
　図３から図７は、実施例１の半導体装置の製造方法を説明する断面図である。なお、ここでは表面側についてのみ説明し、裏面側については図示および説明を省略する。 3 to 7 are cross-sectional views illustrating the method for manufacturing the semiconductor device of Example 1. Note that only the front side will be described here, and illustration and description of the back side will be omitted.
　はじめに、図３に示すように、半導体基板１に第２導電型の不純物を注入し、ガードリング２とボディ層６とを形成する。その後、絶縁膜３を成膜後、必要な箇所に開口部を形成する。 First, as shown in FIG. 3, a second conductivity type impurity is implanted into the semiconductor substrate 1 to form the guard ring 2 and the body layer 6. Thereafter, after forming the insulating film 3, openings are formed at necessary locations.
　次に、図４に示すように、バリアメタル層４となる金属層をスパッタリングや蒸着により形成する。 Next, as shown in FIG. 4, a metal layer that will become the barrier metal layer 4 is formed by sputtering or vapor deposition.
　次に、図５に示すように、ホトレジスト１１を用いてバリアメタル層４をエッチングにより加工する。フィールドプレート５の成膜前にバリアメタル層４をエッチングすることで、バリアメタル層４の残渣が残るのを抑制できるとともに、バリアメタル層４の外形を、フィールドプレート５の外形よりも内側になるように加工することが可能となる。 Next, as shown in FIG. 5, the barrier metal layer 4 is processed by etching using the photoresist 11. By etching the barrier metal layer 4 before forming the field plate 5, it is possible to suppress the residue of the barrier metal layer 4 from remaining, and to change the outer shape of the barrier metal layer 4 to be inside the outer shape of the field plate 5. It becomes possible to process it as follows.
　次に、図６に示すように、フィールドプレート５となる金属層をスパッタリングや蒸着により形成する。 Next, as shown in FIG. 6, a metal layer that will become the field plate 5 is formed by sputtering or vapor deposition.
　次に、図７に示すように、ホトレジスト１１を用いてフィールドプレート５をエッチングにより加工する。このとき、平面視したときフィールドプレート５の外形がバリアメタル層４の外形よりも外側にあるように加工する。これにより、複数のフィールドプレート５の間隔は、複数のバリアメタル層４の間隔よりも小さくなる。その後、ホトレジスト１１を除去することで、図１に示す構造を形成することができる。 Next, as shown in FIG. 7, the field plate 5 is processed by etching using the photoresist 11. At this time, processing is performed so that the outer shape of the field plate 5 is located outside the outer shape of the barrier metal layer 4 when viewed from above. As a result, the distance between the plurality of field plates 5 becomes smaller than the distance between the plurality of barrier metal layers 4. Thereafter, by removing the photoresist 11, the structure shown in FIG. 1 can be formed.
　また、図７に示す工程の後、仮にバリアメタル層４をパターニングする際に残渣が残ったとしても、フィールドプレート５のエッチング中またはエッチング後に、バリアメタル層４を再度エッチングするなどして残渣を除去することもできる。これにより、バリアメタル層４の残渣が残るのを抑制できる。 Furthermore, even if a residue remains when patterning the barrier metal layer 4 after the step shown in FIG. 7, the residue can be removed by etching the barrier metal layer 4 again during or after etching the field plate 5. It can also be removed. Thereby, it is possible to suppress the residue of the barrier metal layer 4 from remaining.
　実施例２は、実施例１の変形例である。実施例２では、実施例１と異なる点を中心に説明し、重複する説明は省略する。 Example 2 is a modification of Example 1. In the second embodiment, points different from the first embodiment will be mainly explained, and redundant explanations will be omitted.
　図８は、実施例２の半導体装置の断面図である。 FIG. 8 is a cross-sectional view of the semiconductor device of Example 2.
　実施例２の半導体装置２０のバリアメタル層４は、絶縁膜３の上面には形成されていない点で実施例１とは異なっている。換言すれば、絶縁膜３の開口部内のみに形成されている。製造方法は、バリアメタル層４のパターニングの形状が異なるだけで、実施例１とほぼ同じである。実施例２でも、実施例１と同様の効果を奏することができる。 The barrier metal layer 4 of the semiconductor device 20 of Example 2 differs from Example 1 in that it is not formed on the upper surface of the insulating film 3. In other words, it is formed only within the opening of the insulating film 3. The manufacturing method is almost the same as in Example 1, except that the patterning shape of the barrier metal layer 4 is different. The second embodiment can also provide the same effects as the first embodiment.
　以上、本発明の実施例を説明したが、本発明は実施例に記載された構成に限定されず、本発明の技術的思想の範囲内で種々の変更が可能である。また、各実施例で説明した構成の一部または全部を組み合わせて適用してもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations described in the embodiments, and various changes can be made within the scope of the technical idea of the present invention. Further, some or all of the configurations described in each embodiment may be combined and applied.
　１…半導体基板、２…ガードリング、３…絶縁膜、４…バリアメタル層、５…フィールドプレート、６…ボディ層、７…表面側主電極、８…バッファ層、９…コレクタ層、１０…裏面側主電極、１１…ホトレジスト、１２…電極層、２０…半導体装置、２１…アクティブ領域、２２…ターミネーション領域 DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Guard ring, 3... Insulating film, 4... Barrier metal layer, 5... Field plate, 6... Body layer, 7... Surface side main electrode, 8... Buffer layer, 9... Collector layer, 10... Back side main electrode, 11... Photoresist, 12... Electrode layer, 20... Semiconductor device, 21... Active region, 22... Termination region

Claims (11)

  1. 　半導体素子が形成されたアクティブ領域と、前記アクティブ領域を囲むターミネーション領域とを有する半導体装置において、
    　前記ターミネーション領域は、
    　第１導電型の半導体基板と、
    　前記半導体基板に形成された第２導電型の複数のガードリングと、
    　前記半導体基板と前記ガードリングとに接し、前記ガードリングと重なる位置に開口部を有する絶縁膜と、
    　少なくとも前記絶縁膜の前記開口部内に形成され、前記ガードリングに接し、互いに離間して配置された複数のバリアメタル層と、
    　平面視したとき外形が前記バリアメタル層の外形よりも外側にあり、前記バリアメタル層の上面と前記絶縁膜の上面とに接し、互いに離間して配置された複数のフィールドプレートと、を有することを特徴とする半導体装置。     A semiconductor device having an active region in which a semiconductor element is formed and a termination region surrounding the active region,
    The termination area is
    a semiconductor substrate of a first conductivity type;
    a plurality of guard rings of a second conductivity type formed on the semiconductor substrate;
    an insulating film that is in contact with the semiconductor substrate and the guard ring and has an opening at a position overlapping the guard ring;
    a plurality of barrier metal layers formed at least in the opening of the insulating film, in contact with the guard ring, and spaced apart from each other;
    A plurality of field plates, the outer shape of which is outside the outer shape of the barrier metal layer when viewed in plan, are in contact with the upper surface of the barrier metal layer and the upper surface of the insulating film, and are spaced apart from each other. A semiconductor device characterized by:
  2. 　請求項１において、
    　前記バリアメタル層は、前記絶縁膜の上面にも形成され、
    　前記フィールドプレートは、前記絶縁膜の上面において前記バリアメタル層の側面に接することを特徴とする半導体装置。     In claim 1,
    The barrier metal layer is also formed on the upper surface of the insulating film,
    The semiconductor device, wherein the field plate is in contact with a side surface of the barrier metal layer on an upper surface of the insulating film.
  3. 　請求項１において、
    　前記バリアメタル層は、前記絶縁膜の上面には形成されていないことを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that the barrier metal layer is not formed on the upper surface of the insulating film.
  4. 　請求項１において、
    　前記バリアメタル層は、前記絶縁膜の前記開口部内において、前記ガードリングと重なる領域のすべてに形成されていることを特徴とする半導体装置。     In claim 1,
    The semiconductor device characterized in that the barrier metal layer is formed in the entire region overlapping with the guard ring within the opening of the insulating film.
  5. 　請求項１において、
    　前記バリアメタル層は、Ｔｉ，ＴｉＮ，ＴｉＷ，ＭｏＳｉ２のうちの何れかにより形成されていることを特徴とする半導体装置。     In claim 1,
    A semiconductor device characterized in that the barrier metal layer is formed of any one of Ti, TiN, TiW, and MoSi2 .
  6. 　請求項１において、
    　前記複数のフィールドプレートの間隔は、前記複数のバリアメタル層の間隔よりも小さいことを特徴とする半導体装置。     In claim 1,
    A semiconductor device, wherein an interval between the plurality of field plates is smaller than an interval between the plurality of barrier metal layers.
  7. 　請求項１において、
    　前記半導体素子は、スイッチング素子であることを特徴とする半導体装置。     In claim 1,
    A semiconductor device, wherein the semiconductor element is a switching element.
  8. 　請求項１において、
    　前記半導体素子は、ダイオード素子であることを特徴とする半導体装置。     In claim 1,
    A semiconductor device, wherein the semiconductor element is a diode element.
  9. 　半導体素子が形成されたアクティブ領域と、前記アクティブ領域を囲むターミネーション領域とを有し、前記ターミネーション領域は、第１導電型の半導体基板と、前記半導体基板に形成された第２導電型の複数のガードリングと、前記半導体基板と前記ガードリングとに接し前記ガードリングと重なる位置に開口部を有する絶縁膜と、前記ガードリングに接し互いに離間して配置された複数のバリアメタル層と、前記バリアメタル層に接し互いに離間して配置された複数のフィールドプレートとを有する半導体装置の製造方法において、
    　前記バリアメタル層の成膜後、かつ、前記フィールドプレートの成膜前に、前記バリアメタル層をエッチングすることを特徴とする半導体装置の製造方法。     The termination region includes a semiconductor substrate of a first conductivity type and a plurality of semiconductor substrates of a second conductivity type formed on the semiconductor substrate. a guard ring, an insulating film contacting the semiconductor substrate and the guard ring and having an opening at a position overlapping the guard ring, a plurality of barrier metal layers contacting the guard ring and spaced apart from each other, and the barrier metal layer. In a method of manufacturing a semiconductor device having a plurality of field plates arranged in contact with a metal layer and spaced apart from each other,
    A method for manufacturing a semiconductor device, characterized in that the barrier metal layer is etched after the barrier metal layer is formed and before the field plate is formed.
  10. 　請求項９において、
    　前記複数のフィールドプレートの間隔は、前記複数のバリアメタル層の間隔よりも小さいことを特徴とする半導体装置の製造方法。     In claim 9,
    A method of manufacturing a semiconductor device, wherein an interval between the plurality of field plates is smaller than an interval between the plurality of barrier metal layers.
  11. 　請求項９において、
    　前記フィールドプレートのエッチング中またはエッチング後に、前記バリアメタル層を再度エッチングすることを特徴とする半導体装置の製造方法。     In claim 9,
    A method of manufacturing a semiconductor device, comprising etching the barrier metal layer again during or after etching the field plate.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021526A (en) * 2007-07-13 2009-01-29 Toshiba Corp Power semiconductor device and its manufacturing method
JP2019169551A (en) * 2018-03-22 2019-10-03 ローム株式会社 Nitride semiconductor device
JP2021005657A (en) * 2019-06-27 2021-01-14 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009021526A (en) * 2007-07-13 2009-01-29 Toshiba Corp Power semiconductor device and its manufacturing method
JP2019169551A (en) * 2018-03-22 2019-10-03 ローム株式会社 Nitride semiconductor device
JP2021005657A (en) * 2019-06-27 2021-01-14 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof

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