JPH08172185A - Offset gate mos transistor - Google Patents

Abstract

PURPOSE: To prevent the increase of element area which is to be caused by a heavily doped channel stopper layer, by constituting the whole region in contact with an offset diffusion layer by using a gate oxide film and a gate electrode, and restraining the spread of a depletion layer in the offset diffusion layer, within the vicinity of the surface. CONSTITUTION: An offset diffusion layer 22 is arranged around a source.drain diffusion layer 26. An oxide film 23 is formed on the offset diffusion layer 22. A gate oxide film 24 and a gate electrode 25 composed of a polysilicon pattern are formed in the facing part of the source4Ndrain diffusion layer 26 and the facing part of the source.drain diffusion layer 26 and the channel stopper diffusion layer 28. Thus the gate oxide film 24 and the gate electrode 25 are formed in the whole periphery isolated from the source.drain diffusion layer 26 by the offset diffusion layer 22. Thereby the spread Xd1 ' stretching from the junction part of the offset diffusion layer 22 is especially restrained within the vicinity of the surface by the electric potential of the upper layer gate electrode 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an offset gate structure used as a high breakdown voltage MOS.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one as described in JP-A-61-171165. FIG. 5 is a sectional view of a manufacturing process of such a conventional high breakdown voltage offset gate MOS transistor. (1) First, as shown in FIG. 5A, the specific resistance is 1 to 2 Ω.
An oxide film 2 having a thickness of about 500Å is formed on the surface of an N-type semiconductor Si substrate 1 of cm, and then an oxidation resistant film 1000Å such as a nitride film is formed, and the oxidation resistant film is formed by a known photolitho etching technique. Pattern 3 is formed. (2) Next, as shown in FIG. 5B, a photoresist pattern 5 is formed on the outer side of the oxidation resistant film pattern 3 with a distance 4 therebetween by a known photolithography technique. Then, using the oxidation resistant film pattern 3 and the photoresist pattern 5 as a mask, boron ions are removed by a known ion implantation technique.
It is introduced under the condition of E13 cm ⁻² to form an offset layer (P implantation layer) 6. (3) Then, as shown in FIG. 5 (c), after removing the photoresist pattern 5, an oxidation treatment is performed at 1000 ° C. for about 400 minutes in a steam atmosphere using the oxidation resistant film pattern 3 as a mask to remove the acid resistance. A thermal oxide film 7 having a thickness of about 10000Å is formed in a region other than the chemical conversion film pattern 3. Next, the oxidation resistant film pattern 3 and the oxide film 2 are removed, and a new gate oxide film 8 is formed in the region of the oxidation resistant film pattern 3. (4) Next, as shown in FIG. 5D, a polysilicon pattern 9 to be a gate electrode is formed by a known photolitho etching technique. Next, the P ⁺ high concentration layer 10 to be the source / drain is formed by the photolithography / ion implantation technique.
Then, the N ⁺ high-concentration layer 15 which becomes the channel stopper is formed. (5) Next, as shown in FIG. 5E, an insulating film 11 made of phosphor silica glass or the like is formed, and a contact hole 12 is opened. Next, a wiring metal 13 such as aluminum is formed, and a passivation film 14 such as a nitride film is formed to complete a high breakdown voltage offset gate MOS transistor.

[0003]

However, in the conventional high breakdown voltage offset gate MOS transistor described above, a high concentration channel stopper layer is indispensable in order to reduce parasitic MOS leakage as element isolation. Normally, the channel stopper layer of this high breakdown voltage offset gate MOS transistor is provided in FIG. 6 (line A-A in FIG. 7) in order to prevent the generation of parasitic MOS leakage at a high operating voltage without deteriorating the high breakdown voltage characteristic. As shown in (corresponding to the cross-sectional view), an N ⁺ high-concentration diffusion layer 15 is formed at a position separated from the low-concentration offset layer by an appropriate distance 16.

At this time, the value of the distance 16 is determined by the performance required for the high breakdown voltage offset gate MOS transistor, but is set so as not to prevent the spread (Xd ₁ ) of the depletion layer extending from the junction of the offset layer. Because
It was an obstacle to the reduction of the element size. In addition, in FIG.
Reference numeral 11 is an insulating film. Also, the high breakdown voltage offset gate M
In the OS transistor, the spread (Xd ₂ ) of the depletion layer in the offset layer is large, which affects its performance.

Therefore, it is desirable that the distance 4 between the P ⁺ high-concentration layer and the offset layer is always constant, but this distance 4 is set larger than a necessary value, which also hinders the element reduction. Was becoming. FIG. 7 is a top view of such a conventional high breakdown voltage offset gate MOS transistor,
FIG. 8 is a sectional view taken along line BB of FIG. 7.

In the high breakdown voltage offset gate MOS transistor having the above-mentioned high-concentration channel stopper layer, the electric field strength of the drain portion is larger in the peripheral portion than in the gate edge portion. It is known that the offset layer corner portion 6a in the top view has the highest electric field strength as shown in FIG. Therefore, when a large surge voltage such as static electricity is input, the breakdown current concentrates on the peripheral portion, especially on the offset layer corner portion 6a, and there is a problem that the element is easily broken.

The present invention eliminates the above problems, prevents an increase in the element area due to the high-concentration channel stopper layer of the high breakdown voltage offset gate MOS transistor, and has an excellent high breakdown voltage offset gate MO having a large electrostatic breakdown resistance.
It is intended to provide an S transistor.

[0008]

According to the present invention, in order to achieve the above object, [1] a pair of second conductivity type source / drain facing each other on a first conductivity type semiconductor substrate (21). A diffusion layer (26),
An offset diffusion layer (22) having a lower concentration than the source / drain diffusion layer of the second conductivity type around the source / drain diffusion layer (26) and a periphery of the offset diffusion layer (22) with a constant distance. A first conductive type channel stopper diffusion layer (28), a gate region composed of a gate insulating film (24) and a gate electrode (25) sandwiched between opposing offset diffusion layers (22), and a source / drain diffusion layer. (26), a channel stopper diffusion layer (28), and an offset diffusion layer (2) having a second insulating film (23) thicker than the gate insulating film (24) in the region excluding the gate region.
2) has a gate region composed of a gate insulating film (24) and a gate electrode (25) in the entire region in contact with the offset diffusion layer (22) of the opposing portion of the channel stopper diffusion layer (28) and the gate insulation. The second insulating film (23) thicker than the film (24) is provided on all of the offset diffusion layer (22).

[2] In the offset gate MOS transistor described in (1) above, a gate region composed of a gate insulating film (24) and a gate electrode (25) sandwiched between opposed offset diffusion layers (22), and offset diffusion. The gate electrode (25) in the gate region, which is composed of the gate insulating film (24) and the gate electrode (25), is in contact with the offset diffusion layer (28) at the portion where the layer (22) and the channel stopper diffusion layer (28) face each other. Second gate electrode (25a)
And the second gate electrode (25b) is connected to the channel stopper diffusion layer (28) with a wiring metal so that the second gate electrode (25b) and the channel stopper diffusion layer (28) have the same potential.

[3] In the offset gate MOS transistor described in (1) above, the offset diffusion layer (2
2) and a part of the gate electrode in the gate region consisting of the gate oxide film (24) and the gate electrode (25) in a region in contact with the offset diffusion layer (22) in the opposing portion of the channel stopper diffusion layer (28), The wiring metal (29) of the drain diffusion layer is arranged in that region.

[4] In the offset gate MOS transistor described in (2) above, the separated gate electrode (2
5a, 25b), the thickness of each gate insulating film (24) is offset more than the gate region composed of the gate insulating film (24) and the gate electrode (25) sandwiched by the offset diffusion layers (22) facing each other. The gate region composed of the second gate oxide film (24b) and the gate electrode (25) which is in contact with the offset diffusion layer in the opposing portion of the diffusion layer (22) and the channel stopper diffusion layer (28) is thinned. is there.

[0012]

According to the present invention, since it is configured as described above, [1] the offset gate MOS transistor according to claim 1, (1) the depletion layer extending from the junction of the offset diffusion layer is expanded. (See FIG. 4) is suppressed by the potential of the gate electrode pattern, especially near the surface. For example, the width of the depletion layer (see FIG. 6) is about 2.0 μm when there is no gate electrode pattern as in the prior art, whereas the width of the depletion layer is about 1. It becomes 5 μm.

Therefore, the distance between the offset diffusion layer and the N ⁺ high-concentration diffusion layer can be reduced by about 25%. (2) The spread of the depletion layer in the offset diffusion layer is
Although there is no change from the conventional technique, the distance between the P ⁺ high-concentration diffusion layer and the offset layer is determined only by the oxidation resistant film pattern, so that the alignment margin required in the past is not necessary. For example, the distance 4 (see FIG. 6), which was required to be 3.0 μm in the past, is 2.0 μ as shown in the distance 41 (see FIG. 4).
m, and reduction of about 30% is possible.

(3) Since the pattern is the same around the drain part, the electric field strength becomes uniform, and when a large surge voltage such as static electricity is input, the breakdown current does not concentrate and the breakdown resistance of the element is reduced. Is greatly improved. (4) Since the thick oxide film terminates in the peripheral portion of the offset diffusion layer, the radius of curvature R'of the bottom corner portion of the offset diffusion layer increases, and the breakdown withstand voltage is expected to improve.

Furthermore, there is no additional step for adding these effects, and there is no increase in cost. [2] According to the offset gate MOS transistor of the second aspect, since the gate electrode is separated into a portion effectively operating as a gate and a portion operating as a channel stopper, the effect of the above [1] is impaired. Without reducing the gate capacitance. Generally, the charging / discharging time of the gate capacitance is an important factor that determines the circuit speed of the transistor, and in this embodiment, the gate capacitance could be reduced to about 1/3 of that in the first embodiment.

[3] The offset gate M according to claim 3.
According to the OS transistor, in addition to the effect of [1] above, since the overlapping portion of the wiring metal of the drain layer and the gate electrode is eliminated, the insulating film defect between the wiring metal and the gate electrode caused by the step of the gate electrode is eliminated. It will not occur. This can particularly increase the surge voltage withstanding capability such as static electricity at the final stage of the transistor circuit.

[4] An offset gate M according to claim 4.
According to the OS transistor, as in the above [2], the gate electrode is divided into a portion that effectively acts as a gate and a portion that acts as a channel stopper, and the gate oxide film thickness of each is changed. The electric field in the stopper portion becomes larger than the portion effectively operating as the gate. Therefore, the spread of the depletion layer extending from the junction of the offset diffusion layer is strongly suppressed by the gate electrode pattern potential of the upper layer, and the distance between the offset diffusion layer and the N ⁺ high concentration layer can be further reduced.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a top view of an offset gate MOS transistor showing a first embodiment of the present invention, FIG. 2 is a sectional view of the offset gate MOS transistor taken along line CC, and FIG. 3 is a sectional view of the offset gate MOS transistor taken along line DD. It is a figure.

As shown in these figures, the offset diffusion layer 22 is arranged around the source / drain diffusion layer 26,
An oxide film 23 is formed on the offset diffusion layer 22.
The opposing portion of the source / drain diffusion layer 26, and the source / drain diffusion layer 26 and the channel stopper diffusion layer (N ⁺
A gate electrode 25 composed of a gate oxide film 24 and a polysilicon pattern was formed on the opposite portion of the high concentration diffusion layer 28.

Therefore, the gate oxide film 24 and the gate electrode 25 are formed on the entire periphery separated from the source / drain diffusion layer 26 by the offset diffusion layer 22. In FIG. 2 and FIG. 3, 21 is an N-type semiconductor Si substrate. With this configuration, as shown in FIG.
In the offset gate MOS transistor of the present invention, (1) firstly, the spread (Xd ₁ ′) of the depletion layer extending from the junction of the offset diffusion layer 22 is caused especially by the potential of the upper gate electrode 25 near the surface. It can be suppressed.

In this embodiment, when there is no gate electrode 25, that is, the value of Xd ₁ is about 2.0 μm as in the prior art (FIG. 5), the gate electrode 25 is formed in FIG. The value of Xd ₁ ′ is about 1.5 μm. Therefore, the offset diffusion layer 22 and the N ⁺ high concentration diffusion layer 28
The distance 42 can be reduced by about 25%.

(2) Secondly, the spread (Xd ₂ ′) of the depletion layer in the offset diffusion layer 22 is the same as in the prior art, but the distance 42 between the N ⁺ high concentration diffusion layer 28 and the offset diffusion layer 22 is 42. However, since it is determined only by the oxidation resistant film pattern,
The alignment margin that was required in the past is no longer necessary. In this embodiment, the distance 32, which was conventionally required to be 3.0 μm, is 2.0 μ.
m, and reduction of about 30% is possible.

(3) Thirdly, since the same pattern is formed around the drain portion, the electric field strength becomes uniform, and when a large surge voltage such as static electricity is input, the breakdown current is not concentrated and the element The breaking strength is greatly improved. (4) Fourth, since a thick oxide film terminates in the peripheral portion of the offset diffusion layer 22, the radius of curvature R ′ of the bottom corner portion of the offset diffusion layer 22 becomes large, and the breakdown breakdown voltage is expected to improve. .

Furthermore, in order to realize these effects,
There is no new process to add and no increase in cost. In FIG. 4, 40 is an insulating film and 41 is a distance. Next, a second embodiment of the present invention will be described with reference to FIGS.
And FIG. 11 will be described.

FIG. 9 is a top view of an offset gate MOS transistor showing a second embodiment of the present invention, FIG. 10 is a sectional view of the offset gate MOS transistor taken along the line EE,
FIG. 11 shows F of the offset gate MOS transistor.
It is a -F line sectional view. The gate electrode 25 of the above-described first embodiment is divided into the first gate electrode 25a and the second gate electrode 25a by separating the facing portion of the source / drain diffusion layer 26 and the facing portion of the source / drain diffusion layer 26 and the channel stopper diffusion layer 28. The gate electrode 25b was formed. In addition, the source
Drain diffusion layer 26 and channel stopper diffusion layer 28
The gate electrode 25b in the opposite portion is connected by a wiring metal 29 so as to have the same potential as the channel stopper diffusion layer 28. 30 is a contact.

According to this embodiment, the gate electrode is separated into a portion effectively operating as a gate, that is, a first gate electrode 25a and a portion operating as a channel stopper, that is, a second gate electrode 25b. Therefore, the gate capacitance can be reduced without impairing the effects of the first embodiment. Generally, the charging / discharging time of the gate capacitance is an important factor that determines the circuit speed of the transistor, and in this embodiment, the gate capacitance could be reduced to about 1/3 of that in the first embodiment.

Next, a third embodiment of the present invention will be described with reference to FIG.
And FIG. 13 will be described. FIG. 12 is a top view of an offset gate MOS transistor showing a third embodiment of the present invention, and FIG. 13 is a sectional view taken along line HH of this offset gate MOS transistor. The sectional view taken along the line GG of the offset gate MOS transistor is the same as that shown in FIG.

In this embodiment, a part of the gate electrode 25 of the above-described first embodiment (see FIG. 1) is cut, and the extraction electrode 31 of the source / drain diffusion layer 26 and the gate electrode 25 are cut.
It has a structure that eliminates the overlapping part. According to this embodiment, since the wiring metal 31 of the source / drain diffusion layer 26 and the overlapping portion of the gate electrode 25 are eliminated, the insulating film defect between the wiring metal 31 and the gate electrode 25 caused by the step of the gate electrode 25 is eliminated. It will not occur.

This makes it possible to increase the surge voltage withstanding capability such as static electricity in the final stage of the transistor circuit.
Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 14 is a top view of an offset gate MOS transistor showing a fourth embodiment of the present invention, and FIG. 15 is a sectional view taken along the line I-I of this offset gate MOS transistor. The sectional view taken along the line JJ of this offset gate MOS transistor is the same as that in FIG.

Similar to the second embodiment described above, the opposing portions of the source diffusion layer and the drain diffusion layer and the opposing portions of the source / drain diffusion layer 26 and the channel stopper diffusion layer 28 are separated to separate the first gate electrode. 25a and the second gate electrode 25b are formed, and the first gate oxide film 2 thereunder is formed.
The film thicknesses of 4a and the second gate oxide film 24b are changed. In this embodiment, the thickness of the first gate oxide film 24a is set to 100.
0 Å and the thickness of the second gate oxide film 24b is 200 Å
And The 200 Å second gate oxide film 24b is
High breakdown voltage offset gate MO formed in the same chip
It is a gate oxide film of a control low breakdown voltage transistor that drives an S transistor, and in the case of a semiconductor element having such a control low breakdown voltage transistor, it can be formed without adding a new step.

As described above, similarly to the second embodiment, the portion effectively operating the gate electrode as a gate, that is, the first
The gate electrode 25a and the portion that operates as a channel stopper, that is, the second gate electrode 25b is separated and the thickness of each gate oxide is changed, so that the electric field of the channel stopper portion effectively operates as a gate. It becomes larger than the part to do.

Therefore, the spread of the depletion layer extending from the junction of the offset diffusion layer is strongly suppressed by the gate electrode pattern potential of the upper layer, so that the distance between the offset diffusion layer and the N ⁺ high concentration diffusion layer as the channel stopper is reduced. It can be made even smaller. The present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0033]

As described in detail above, according to the present invention, the following effects can be obtained. [1] According to the invention described in claim 1, (1) The spread of the depletion layer extending from the junction of the offset diffusion layer (see FIG. 4) is suppressed by the potential of the gate electrode pattern, particularly near the surface. For example, the width of the depletion layer (see FIG. 6) is about 2.0 μm when there is no gate electrode pattern as in the prior art, whereas the width of the depletion layer is about 1. It becomes 5 μm.

Therefore, the distance between the offset diffusion layer and the N ⁺ high-concentration diffusion layer can be reduced by about 25%. (2) The spread of the depletion layer in the offset diffusion layer is
Although there is no change from the conventional technique, the distance between the P ⁺ high-concentration diffusion layer and the offset layer is determined only by the oxidation-resistant film pattern, so that the alignment margin required conventionally is not necessary. For example, the distance 4 (see FIG. 5), which was required to be 3.0 μm in the past, becomes 2.0 μm, and the reduction of about 30% is possible.

(3) Since the pattern is the same around the drain part, the electric field strength becomes uniform, and when a large surge voltage such as static electricity is input, the breakdown current does not concentrate and the breakdown resistance of the element is reduced. Is greatly improved. (4) Since the thick oxide film terminates in the peripheral portion of the offset diffusion layer, the radius of curvature R'of the bottom corner portion of the offset diffusion layer increases, and the breakdown withstand voltage is expected to improve.

Furthermore, there is no additional step for adding these effects, and there is no increase in cost. [2] According to the invention of claim 2, the gate electrode is separated into a portion effectively operating as a gate and a portion operating as a channel stopper.
The gate capacitance can be reduced without impairing the effect of. Generally, the charging / discharging time of the gate capacitance is an important factor that determines the circuit speed of the transistor, and in this embodiment, the gate capacitance could be reduced to about 1/3 of that in the first embodiment.

[3] According to the invention of claim 3, in addition to the effect of the above [1], the wiring caused by the step of the gate electrode is eliminated by eliminating the overlapping portion of the wiring metal of the drain layer and the gate electrode. Insulating film failure between metal and gate electrode does not occur. This can particularly increase the surge voltage withstanding capability such as static electricity at the final stage of the transistor circuit.

[4] According to the invention described in claim 4, as in the above-mentioned [2], the gate electrode is divided into a portion effectively operating as a gate and a portion operating as a channel stopper, and each gate oxidation is performed. Because the film thickness is changed,
The electric field in the channel stopper portion becomes larger than that in the portion effectively operating as the gate. Therefore, the spread of the depletion layer extending from the junction portion of the offset diffusion layer is strongly suppressed by the upper polysilicon pattern potential, and the distance between the offset diffusion layer and the N ⁺ high concentration layer can be further reduced.

[Brief description of drawings]

FIG. 1 is an offset gate M showing a first embodiment of the present invention.
It is a top view of an OS transistor.

FIG. 2 is an offset gate M showing a first embodiment of the present invention.
It is a CC sectional view taken on the line of an OS transistor.

FIG. 3 is an offset gate M showing a first embodiment of the present invention.
It is the DD sectional view taken on the line of an OS transistor.

FIG. 4 is an offset gate MO for explaining the effect of the present invention.
It is a drain part enlarged sectional view of an S transistor.

FIG. 5 is a sectional view of a manufacturing process of a conventional high breakdown voltage offset gate MOS transistor.

FIG. 6 is an enlarged cross-sectional view of a drain portion of a conventional offset gate MOS transistor.

FIG. 7 is a top view of a conventional offset gate MOS transistor.

FIG. 8 is a sectional view taken along line BB in FIG.

FIG. 9 is an offset gate M showing a second embodiment of the present invention.
It is a top view of an OS transistor.

FIG. 10 is a sectional view taken along the line EE of the offset gate MOS transistor showing the second embodiment of the present invention.

FIG. 11 is a sectional view taken along line FF of the offset gate MOS transistor showing the second embodiment of the present invention.

FIG. 12 is a top view of an offset gate MOS transistor showing a third embodiment of the present invention.

FIG. 13 is a sectional view taken along line HH of the offset gate MOS transistor showing the third embodiment of the present invention.

FIG. 14 is a top view of an offset gate MOS transistor showing a fourth embodiment of the present invention.

FIG. 15 is a cross-sectional view taken along line I-I of an offset gate MOS transistor showing a fourth embodiment of the present invention.

[Explanation of symbols]

21 N-type semiconductor Si substrate 22 Offset diffusion layer 23 Oxide film 24 Gate oxide film 24a First gate oxide film 24b Second gate oxide film 25 Gate electrode 25a First gate electrode 25b Second gate electrode 26 Source / drain Diffusion layer 28 Channel stopper diffusion layer (N ⁺ high concentration diffusion layer) 29, 31 Wiring metal 30 Contact

Claims (4)

[Claims] 1. A pair of second-conductivity-type source / drain diffusion layers facing each other on a first-conductivity-type semiconductor substrate.
(B) an offset diffusion layer having a lower concentration than the source / drain diffusion layer of the second conductivity type around the source / drain diffusion layer, and (c) a first surrounding the periphery of the offset diffusion layer with a certain distance from the offset diffusion layer. A conductive type channel stopper diffusion layer, (d) a gate region composed of a gate insulating film and a gate electrode sandwiched between opposed offset diffusion layers, (e) the source / drain diffusion layer, the channel stopper diffusion layer, and the A gate region including a gate oxide film and a gate electrode in the entire region contacting the offset diffusion layer having a second insulating film thicker than the gate insulating film in the region excluding the gate region and the portion opposite to the channel stopper diffusion layer. And a second insulating film thicker than the gate insulating film in all of the offset diffusion layer portion. Set gate MOS transistor. 2. The offset gate MOS according to claim 1.
In a transistor, a gate region composed of the gate insulating film and a gate electrode sandwiched between opposing offset layers, and a gate insulating film and a gate electrode in contact with the offset diffusion layer in the opposing portion of the offset diffusion layer and the channel stopper diffusion layer. An offset gate MOS transistor in which the gate electrode of the gate region is separated and the latter gate electrode is connected by a wiring metal so as to have the same potential as the channel stopper diffusion layer. 3. The offset gate MOS according to claim 1.
In the transistor, a part of a gate electrode of a gate region formed of a gate oxide film and a gate electrode in a region in contact with the offset diffusion layer in a portion facing the offset diffusion layer and the channel stopper diffusion layer is separated, and the drain diffusion is performed in the region. Offset gate MOS transistor in which layer wiring metal is arranged. 4. The offset gate MOS according to claim 2.
In the transistor, the thickness of the gate insulating film of each of the separated gate electrodes is set such that the offset diffusion layer and the channel stopper diffusion are larger than the gate region formed by the gate insulating film and the gate electrode sandwiched between the offset diffusion layers facing each other. An offset gate MOS transistor having a thinned gate region consisting of a gate oxide film and a gate electrode in contact with an offset diffusion layer in a facing portion of the layer.