JPH0770714B2 - High voltage semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A high withstand voltage semiconductor device having a large driving capability, a small leak current, and a structure suitable for shortening the channel, and an extremely simple modification to the structure. Therefore, the source resistance is small, the generation of a leak path between the drain and the source is prevented, and the leak current is suppressed regardless of the impurity concentration of the semiconductor substrate. A channel stopper region formed so as to cover the lower surface of the insulating film and having an edge reaching the surface of the semiconductor substrate, and an edge of the channel stopper region inside the opening in the field insulating film and overlapping with the gate. Of the channel stopper region inside the opening in the field insulating film and the source region formed without being offset. A drain region formed at a distance from the edge and offset from the gate, and a threshold of the channel region formed by introducing impurities so that both ends in the gate width direction reach near the edge of the channel stopper region. And an impurity introduction region for adjusting the voltage.

[Industrial application field]

The present invention relates to a high breakdown voltage semiconductor device having a large driving capability, a small leak current, and a structure suitable for shortening a channel.

[Conventional technology]

9 to 11 are views for explaining a conventional example of a high breakdown voltage semiconductor device. FIG. 9 is a plan view of an essential part, and FIG. 10 is an essential part taken along the line YY of FIG. FIG. 11 is a sectional side view, and FIG. 11 is a sectional side view taken along the line XX of FIG.

In the figure, 1 is a p ^- type silicon semiconductor substrate, 2 is a p-type channel stopper region, 3 is a field insulating film made of silicon dioxide, 4 is a gate insulating film made of silicon dioxide, and 5 is made of polycrystalline silicon. Gate electrode, 6 is n ⁺
A type source region, 7 is an n ⁺ type drain region, 7A is an n ⁻ type drain region, 8 is a wiring, and LK is a leak path.

As is apparent from the drawing, in this conventional example, the transistor regions such as the source region 6 and the drain region 7 are defined by the openings formed in the field insulating film 3, and the channel stopper region 2 is formed by the field insulating film. A thick arrow is formed between the channel stopper region 2 and the edge of the field insulating film 3 which is formed at a position further away from the transistor region than the edge of the film 3 and defines the drain region 7. They are spaced as shown.

[Problems to be solved by the invention]

In the high breakdown voltage semiconductor device described with reference to FIGS. 9 to 11, the impurity concentration of the semiconductor substrate 1 is being reduced in order to further improve the drain breakdown voltage, and it is currently 20 [Ω · cm]. Those having the above high resistance are being used.

However, it is known that such a high resistance type has a large leak current. The reason is that, as described above, there is a space between the channel stopper region 2 and the edge of the field insulating film 3 as shown by the thick arrow in FIGS. 10 and 11. That is, the vacant portion is the p ⁻ type semiconductor substrate 1 itself, that portion is a so-called weak inversion region (depletion-like), and the region indicated by a broken line circle in FIG. 9 is in that state, Leakage from drain region 7 to source region 6
The path LK will be generated. It should be noted that such a phenomenon also occurs on the opposite side of the region indicated by the broken line circle.

In order to reduce the leakage current flowing through such a leakage path LK, although it can be achieved by forming a channel stopper region extending from the source side to a part below the gate, it is possible to shorten the channel. It will be impossible at all.

The present invention prevents the generation of a leak path between the drain and source by suppressing the leak current regardless of the impurity concentration of the semiconductor substrate by making a very simple modification to the structure. .

[Means for solving problems]

1 to 3 are views of a semiconductor device for explaining the principle of the present invention. FIG. 1 is a plan view of an essential part, and FIG. 2 is an essential part taken along the line YY of FIG. FIG. 9 is a sectional side view, and FIG. 3 is a sectional side view of an essential part taken along line XX in FIG.
The same symbols as those used in FIGS. 11 to 11 represent the same parts or have the same meanings.

The semiconductor device of the present invention shown in FIG. 1 to FIG.
Differences from the conventional example described with reference to FIGS. 11 to 11 are: (1) The channel stopper region 2 is a field insulating film 3;
(2) The transistor region such as the drain region 7 is formed inside the opening formed in the field insulating film 3, and at least the drain regions 7 and 7A of the transistor region and the field insulating film are formed. The edge of 3 is that there is a space as indicated by the arrow A1 in the figure, and (3) the edges of the channel stopper region 2 and the source region 6 are overlapped.

Due to the structure of the semiconductor device shown in FIGS. 1 to 3, the surface of the semiconductor substrate 1 in the vicinity immediately below the gate between the channel stopper region 2 and the drain region 7, that is,
Since a process of introducing impurities for adjusting the threshold voltage V _th is necessarily taken in a portion corresponding to the vicinity of the broken line circle shown in FIG. 9, that portion is the semiconductor substrate 1 of p ⁻
It is not in its own state, so it is not a weak inversion area, and the leak path seen in Fig. 9
LK is never generated.

Therefore, in the high breakdown voltage semiconductor device of the present invention,
A channel stopper region (for example, p-type channel stopper region 2) which is formed so as to cover the lower surface of the field insulating film (for example, field insulating film 3) and whose edge reaches the surface of the semiconductor substrate (for example, silicon semiconductor substrate 1); A source region (for example, n ⁺ type source region 6) formed inside the opening in the field insulating film so as to overlap with the edge of the channel stopper region and without offsetting with respect to the gate; A drain region (for example, n ⁺ type drain region 7) formed inside the opening at a distance from the edge of the channel stopper region and offset from the gate, and both ends in the gate width direction of the channel region. Threshold of channel region formed by introducing impurities to reach near the edge of stopper region And a impurity introduction region for adjusting the pressure.

[Action]

When the channel stopper region and the drain region are separated by adopting the above means, the withstand voltage is improved, and the impurity concentration of the semiconductor substrate is lowered to increase the withstand voltage in order to increase the drain withstand voltage. However, there is no occurrence of leak paths at both ends in the gate width direction, leak current is reduced, and the drain region is offset from the gate, but the source region is offset. Moreover, since it is made as wide as possible so that it overlaps with the channel stopper region,
The source resistance is small, and thus the large driving ability is maintained. Even if the source region is configured in this way, no problem occurs in maintaining the breakdown voltage.

〔Example〕

FIG. 4 to FIG. 8 are side sectional views of a main part of a semiconductor device in process steps for explaining a case of manufacturing an embodiment of the present invention, which will be described below with reference to these figures. To do.

See FIG. 4. (1) By applying the thermal oxidation method, the protective film 12 made of silicon dioxide and having a thickness of about 500 [Å] is formed on the surface of the p ⁻ type silicon semiconductor substrate 11.

(2) Chemical vapor deposition (CV)
By applying the method D), the mask film 13 made of silicon nitride is formed.

(3) The mask film 13 is patterned by applying a normal photolithography technique, and an opening is formed in a portion where a field insulating film is to be formed.

(4) By applying a resist process in a normal photolithography technique, a photoresist film 14 having an opening is formed in a p-channel transistor portion where an n-type well is to be formed.

(5) Phosphorus ions are implanted by applying the ion implantation method. The reason why phosphorus ions are adopted here is that the diffusion coefficient is large.

In this case, the ion implantation conditions may be selected such that the dose amount is about 3 × 10 ¹² [cm ⁻² ] and the implantation energy is about 180 [KeV]. Since the phosphorus ions penetrate the mask film 13 and the protective film 12, they are implanted into the entire surface of the portion where the photoresist film 14 does not exist, that is, the portion where the n-type well is to be formed.

See FIG. 5 (6) With the photoresist film 14 left, the arsenic ions are implanted by applying the ion implantation method. The reason why arsenic ions are used here is that the diffusion coefficient is small.

In this case, as a condition for performing the ion implantation, the dose amount may be selected to be about 8 × 10 ¹² [cm ⁻² ] and the implantation energy may be selected to be about 60 [KeV]. Since the arsenic ion does not penetrate the mask film 13, it is implanted only in the portion where the channel stopper is to be formed.

See Fig. 6 (7) Temperature 1200 after removing the photoresist film 14.
Heat treatment is performed at [° C.] for a time of 6 [hours] to activate the ions implanted in the steps (5) and (6), and the n ⁻ type well 15 and the n type channel stopper region 16 are made operable. To do.

(8) A photoresist film 17 covering the p-channel transistor portion is formed in the same manner as in the step (4).

It should be noted that the edge of the photoresist film 17 in contact with the n-channel transistor portion extends beyond the edge of the n ⁻ type well 15 to the n-channel transistor portion side. This is the p
This is to prevent the type channel stopper region from colliding with the n ⁻ type well 15, especially the n type channel stopper region 16.

(9) Boron ions are implanted by applying the ion implantation method.

In this case, the ion implantation conditions may be selected such that the dose amount is about 9 × 10 ¹³ [cm ⁻² ] and the implantation energy is about 25 [KeV]. Since boron ions do not penetrate the mask film 13, they are implanted only in the portion where the channel / stopper is to be formed.

See FIG. 7 (10) By removing the photoresist film 17, and then applying a normal selective thermal oxidation method (for example, Locos method) using the mask film 13 made of silicon nitride as an oxidation resistant mask, A field insulating film 18 made of silicon dioxide is formed. At the same time, the ions implanted in the step (9) are activated to make the p-type channel stopper region 19 operable. The thermal oxidation in this case can be carried out in an oxidizing atmosphere at a temperature of 900 ° C. for a time of 10 hours.

(11) The mask film 13 and the protective film 12 used as the oxidation resistant mask are removed. As indicated by arrow A3,
A gap is formed between the p-type channel stopper region 19 and the n-type channel stopper region 16 at the location where the n-channel transistor portion and the p-channel transistor portion are adjacent to each other.

See FIG. 8 (12) After that, an ordinary technique is applied to form an n-channel transistor portion and a p-channel transistor portion.

To exemplify the order, formation of an impurity introduction region (not shown) for adjusting the threshold voltage, formation of the gate insulating film 20,
Formation of polycrystalline silicon gate electrodes 21N and 21P, insulating film 22 made of silicon dioxide covering the gate electrodes 21N and 21P
Formation, n ^-- type drain region 23N and p ^-- type drain region 23P
Formation of the interlayer insulating film 24 made of silicon dioxide,
Formation of n ⁺ type source region 25N, n ⁺ type drain region 26N and n ⁺ type well contact region 27A, p ⁺ type source region 25P and p ⁺
The formation of the type drain region 26P and the p ⁺ type substrate contact region 27B, the formation of various electrodes, and the like.

What should be noted here is the formation of the impurity introduction region and the formation of the drain regions 26N and 26P for adjusting the threshold voltage.

In forming the impurity-introduced region, the edge in the gate width direction must reach at least the vicinity of the edge of the p-type channel stopper region 19 or the n-type channel stopper region 16 as a matter of course from the process. I have to.

Further, in forming the drain regions 26N and 26P, as indicated by an arrow A4 in FIG.
It is necessary to separate from the edge of the stopper region 19 or the edge of the n-type channel stopper region 16, and for that purpose, ion implantation may be performed using an appropriate mask.

In the complementary semiconductor device manufactured as described above, both the n-channel transistor portion and the p-channel transistor portion have high breakdown voltage, and the leakage current is significantly smaller than that of the conventional one. It has been confirmed that

〔The invention's effect〕

In the high breakdown voltage semiconductor device according to the present invention, the channel stopper region formed to cover the lower surface of the field insulating film and reaching the edge of the semiconductor substrate, and the channel stopper region inside the opening in the field insulating film are provided. The source region is formed so as to overlap the edge of the channel stopper region and not offset with respect to the gate, and is spaced apart from the edge of the channel stopper region inside the opening in the field insulating film, and the gate And a drain region formed to be offset with respect to the channel region, and an impurity introduction region for adjusting the threshold voltage of the channel region formed by introducing impurities so that both ends in the gate width direction reach near the edges of the channel stopper region. It has and.

In the case where the channel stopper region and the drain region are separated from each other by adopting the above configuration, the withstand voltage is improved, and the impurity concentration of the semiconductor substrate is lowered to increase the drain withstand voltage to increase the resistance. However, there is no occurrence of leak paths at both ends in the gate width direction, leak current is reduced, and the drain region is offset from the gate, but the source region is offset. Moreover, since it is made as wide as possible so that it overlaps with the channel stopper region,
The source resistance is small, so that a large driving capability can be maintained. Needless to say, even if the source region is configured as described above, no problem occurs in maintaining the breakdown voltage.

[Brief description of drawings]

1 is a plan view of an essential part of an embodiment of the present invention, FIG. 2 is a sectional side view of an essential part taken along the line YY of FIG. 1, and FIG. 3 is a view taken along the line XX of FIG. 4 to 8 are sectional side views of essential parts of a complementary semiconductor device, and FIG. 9 is a sectional side view of essential parts of a complementary semiconductor device in a process main part for explaining a case of manufacturing an embodiment of the present invention. FIG. 10 is a side view of a main part cut along line YY of FIG. 9, and FIG. 11 is a side view of the main part cut along line XX of FIG. Each represents. In the figure, 1 is a p ^- type silicon semiconductor substrate, 2 is a p-type channel stopper region, 3 is a field insulating film made of silicon dioxide, 4 is a gate insulating film made of silicon dioxide, and 5 is made of polycrystalline silicon. Gate electrode, 6 is n ⁺
A type source region, 7 is an n ⁺ type drain region, 7A is an n ⁻ type drain region, 8 is a wiring, and LK is a leak path.

Claims (1)

[Claims] 1. A channel stopper region formed so as to cover a lower surface of a field insulating film and having an edge reaching a surface of a semiconductor substrate, and an edge of the channel stopper region overlapping an inside of an opening in the field insulating film. And the source region formed without offset with respect to the gate, and formed with being spaced apart from the edge of the channel stopper region inside the opening in the field insulating film and offset with respect to the gate. A drain region; and an impurity introduction region for adjusting the threshold voltage of the channel region formed by introducing impurities so that both ends in the gate width direction reach the vicinity of the edge of the channel stopper region. High voltage semiconductor device.