JPH04309269A - Semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently reduce the turning-on resistance of a semiconductor device by increasing the cell density of the device. CONSTITUTION:This semiconductor device is provided with a source area 5 formed on the upper surface side of a semiconductor substrate, drain areas 1 and 2 formed on the lower surface side of the substrate, channel area 3 formed between the area 5 and areas 1 and 2, and gate electrode 7 which is buried in the substrate and induces a channel in the area 3 from at least both sides of the area 3 in the width direction through a gate insulating film 11 and the width of the channel area 3 is made narrower than that of a source contact area 12 on the surface of the semiconductor substrate.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a vertical MOSFET structure.

0002

2. Description of the Related Art Conventional semiconductor devices having a vertical MOSFET structure include those shown in FIGS. 12 and 13, for example. This semiconductor device is called a UMOS because of the shape of its gate electrode. An N-type epitaxial layer 2 is formed on an N+-type substrate 1 serving as a drain region, and a P-type channel region 17 and an N+-type source region 18 are formed on the surface thereof by diffusion of P-type and N-type impurities. Further, a part of the N-type epitaxial layer 2 is removed, and the gate electrode 19 is buried in a protruding shape with the gate oxide film 21 interposed therebetween. 13 is an interlayer insulating film, and 14 is a source electrode, which is connected to the source region 18 and channel region 17 via a contact hole 22 and a channel contact region 23. Further, a drain electrode 16 is formed on the back surface of the N+ type substrate 1. Note that, for ease of viewing, the interlayer insulating film and source electrode are not shown in the plan view of FIG.

In the vertical MOSFET, a positive drain voltage is applied to the drain electrode 16 and the gate electrode 19
When a gate voltage exceeding the threshold is applied to the channel region 17, a channel is induced in the vertical direction in the drain region (
The N+ type substrate 1, the N type epitaxial layer 2), and the source region 18 are electrically connected to be in an on state. At this time, in order to suppress heat generation, it is necessary to reduce the on-resistance.
To achieve this, it is sufficient to increase the density of the source region 18, that is, the cell density, which is determined by design rules. To explain this using the plan view of FIG. 12, the minimum rule is the size of the channel contact region 23, and by forming the contact hole 22 slightly larger than that (a value determined by process errors such as mask alignment accuracy), the maximum density can be achieved. This allows the source region 18 to be integrated.

0004

[Problems to be Solved by the Invention] Conventional semiconductor devices with a vertical MOSFET structure have a structure in which the potential of the channel region must be fixed in order to suppress parasitic bipolar operation and determine operating conditions. A channel contact region for fixing channel potential was provided on the substrate surface, and electrodes were taken out from the substrate surface. Therefore, in order to increase cell density, the channel contact region must be designed using minimum rules. However, since the area of one cell requires consideration of two photolithography processes: forming a channel contact region and forming a source contact hole, there is a limit to miniaturization of the cell size. The problem was that it was difficult to create resistance.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can increase cell density and have sufficiently low on-resistance.

[0006]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a source region formed on the surface side of a semiconductor substrate, a drain region formed inside or on the bottom side of the semiconductor substrate, and a drain region formed on the inside or bottom side of the semiconductor substrate. A channel region formed between a source region and a drain region; The present invention is directed to a semiconductor device having a gate electrode that induces , the width of a channel region between the gate electrodes being narrower than the width of a source contact region on the surface of the semiconductor substrate.

[0007]

[Operation] The width of the channel region sandwiched between the gate electrodes from both sides in the width direction via the gate insulating film is formed to be narrower than the width of the source contact region. For this reason,
The potential of the channel region is determined by the combination of the source potential, gate potential, and drain potential, eliminating the need to provide a channel contact region on the substrate surface. Therefore, it is possible to increase cell density and achieve sufficiently low on-resistance.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIGS. 1 to 6 are diagrams showing a first embodiment of the present invention.

Note that in FIGS. 1, 2, etc. and figures showing each embodiment described later, the same or equivalent members as those in FIG. Omitted.

First, the structure of the semiconductor device will be explained using FIGS. 1 and 2. A P type channel region 3 and an N + type source region 5 are formed in the N type epitaxial layer 2 by diffusion of P type impurities and N type impurities. Further, a part of the N-type epitaxial layer 2 is removed, and the gate electrode 7 is buried in a protruding shape with a gate oxide film 11 serving as a gate insulating film interposed therebetween. The channel region 3 is made sufficiently thin (0.01 μm to 1 μm) in the narrowest part between the gate electrodes 7.
m). Further, the source region 5 is formed to extend upward from the channel region 3. In this way, since the channel region 3 is sufficiently thinned, the potential of the channel region 3 is determined by the combination of the source potential, gate potential, and drain potential. For this reason,
In this embodiment, there is no channel contact region for fixing the channel potential on the substrate surface, and the source electrode 14 is connected only to the source region 5 via a contact hole (source contact region) 12. If the same design rules as the conventional one are used, the contact hole 12 is formed to be smaller due to the absence of the channel contact region, but the width of the channel region 3 is formed to be even narrower than the width of the contact hole 12. ing. Note that, for ease of viewing, the interlayer insulating film and the source electrode are not shown in the plan view of FIG.

Next, the structure will be explained in further detail by explaining an example of the manufacturing process using FIGS. 3 and 4.

(a) An epitaxial silicon substrate in which an N type epitaxial layer 2 is formed on a heavily doped N + type substrate 1 is doped with P type impurities and a high concentration N type impurity from the surface to form a channel. A P-type layer that will become region 3 and an N+ layer that will become source region 5 are formed (FIG. 3(a))
.

(b) An oxide film is formed on the surface of the substrate by a method such as thermal oxidation, and the portion other than the portion that will become the source contact region is removed by photoetching to form a mask oxide film 24 that will serve as a mask for the next step (see FIG. 3(b)).

(c) RIE using the mask oxide film 24 as a mask
The epitaxial silicon substrate is etched using a method such as reactive ion etching, and trenches 25 are etched.
form. Thereafter, a mask insulating film 26 is formed on the bottom surface of the trench 25 by, for example, oxygen ion implantation. The mask insulating film 26 is used to prevent the bottom of the gate electrode from becoming sharp due to etching in the next step and from deteriorating the gate breakdown voltage due to electric field concentration. However, depending on the usage conditions of this device, the mask insulating film 26 can be omitted (FIG. 3(c)).

(d) A gate forming hole 27 is formed by performing anisotropic etching of silicon using an alkaline etching solution. As a result, a thin layer (0.01 μm ~
A channel region 3 with a thickness of about 1 μm) is formed, and the shape of a source region 5 is adjusted (FIG. 4(a)).

(e) Gate oxide film 11 is formed on the surfaces of source region 5, channel region 3, and N-type epitaxial layer 2 by, for example, thermal oxidation. After that, polycrystalline silicon is filled into the gate formation hole 27 by low pressure CVD method or the like.
By using etchback technology, the gate electrode 7
(Fig. 4(b)).

(f) After oxidizing the surface of the gate electrode 7,
For example, an interlayer insulating film 13 such as PSG is formed by CVD method,
Thereafter, the source contact region is photo-etched to form a contact hole 12. Finally, the source electrode 14
is formed to complete the semiconductor device shown in the cross-sectional view of FIG. Note that after this, a final protective film forming step is performed, but it is not shown (FIG. 4(c)).

Next, the operation of the semiconductor device constructed as described above will be explained.

A major feature of the semiconductor device structure of this embodiment is that the channel region 3 is thinned;
is sandwiched between gate electrodes 7 from both sides. Therefore, the operating conditions of the device are determined by the combination of the source potential, gate potential, and drain potential without taking the channel potential from the substrate surface, and parasitic effects can also be suppressed.

Now, this can be expressed as the relationship between the maximum width of the depletion region and the substrate impurity concentration in FIG.
Further explanation will be given with reference to "Fundamentals of Semiconductor Devices" (McGraw-Hill Publishing). In the cross-sectional view of FIG. 2, in order to bring the channel region 3 into a completely depleted state by controlling the potential of the gate electrodes 7 on both sides of the channel region 3, the channel region 3
Since the depletion layer spreads from both left and right sides thereof, the thickness may be less than twice the maximum width Xdmax of the depletion region shown in FIG. For example, the impurity concentration of the channel region 3 is set to 1×1.
016cm-3, its width is approximately 0.3×2=0
．． If the thickness is 6 μm or less, the channel region 3 can become completely depleted, and the above-mentioned effect will appear.

As described above, the semiconductor device of this embodiment has the following features:
Since there is no need to provide a channel contact region on the substrate surface, the cell integration density is greatly improved. Below, Figure 5
This will be explained using specific numerical examples using FIG. 6, which is a comparative example. Now, considering that a design rule of 1 .mu.m is used, in this embodiment, as can be seen from FIG. 5, an area of 4.times.4 .mu.m.sup.2 is sufficient for each unit cell. On the other hand, in the comparative example (conventional example), as can be seen from FIG.
m2 area is required, and in this embodiment, the cell integration density is improved by 2.25 times. this is,
Considering the on-resistance, this shows that the on-resistance per unit chip area is 1/2.25, which means that the heat generation of the device is suppressed by that much.

Next, FIGS. 7 and 8 show the second embodiment of the present invention.
An example is shown.

In this embodiment, an electrochemical etch stop technique is used to thin the channel region, so that the thin channel region can be formed with good controllability.

An example of the manufacturing process will be described below with reference to FIGS. 7 and 8.

(a) An N+ buried layer 32 is formed on a P-type silicon substrate 31, and an N-type epitaxial layer 2 is formed thereon. After doping the surface of the N-type epitaxial layer 2 with P-type impurities to form a P-type layer that will become the channel region 3, a mask oxide film 2 that will become a mask for trench etching is formed.
form 4. The above-mentioned N+ buried layer 32 is formed to take out the drain terminal from the surface, and is a method often used in vertical bipolar transistors, power MOSFETs, etc. (FIG. 7(a)).

(b) RIE using the mask oxide film 24 as a mask
A trench 25 is formed by etching the substrate by a method such as a method. Thereafter, a mask insulating film 26 is formed on the bottom surface of the trench 25 by, for example, oxygen ion implantation. The mask insulating film 26 is used to prevent a high concentration diffusion layer from being formed at the bottom of the trench in the next step, and also to prevent an increase in drain resistance due to thinning of the drain part.
Figure 7(b)).

(c) A P-type diffusion region 28 is formed by doping P-type impurities from the sides of the trench 25 at a high concentration. Here, it is important to set the diffusion depth of the P-type diffusion region 28 to such an extent that the P-type impurity is diffused from the trenches 25 on both adjacent sides, leaving a channel region (FIG. 7(c)).

(d) By electrolytically etching silicon using an HF (hydrofluoric acid) type etching solution, only the P type diffusion region 28 is selectively removed, and a gate forming hole 29 is formed. As a result, a thin layer (about 0.01 μm to 1 μm)
A channel region 3 is formed (FIG. 8(a)).

(e) For example, by thermal oxidation, the portion that will become the source region, the channel region 3, and the N-type epitaxial layer 2 are removed.
After forming a gate oxide film 11 on the surface, polycrystalline silicon is filled in the gate formation hole 29 by low pressure CVD method or the like, and the gate electrode 8 is formed by using an etch-back technique in combination. Thereafter, the source region 5 is formed by doping N-type impurities from the surface at a high concentration (FIG. 8(b)).

(f) After oxidizing the surface of the gate electrode 8,
For example, an interlayer insulating film 13 such as PSG is formed by CVD method,
Thereafter, the source contact region is photo-etched to form a contact hole 12. Note that after this, a source electrode forming step and a final protective film forming step are performed, but they are not shown (FIG. 8(c)).

FIGS. 9 and 10 show a third embodiment of the present invention.

In this embodiment, the size of the cell is reduced to the final dimension of photolithography by using a method of forming a source electrode without opening a source contact hole for each cell. This embodiment is effective when the accuracy of photolithography is smaller than the critical channel width explained using FIG. 11 above. In FIG. 9, 4 is a channel region, 6 is a source region, 3
3 is an interlayer insulating film, and the source electrode 15 is connected to the source region 6 without making a contact hole. Then, the N+ type substrate 1 becomes the drain region and the vertical MO
A semiconductor device having an SFET structure is configured. Note that a signal is supplied to the gate electrode 9 via the gate contact 35.

The operation is almost the same as that of the first embodiment.

Next, an example of the manufacturing process will be explained using FIG. 10.

(a) An epitaxial silicon substrate on which an N type epitaxial layer 2 is formed on an N + type substrate 1 is coated with a P layer.
By diffusing type and N type impurities, a P type layer which will become the channel region 4 and an N+ layer which will become the source region 6 are formed (Fig. 1
0(a)).

(b) An oxide film is formed by the CVD method, and holes are opened in areas other than the cell portion by photolithography to form a trench etch protection film 34. Thereafter, a silicon trench is etched using a technique such as RIE, and a gate oxide film 11 is formed on the bottom and side surfaces of the silicon trench by, for example, thermal oxidation (FIG. 10(b)).

(c) Polycrystalline silicon doped with low resistance impurities is deposited on the entire surface, and the polycrystalline silicon is left in a part of the trench by an etch-back method to form the gate electrode 9. Thereafter, an interlayer insulating film 33 is formed over the trench by a spin-on method or the like (FIG. 10(c)).

(d) Finally, a source electrode 15 is formed on the entire upper surface of the cell portion by metal sputtering or the like (see FIG. 10(d)
)).

In the first to third embodiments described above, the channel region is P type, but even if it is N type or I type (semi-insulating), the channel will not be completely formed due to the work function difference with the gate electrode. Since this is a depletion, the off-state characteristics can be realized without any problem.

[0041]

As described above, according to the present invention, the width of the channel region sandwiched between the gate electrodes from both sides via the gate insulating film is narrower than the width of the source contact region on the substrate surface. Since the layer is formed thinner, the potential of the channel region is determined by the combination of the source potential, gate potential, and drain potential, and there is no need to provide a channel contact region on the substrate surface. Therefore, it is possible to increase the cell density and achieve sufficiently low on-resistance.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is a sectional view taken along the line AA in FIG. 1;

FIG. 3 is a process diagram showing an example of the manufacturing process of the first embodiment.

FIG. 4 is a process diagram showing an example of the manufacturing process of the first embodiment.

FIG. 5 is a diagram for explaining the use of the first embodiment.

FIG. 6 is a diagram showing a comparative example of FIG. 5;

FIG. 7 is a diagram showing an example of a manufacturing process of a second embodiment of the present invention.

FIG. 8 is a diagram showing an example of a manufacturing process of a second embodiment of the present invention.

FIG. 9 is a plan view and a sectional view showing a third embodiment of the invention.

FIG. 10 is a diagram showing an example of the manufacturing process of the third embodiment.

FIG. 11 is a diagram showing the relationship between the maximum width of a depletion region and the substrate impurity concentration.

FIG. 12 is a plan view of a conventional semiconductor device.

13 is a cross-sectional view taken along the line AA in FIG. 12. FIG.

[Explanation of symbols]

1 N+ type substrate 2 serving as a drain region N type epitaxial layers 3, 4 Channel regions 5, 6 Source regions 7, 8, 9 Gate electrode 11 Gate oxide film (gate insulating film) 12 Contact hole (source contact region) 14, 15 source electrode

Claims (1)

[Claims] 1. A source region formed on the surface side of a semiconductor substrate, a drain region formed inside or on the bottom side of the semiconductor substrate, and a channel region formed between the source region and the drain region. , a semiconductor device having a gate electrode embedded in the semiconductor substrate and inducing a channel in the channel region in the depth direction of the semiconductor substrate from at least both sides of the channel region via a gate insulating film, A semiconductor device characterized in that the width of a channel region between gate electrodes is narrower than the width of a source contact region on the surface of the semiconductor substrate.