JPH10112545A - High avalanche breakdown strength mosfet and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an MOSFET of high avalanche breakdown strength. SOLUTION: A breakdown voltage of a tubular junction part 92 of a channel region 63 of a double diffusion longitudinal MOSFET is made at most a breakdown voltage of a spherical junction part 91. When a p-n junction breaks down by reverse electromotive force of inductive load, the tubular junction part 92 of a large area breaks down and avalanche current flows in the part, thus improving breakdown strength. It is desirable to provide an avalanche breakdown induced layer 58 which has the same conductivity type as a drain region and high impurity concentration between opposite sides of the channel diffusion layer 63 for keeping breakdown strength of the tubular junction part 92 low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the technical field of power MOSFETs, and more particularly to a power MOSFET for driving an inductive load.
The present invention relates to a technology for improving avalanche resistance of ET.

[0002]

2. Description of the Related Art MO is one of the insulated gate semiconductor devices.
SFETs have the advantages of being able to be driven with low power, capable of high-speed switching operation, and having higher breakdown strength against inductive loads than bipolar transistors. It is used in many devices that require high breakdown voltage.

[0003] A circuit for measuring the avalanche breakdown withstand capability of such a power MOSFET is shown by reference numeral 200 in FIG.

The measuring circuit 200 has an n-channel power
This is a circuit for measuring the avalanche breakdown withstand capability of the MOSFET 202. One end of an inductive load 205 is connected to the drain terminal of the n-channel power MOSFET 202, and a DC power supply 204 is connected between the other end and the source terminal. A pulse power supply 206 is connected between the source terminals via a resistor 207.

When the DC power supply 204 is operated, a DC voltage is applied between the drain terminal and the source terminal, and the pulse power supply 206 is started in that state, and a positive voltage is applied to the gate terminal, the n-channel power MOSFET 202 is turned on. become.

[0006] Connect a voltmeter and ammeter (not shown) to the drain terminal of n-channel power MOSFET 202, the drain voltage V _D and the drain current (the current flowing through the inductive load 205)
When the _ID is measured, the operating state of the MOSFET 202 is shown in FIG.
The result is as shown in FIG. V _G is the gate voltage.

When the MOSFET 202 is in the OFF state, the drain voltage V _D is the voltage of the DC power supply 204, and when the state changes from the OFF state to the ON state, the voltage drops to the conduction voltage of the MOSFET 202. After the ON state, the drain current _ID gradually increases. When the drain current I _D increases to rated current, when the gate voltage V _G is zero (V), a MOSFET
T202 changes from the ON state to the OFF state.

At this time, a large back electromotive force is generated in the inductive load 205, a reverse bias voltage is applied between the drain and the source, the drain voltage V _D greatly exceeds the voltage of the DC power supply 204, and the Avalanche current flows through

[0009] The MOSFET202 is a diffusion structure as shown in FIG. (C), N of the silicon substrate 221 ^- drain region 222 is formed by the shape silicon single crystal layer. The MOSFET 202 has a p ^{+ type} main diffusion region 22.
4 and p ⁻ -type channel diffusion layer 225 and main diffusion region 22.
4 and n diffused from the surface of the channel diffusion layer 225.
^{A + -type} source diffusion layer 226, and a gate insulating film 231, a gate electrode film 232, an interlayer insulating film 233, and a source electrode film 234 are formed on the surface thereof in this order.
The drain electrode film 235 is formed on the back surface.

In MOSFET 202, source diffusion layer 226 and main diffusion layer 224 are short-circuited by source electrode film 234, and channel diffusion layer 225 is electrically conductive with source electrode film 234 via main diffusion region 224. It is configured to be placed on the order.

Since the breakdown voltage of the pn junction formed by the N ⁻ layer of the silicon substrate 221 serving as the drain region and the channel diffusion layer 225 is low, the MOSFET 202 changes from the ON state to the OFF state.
Then, when a high voltage is applied, the pn junction breaks down and the avalanche current 230 changes to the channel diffusion layer 225.
Flowing inside.

Since source diffusion layer 226 is diffused above channel diffusion layer 225, avalanche current 230
Flows through the channel diffusion layer 225, the dive resistance 2 sandwiched between the source diffusion layer 226 and the drain region 222.
Although it passes through the portion 40, the resistance value of the dive resistor 240 is large, so that the potential difference between the end of the channel diffusion layer 225 and the source electrode 234 tends to increase due to the flow of the avalanche current 230.

On the other hand, in this MOSFET 202, a parasitic NP having a drain region 222 as a collector, a channel diffusion layer 225 as a base, and a source diffusion layer 226 as an emitter.
Although the N transistor 241 is formed, the potential difference between the channel diffusion layer 225 and the source electrode 234 caused by the flow of the avalanche current 230 is caused by the parasitic NPN.
This is a polarity for forward biasing between the base and the emitter of the transistor 241. When the potential difference becomes large enough to allow the base current to flow, the parasitic NPN transistor 241
N.

The parasitic NPN transistor 241 is turned on
When the collector current flows, the drain region 22
2, a large current instantaneously flows into the source diffusion layer 226.

A power MOSFET generally has a rectangular cell 228 formed of a main diffusion layer 224 and a channel diffusion layer 225 as shown in FIG. The parasitic NPN transistor 241 is formed over the entire periphery of the channel diffusion layer 225 of each cell 228.

In this case, each channel diffusion layer 225 is formed by diffusion from a rectangular window, and a pn junction formed with the drain region 222 is formed at four corners 241 of each cell 228 when viewed from the cross section. It becomes a spherical joint,
The four sides 242 form a cylindrical joint.

Since the breakdown voltage of the spherical junction of the pn junction is lower than that of the cylindrical junction, the MOSFET 2
When 02 changes from ON to OFF, the spherical junction breaks down, and an avalanche current flows in that portion. for that reason,
The four corners of the parasitic NPN transistor 241 are turned on, and current flows intensively at the spherical junction, and the four corners 241 are destroyed.

[0018]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and has as its object to provide a MOSFET having a high avalanche breakdown resistance.

[0019]

According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor substrate and a drain region formed of the semiconductor substrate, wherein the conductive region is different from the drain region. The main diffusion layer is diffused in an island shape apart from the semiconductor substrate surface, the channel diffusion layer of the same conductivity type as the main diffusion layer is diffused around each of the main diffusion layers, and the drain region and A source diffusion layer of the same conductivity type is diffused from each of the main diffusion layers and each of the channel diffusion layers, and a voltage is applied to a gate electrode film provided on the channel diffusion layer, and the surface of each of the channel diffusion layers is reduced. A MOSFET configured to allow a current to flow between the drain region and each of the source diffusion layers when inverted, and a cylindrical pn junction formed by the channel diffusion layer and the drain region. Breakdown voltage of the engagement portion, characterized in that it is in the following breakdown voltage of the spherical junction.

On the other hand, the invention according to claim 2 has a semiconductor substrate and a drain region formed of the semiconductor substrate, and a main diffusion layer of a conductivity type different from that of the drain region is formed from the surface of the semiconductor substrate. Channel diffusion layers of the same conductivity type as the main diffusion layer are diffused around each of the main diffusion layers, and the source diffusion layers of the same conductivity type as the drain region are each of the main diffusion layers. When a voltage is applied to the diffusion layer and the gate electrode film provided on the channel diffusion layer, which is diffused from the surface of each channel diffusion layer, and the surface of the channel diffusion layer is inverted, the drain region and each of the source diffusion layers Was configured to allow current to flow between
In a MOSFET, a drain region between a cylindrical junction portion of a pn junction formed by each of the channel diffusion layers and the drain region has the same conductivity type as that of the drain region and has a lower impurity concentration than the drain region. A high avalanche breakdown inducing layer is provided.

When the MOSFET has such a structure, the breakdown voltage at the cylindrical junction of the pn junction formed by the channel diffusion layer and the drain region can be reduced.

In that case, as in the third aspect of the present invention,
It is effective to make the surface concentration of the avalanche breakdown inducing layer 10 times or more the concentration of the drain region.

Further, in the case where the diffusion depth of the avalanche breakdown inducing layer is set at a position where the impurity concentration is reduced to twice the impurity concentration of the drain region, according to any one of claims 2 and 3, As for the MOSFET, it is effective to set the diffusion depth to 2.5 × 10 ⁻⁶ m or more as in the invention described in claim 4.

In the case of manufacturing the MOSFET according to any one of claims 2 to 4, the gate electrode film is formed and then patterned to form the avalanche. Exposing the surface of the semiconductor substrate on which a breakdown inducing layer is to be formed, the surface of the main diffusion layer, and the semiconductor substrate around the main diffusion layer, and then forming and patterning a resist film to form the avalanche breakdown inducing layer It is preferable to remove the resist film on the region where the film is to be formed and the resist film around the region, implant impurities using the resist film and the gate electrode film as a mask, and form the avalanche breakdown inducing layer.

According to the configuration of the present invention described above, when a MOSFET is formed using a semiconductor substrate as a drain region, a main diffusion layer of a conductivity type different from the drain region and a channel diffusion layer of the same conductivity type as the main diffusion layer. And, a source diffusion layer of the same conductivity type as the drain region is diffused from the surface of the semiconductor substrate, and when a voltage is applied to a gate electrode provided on the channel diffusion layer to invert the surface of the channel diffusion layer, A current can flow between the drain region and the source diffusion layer.

When the load connected to this MOSFET is inductive, the pn generated by the drain region and the channel diffusion layer is generated by the electromotive force generated in the inductive load when the MOSFET changes from the ON state to the OFF state. The junction causes avalanche breakdown, causing an avalanche current to flow through the MOSFET in the OFF state.

Generally, a main diffusion layer of a power MOSFET is diffused from a rectangular window, and a plurality of power diffusion layers are independently arranged in an island shape in a semiconductor substrate.
It is provided in contact with each main diffusion layer and has a substantially constant width around the main diffusion layer.

Therefore, the pn junction formed by the channel diffusion layer and the drain region is a cylindrical junction at the side and a spherical junction at the corner. When the breakdown voltage of the pn junction formed by the same diffusion layer is compared, the breakdown voltage of the spherical junction of the pn junction is lower than the breakdown voltage of the cylindrical junction. Therefore, the avalanche current is generated by the electromotive force of the inductive load. , The breakdown of the pn junction occurs intensively at the spherical junction, and the current flows intensively at that portion, and the four corners of the channel region are destroyed.

In the MOSFET of the present invention, the breakdown voltage of the cylindrical junction of the pn junction formed by the channel diffusion layer and the drain region is set to a voltage lower than the breakdown voltage of the spherical junction, and therefore the spherical junction Avalanche breakdown occurs in the cylindrical joint portion having a larger area than that of the above, and current flows through the portion, thereby improving the breakdown strength of the MOSFET.

In order to make the breakdown voltage of the cylindrical junction lower than the breakdown voltage of the spherical junction, for example, between the cylindrical junction of each cell in the drain region, the same conductivity type as the drain region is used. The avalanche breakdown inducing layer having an impurity concentration higher than that of the drain region can be provided.
In this case, if the avalanche breakdown inducing layer is not provided between the spherical junctions of the drain region, the expansion of the depletion layer at the cylindrical junction is suppressed, and the breakdown voltage at that portion is reduced.

This will be described with reference to FIGS. 7A and 7B. As shown in FIG. 7A, an avalanche breakdown inducing layer is provided in a drain region between cylindrical junctions formed by a channel diffusion layer. when provided, a reverse bias voltage is applied to the pn junction formed by the channel diffusion layer and the drain region, when the depletion layer spreads, the depletion layer towards the avalanche breakdown inducing layer, cell a ₁ and cell While extending from a ₂ Metropolitan drain regions, pleasure will not extend the avalanche breakdown induced layer increases the electric field intensity of that portion, it becomes prone to avalanche breakdown, the breakdown voltage is lowered.

On the other hand, if the avalanche breakdown inducing layer is not provided between the spherical junctions, the elongation of the depletion layer at that portion is not suppressed, and the breakdown voltage does not change.

When the avalanche breakdown inducing layer is not provided as in the prior art, as shown in FIG. 7B, the depletion layer extending into the drain region from the adjacent cells B ₁ and B ₂ , And come into contact with each other at an intermediate position of the cylindrical joint portion, and are integrally spread in the direction of the back surface of the substrate. When the depletion layers are in contact with each other, the end of the depletion layer does not exist on the surface of the drain region, and the depletion layer easily extends downward of the drain region, and the electric field intensity hardly increases on the surface of the drain region. Therefore,
Avalanche breakdown on the surface of the drain region hardly occurs.

On the other hand, since the distance between the channel diffusion layers is large between the opposing spherical junctions, even if the depletion layer at the cylindrical junction is in contact, the depletion layer is not at the spherical junction and the depletion layer is depleted on the surface of the drain region. It is in a state where the layer end exists. In this state, the electric field strength at the end of the depletion layer tends to increase, so that the breakdown voltage of the spherical junction is generally lower than the breakdown voltage of the cylindrical junction. Therefore, if the depletion layer is not in contact with the cylindrical joint portion, or if the depletion layer does not easily extend downward even if it does, the breakdown voltage of the cylindrical joint portion can be reduced.

When the junction breaks down and an avalanche current flows through the MOSFET, the current flows intensively only at the spherical junction where the breakdown occurs. In the entire MOSFET, the area of the spherical junction is smaller than the area of the cylindrical junction. Therefore, if only the spherical junction yields, avalanche breakdown is likely to occur.

On the other hand, if the breakdown voltage at the cylindrical junction is made lower than the breakdown voltage at the spherical junction, and the avalanche current flows through the cylindrical junction, the current density in the MOSFET becomes smaller, so that the avalanche The breakdown strength is improved.

In this case, it is not necessary to make the breakdown voltage of all the cylindrical joints lower than the breakdown voltage of the spherical joint. The current may be dispersed to such an extent that the avalanche current is dispersed and not destroyed.

Further, the breakdown voltage of the cylindrical junction does not have to be lower than the breakdown voltage of the spherical junction. If the breakdown voltage of the cylindrical junction is reduced to near the breakdown voltage of the spherical junction, both the spherical junction and the cylindrical junction will break down and the avalanche current flowing will be dispersed, so the MOSFET's breakdown strength Improves.

In the present invention, between the cylindrical junction of the pn junction formed by each channel diffusion layer and the drain region,
An avalanche breakdown inducing layer having a higher concentration than the drain region is provided to suppress the spread of the depletion layer on the surface of the drain region, thereby reducing the breakdown voltage at the cylindrical junction.

FIG. 9 shows the relationship between the surface concentration of the avalanche breakdown inducing layer and the avalanche breakdown voltage. The vertical axis indicates the breakdown voltage, and the horizontal axis indicates the concentration. The surface concentration of the avalanche breakdown inducing layer is represented by a magnification of the concentration of the drain region. In FIG. 9, when the position where the impurity concentration of the avalanche breakdown inducing layer is reduced to twice the impurity concentration of the drain region is defined as the diffusion depth, the diffusion depth is 2 μm and 2.5 μm.
3 shows three avalanche breakdown inducing layers of 3 μm and 3 μm.

As can be seen from this graph, the higher the surface concentration of the avalanche breakdown inducing layer is, the more effective it is. When the surface concentration is 10 times or more the drain region, the breakdown voltage at the cylindrical junction is reduced to such an extent that the avalanche current is not concentrated. Can be reduced.

The three graphs in FIG. 9 show that the distance between adjacent cylindrical joints is kept constant and the diffusion depth of the avalanche breakdown inducing layer is changed.
Since the avalanche breakdown inducing layer and the cylindrical junction are close to each other, the deeper the diffusion depth, the lower the breakdown voltage,
In this graph, it can be seen that 2.5 μm (2.5 × 10 ⁻⁶ m) or more is effective.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings together with a manufacturing process. Reference numeral 51 in FIG.
A silicon semiconductor substrate having an N ⁻ epitaxial layer deposited on an N ⁺ single crystal substrate. On the surface of the silicon substrate 51 (the N ⁻ epitaxial layer side), a primary oxide film 52 made of a silicon thermal oxide film is entirely formed (in this figure and the following figures,
A thin film such as a silicon thermal oxide film formed on the back surface is omitted).

Next, through a photolithography process and an etching process, a large number of square windows 53 are formed at predetermined positions of the primary oxide film 52 at regular intervals (FIG. 4B). Boron is implanted by ion implantation using 52 as a mask, and thermal diffusion is performed to form ap ⁺ -type main diffusion layer 54 (FIG. 3C). Next, the primary oxide film 52 is removed to expose the surface of the N ⁻ epitaxial layer (drain region) on the surface of the silicon substrate 51 and the surface of the main diffusion layer 54 (FIG. 4D).

A resist film 55 is formed on the surface, a rectangular window portion 56 is opened between opposing sides of each main diffusion layer 54 by a photolithography process, and the N ^- epitaxial layer at that portion is exposed, thereby forming a resist. Using the film 55 as a mask, phosphorus is implanted by ion implantation to form an n ⁺ -type impurity layer 57 (FIG. 2E).

After removing the resist film 55, the impurity layer 5 is removed.
7 is thermally diffused to form an avalanche breakdown inducing layer 58;
Next, a silicon oxide film is formed by thermal oxidation to form a gate insulating film 59 (FIG. 6F). The concentration of the avalanche breakdown inducing layer 58 is higher than the impurity concentration of the N ⁻ layer.

Next, a gate electrode film 60 made of a highly conductive polysilicon film is formed on the surface of the gate insulating film 59, and windows 61 and 67 are provided through a photolithographic process and an etching process. 59 and gate electrode film 6
0, and the surface of each main diffusion layer 54 and the surface of each avalanche breakdown inducing layer 58 are exposed (FIG. 4H).

The window 61 has a square shape larger than the surface of the main diffusion layer 54, and the surface 52 of the N ⁻ epitaxial layer around the main diffusion layer 54 is exposed in a square ring shape. In that state, the patterned gate electrode film 60
Is used as a mask, boron is implanted by ion implantation to expose the exposed N ⁻ epitaxial layer 5.
When p-type impurities are introduced into the two surfaces and thermal diffusion is performed, ap ⁻ -type channel diffusion layer 63 having a concentration lower than the impurity concentration of the main diffusion layers 54 is formed around each main diffusion layer 54 ( FIG.
(i)). At this time, the channel diffusion layer 63 has entered under the gate insulating film 59 by lateral diffusion.

Next, a patterned resist film 64 is formed on the surface, and the peripheral portion of each main diffusion layer 54 and the channel diffusion layer 63 are exposed by a window 65 provided in the resist film 64 (FIG. 6). (j)), phosphorus is implanted by ion implantation to form an impurity layer 66 (FIG. 9 (k)), and after removing the resist film 64, thermal diffusion is performed to form a source diffusion layer 69. The channel diffusion layer 63 is formed under the gate insulating film 59 by diffusion.
And the source diffusion layer 69 enter (FIG. 1 (l)).

Thus, the diffusion process is completed, and the drain region 72 is formed by the N ⁻ layer of the silicon substrate 51.

FIG. 5 is a plan view showing the state of FIG. 3 (l) as a sectional view taken along the line AA. The main diffusion layers 54 have the same size and are diffused from the square windows 53 arranged at equal intervals in parallel with each other, and the main diffusion layers 54 are arranged in island shapes at equal intervals.

Since the square ring-shaped exposed portion 62 of the N ^- layer is formed to have substantially the same width, the width of each channel diffusion layer 63 diffused from that portion is also substantially equal. . Therefore, the cells 80 composed of the main diffusion layers 54 and the channel diffusion layers 63 are also arranged at equal intervals in an island shape.

A gate electrode film 59 is formed between the cells 80 in a lattice pattern, and the avalanche breakdown inducing layer 5 is formed.
Reference numeral 8 is arranged at the center between the cells 80. The length of the avalanche breakdown inducing layer 58 is substantially the same as the length of one side of each cell 80.

The reason why the gate insulating film 59 and the gate electrode film 60 on the surface of each avalanche breakdown inducing layer 58 are removed is to prevent the gate input capacitance from increasing.

From the state shown in FIG.
A G film is formed on the entire surface and patterned to provide a window 69,
An interlayer insulating film 68 is formed (FIG. 3 (m)).

Window 69 provided in interlayer insulating film 68
Accordingly, the surface of the source diffusion layer 69 on the surface of the main diffusion layer 54 is compared with the surface of the main diffusion layer 54 where the source diffusion layer 69 is not formed.
When the source wiring film 70 made of an aluminum thin film is formed on the surface, the source diffusion layer 69 and the main diffusion layer 54 are short-circuited.
The SFET 2 is formed (FIG. 3 (n): the protective film on the surface of the source wiring film 70 is omitted). Note that a drain electrode film 71 made of a metal thin film is formed on the back surface.

In this MOSFET 2, the N ⁻ layer is the drain region 72, the source wiring film 70 is grounded, a positive voltage is applied to the drain electrode film 71, and a positive voltage equal to or higher than the threshold voltage is applied to the gate wiring film 60. When applied, the surface of the p ⁻ -type channel diffusion layer 63 is inverted to n ⁺ , and the drain region 72 and the source diffusion layer 69 are electrically connected, so that a current can flow.

In this MOSFET 2, as can be seen from FIG. 5, which is a plan view of FIG. 3 (l), the window portion 53 (portion of the main diffusion layer 54 into which impurities are introduced) is formed in a square shape (FIG. 1 (b)). ),
Channel diffusion layer 63 provided around each main diffusion layer 54
Are diffused from a square window 61 larger than the surface of the main diffusion layer 54. Therefore, the pn junction formed by each channel diffusion layer 63 with the drain region 72 forms a spherical junction at four corners and a cylindrical junction at four sides.

The avalanche breakdown inducing layer 58 is formed in each cell 8
The avalanche breakdown occurs as uniformly as possible at a cylindrical junction portion 92 of a pn junction formed by the channel diffusion layer 63 and the drain region 72 at the center of the cell 80, and the current concentration occurs. Not to be.

Next, another method of manufacturing a MOSFET according to the present invention will be described. In this manufacturing method, FIGS. 1A to 1D show the same steps, and the same thin films and the same diffusion layers as those in the above embodiment are denoted by the same reference numerals.

After forming the main diffusion layer 54 as shown in FIG. 1D, a gate insulating film 59 and a gate electrode film 60 are formed in this order on the exposed silicon substrate 51 (FIG. 4). (p)) Then, a photolithography step and an etching step are performed to pattern the gate insulating film 59 and the gate electrode film 60, and a window portion is formed on the surface of the N ^- epitaxial layer (drain region) between the main diffusion layers 54. 76, and
A window 77 is formed on the surface of the main diffusion layer 54 (FIG. 1 (q)).

The shape of the window 76 on the surface of the main diffusion layer 54 is as follows.
The main diffusion layer 54 has a square shape larger than that of the main diffusion layer 54.
Along with the four surfaces, the surface of the N ⁻ epitaxial layer surface indicated by reference numeral 62 is exposed. The window 76 has a rectangular shape with the longitudinal direction along each side between the opposing sides of each main diffusion layer 54.

[0063] Then, a resist film is formed over the entire surface, and patterned, the resist film formed on the window portion 77 the surface on the main diffusion layer 54 leaves, N ^- window 76 on the epitaxial layer
The resist film formed on the surface is removed. At this time, a portion of the resist film on the surface of the gate electrode film 60 forming the window portion 76 around the window portion 76 is removed.

Using the patterned resist film 75 as a mask, phosphorus is implanted by ion implantation to form an impurity layer 57 on the surface of the silicon substrate 51 (FIG. 4 (r)). At this time, in the window portion 76 on the surface of the N ⁻ epitaxial layer, the n ⁺ -type impurity layer 57 is formed using the gate electrode film 60 as a mask.

Next, after the resist film 75 is removed, thermal diffusion is performed to form the avalanche breakdown inducing layer 58 (FIG. 7 (s)). This state is the same as the state shown in FIG. 2 (h). Thereafter, boron is implanted around the main diffusion layer 54 to form a channel diffusion layer 63 by thermal diffusion (FIG. 3 (i)).
Thereafter, the MOSFET 2 is formed through the same manufacturing steps as those shown in FIG. 3 (FIG. 3 (n)).

In the MOSFET 2 described above, the main diffusion layer 54
When the cells 80 formed of and the channel diffusion layer 63 are arranged in an island shape, they are arranged in an array as shown in FIG. 5, but FIG. 3 (l) is a sectional view taken along the line BB. As in the plan view shown in FIG. 6, even in the case where the cells 80 are alternately arranged in parallel, the cells 80 are arranged at the center between the opposite sides of each cell 80.
If the avalanche breakdown inducing layer 58 is provided in parallel with each side, the breakdown voltage of the cylindrical junction portion 92 of the channel diffusion layer 63 decreases, so that the avalanche current does not concentrate and flow in the spherical junction portion 91. In addition, the breakdown strength of the MOSFET can be improved.

4 and 5, no avalanche breakdown inducing layer is provided between the spherical junctions 91 of the channel diffusion layers 63, and the spherical junctions 91 are not provided.
It is necessary to prevent the breakdown voltage from being lowered.

The avalanche breakdown inducing layer 58 described above is used.
Is formed by independently providing a step of diffusing the impurity layer 57. However, the impurity layer 57 can be diffused when a silicon thermal oxide film is formed later or when the source diffusion layer 69 is diffused. Alternatively, the step of diffusing the independent impurity layer 57 can be omitted.

[0069]

According to the present invention, current due to avalanche breakdown does not flow intensively at the spherical junction, so that the breakdown strength is high.
MOSFET can be obtained.

[Brief description of the drawings]

FIGS. 1A to 1D are diagrams for explaining an example of a manufacturing process of a MOSFET according to the present invention.

FIGS. 2 (e) to 2 (h): diagrams for explaining a subsequent manufacturing process.

FIGS. 3 (i) to 3 (n): diagrams for explaining the subsequent manufacturing steps

FIGS. 4A to 4C are diagrams for explaining a part of another manufacturing process.

FIG. 5 is a plan view of an example of the MOSFET of the present invention.

FIG. 6 is a plan view of another example of the MOSFET of the present invention.

7A is a diagram for explaining the principle of improving the breakdown strength of the MOSFET of the present invention. FIG. 7B is a diagram for explaining the reason why the MOSFET of the prior art has a low breakdown strength.

8 (a): Circuit for measuring breakdown strength of MOSFET (b): Current / voltage waveform when MOSFET having an inductive load changes from ON to OFF (c): For explaining avalanche breakdown of MOSFET Figure

FIG. 9 is a graph showing the relationship between surface concentration and avalanche breakdown voltage.

FIG. 10 is a plan view of a conventional MOSFET.

[Explanation of symbols]

2 MOSFET 51 Semiconductor substrate 54 Main diffusion layer 58 Avalanche breakdown inducing layer 60 Gate electrode film 63 Channel diffusion layer 69 Source diffusion layer 72 Drain region 91 Spherical junction Portion 92: Cylindrical joint

Claims (5)

[Claims] 1. A semiconductor device, comprising: a semiconductor substrate; and a drain region formed of the semiconductor substrate. A main diffusion layer having a conductivity type different from that of the drain region is separated from the surface of the semiconductor substrate and diffused in an island shape. A channel diffusion layer of the same conductivity type as the main diffusion layer is diffused around each of the main diffusion layers; and a source diffusion layer of the same conductivity type as the drain region is formed of the main diffusion layer and the channel diffusion layers. When a voltage is applied to the gate electrode film provided on the channel diffusion layer and is inverted from the surface, and the surface of each channel diffusion layer is inverted, a current can flow between the drain region and each of the source diffusion layers. Wherein the breakdown voltage of the cylindrical junction of the pn junction formed by the channel diffusion layer and the drain region is lower than the breakdown voltage of the spherical junction. MOSFET according to claim. 2. A semiconductor device comprising: a semiconductor substrate; and a drain region formed of the semiconductor substrate. A main diffusion layer having a conductivity type different from that of the drain region is separated from the surface of the semiconductor substrate and diffused in an island shape. A channel diffusion layer of the same conductivity type as the main diffusion layer is diffused around each of the main diffusion layers; and a source diffusion layer of the same conductivity type as the drain region is formed of the main diffusion layer and the channel diffusion layers. A voltage is applied to a gate electrode film provided on the channel diffusion layer, which is diffused from the surface, and when the surface of the channel diffusion layer is inverted, a current can flow between the drain region and each of the source diffusion layers. A MOSFET having the same conductivity type as the drain region in a drain region between a cylindrical junction of a pn junction formed by each of the channel diffusion layers and the drain region. MOSFET, wherein a high avalanche breakdown inducing layer impurity concentration than the drain region are provided. 3. The MOSFET according to claim 2, wherein a surface concentration of the avalanche breakdown inducing layer is set to be 10 times or more of a concentration of the drain region. 4. When a position where the impurity concentration of the avalanche breakdown inducing layer is reduced to twice the impurity concentration of the drain region is defined as a diffusion depth, the diffusion depth is 2.5 × 1.
4. The MOSFET according to claim 2, wherein the thickness is set to 0 ^-6 m or more. 5. The method for manufacturing a MOSFET according to claim 2, wherein the gate electrode film is formed and then patterned to form the avalanche breakdown inducing layer. Exposing the surface of the semiconductor substrate to be formed, the surface of the main diffusion layer, and the semiconductor substrate around the main diffusion layer, then forming a resist film and patterning the region to form the avalanche breakdown inducing layer Removing the resist film and the resist film surrounding the region, implanting impurities using the resist film and the gate electrode film as a mask, and forming the avalanche breakdown inducing layer. .