WO2024011880A1 - 适用于晶圆级异质异构芯粒的集成结构和集成方法 - Google Patents

适用于晶圆级异质异构芯粒的集成结构和集成方法 Download PDF

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WO2024011880A1
WO2024011880A1 PCT/CN2023/071482 CN2023071482W WO2024011880A1 WO 2024011880 A1 WO2024011880 A1 WO 2024011880A1 CN 2023071482 W CN2023071482 W CN 2023071482W WO 2024011880 A1 WO2024011880 A1 WO 2024011880A1
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wafer
heterogeneous
silicon
substrate
core particles
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English (en)
French (fr)
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李顺斌
王伟豪
张汝云
刘勤让
万智泉
沈剑良
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之江实验室
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Priority to US18/298,379 priority Critical patent/US11887964B1/en
Publication of WO2024011880A1 publication Critical patent/WO2024011880A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting

Definitions

  • the present application relates to the field of integrated circuit technology, and in particular to an integrated structure and integration method suitable for wafer-level heterogeneous core particles.
  • the SoW system is oriented to the integration scale of >50 chips on the wafer to achieve ultra-high density integration, ultra-short signal transmission distance, and super system processing performance.
  • Domain-specific SoW systems often integrate homogeneous cores, such as Cerebras WSE and Tesla Tojo, which both integrate high-performance computing units. This is due to limitations in the current patterning process of large-size wafer (wafer ⁇ 8-inch) chip manufacturing. During the wafer preparation process in the wafer factory, the mask pattern cannot be frequently replaced.
  • an integrated structure suitable for wafer-level heterogeneous core particles including sequentially connected heterogeneous core particles, a wafer substrate, and a core particle configuration substrate.
  • the heterogeneous core particles are connected to the silicon adapter board to form a standard integrated component.
  • a group of standard integrated components are then connected to a standard integrated area set on the wafer substrate.
  • the upper surface of the silicon adapter plate is provided with heterogeneous adapter plate micro-bumps for bonding heterogeneous core particles, and the lower surface of the silicon adapter plate is provided with standardized micro-bumps that match the standard integration area of the wafer substrate.
  • the micro-pads of the adapter board are used to bond the wafer substrate.
  • the micro-bumps of the adapter board and the micro-pads of the adapter board are matched and connected in the silicon adapter board.
  • the wafer substrate size is greater than or equal to 8 inches.
  • a repeated array of standardized micro-bumps is provided on the upper surface of the wafer substrate for bonding to the micro-pads of the transfer board, and the micro-bumps of the substrate are led out on the lower surface of the wafer substrate through through-silicon vias.
  • the extracted through-silicon vias are bonded to the core chip configuration substrate through ball implantation.
  • the silicon adapter board is provided with multiple rewiring layers for connecting heterogeneous core particles and/or wafer substrates; and/or, the wafer substrate is provided with Multiple rewiring layers to connect to the silicon interposer and/or die configuration substrate.
  • An integration method suitable for wafer-level heterogeneous core particles includes the following steps:
  • a through-silicon via array is set on the wafer through standard semiconductor processes. Based on the through-silicon via array, a micro-bump array is constructed on the upper surface of the wafer. The patterning process is repeated to form a repeating pattern on the wafer.
  • the standard integration area forms the wafer substrate;
  • a silicon adapter plate is prepared, wherein, through a silicon adapter plate preparation process, the prepared silicon adapter plate is provided with heterogeneous adapter plate micro-bumps on the upper surface for bonding heterogeneous core particles, and the lower surface is provided with There are standardized transfer board micro-pads that match the standard integration area of the wafer substrate and are used to bond the wafer substrate.
  • the transfer board micro-bumps and the transfer board micro-pads are matched and connected in the silicon transfer board;
  • a set of heterogeneous core particles are bonded to the surface of the silicon adapter plate to form a standard integrated component
  • the heterogeneous integrated wafer is bonded to the core particle configuration substrate to form a complete wafer-level integrated structure of heterogeneous heterogeneous core particles.
  • the through-hole backside exposure process is used to thin the lower surface of the wafer substrate using chemical mechanical polishing, and then the through-silicon via is led out from the lower surface of the wafer substrate.
  • the heterogeneous core particles are bonded to the micro-bumps of the adapter board through the micro-pads of the core particles provided on the lower surface.
  • the silicon adapter board is provided with multiple rewiring layers for connecting heterogeneous core chips and/or wafer substrates; and/or the wafer substrate is provided with multiple rewiring layers.
  • Layer redistribution layer used to connect the silicon interposer and/or die configuration substrate.
  • the heterogeneous core particles are bonded to a silicon adapter plate, and after injection molding and/or grinding and thinning, a standard integrated part is formed.
  • the upper surface of the heterogeneous integrated wafer is plastic-sealed; the through-silicon via balls extracted from the lower surface of the heterogeneous integrated wafer are used to configure the substrate to fit the core particles.
  • Figure 1 is a schematic cross-sectional view of the wafer-level heterogeneous core particle integrated structure in an embodiment of the present application.
  • Figure 2 is a schematic top view of the wafer-level heterogeneous core particle integrated structure in the embodiment of the present application.
  • Figure 3 is a flow chart of the integration method of wafer-level heterogeneous core particles in an embodiment of the present application.
  • Figure 4 is a schematic structural diagram of a silicon wafer in the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a standard integration area constructed on a silicon wafer in the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a wafer substrate in the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • Figure 7a is a schematic structural diagram of the first silicon adapter plate of the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • Figure 7b is a schematic structural diagram of the second silicon adapter plate of the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • Figure 8a is a schematic diagram of the first standard integrated component structure of the wafer-level heterogeneous core particle integration method according to the embodiment of the present application.
  • Figure 8b is a schematic diagram of the second standard integrated component structure of the wafer-level heterogeneous core particle integration method according to the embodiment of the present application.
  • Figure 9 is a schematic structural diagram of a heterogeneous integrated wafer in the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of the integration structure of wafer-level heterogeneous core particles in the integration method of wafer-level heterogeneous core particles according to the embodiment of the present application.
  • Heterogeneous heterogeneous core particles 2. Silicon adapter board, 3. Standard integrated parts, 4. Standard integrated area, 5. Through silicon vias, 6. Ball implanting, 7. Rewiring layer, 8. Core particle configuration substrate pad, 9. Core particle configuration substrate, 10. Connector, 11. Power chip, 12. Silicon wafer, 13. Wafer substrate, 14. Substrate micro-bumps, 15. Adapter board micro-welding Disk, 16. Adapter board micro-bumps, 17. Core particle micro-pad, 18a, 18b, 18c, 18d represent different types of silicon adapter boards respectively, 19a, 19b, 19c, 19d respectively represent different types of heterogeneous Heterogeneous core particles.
  • an embodiment means that a particular feature, structure or characteristic described in connection with the embodiment may be included in at least one embodiment of the application.
  • the appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by those of ordinary skill in the art that the embodiments described in this application may be combined with other embodiments without conflict.
  • An integrated structure suitable for wafer-level heterogeneous core particles includes: heterogeneous core particles 1, wafer substrate 13 and core particle configuration substrate 9 connected in sequence.
  • the pellet 1 is connected to the silicon adapter plate 2 to form a standard integrated component 3.
  • a set of standard integrated components 3 is then connected to the standard integrated area 4 provided on the wafer substrate 13.
  • the micro bumps 16 of the adapter board are connected to the micro bumps 16 of the adapter board.
  • the pads 15 are mated and connected in the silicon adapter board 2 .
  • the upper surface of the silicon adapter plate 2 is provided with heterogeneous adapter plate micro-bumps 16 for bonding heterogeneous heterogeneous core particles 1, and the lower surface of the silicon adapter plate 2 is provided with a standard integration area with the wafer substrate 13 4 matched standardized transfer board micro pads 15 for bonding the wafer substrate 13.
  • Multilayer rewiring layers 7 are filled between the bonded silicon adapter plate 2 and the heterogeneous core particles 1 , and/or between the silicon adapter plate 2 and the wafer substrate 13 .
  • the upper surface of the silicon adapter plate 2 is connected to a set of heterogeneous core particles 1, and the lower surface of the silicon adapter plate 2 is standardized and connected to the wafer substrate.
  • the surface is connected with the standard integration area 4 set up.
  • the micro-bumps 16 of the adapter plate on the upper surface of the silicon adapter plate 2 it can adapt to the integration of various heterogeneous core particles, thereby standardizing wafer preparation and forming a standard integrated part 3.
  • the adapter plate micro-pads 15 on the lower surface of the silicon adapter plate 2 can be directly integrated with various standard integrated components 3 configured with different core chips.
  • the upper surface of the silicon adapter plate 2 has heterogeneous adapter plate micro bumps 16 for bonding heterogeneous heterogeneous core particles 1; the lower surface of the silicon adapter plate 2 has adapter plate micro pads 15 and wafer substrate. Standard integration area 4 connected.
  • the micro-pads 15 of the adapter plate on the lower surface of the silicon adapter plate 2 may not completely correspond to the unified and standardized micro-bump array of the wafer substrate 13 .
  • the silicon adapter board 2 realizes the interconnection between one or more heterogeneous core particles 1 and the wafer substrate 13 through the multi-layer rewiring layer 7 .
  • heterogeneous core particles 1 of different sizes and shapes can be integrated into the wafer substrate 13 as needed; standard integrated components 3 with different functions can be formed on the wafer substrate 13.
  • 18a, 18b, 18c, and 18d respectively represent different types of silicon adapter boards, and 19a, 19b, 19c, and 19d respectively represent different types of heterogeneous core particles.
  • the silicon adapter board 2 is provided with four different types: a first silicon adapter board, a second silicon adapter board, a third silicon adapter board and a fourth silicon adapter board; According to different heterogeneous core particles 1, four different types of first heterogeneous prefabricated parts, second heterogeneous prefabricated parts, third heterogeneous prefabricated parts and fourth heterogeneous prefabricated parts are configured on the connecting plate 2.
  • the upper surface of the wafer substrate 13 is provided with a repeated array of standardized micro-bumps for bonding the micro-pads 15 of the transfer board.
  • the micro-bumps 14 of the substrate are placed on the wafer substrate 13 through through silicon vias (TSV) 5 It is extracted from the lower surface, and the extracted through silicon via 5 is bonded to the core particle configuration substrate 9 through the ball implant 6 .
  • TSV silicon vias
  • the upper surface of the wafer substrate 13 has a redistribution layer 7 (RDL) and a unified and standardized micro-bump array, forming a standard integration area 4 and connected to the standard integrated component 3; the wafer substrate 13
  • the lower surface of 13 is provided with a through silicon hole 5, and the ball implant 6 at the end of the through silicon hole 5 is connected to the core particle configuration substrate 9.
  • the wafer substrate 13 uses repeated photolithography and other patterning methods to form repeated standard integration areas 4, and the range of the standard integration areas 4 is not larger than the maximum area of one photolithography.
  • the size of the wafer substrate 13 is greater than or equal to 8 inches.
  • the wafer substrate 13 is a silicon wafer 12 with a size of 12 inches. Since the step-type photolithography of the large-size wafer-level wafer substrate 13 is difficult to achieve surface heterogeneity, the present application can enable the large-size wafer-level wafer substrate 13 to also achieve surface heterogeneity. Core particle 1 integrated.
  • the chip configuration substrate 9 is a PCB circuit board, which has functions such as chip configuration, testing, clock, power supply, and system configuration.
  • An integration method suitable for wafer-level heterogeneous core particles includes the following steps:
  • Step S1 Prepare a wafer substrate 13, in which a through-silicon via array is provided on the wafer through a standard semiconductor process. Based on the through-silicon via array, a coordinated redistribution layer 7 and a micro-bump array are constructed on the upper surface of the wafer. , repeat the patterning process to form a set of standard integration areas 4 on the wafer to form the wafer substrate 13.
  • CMP chemical mechanical polishing
  • standard semiconductor processes such as deep etching, sputtering, and electroplating are used to form a through silicon via array on the silicon wafer 12; as shown in Figure 5, standard semiconductor metal processes are used to form The surface redistribution layer 7 and the micro-bump array on the wafer repeat the patterning process to form a standard integration area 4 on the entire wafer.
  • the through silicon via 5 is passed through the rewiring layer 7 on the lower surface of the silicon wafer 12, from the silicon wafer 12.
  • the lower surface of 12 is extracted to obtain a wafer substrate 13.
  • Step S2 Prepare a silicon adapter plate 2, in which a silicon adapter plate is prepared whose upper surface is matched with a set of heterogeneous core particles 1 and whose lower surface is matched with a standard integration area 4 through a silicon adapter plate preparation process. 2.
  • the upper surface of the prepared silicon adapter plate 2 has adapter plate micro-bumps 16, which is suitable for heterogeneous core particles, and the lower surface is provided with micro-bumps 14 arranged in conjunction with the substrate.
  • the transfer board micro-pads 15, the transfer board micro-bumps 16 and the transfer board micro-pads 15 are matched and connected in the silicon transfer board 2. For example: when designing wiring lines based on chip functions, direct connection can be used for single signal transmission, or power supply signals can be combined.
  • Step S3 Bond a set of heterogeneous core particles 1 to the upper surface of the silicon adapter plate 2 to form a standard integrated component 3.
  • the heterogeneous core particles 1 are bonded to the micro-bumps 16 of the adapter plate through the core particle micro-pads 17 provided on the lower surface.
  • the rewiring layer 7 is filled around the core particle micro pads 17 and the transfer board micro bumps 16 .
  • the bonding of the heterogeneous core particles 1 and the silicon adapter plate 2 forms a standard integrated part 3 after injection molding and/or grinding and thinning.
  • the first heterogeneous core particles and the second heterogeneous core particles are bonded to the first silicon adapter plate, and then grinded and thinned after injection molding.
  • the first standard integrated part is formed;
  • the third heterogeneous core particles and the fourth heterogeneous isomeric core particles are bonded to the second silicon adapter plate, and grinded and thinned after injection molding to form the second standard integrated part.
  • Step S4 Integrate a set of standard integrated components 3 and the wafer substrate 13 through die-to-wafer (D2W) bonding to obtain a heterogeneous integrated wafer.
  • D2W die-to-wafer
  • the upper surface of the heterogeneous integrated wafer is plastic-sealed.
  • the through-silicon vias 5 drawn from the lower surface of the heterogeneous integrated wafer are ball-planted.
  • a rewiring layer 7 is provided around the ball planting 6 .
  • the first standard integrated component and the second standard integrated component are integrated with the wafer substrate 13 through D2W bonding to form a heterogeneous integrated wafer, and the front side of the integrated wafer is plastic-sealed.
  • the TSV balls drawn from the back are used to fit the core particles to configure the substrate 9 .
  • Ball planting methods include laser ball planting, etc.
  • Step S5 Bond the heterogeneous integrated wafer to the core chip configuration substrate 9 to form a complete wafer-level integrated structure of heterogeneous core chips.
  • the core chip configuration substrate pad 8 is attached to the ball mounting 6, and the bottom of the core chip configuration substrate 9 is connected to the connector 10 and the power chip 11.
  • This application uses semiconductor manufacturing and packaging technology to realize the integration of heterogeneous core particles at the wafer level, and realizes the flexible integration of heterogeneous core particles on the basis of a normalized wafer substrate.
  • the formed on-wafer system can be applied In various fields such as artificial intelligence, intelligent computing, high-performance computing, and on-chip network switching.
  • This application uses the same photolithography mask when manufacturing the wafer substrate to realize the grid units to be integrated on the wafer, solving the process problem that the mask pattern cannot be frequently replaced during the wafer preparation process in the wafer factory, thereby providing a better solution for the wafer.
  • the assembly and integration of circular-level heterogeneous core particles provides efficient and feasible technical support.
  • This application does not need to constrain the design of various types of heterogeneous core particles. It only needs to form standard integrated components through specific silicon adapter boards to realize the interconnection of various types of heterogeneous core particles.

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Abstract

一种适用于晶圆级异质异构芯粒的集成结构与集成方法。集成结构包括晶圆基板(13)、硅转接板(2)、异质异构芯粒(1)、以及芯粒配置基板(9)，异质异构芯粒(1)通过硅转接板(2)形成标准集成件(3)与晶圆基板(13)上表面相连，芯粒配置基板(9)与晶圆基板(13)下表面相连。晶圆基板(13)利用其底部硅通孔(5)与芯粒配置基板(9)连接；晶圆基板(13)顶部具有重布线层(7)和统一标准化的微凸点阵列，形成标准集成区域(4)与标准集成件(3)相连。

Description

适用于晶圆级异质异构芯粒的集成结构和集成方法
相关申请
本申请要求2022年7月12日申请的，申请号为202210812604.0，发明名称为“一种适用于晶圆级异质异构芯粒的集成结构和集成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及集成电路技术领域，尤其是涉及一种适用于晶圆级异质异构芯粒的集成结构和集成方法。
背景技术
随着集成电路产业进入到后摩尔定律时代，先进集成封装逐步成为半导体领域潮流的浪尖。领域中涌现出各式各样SoC(System on Chip系统级芯片)以及SiP(System in package系统级封装)，通过芯粒Chiplet模式，利用芯片到芯片之间die-to-die内部互联技术将多个模块芯片与底层基础芯片封装在一起，构成多功能的异构的SiP芯片模式。在2021年台积电将系统集成进一步扩展到了晶圆上，发布了InFO_SoW(Integrated Fan Out_System on Wafer)晶上系统技术，美国Cerebras以及特斯拉分别利用SoW技术发布了其晶圆级深度学习芯片WSE(Wafer scale engine)以及Tesla Tojo产品用于高性能人工智能计算系统。
不同于Chiplet集成数<10个芯粒的规模，SoW系统面向在晶圆上集成>50个的芯粒集成规模，以达到超高密度集成、超短信号传输距离、以及超强的系统处理性能。在面向领域专用的SoW系统往往集成的都是同质化芯粒，如Cerebras WSE以及Tesla Tojo均集成了高性能计算单元。这是由于受限于目前大尺寸晶圆(晶圆≥8寸)芯片制造的图形化工艺流程，在晶圆厂晶圆制备过程中，光罩图案无法频繁更换。目前针对大尺寸晶圆最大的步进式光刻尺寸为25.5×33mm 2，这使得晶圆基板制造时会形成区域的重复结构单元，难以在晶圆上实现异质异构芯粒的集成。因此，急需一种晶圆级的异质异构芯粒拼装集成，提供高效可行的技术保障的集成结构及方法。
发明内容
根据本申请的各种实施例，提供一种适用于晶圆级异质异构芯粒的集成结构，包括依 次连接的异质异构芯粒、晶圆基板以及芯粒配置基板，一组异质异构芯粒与硅转接板连接，形成的标准集成件，一组标准集成件再与晶圆基板上配合设置的标准集成区域相连。
硅转接板上表面设有异构的转接板微凸点，用于键合异质异构芯粒，硅转接板下表面设有与晶圆基板的标准集成区域相配合的标准化的转接板微焊盘，用于键合晶圆基板，转接板微凸点与转接板微焊盘在硅转接板内配合连接。
在一些实施例中，所述晶圆基板尺寸大于或等于8寸。
在一些实施例中，所述晶圆基板上表面设有重复的标准化微凸点阵列，用于键合转接板微焊盘，基板微凸点经硅通孔在晶圆基板下表面引出，引出的硅通孔通过植球与芯粒配置基板贴合。
在一些实施例中，所述硅转接板中设有多层重布线层，用于连接异质异构芯粒和/或晶圆基板；和/或，所述的晶圆基板中设有多层重布线层，用于连接硅转接板和/或芯粒配置基板。
一种适用于晶圆级异质异构芯粒的集成方法，包括如下步骤：
制备晶圆基板，其中，通过标准半导体工艺，在晶圆上设置硅通孔阵列，基于硅通孔阵列，在晶圆上表面构建微凸点阵列，重复图形化过程，在晶圆上形成重复的标准集成区域，形成晶圆基板；
制备硅转接板，其中，通过硅转接板制备工艺，制备的硅转接板上表面设有异构的转接板微凸点，用于键合异质异构芯粒，下表面设有与晶圆基板标准集成区域相配合的标准化的转接板微焊盘，用于键合晶圆基板，转接板微凸点与转接板微焊盘在硅转接板内配合连接；
将一组异质异构芯粒与硅转接板上表面键合，形成标准集成件；
将一组标准集成件与晶圆基板通过芯粒-晶圆键合方式集成，得到异质异构集成晶圆；
将异质异构集成晶圆与芯粒配置基板贴合，形成完整的晶圆级异质异构芯粒的集成结构。
在一些实施例中，在制备晶圆基板时，通过通孔背面露头工艺，利用化学机械抛光将晶圆基板下表面减薄后，使硅通孔从晶圆基板下表面引出。
在一些实施例中，异质异构芯粒，通过下表面设有的芯粒微焊盘，与转接板微凸点键合。
在一些实施例中，所述硅转接板中设有多层重布线层，用于连接异质异构芯粒和/或晶圆基板；和/或，所述晶圆基板中设有多层重布线层，用于连接硅转接板和/或芯粒配置基板。
在一些实施例中，异质异构芯粒与硅转接板键合，在注塑和/或研磨减薄后，形成标准集成件。
在一些实施例中，将异质异构集成晶圆上表面塑封；将异质异构集成晶圆下表面引出的硅通孔植球，用于贴合芯粒配置基板。
本申请的一个或多个实施例的细节在以下附图和描述中提出，以使本申请的其他特征、目的和优点更加简明易懂。
附图说明
为了更好地描述和说明这里公开的本申请的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的申请、目前描述的实施例和/或示例以及目前理解的这些申请的最佳模式中的任何一者的范围的限制。
图1为本申请实施例中晶圆级异质异构芯粒集成结构剖面示意图。
图2为本申请实施例中晶圆级异质异构芯粒集成结构俯视示意图。
图3为本申请实施例中晶圆级异质异构芯粒的集成方法流程图。
图4为本申请实施例的晶圆级异质异构芯粒的集成方法中硅晶圆的结构示意图。
图5为本申请实施例的晶圆级异质异构芯粒的集成方法中硅晶圆构建标准集成区域的结构示意图。
图6为本申请实施例的晶圆级异质异构芯粒的集成方法中晶圆基板的结构示意图。
图7a为本申请实施例的晶圆级异质异构芯粒的集成方法的第一硅转接板结构示意图。
图7b为本申请实施例的晶圆级异质异构芯粒的集成方法的第二硅转接板结构示意图。
图8a为本申请实施例的晶圆级异质异构芯粒的集成方法的第一标准集成件结构示意图。
图8b为本申请实施例的晶圆级异质异构芯粒的集成方法的第二标准集成件结构示意图。
图9为本申请实施例的晶圆级异质异构芯粒的集成方法中异质异构集成晶圆的结构示意图。
图10为本申请实施例的晶圆级异质异构芯粒的集成方法中晶圆级异质异构芯粒的集成结构的结构示意图。
图中：1、异质异构芯粒，2、硅转接板，3、标准集成件，4、标准集成区域，5、硅通孔，6、植球，7、重布线层，8、芯粒配置基板焊盘，9、芯粒配置基板，10、接插件，11、电源芯片，12、硅晶圆，13、晶圆基板，14、基板微凸点，15、转接板微焊盘，16、 转接板微凸点，17、芯粒微焊盘，18a、18b、18c、18d分别表示不同类型的硅转接板，19a、19b、19c、19d分别表示不同类型的异质异构芯粒。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行描述和说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。基于本申请提供的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本申请保护的范围。此外，还可以理解的是，虽然这种开发过程中所作出的努力可能是复杂并且冗长的，然而对于与本申请公开的内容相关的本领域的普通技术人员而言，在本申请揭露的技术内容的基础上进行的一些设计，制造或者生产等变更只是常规的技术手段，不应当理解为本申请公开的内容不充分。
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域普通技术人员显式地和隐式地理解的是，本申请所描述的实施例在不冲突的情况下，可以与其它实施例相结合。
除非另作定义，本申请所涉及的技术术语或者科学术语应当为本申请所属技术领域内具有一般技能的人士所理解的通常意义。本申请所涉及的“一”、“一个”、“一种”、“该”等类似词语并不表示数量限制，可表示单数或复数。本申请所涉及的“多个”是指大于或者等于两个。本申请所涉及的术语“包括”、“包含”、“具有”以及它们任何变形，意图在于覆盖不排他的包含。
以下结合附图对本申请的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本申请，并不用于限制本申请。
一种适用于晶圆级异质异构芯粒的集成结构，其结构包括：依次连接的异质异构芯粒1、晶圆基板13以及芯粒配置基板9，一组异质异构芯粒1与硅转接板2连接，形成标准集成件3，一组标准集成件3再与晶圆基板13上配合设置的标准集成区域4相连，转接板微凸点16与转接板微焊盘15在硅转接板2内配合连接。
硅转接板2上表面设有异构的转接板微凸点16，用于键合异质异构芯粒1，硅转接板2下表面设有与晶圆基板13的标准集成区域4相配合的标准化的转接板微焊盘15，用于键合晶圆基板13。键合的硅转接板2与异质异构芯粒1之间，和/或硅转接板2与晶圆基板13之间，填充多层重布线层7。
本申请实施例中，如图1和图2所示，硅转接板2上表面与一组异质异构芯粒1连接， 硅转接板2下表面经标准化后，与晶圆基板上表面配合设置的标准集成区域4连接，通过改变硅转接板2上表面的转接板微凸点16，可以适应各类异质芯粒集成，从而规范化晶圆制备，形成标准集成件3，通过标准化硅转接板2下表面的转接板微焊盘15，使得设置标准集成区域4的晶圆基板13能够与配置不同芯粒的各类标准集成件3直接集成。硅转接板2上表面具有异构的转接板微凸点16用于键合异质异构芯粒1；硅转接板2下表面具有转接板微焊盘15与晶圆基板的标准集成区域4相连。硅转接板2下表面的转接板微焊盘15与晶圆基板13的统一标准化的微凸点阵列可以不完全对应。硅转接板2通过多层重布线层7实现一个或者多个异质异构芯粒1相互连接以及与晶圆基板13的互通连接。通过硅转接板2，可以根据需要，集成大小、形状不同的异质异构芯粒1到晶圆基板13；可以在晶圆基板13上形成不同功能的标准集成件3。如图2所示，18a、18b、18c、18d分别表示不同类型的硅转接板，19a、19b、19c、19d分别表示不同类型的异质异构芯粒。
本申请实施例中，硅转接板2设有互不相同的第一硅转接板、第二硅转接板、第三硅转接板和第四硅转接板四种类型；硅转接板2上根据不同的异质异构芯粒1，又配置不同的第一异构预制件、第二异构预制件、第三异构预制件和第四异构预制件四种类型。
晶圆基板13上表面设有重复的标准化微凸点阵列，用于键合转接板微焊盘15，基板微凸点14经硅通孔(Through Silicon Via，TSV)5在晶圆基板13下表面引出，引出的硅通孔5通过植球6与芯粒配置基板9贴合。
本申请实施例中，晶圆基板13上表面具有重布线层7(Re-distributed layer，RDL)和统一标准化的微凸点阵列，形成标准集成区域4并与标准集成件3相连；晶圆基板13下表面设有硅通孔5，硅通孔5末端的植球6与芯粒配置基板9连接。晶圆基板13利用重复的光刻刻蚀等图形化手段，形成重复的标准集成区域4，标准集成区域4范围不大于一次光刻的最大区域。
晶圆基板13的尺寸大于或等于8寸，本申请的实施例中，晶圆基板13为硅晶圆12，尺寸为12寸。由于大尺寸晶圆级晶圆基板13的步进式光刻，难以做到表面异质异构，因此通过本申请，能够使面向大尺寸晶圆级的晶圆基板13也能够与异质异构芯粒1集成。
芯粒配置基板9为PCB电路板，具有芯片配置、测试、时钟、供电以及系统配置等功能。
一种适用于晶圆级异质异构芯粒的集成方法，如图3所示，包含以下步骤：
步骤S1：制备晶圆基板13，其中，通过标准半导体工艺，在晶圆上设置硅通孔阵列，基于硅通孔阵列，在晶圆上表面构建配合设置的重布线层7及微凸点阵列，重复图形化过程，在晶圆上形成一组标准集成区域4，形成晶圆基板13。
通过通孔背面露头(Backside Via Reveal，BVR)工艺，利用化学机械抛光(Chemical Mechanical Polishing，CMP)将晶圆基板13下表面减薄后，使硅通孔5通过晶圆基板13下表面的重布线层7，从晶圆基板13下表面引出。
本申请的实施例中，如图4所示，利用深刻蚀工艺、溅射、电镀等标准半导体工艺在硅晶圆12上形成硅通孔阵列；如图5所示，利用标准半导体金属工艺形成晶圆上表面重布线层7以及微凸点阵列，重复图形化过程，在整个晶圆上形成标准集成区域4。如图6所示，通过通孔背面露头工艺，利用化学机械抛光将硅晶圆12下表面减薄后，使硅通孔5通过硅晶圆12下表面的重布线层7，从硅晶圆12下表面引出，得到晶圆基板13。
步骤S2：制备硅转接板2，其中，通过硅转接板制备工艺，制备上表面与一组异质异构芯粒1配合设置，下表面与标准集成区域4配合设置的硅转接板2。
如图7a、图7b所示，制备的硅转接板2上表面具有转接板微凸点16，适用于异质异构的芯粒，下表面设有与基板微凸点14配合设置的转接板微焊盘15，所述转接板微凸点16与转接板微焊盘15在硅转接板2内配合连接。例如：根据芯片功能设计布线线路时，可以对单一信号传输可以采用直连，也可以将电源信号类合并。
步骤S3：将一组异质异构芯粒1与硅转接板2上表面键合，形成标准集成件3。
异质异构芯粒1，通过下表面设有的芯粒微焊盘17，与转接板微凸点16键合。
芯粒微焊盘17与转接板微凸点16周围，填充重布线层7。
异质异构芯粒1与硅转接板2的键合，在注塑和/或研磨减薄后，形成标准集成件3。
本申请的实施例中，如图8a、图8b所示，将第一异质异构芯粒和第二异质异构芯粒与第一硅转接板键合，注塑后研磨减薄，形成第一标准集成件；将第三异质异构芯粒和第四异质异构芯粒与第二硅转接板键合，注塑后研磨减薄，形成第二标准集成件。
步骤S4：将一组标准集成件3与晶圆基板13通过芯粒-晶圆(Die to wafer，D2W)键合方式集成，得到异质异构集成晶圆。
将异质异构集成晶圆上表面塑封。将异质异构集成晶圆下表面引出的硅通孔5植球。植球6周围设置重布线层7。
如图9所示，将第一标准集成件以及第二标准集成件与晶圆基板13通过D2W键合方式集成，形成异质异构集成晶圆，并将集成后的晶圆正面塑封后，将背面引出的TSV植球，用于贴合芯粒配置基板9。植球方式包括激光植球等。
步骤S5：将异质异构集成晶圆与芯粒配置基板9贴合，形成完整的晶圆级异质异构芯粒的集成结构。如图10所示，芯粒配置基板焊盘8与植球6贴合，芯粒配置基板9底部连接接插件10和电源芯片11等。
本申请利用半导体制造以及封装技术，实现晶圆级异质异构芯粒的集成，在归一化的晶圆基板基础上实现异质异构芯粒的灵活集成，形成的晶上系统可以应用于人工智能、智能计算、高性能计算、晶上网络交换等各领域。
本申请在晶圆基板制造时采用相同的光刻掩模版实现晶圆上的待集成网格单元，解决因晶圆厂晶圆制备过程中光罩图案无法频繁更换的工艺流程问题，从而为晶圆级的异质异构芯粒拼装集成提供高效可行的技术保障。
本申请不需要约束各类异质异构芯粒的设计，只需要通过特定的硅转接板形成标准集成件，就可以实现各类异质异构芯粒的互通互连。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种适用于晶圆级异质异构芯粒的集成结构，包括依次连接的异质异构芯粒、晶圆基板以及芯粒配置基板，其特征在于：
    一组所述异质异构芯粒与硅转接板连接，形成的标准集成件，一组标准集成件再与晶圆基板上配合设置的标准集成区域相连；
    所述硅转接板上表面设有异构的转接板微凸点，用于键合所述异质异构芯粒，所述硅转接板下表面设有与所述晶圆基板的所述标准集成区域相配合的标准化的转接板微焊盘，用于键合所述晶圆基板，所述转接板微凸点与所述转接板微焊盘在所述硅转接板内配合连接。
  2. 根据权利要求1所述的适用于晶圆级异质异构芯粒的集成结构，其中：所述晶圆基板的尺寸大于或等于8寸。
  3. 根据权利要求1所述的适用于晶圆级异质异构芯粒的集成结构，其中：所述晶圆基板上表面设有重复的标准化微凸点阵列，用于键合所述转接板微焊盘，基板微凸点经硅通孔在所述晶圆基板下表面引出，引出的硅通孔通过植球与所述芯粒配置基板贴合。
  4. 根据权利要求1所述的适用于晶圆级异质异构芯粒的集成结构，其中：所述硅转接板中设有多层重布线层，用于连接所述异质异构芯粒和/或所述晶圆基板；和/或，所述晶圆基板中设有多层重布线层，用于连接所述硅转接板和/或所述芯粒配置基板。
  5. 一种适用于晶圆级异质异构芯粒的集成方法，其特征在于，所述集成方法包括如下步骤：
    制备晶圆基板，其中，通过标准半导体工艺，在晶圆上设置硅通孔阵列，基于所述硅通孔阵列，在所述晶圆上表面构建微凸点阵列，重复图形化过程，在晶圆上形成重复的标准集成区域，形成所述晶圆基板；
    制备硅转接板，其中，通过硅转接板制备工艺，制备的所述硅转接板上表面设有异构的转接板微凸点，用于键合异质异构芯粒，下表面设有与所述晶圆基板的标准集成区域相配合的标准化的转接板微焊盘，用于键合所述晶圆基板，所述转接板微凸点与所述转接板微焊盘在所述硅转接板内配合连接；
    将一组所述异质异构芯粒与所述硅转接板上表面键合，形成标准集成件；
    将一组所述标准集成件与所述晶圆基板通过芯粒-晶圆键合方式集成，得到异质异构集成晶圆；
    将所述异质异构集成晶圆与芯粒配置基板贴合。
  6. 根据权利要求5所述的适用于晶圆级异质异构芯粒的集成方法，其中，在制备晶圆基板时，通过通孔背面露头工艺，利用化学机械抛光将所述晶圆基板下表面减薄后，使硅通孔从所述晶圆基板下表面引出。
  7. 根据权利要求5所述的适用于晶圆级异质异构芯粒的集成方法，其中，所述异质异构芯粒，通过下表面设有的芯粒微焊盘，与所述转接板微凸点键合。
  8. 根据权利要求5所述的适用于晶圆级异质异构芯粒的集成方法，其中：所述硅转接板中设有多层重布线层，用于连接所述异质异构芯粒和/或所述晶圆基板；和/或，所述晶圆基板中设有多层重布线层，用于连接所述硅转接板和/或所述芯粒配置基板。
  9. 根据权利要求5所述的适用于晶圆级异质异构芯粒的集成方法，其中，所述异质异构芯粒与所述硅转接板键合，在注塑和/或研磨减薄后，形成所述标准集成件。
  10. 根据权利要求5所述的适用于晶圆级异质异构芯粒的集成方法，其中：将所述异质异构集成晶圆上表面塑封；将所述异质异构集成晶圆下表面引出的硅通孔植球，用于贴合所述芯粒配置基板。
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