CN110797335A - 异质集成芯片的系统级封装结构 - Google Patents
异质集成芯片的系统级封装结构 Download PDFInfo
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- CN110797335A CN110797335A CN201911188487.XA CN201911188487A CN110797335A CN 110797335 A CN110797335 A CN 110797335A CN 201911188487 A CN201911188487 A CN 201911188487A CN 110797335 A CN110797335 A CN 110797335A
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 60
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- 238000004806 packaging method and process Methods 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims description 9
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 230000010354 integration Effects 0.000 abstract description 12
- 238000004519 manufacturing process Methods 0.000 abstract description 4
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- 238000000034 method Methods 0.000 description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201911188487.XA CN110797335A (zh) | 2019-11-28 | 2019-11-28 | 异质集成芯片的系统级封装结构 |
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CN201911188487.XA CN110797335A (zh) | 2019-11-28 | 2019-11-28 | 异质集成芯片的系统级封装结构 |
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CN110797335A true CN110797335A (zh) | 2020-02-14 |
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CN201911188487.XA Pending CN110797335A (zh) | 2019-11-28 | 2019-11-28 | 异质集成芯片的系统级封装结构 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113451292A (zh) * | 2021-08-09 | 2021-09-28 | 华天科技(西安)有限公司 | 一种高集成2.5d封装结构及其制造方法 |
CN114267656A (zh) * | 2021-06-02 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 功率模块的封装结构及封装方法 |
CN114487788A (zh) * | 2022-04-02 | 2022-05-13 | 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) | 封装器件的失效定位方法 |
CN114554689A (zh) * | 2022-02-23 | 2022-05-27 | 展讯通信(上海)有限公司 | 一种智能终端主板及智能终端 |
CN114899185A (zh) * | 2022-07-12 | 2022-08-12 | 之江实验室 | 一种适用于晶圆级异质异构芯粒的集成结构和集成方法 |
US11887964B1 (en) | 2022-07-12 | 2024-01-30 | Zhejiang Lab | Wafer-level heterogeneous dies integration structure and method |
CN118289700A (zh) * | 2024-06-04 | 2024-07-05 | 深圳北航新兴产业技术研究院 | 一种新型sip封装的多功能融合传感芯片 |
-
2019
- 2019-11-28 CN CN201911188487.XA patent/CN110797335A/zh active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114267656A (zh) * | 2021-06-02 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 功率模块的封装结构及封装方法 |
CN113451292A (zh) * | 2021-08-09 | 2021-09-28 | 华天科技(西安)有限公司 | 一种高集成2.5d封装结构及其制造方法 |
CN114554689A (zh) * | 2022-02-23 | 2022-05-27 | 展讯通信(上海)有限公司 | 一种智能终端主板及智能终端 |
CN114487788A (zh) * | 2022-04-02 | 2022-05-13 | 中国电子产品可靠性与环境试验研究所((工业和信息化部电子第五研究所)(中国赛宝实验室)) | 封装器件的失效定位方法 |
CN114899185A (zh) * | 2022-07-12 | 2022-08-12 | 之江实验室 | 一种适用于晶圆级异质异构芯粒的集成结构和集成方法 |
WO2024011880A1 (zh) * | 2022-07-12 | 2024-01-18 | 之江实验室 | 适用于晶圆级异质异构芯粒的集成结构和集成方法 |
US11887964B1 (en) | 2022-07-12 | 2024-01-30 | Zhejiang Lab | Wafer-level heterogeneous dies integration structure and method |
CN118289700A (zh) * | 2024-06-04 | 2024-07-05 | 深圳北航新兴产业技术研究院 | 一种新型sip封装的多功能融合传感芯片 |
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Effective date of registration: 20240129 Address after: 410000 East, 2nd floor, building C, Lugu high level Talents Innovation and entrepreneurship Park, no.1698, Yuelu West Avenue, Changsha high tech Development Zone, Changsha City, Hunan Province Applicant after: Changsha Anmuquan Intelligent Technology Co.,Ltd. Country or region after: China Address before: Yuelu District City, Hunan province 410000 Changsha Lushan Road No. 932 Applicant before: CENTRAL SOUTH University Country or region before: China Applicant before: Changsha Anmuquan Intelligent Technology Co.,Ltd. |