WO2024004263A1 - 基板 - Google Patents

基板 Download PDF

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Publication number
WO2024004263A1
WO2024004263A1 PCT/JP2023/005690 JP2023005690W WO2024004263A1 WO 2024004263 A1 WO2024004263 A1 WO 2024004263A1 JP 2023005690 W JP2023005690 W JP 2023005690W WO 2024004263 A1 WO2024004263 A1 WO 2024004263A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic components
filler
particle diameter
substrate
wall surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/005690
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
竜一 久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2023579251A priority Critical patent/JP7537637B2/ja
Priority to CN202380036950.7A priority patent/CN119032635A/zh
Publication of WO2024004263A1 publication Critical patent/WO2024004263A1/ja
Priority to US18/930,079 priority patent/US20250056729A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0263—Details about a collection of particles
    • H05K2201/0266—Size distribution
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305—Moulding and encapsulation

Definitions

  • the present invention relates to a substrate.
  • Patent Document 1 describes a core member, a through hole penetrating the core member, one or more passive components arranged in the through hole, and a core member that covers at least a portion of the passive component and fills at least a portion of the through hole.
  • a semiconductor package including a sealing material is described (see, for example, FIG. 9).
  • Patent Document 2 discloses a core substrate provided with an opening penetrating a core material, a plurality of types of electronic components housed in the opening, and a core substrate formed in the opening with a plurality of types of electronic components housed in the core substrate.
  • a printed wiring board including a fixing resin is described (see, for example, FIG. 1).
  • the gap between the electronic components may not be sufficiently filled with a sealing material for sealing the electronic components within the substrate.
  • the present invention has been made to solve the above problems, and an object of the present invention is to provide a substrate with excellent filling properties of a sealing material between electronic components.
  • the substrate of the present invention has a core substrate having a first surface and a second surface opposite to the first surface, and an opening provided therein; and at least a plurality of electronic components provided in the opening.
  • a sealing material that is provided between the opening and the plurality of electronic components and between the plurality of electronic components and includes a resin and a filler, wherein the average distance between the plurality of electronic components is the It is smaller than the shortest distance between the wall of the opening and the electronic component adjacent to the wall.
  • FIG. 1 is a cross-sectional view schematically showing an example of a substrate according to an embodiment of the present invention.
  • FIG. 2 is a plan view schematically showing an example of a core board and electronic components included in the board shown in FIG.
  • FIG. 3 is an enlarged schematic cross-sectional view of the opening of the substrate shown in FIG.
  • FIG. 4 is a plan view schematically showing when electronic components are sealed with a sealing material.
  • FIG. 5 is a cross-sectional view schematically showing when electronic components are sealed with a sealing material.
  • FIG. 6 is a plan view schematically showing a state in which the core substrate included in the substrate shown in FIG. 1 is deformed.
  • FIG. 7 is a cross-sectional view schematically showing a modification of the substrate shown in FIG. FIG.
  • FIG. 8 is a diagram schematically showing an example of a process of attaching an adhesive film for fixing electronic components to a core substrate.
  • FIG. 9 is a cross-sectional view schematically showing an example of a process of arranging electronic components (passive components) on an adhesive film.
  • FIG. 10 is a cross-sectional view schematically showing an example of a process of arranging electronic components (passive components and semiconductor chips) on an adhesive film.
  • FIG. 11 is a cross-sectional view schematically showing an example of the process of filling the opening of the core substrate with a sealing material.
  • FIG. 12 is a cross-sectional view schematically showing an example of the process of forming a via.
  • FIG. 13 is a cross-sectional view schematically showing an example of the process of forming a wiring layer.
  • FIG. 14 is a cross-sectional view schematically showing an example of the process of forming a buildup layer.
  • the present invention is not limited to the following configuration, and can be modified and applied as appropriate without changing the gist of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described below.
  • FIG. 1 is a cross-sectional view schematically showing an example of a substrate according to an embodiment of the present invention.
  • FIG. 2 is a plan view schematically showing an example of a core board and electronic components included in the board shown in FIG. Note that FIG. 1 is a cross-sectional view taken along the line XX shown in FIG. 2.
  • the substrate 100 shown in FIGS. 1 and 2 has a first surface 11 and a second surface 12 opposite to the first surface 11, and includes a core substrate 10 in which an opening 13 is provided, and a core substrate 10 in which an opening 13 is provided. At least a plurality of electronic components 20 are provided, a third surface 31 on the first surface 11 side and a third surface 31 on the second surface 12 side are provided between the opening 13 and the electronic components 20, and between the plurality of electronic components 20.
  • a sealing material 30 having four surfaces 32; a plurality of first via conductors 40 penetrating the third surface 31 of the sealing material 30 and electrically connected to the first electrodes 21 of the plurality of electronic components 20; A plurality of second via conductors 50 electrically connected to the second electrodes 22 of the plurality of electronic components 20 and a plurality of second via conductors 50 provided on the first surface 11 of the core substrate 10 and the third surface 31 of the sealing material 30.
  • the core substrate 10 a resin substrate, a glass substrate, a ceramic substrate, etc. can be used.
  • the core substrate 10 may be a printed wiring board having conductor wiring provided on its surface or inside.
  • an insulating support substrate (core material) formed from a resin such as epoxy resin and a reinforcing material such as glass cloth can be used.
  • the supporting substrate may contain inorganic particles such as silica particles and alumina particles.
  • the first surface 11 and second surface 12 of the core substrate 10 are parallel surfaces to each other, and constitute a pair of opposing main surfaces of the core substrate 10.
  • the opening 13 of the core substrate 10 passes through the core substrate 10.
  • the shape of the opening 13 when the core substrate 10 is viewed from above is not particularly limited, and in addition to the rectangle shown in FIG. It's okay.
  • the substrate 100 is a component-embedded substrate in which a plurality of electronic components 20 are embedded, and each electronic component 20 is not placed on the first surface 11 and second surface 12 of the core substrate 10 but inside the opening 13 of the core substrate 10. It is stored in.
  • the electronic component 20 may be arranged two-dimensionally within the opening 13 as shown in FIG. 2, or may be arranged one-dimensionally within the opening 13. In the former case, the electronic components 20 may be arranged, for example, in a matrix (FIG. 2) or in a staggered manner.
  • the spacing S1 between the plurality of electronic components 20 (that is, the spacing between adjacent electronic components 20) is not particularly limited, but the average spacing S1 is preferably 10 ⁇ m or more and 100 ⁇ m or less, and preferably 10 ⁇ m or more and 50 ⁇ m or less. It is more preferable that there be.
  • the average of the intervals S1 is determined by image analysis of a photograph of the substrate 100. More specifically, an enlarged photograph of a cross section parallel to the second surface 12 of the core substrate 10 is obtained using a scanning electron microscope (SEM) or a transmission electron microscope (TEM), and for each set of adjacent electronic components 20, Using image analysis software, line segments are drawn on each of the opposing contour lines, and the average distance between the line segments is determined. Then, the average of the average distances obtained from all the combinations of electronic components 20 is determined, and the average value is set as the average of the interval S1.
  • An X-ray photograph may be used instead of a photograph taken by a scanning electron microscope (SEM) or a transmission electron microscope (TEM).
  • spacing S1 between the electronic components 20 may be substantially constant (the same no matter where) as shown in FIGS. It's okay.
  • the average distance S1 only needs to be measured on one cross section parallel to the second surface 12, and does not necessarily need to be measured on two or more cross sections parallel to the second surface 12.
  • FIG. 1 shows a cross section perpendicular to the second surface 12 of the core substrate 10.
  • this cross section may be simply referred to as a "vertical cross section.”
  • passive components 20A such as a capacitor (for example, a multilayer ceramic capacitor (MLCC)) and an inductor are arranged here.
  • These electronic components 20 are chip components having a longitudinal shape such as a rectangular parallelepiped shape or a cylindrical shape.
  • the electronic components 20 of the same type are components of the same size as defined by the size notation of chip components.
  • the size notation is a notation defined by JIS (Japanese Industrial Standards) and EIA (Electronic Industries Alliance), and examples of JIS include 0603 and the like.
  • the electronic components 20 of the same type may be components of the same type among the basic components of an electric circuit, such as capacitors or inductors.
  • the electronic components 20 of the same type may be, for example, components having the same model among capacitors or inductors.
  • Each electronic component 20 has a shape whose longitudinal direction extends in a direction perpendicular to the second surface 12 of the core substrate 10 (first direction D1 or second direction D2, which will be described later). In this case, it becomes particularly difficult to fill the gaps between the electronic components 20 with the sealing material 30, but according to the present embodiment, as will be described later, the filling performance of the sealing material 30 between the electronic components 20 can be improved. is possible.
  • each electronic component 20 In a vertical cross section, the dimensions of each electronic component 20 are larger in a direction perpendicular to the second surface 12 (first direction D1 or second direction D2 described later) than in a direction parallel to the second surface 12 of the core substrate 10. bigger. Thereby, the electronic components 20 can be arranged with higher density.
  • each electronic component 20 has a first electrode 21 in a first direction D1 that is perpendicular to the second surface 12 of the core substrate 10 and faces the first surface 11 side, and is opposite to the first direction D1. It has a second electrode 22 in the second direction D2.
  • the first electrode 21 and the second electrode 22 are located at one end and the other end in the longitudinal direction of the elongated electronic component 20, respectively.
  • At least one dimension of the electronic component 20 is determined in a vertical cross section in a direction perpendicular to the second surface 12 (first direction D1 or second direction D2) rather than in a direction parallel to the second surface 12 of the core substrate 10. ) may be smaller. Furthermore, in at least one of the electronic components 20, the first electrode 21 and the second electrode 22 may be arranged in a direction parallel to the core substrate 10.
  • FIG. 3 is an enlarged schematic cross-sectional view of the opening of the substrate shown in FIG. Note that FIG. 3 is a part of a cross-sectional view taken along the line XX shown in FIG. 2, and shows a vertical cross-section.
  • the sealing material 30 is a member for sealing the electronic component 20 within the opening 13, and is filled around each electronic component 20 within the opening 13. As shown in FIGS. 2 and 3, the sealing material 30 includes a resin 33 and a filler 34.
  • Examples of the resin 33 include epoxy resin, polyimide, etc., and among them, epoxy resin is preferable.
  • the filler 34 contains particles, as shown in FIGS. 2 and 3.
  • the filler 34 for example, inorganic particles such as silica particles and alumina particles are suitable.
  • SiO 2 and Al 2 O 3 are suitable as the material for the filler 34, and it is preferable that the filler 34 contains at least one of SiO 2 and Al 2 O 3 .
  • the shape of the filler 34 is not particularly limited, and may be, for example, spherical as shown in FIGS. 2 and 3, or may be ellipsoidal, plate-like, acicular, irregular, etc. .
  • At least one first via conductor 40 is provided for each electronic component 20, and each electronic component 20 is electrically connected to the first buildup layer 60 via the first via conductor 40.
  • Each first via conductor 40 penetrates at least the insulating layer 61 of the first buildup layer 60 closest to the core substrate 10 and the third surface 31 of the sealing material 30, and extends through the first electrode of the corresponding electronic component 20. It has reached 21.
  • At least one second via conductor 50 is provided for each electronic component 20, and each electronic component 20 is electrically connected to the second buildup layer 70 via the second via conductor 50.
  • Each second via conductor 50 at least penetrates the insulating layer 71 of the second buildup layer 70 closest to the core substrate 10 and reaches the second electrode 22 of the corresponding electronic component 20 .
  • the first buildup layer 60 electrically connects the electronic components 20 to each other, the electronic components 20 to other components, through holes, terminals, etc., and includes at least one insulating layer 61 and at least one wiring layer 62. are stacked alternately.
  • the second buildup layer 70 electrically connects the electronic components 20 to each other, the electronic components 20 to other components, through holes, terminals, etc., and includes at least one insulating layer 71 and at least one wiring.
  • the layers 72 are alternately stacked.
  • FIG. 4 is a plan view schematically showing when electronic components are sealed with a sealing material.
  • FIG. 5 is a cross-sectional view schematically showing when electronic components are sealed with a sealing material.
  • FIG. 6 is a plan view schematically showing a state in which the core substrate included in the substrate shown in FIG. 1 is deformed.
  • the average interval S1 between the plurality of electronic components 20 is the shortest distance S2 between the wall surface 13a of the opening 13 and the electronic component 20 adjacent to the wall surface 13a. smaller than In this way, since there is a space around the area where the electronic component 20 is mounted, when the electronic component 20 is sealed with the sealing material 30, as shown in FIGS. This allows the sealing material 30 to flow, increasing the fluidity of the sealing material 30. As a result, bubble clogging and clogging of the filler 34 are suppressed, so that the filling performance of the sealing material 30 between the electronic components 20 is improved.
  • the electrodes (the first electrode 21 and the second electrode 22) of the electronic component 20 are located at one end and the other end in the longitudinal direction of the elongated electronic component 20. If an electrode is provided at this position, the position where the filler 34 contacts the electronic component 20 when filling the sealing material 30 becomes the electrode.
  • the material of the electrode is typically metal, which has higher strength than parts other than the electrode (typically ceramic), so even if the filler 34 comes into contact with the electrode, the electrode is not easily damaged.
  • the large filler 34 is formed between the electronic components 20 in a portion other than the longitudinal end of the electronic component 20.
  • the ceramic portion of the electronic component 20 between the plurality of electronic components 20 is prevented from being damaged.
  • the electronic component 20 is prevented from being damaged by contact with the filler 34 when the sealing material 30 is filled.
  • the ratio between the average interval S1 and the shortest distance S2 is not particularly limited, the shortest distance S2 is preferably 5 times or more, more preferably 8 times or more, as compared to the average interval S1, More preferably, it is substantially 10 times or more.
  • the shortest distance S2 is also not particularly limited, but is preferably 50 ⁇ m or more, more preferably 100 ⁇ m or more.
  • the shortest distance S2 is determined by image analysis of a photograph of the substrate 100. More specifically, an enlarged photograph of a cross section parallel to the second surface 12 of the core substrate 10 is obtained using a scanning electron microscope (SEM) or a transmission electron microscope (TEM), and the wall surface 13a of the opening 13 and the wall surface 13a are For each of the adjacent electronic components 20, line segments are drawn on the opposing contours using image analysis software, and the minimum interval between the line segments is determined. Then, the shortest distance among the determined minimum intervals is defined as the shortest distance S2.
  • An X-ray photograph may be used instead of a photograph taken by a scanning electron microscope (SEM) or a transmission electron microscope (TEM).
  • all the spacings S1 between the plurality of electronic components 20, that is, all the spacings S1 between adjacent sets of electronic components 20, may be smaller than the shortest distance S2.
  • the average particle diameter of the filler 34 filled in the area A1 between the wall surface 13a of the opening 13 and the plurality of electronic components 20 adjacent to the wall surface 13a is It is preferable that the average particle diameter is larger than the average particle diameter of the filler 34 filled in the area A2 between 20 and 20 mm.
  • the filling rate of the fillers 34 tends to be small.
  • the ratio of the resin 33 becomes large. Since the resin having a small elastic modulus can be placed around the electronic component 20, the stress from the core substrate 10 can be further alleviated. That is, in the vertical cross section, the ratio of the area occupied by the filler 34 filled in the area A1 between the wall surface 13a of the opening 13 and the plurality of electronic components 20 adjacent to the wall surface 13a is smaller than the area between the plurality of electronic components 20. It is preferable that the area occupied by the filler 34 filled in A2 is smaller than the area occupied by the filler 34.
  • the filling rate of the filler 34 can be determined as the ratio of the area occupied by the filler 34 per unit area in an image in a vertical section. By adjusting the filling rate of the filler 34 in the area A1, it is possible to adjust the linear expansion coefficient of the encapsulant 30 and the thermal contraction during curing of the encapsulant 30, thereby preventing the occurrence of cracks and electronic components. The load on 20 can be suppressed.
  • the filler 34 having a large particle size is difficult to fill in the area A2 between the plurality of electronic components 20, and is difficult to fill in the area A2 between the plurality of electronic components 20, and between the wall surface of the opening 13, the wall surface 13a of the opening 13, and the plurality of electronic components 20 adjacent to the wall surface 13a.
  • the area A1 is likely to be filled. That is, the filler 34 having a large particle size is unevenly distributed in the area A1. Utilizing this property, by changing the materials of the filler 34 with a large particle size and the filler 34 with a small particle size, the characteristics of the sealing material 30 can be controlled between the mounting area of the electronic component 20 and the surrounding area. You can make a difference.
  • Examples of the properties of the sealing material 30 that can be changed by changing the material of the filler 34 include properties such as linear expansion coefficient, dielectric constant, Young's modulus, thermal conductivity, electromagnetic wave absorption, and moisture absorption.
  • the thermal conductivity of the filler 34 having a small particle size is increased, and the thermal conductivity of the filler 34 having a large particle size is decreased.
  • the thermal conductivity of the sealing material 30 in the area A2 becomes high, and the thermal conductivity of the sealing material 30 in the area A1 becomes low.
  • the heat generated by the electronic component 20 built into the opening 13 can be efficiently released to the upper and lower surfaces of the board 100 without escaping in the horizontal direction (lateral direction) to the second surface 12.
  • Examples of such a combination of fillers 34 include using silica as the filler 34 with a large particle size and using boron nitride or aluminum nitride as the filler 34 with a small particle size.
  • Another example is an example in which electromagnetic wave absorption performance is added to the filler 34 having a large particle size.
  • the electromagnetic wave shielding property of the sealing material 30 becomes high in the region A1. In this way, it is possible to block the influence of noise from outside the opening 13 while maintaining electrical characteristics in the sealing material 30 around the electronic component 20 (area A2).
  • An example of such a combination of fillers 34 is an example in which iron oxide is used as the filler 34 having a large particle size.
  • Another example is to use a material with a small dielectric constant and dielectric loss as the filler 34 with a small particle size, and use a material with a small coefficient of linear expansion as the filler 34 with a large particle size.
  • the linear expansion coefficient of the encapsulant 30 in the area A1 is reduced while improving the electrical characteristics (reducing loss) of the electronic component 20 in the encapsulant 30 around the electronic component 20 (area A2). By doing so, the physical effects of heat can be reduced.
  • Examples of such a combination of fillers 34 include using a zirconium phosphate compound (manufactured by Toagosei, Ultair TM, etc.) as the filler 34 with a large particle size, and using silica as the filler 34 with a small particle size.
  • a zirconium phosphate compound manufactured by Toagosei, Ultair TM, etc.
  • silica silica
  • Another example is to use a material with a small dielectric constant and dielectric loss as the filler 34 with a small particle size, and use a material with a high thermal conductivity as the filler 34 with a large particle size. In this way, heat is efficiently released through the sealing material 30 in the area A1 while improving the electrical characteristics (reducing loss) of the electronic component 20 in the sealing material 30 around the electronic component 20 (area A2). It can be released outside the section 13.
  • Examples of such a combination of fillers 34 include using boron nitride or aluminum nitride as the filler 34 with a large particle size, and using silica as the filler 34 with a small particle size.
  • the sealing material 30 in the region A1 contains a large amount of filler 34 with a large particle size, the continuity of the fracture surface will be inhibited. That is, the sealing material 30 becomes more difficult to break.
  • the average particle diameter of the filler 34 is determined by image analysis of a photograph of a vertical cross section. More specifically, in an enlarged photograph of a vertical cross section obtained by a scanning electron microscope (SEM) or a transmission electron microscope (TEM), each outline of at least 50 fillers 34 included in area A1 or A2 is shown. The diameter of a circle equal to the area within the closed curve formed by the line, that is, the equivalent circle diameter is determined, and the average value thereof is determined as the average particle diameter of the filler 34.
  • SEM scanning electron microscope
  • TEM transmission electron microscope
  • the region A1 may be the entire region sandwiched between the wall surface 13a of the opening 13 and the electronic component 20 adjacent to the wall surface 13a in a vertical cross section. Further, the region A2 may be the entire region sandwiched between at least one set (or each set) of two adjacent electronic components 20 in the vertical cross section.
  • the position of the vertical cross section for comparing the average particle diameters is not particularly limited, but as shown in FIG. Good too. Further, the vertical cross section for comparing the average particle diameters may or may not be the cross section where the shortest distance S2 appears.
  • the average particle diameter of the filler 34 filled in area A1 and the average particle diameter of the filler 34 filled in area A2 only need to satisfy the above relationship in one vertical section, and in two or more vertical sections. The above relationship does not necessarily have to be satisfied.
  • the average particle diameter of the filler 34 filled in the area A1 may be 5 times or more the average particle diameter of the filler 34 filled in the area A2. It is preferably 10 times or more, and more preferably 10 times or more.
  • the average particle diameter of the filler 34 filled in region A1 is preferably 10 ⁇ m or more and 100 ⁇ m or less, more preferably 50 ⁇ m or more and 100 ⁇ m or less.
  • the average particle diameter of the filler 34 filled in region A2 is preferably 10 nm or more and 100 ⁇ m or less, more preferably 10 nm or more and 50 ⁇ m or less.
  • the maximum particle diameter of the filler 34 filled in the area between the wall surface 13a and the plurality of electronic components 20 adjacent to the wall surface 13a is It is preferable that the particle size is larger than the maximum particle diameter of the filler 34 filled in the area between the electronic components 20. That is, it is preferable that the maximum particle diameter of the filler 34 filled in the area A1 is larger than the maximum particle diameter of the filler 34 filled in the area A2.
  • the maximum particle diameter of the filler 34 filled in region A1 is preferably 10 ⁇ m or more and 100 ⁇ m or less, more preferably 50 ⁇ m or more and 100 ⁇ m or less.
  • the maximum particle diameter of the filler 34 filled in region A2 is preferably 10 nm or more and 100 ⁇ m or less, more preferably 10 nm or more and 50 ⁇ m or less.
  • the maximum particle diameter of the filler 34 filled in the area A1 between the wall surface 13a and the plurality of electronic components 20 adjacent to the wall surface 13a is It is preferable that the spacing S1 between the electronic components 20 is larger than the average. This indicates that filler 34 of a size that cannot be filled between electronic components 20 exists in region A1.
  • the maximum particle diameter of the filler 34 is determined by image analysis of a photograph of a vertical cross section. More specifically, filler 34 included in area A1 or A2 is observed as a large filler in an enlarged photograph of a vertical cross section obtained by a scanning electron microscope (SEM) or a transmission electron microscope (TEM). For some of these, the diameter of a circle equal to the area within the closed curve formed by each contour line, that is, the equivalent circle diameter, is determined, and the maximum value thereof is determined as the maximum particle diameter of the filler 34.
  • SEM scanning electron microscope
  • TEM transmission electron microscope
  • FIG. 7 is a cross-sectional view schematically showing a modification of the substrate shown in FIG. 1.
  • a semiconductor chip 20B such as an integrated circuit (IC) may be mounted together with a passive component 20A as an electronic component 20 in the opening 13 of the core substrate 10.
  • the average distance S1 is determined by using not only the distance S1 (average distance) between the passive components 20A but also the distance S1 (average distance) between the passive components 20A and the semiconductor chip 20B, as shown in FIG. Calculated.
  • the semiconductor chip 20B may be arranged adjacent to the wall surface 13a of the opening 13, and in this case, the shortest distance S2 is the distance between the wall surface 13a and the semiconductor chip 20B adjacent to the wall surface 13a. It may be the distance between. Further, in this case, the region A1 may be a region between the wall surface 13a and the semiconductor chip 20B adjacent to the wall surface 13a in a vertical section.
  • the region A2 may include a region sandwiched between at least one set (or each set) of adjacent passive components 20A and semiconductor chip 20B in the vertical cross section.
  • the thickness of the encapsulant 30 in the direction orthogonal to the second surface 12 from the surface of the electronic component 20 is such that Preferably, the spacing S1 between the parts 20 is larger than the average.
  • the thickness of the encapsulant 30 in the direction orthogonal to the second surface 12 from the surface of the electronic component 20 is such that The average particle diameter of the filler 34 filled in the region that is larger than the average spacing S1 between the components 20 may be larger than the average particle diameter of the filler 34 filled in the region between the plurality of electronic components 20. preferable.
  • the thickness S3 of the sealing material 30 present on the upper surface of the semiconductor chip 20B is larger than the average of the intervals S1.
  • the filler 34 having a large particle size can be present in the sealing material 30 located on the upper surface of the semiconductor chip 20B.
  • the average particle diameter of the filler 34 present in this region is larger than the average particle diameter of the filler 34 filled in the region between the plurality of electronic components 20.
  • the filler 34 having a large particle size as a filler having high electromagnetic wave absorption performance, it is possible to block the influence of external noise on the semiconductor chip 20B. Moreover, by using the filler 34 having a large particle size as a material having a small coefficient of linear expansion, the coefficient of linear expansion of the sealing material 30 can be made small and the physical influence of heat on the semiconductor chip 20B can be reduced.
  • FIG. 8 is a diagram schematically showing an example of a process of attaching an adhesive film for fixing electronic components to a core substrate.
  • an opening 13 is formed in the core substrate 10, and an adhesive film 80 for fixing electronic components is attached to the second surface 12 of the core substrate 10.
  • FIG. 9 is a cross-sectional view schematically showing an example of the process of arranging electronic components (passive components) on an adhesive film.
  • FIG. 10 is a cross-sectional view schematically showing an example of a process of arranging electronic components (passive components and semiconductor chips) on an adhesive film.
  • a plurality of electronic components 20 are placed on the adhesive film 80.
  • the passive component 20A is arranged on the adhesive film 80 so that the first electrode 21 faces upward and the second electrode 22 faces downward. Thereby, the second electrode 22 is attached to the adhesive film 80.
  • the passive component 20A and the semiconductor chip 20B may be mounted together.
  • FIG. 11 is a cross-sectional view schematically showing an example of the process of filling the opening of the core substrate with a sealing material.
  • the electronic component 20 is sealed with a sealing material 30.
  • a sealing material 30 Specifically, an uncured film containing a thermosetting resin and a filler is laminated on the first surface 11 of the core substrate 10 under vacuum. Thereafter, this film is heated and pressed to soften it, thereby filling the area around each electronic component 20 in the opening 13 with a thermosetting resin and filler.
  • the sealing material 30 sufficiently filled between the electronic components 20 is formed.
  • FIG. 12 is a cross-sectional view schematically showing an example of the process of forming a via.
  • an insulating layer 61 is formed on the first surface 11 of the core substrate 10 and the third surface 31 of the sealing material 30.
  • An insulating layer 71 is formed on the second surface 12 and the fourth surface 32 of the sealing material 30. Note that the adhesive film 80 can also be used as it is without being peeled off.
  • a via 82 is formed in the insulating layer 61 to expose the first electrode 21, and a via 83 is formed in the insulating layer 71 to expose the second electrode 22.
  • FIG. 13 is a cross-sectional view schematically showing an example of the process of forming a wiring layer.
  • plating for example, semi-additive method
  • plating is used to fill the vias 82 and 83 to form the first via conductor 40 and the second via conductor 50, and to form the wiring layers 62 and 72. do.
  • FIG. 14 is a cross-sectional view schematically showing an example of the process of forming a buildup layer.
  • layers are added as necessary to form the first buildup layer 60 and the second buildup layer 70.
  • the substrate 100 can be manufactured.
  • a core substrate having a first surface and a second surface opposite to the first surface, and having an opening provided therein; at least a plurality of electronic components provided in the opening; a sealing material that is provided between the opening and the plurality of electronic components and between the plurality of electronic components and includes a resin and a filler; Equipped with A substrate, wherein an average distance between the plurality of electronic components is smaller than a shortest distance between a wall surface of the opening and an electronic component adjacent to the wall surface.
  • the average particle diameter of the filler filled in the region between the wall surface and the plurality of electronic components adjacent to the wall surface is equal to the average particle diameter of the filler filled in the region between the plurality of electronic components.
  • the ratio of the area occupied by the filler filled in the area between the wall surface and the plurality of electronic components adjacent to the wall surface is equal to the area between the plurality of electronic components.
  • the maximum particle diameter of the filler filled in the region between the wall surface and the plurality of electronic components adjacent to the wall surface is the maximum particle diameter of the filler filled in the region between the plurality of electronic components.
  • the maximum particle diameter of the filler filled in the area between the wall surface and the plurality of electronic components adjacent to the wall surface is determined by the average spacing between the plurality of electronic components.
  • each of the plurality of electronic components has a shape whose longitudinal direction extends in a direction perpendicular to the second surface.
  • ⁇ 7> The board according to ⁇ 6>, wherein the electrodes of the electronic component are located at one end and the other end in the longitudinal direction.
  • the thickness of the encapsulant in the direction perpendicular to the second surface from the surface of the electronic component is the same as that between the plurality of electronic components.
  • the thickness of the encapsulant in the direction perpendicular to the second surface from the surface of the electronic component is the same as that between the plurality of electronic components.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
PCT/JP2023/005690 2022-06-27 2023-02-17 基板 Ceased WO2024004263A1 (ja)

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JP2023579251A JP7537637B2 (ja) 2022-06-27 2023-02-17 基板
CN202380036950.7A CN119032635A (zh) 2022-06-27 2023-02-17 基板
US18/930,079 US20250056729A1 (en) 2022-06-27 2024-10-29 Substrate

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JP2022-102606 2022-06-27
JP2022102606 2022-06-27

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US20240243036A1 (en) * 2023-01-12 2024-07-18 Qualcomm Incorporated Cavity-embedded tunable filter

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WO2006011508A1 (ja) * 2004-07-30 2006-02-02 Murata Manufacturing Co., Ltd. 複合型電子部品及びその製造方法
JP2019207978A (ja) * 2018-05-30 2019-12-05 イビデン株式会社 プリント配線板

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US20250056729A1 (en) 2025-02-13
CN119032635A (zh) 2024-11-26
JPWO2024004263A1 (https=) 2024-01-04

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