WO2024000547A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

Info

Publication number
WO2024000547A1
WO2024000547A1 PCT/CN2022/103187 CN2022103187W WO2024000547A1 WO 2024000547 A1 WO2024000547 A1 WO 2024000547A1 CN 2022103187 W CN2022103187 W CN 2022103187W WO 2024000547 A1 WO2024000547 A1 WO 2024000547A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
transistor
signal terminal
circuit
reset
Prior art date
Application number
PCT/CN2022/103187
Other languages
English (en)
French (fr)
Inventor
王苗
肖云升
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/103187 priority Critical patent/WO2024000547A1/zh
Priority to CN202280002087.9A priority patent/CN117678010A/zh
Publication of WO2024000547A1 publication Critical patent/WO2024000547A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit and a driving method thereof, and a display panel.
  • AMOLED (Active-matrix Organic Light-Emitting Diode, active matrix organic light-emitting diode) display panel has many advantages such as self-illumination, ultra-thinness, fast response speed, high contrast, wide viewing angle, etc. It is a display device that has attracted widespread attention at present. .
  • the AMOLED display panel includes multiple pixel drive circuits and multiple light-emitting elements.
  • the pixel drive circuit is used to drive the corresponding light-emitting elements to emit light to achieve display functions.
  • a pixel driving circuit Including: driving sub-circuit, writing sub-circuit, compensation sub-circuit and regulating sub-circuit.
  • the driving sub-circuit is coupled to the first node, the second node and the third node.
  • the driver sub-circuit is configured to transmit the voltage from the second node to the third node under control of the voltage of the first node.
  • the writing sub-circuit is coupled to the second node, the first scan signal terminal and the data signal terminal.
  • the write sub-circuit is configured to, during the write phase, transmit the data signal received at the data signal terminal to the third scan signal under the control of the raster scan signal received from the first scan signal terminal. Two nodes.
  • the compensation sub-circuit is coupled to the first node, the third node and the compensation control terminal.
  • the compensation sub-circuit is configured to, during the writing phase, transmit the voltage of the third node to the first node under the control of a compensation signal received from the compensation control terminal.
  • the adjustment subcircuit is coupled to the second node and/or the third node, and coupled to the second scan signal terminal and the first reference voltage signal terminal.
  • the adjustment subcircuit is configured to, during the light emission adjustment phase, transmit the reference voltage signal received at the first reference voltage signal terminal to the first reference voltage signal terminal under the control of the scanning signal transmitted from the second scanning signal terminal. the second node and/or the third node.
  • the regulating subcircuit is further configured to, during the reset phase, control the scanning signal transmitted from the second scanning signal terminal, and adjust the voltage received at the first reference voltage signal terminal.
  • the reference voltage signal is transmitted to the second node to reset the second node.
  • the regulator subcircuit includes a second transistor.
  • the gate of the second transistor is coupled to the second scan signal terminal.
  • the first pole of the second transistor is coupled to the second node, and the second pole of the second transistor is coupled to the first reference voltage signal terminal.
  • the driver subcircuit includes a driver transistor.
  • the gate of the drive transistor is coupled to the first node.
  • the first electrode of the driving transistor is coupled to the second node, and the second electrode of the driving transistor is coupled to the third node.
  • the write subcircuit includes a third transistor.
  • the gate of the third transistor is coupled to the first scan signal terminal.
  • the first electrode of the third transistor is coupled to the data signal terminal, and the second electrode of the third transistor is coupled to the second node.
  • the first scan signal terminal is configured to control the third transistor to turn on at least once before controlling the first pole of the third transistor to receive the data signal from the data signal terminal.
  • the pixel driving circuit further includes a first storage sub-circuit.
  • the first memory sub-circuit is coupled to the first voltage terminal and the second node.
  • the first storage sub-circuit includes a first capacitor. The first plate of the first capacitor is coupled to the first voltage terminal, and the second plate of the first capacitor is coupled to the second node.
  • the pixel driving circuit further includes: a second energy storage subcircuit.
  • the second energy storage sub-circuit includes a second capacitor.
  • the first plate of the second capacitor is coupled to the first voltage terminal, and the second plate of the second capacitor is coupled to the first node.
  • C1 is the capacitance value of the first capacitor
  • Cst is the capacitance value of the second capacitor.
  • the pixel driving circuit further includes: a first reset subcircuit.
  • the first reset sub-circuit is coupled to the first node, the first reset signal terminal, and the first initialization signal terminal.
  • the first reset subcircuit is configured to, during the reset phase, transmit the initialization signal received at the first initialization signal terminal to the third under the control of the reset signal received from the first reset signal terminal.
  • a node is used to reset the first node.
  • the first reset sub-circuit includes a fourth transistor group including at least two fourth transistors connected in series.
  • the gates of all fourth transistors in the fourth transistor group are coupled to the first reset signal terminal, and the first electrode of the first fourth transistor in the fourth transistor group is connected to the first The node is coupled, and the second pole of the last fourth transistor in the fourth transistor group is coupled with the first initialization signal terminal.
  • the first reset signal terminal is configured to control at least one fourth transistor to turn on at least once before controlling the second pole of the at least one fourth transistor to receive the first initialization signal from the first initialization signal terminal.
  • the pixel driving circuit further includes: a light emission control subcircuit.
  • the light-emitting control sub-circuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light-emitting device; the light-emitting control sub-circuit is configured to: Under the control of the enable signal at the enable signal end, it cooperates with the drive sub-circuit to transmit the drive signal to the light-emitting device.
  • the lighting control sub-circuit includes a fifth transistor and a sixth transistor.
  • the gate of the fifth transistor is coupled to the enable signal terminal, the first pole of the fifth transistor is coupled to the first voltage signal terminal, and the second pole of the fifth transistor is coupled to the enable signal terminal.
  • the second node is coupled.
  • the gate electrode of the sixth transistor is coupled to the enable signal terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the light emitting device. coupling.
  • the pixel driving circuit further includes a second reset subcircuit.
  • the second reset sub-circuit is coupled to the second reset signal terminal, the second initialization signal terminal, and the light-emitting device; the second reset sub-circuit is configured to receive a reset signal from the second reset signal terminal. Under the control of the signal, the initialization signal received at the second initialization signal terminal is transmitted to the light-emitting device.
  • the second reset subcircuit includes a seventh transistor.
  • the gate of the seventh transistor is coupled to the second reset signal terminal, the first pole of the seventh transistor is coupled to the optical device, and the second pole of the seventh transistor is coupled to the second initialization signal. terminal coupling.
  • the second reset signal terminal and the second scan signal terminal respond to the control of the same control signal.
  • the initialization signal received by the second initialization signal terminal is inverse phase with the enable signal received by the enable signal terminal.
  • the reference voltage signal received at the first reference voltage signal terminal has a value ranging from -5V to 5V.
  • the reference voltage signal received at the first reference voltage signal terminal is approximately 2V.
  • the pixel driving circuit includes: a driving subcircuit, a writing subcircuit, a compensation subcircuit, a light emitting control subcircuit and an adjustment subcircuit.
  • the driving sub-circuit is coupled to the first node, the second node and the third node.
  • the writing sub-circuit is coupled to the second node, the first scan signal terminal and the data signal terminal.
  • the compensation sub-circuit is coupled to the first node, the third node and the compensation control terminal.
  • the light-emitting control sub-circuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light-emitting device.
  • the regulating subcircuit is coupled to the second node and/or the third node, and the second scanning signal terminal and the first reference voltage signal terminal are coupled.
  • the driving method includes: multiple light-emitting periods, and one light-emitting period includes a reset stage, a writing stage, a first light-emitting stage, a light-emitting adjustment stage and a second light-emitting stage.
  • the writing sub-circuit transmits the data signal received at the data signal terminal to the second scan signal under the control of the raster scan signal received from the first scan signal terminal. node; the driving subcircuit transmits the data signal from the second node to the third node; the compensation subcircuit transmits the voltage of the third node to the first node.
  • the adjustment subcircuit under the control of the scanning signal transmitted from the second scanning signal terminal, transmits the reference voltage signal received at the first reference voltage signal terminal to the the second node and/or the third node.
  • the lighting control sub-circuit cooperates with the driving sub-circuit under the control of the signal from the enable signal terminal and the control of the first node. , transmitting the voltage signal provided by the first voltage terminal to the light-emitting device to drive the light-emitting device to emit light.
  • the regulator subcircuit transmits the reference voltage signal received at the first reference voltage signal terminal to the second node, and performs at least one operation on the second node. reset.
  • the second node is reset multiple times.
  • the second node is reset 2 to 4 times.
  • the pixel driving circuit further includes a first reset subcircuit.
  • the first reset sub-circuit is coupled to the first node, the first reset signal terminal, and the first initialization signal terminal.
  • the first reset sub-circuit under the control of the first reset signal received from the first reset signal terminal, will The initialization signal received by the first initialization signal terminal is transmitted to the first node.
  • the adjustment subcircuit transmits the data signal from the second scan signal terminal. Under the control of the scan signal, the reference voltage signal received at the first reference voltage signal terminal is transmitted to the second node, and the second node is reset.
  • the pixel driving circuit further includes a first storage sub-circuit.
  • the first memory sub-circuit is coupled to the first voltage terminal and the second node.
  • the first storage circuit is charged.
  • the first storage circuit discharges to the second node to compensate the voltage of the second node.
  • the pixel driving circuit further includes a second reset subcircuit.
  • the second reset sub-circuit is coupled to the second reset signal terminal, the second initialization signal terminal, and the light-emitting device; the second reset signal terminal and the second scan signal terminal respond to the same control signal control.
  • the adjustment sub-circuit transmits the reference voltage signal received at the first reference voltage signal terminal to the second node; at the same time, the second reset sub-circuit , will be transmitted to the light-emitting device at the second initialization signal terminal under the control of the second reset signal received from the second reset signal terminal.
  • the pixel driving circuit further includes a light emission control subcircuit and a second reset subcircuit.
  • the light-emitting control sub-circuit is coupled to the first voltage terminal, the enable signal terminal, the second node, the third node and the light-emitting device.
  • the second reset sub-circuit is coupled to the second reset signal terminal, the second initialization signal terminal, and the light-emitting device.
  • the initialization signal received by the second initialization signal terminal is inverted with the enable signal received by the enable signal terminal.
  • the lighting control sub-circuit cooperates with the driving sub-circuit to transmit driving signals to the light-emitting device under the control of the enable signal from the enable signal terminal.
  • the second reset sub-circuit transmits the initialization signal received at the second initialization signal terminal under the control of the reset signal received from the second reset signal terminal. to the light-emitting device.
  • the display panel includes: the pixel driving circuit as described in any of the above embodiments. and a light-emitting device electrically connected to the pixel driving circuit.
  • the display panel includes: a substrate and a first gate conductive layer.
  • the first gate conductive layer is located on one side of the substrate.
  • the first gate conductive layer includes a second scanning signal line extending along a first direction.
  • the pixel driving circuit includes a second transistor and the seventh transistor.
  • the second scanning signal line includes a first part and a second part; the first part is multiplexed as the gate of the second transistor, and the second part is multiplexed as the gate of the seventh transistor.
  • the display panel further includes: a shielding layer, an active layer, a second gate conductive layer, and a first source-drain conductive layer.
  • the shielding layer is located on a side of the substrate close to the first gate conductive layer; the active layer is located between the shielding layer and the first gate conductive layer.
  • the second gate conductive layer is located on a side of the first gate conductive layer away from the active layer.
  • the first source-drain conductive layer is located on a side of the second gate conductive layer away from the active layer.
  • the pixel driving circuit includes a first capacitor. The first plate of the first capacitor and the second plate of the first capacitor are respectively located on the shielding layer, the active layer, the first gate conductive layer, the second gate conductive layer and the There are at least two layers in the first source and drain conductive layers.
  • the pixel driving circuit includes a second capacitor, a third transistor and a fifth transistor.
  • the active layer includes an active part of the third transistor, an active part of the fifth transistor, and a first plate of the first capacitor; the first plate of the first capacitor is located on the between the active part of the third transistor and the active part of the fifth transistor.
  • the second gate conductive layer includes a first plate of a second capacitor; the second plate of the first capacitor is on the same layer as the first plate of the second capacitor and is electrically connected.
  • the pixel driving circuit includes a second transistor, a third transistor, and a fifth transistor.
  • the active layer includes an active part of the third transistor, an active part of the fifth transistor, and a first plate of the first capacitor, the first plate of the first capacitor is located at between the active part of the third transistor and the active part of the fifth transistor;
  • the first source-drain conductive layer includes the first electrode of the second transistor, the second electrode of the third transistor, and a second plate of the first capacitor, the second plate of the first capacitor is located between the first pole of the second transistor and the second pole of the third transistor.
  • Figure 1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • Figure 2 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • Figure 3 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 4 is a simulation diagram of brightness changes of a light-emitting device driven by a pixel driving circuit according to some embodiments of the present disclosure
  • Figure 5 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 6 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 7 is a simulation diagram of the voltage changes of the voltage of the first node and the anode voltage of the light-emitting device in a pixel driving circuit according to some embodiments of the present disclosure in a high grayscale state;
  • Figure 8 is a simulation diagram of the voltage changes of the voltage of the first node and the anode voltage of the light-emitting device in a pixel driving circuit according to some embodiments of the present disclosure in a low gray-scale state;
  • Figure 9 is a structural diagram of another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 10 is a structural diagram of another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 11 is a structural diagram of another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 12 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 13 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 14 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 15 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 16 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • Figure 17 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in a display panel according to some embodiments of the present disclosure
  • Figures 17A to 17D are structural diagrams of some film layers in Figure 17 respectively;
  • Figure 18 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure
  • Figure 18A is a structural diagram of the active layer in Figure 18;
  • Figure 18B is a structural diagram of the occlusion layer in Figure 18;
  • Figure 19 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure.
  • Figure 19A is a structural diagram of the second gate conductive layer in Figure 19;
  • Figure 20 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure
  • Figure 20A is a structural diagram of the first gate-source conductive layer in Figure 20;
  • Figure 21 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in another display panel according to some embodiments of the present disclosure.
  • Figures 21A to 21F are structural diagrams of some film layers in Figure 21 respectively;
  • Figure 22 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure
  • Figure 23 is a circuit structure diagram of a shift register according to some embodiments of the present disclosure.
  • Figure 24 is a timing diagram of the shift register in Figure 23;
  • Figure 25 is a circuit structure diagram of yet another shift register according to some embodiments of the present disclosure.
  • Figure 26 is a timing diagram of the shift register in Figure 25;
  • Figure 27 is a circuit structure diagram of yet another shift register according to some embodiments of the present disclosure.
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • At least one of A, B and C has the same meaning as “at least one of A, B or C” and includes the following combinations of A, B and C: A only, B only, C only, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • the term “if” is optionally interpreted to mean “when” or “in response to” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrase “if it is determined" or “if [stated condition or event] is detected” is optionally interpreted to mean “when it is determined" or “in response to the determination" or “on detection of [stated condition or event]” or “in response to detection of [stated condition or event]”.
  • Example embodiments are described herein with reference to cross-sectional illustrations and/or plan views that are idealized illustrations.
  • the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes in the drawings due, for example, to manufacturing techniques and/or tolerances are contemplated.
  • example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Accordingly, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shapes of regions of the device and are not intended to limit the scope of the exemplary embodiments.
  • the transistors used in the circuit structure may be thin film transistors (Thin Film Transistor, TFT for short), field effect transistors (Metal Oxide Semiconductor, MOS for short) or other
  • thin film transistors are used as examples in the embodiments of the present disclosure for description.
  • the first electrode of each transistor used is one of the source electrode and the drain electrode
  • the second electrode of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of the transistor may be symmetrical in structure, the source and drain of the transistor may be structurally indistinguishable. That is to say, the first electrode and the third electrode of the transistor in the embodiment of the present disclosure
  • the two poles can be structurally indistinguishable.
  • the transistor is a P-type transistor
  • the first electrode of the transistor is the source electrode
  • the second electrode is the drain electrode
  • the first electrode of the transistor is the drain electrode
  • the second pole is the source.
  • nodes such as the first node and the second node do not represent actual existing components, but represent the meeting points of relevant couplings in the circuit diagram. That is to say, these nodes are formed by the relevant couplings in the circuit diagram.
  • the transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or some may be N-type transistors and the other may be P-type transistors.
  • an "effective level" refers to a level that enables a transistor to turn on. Among them, P-type transistors can be turned on under the control of low-level signals, and N-type transistors can be turned on under the control of high-level signals.
  • the P-type transistor can be turned on under the control of a low-level signal
  • the N-type transistor can be turned on under the control of a high-level signal
  • FIG. 1 is a structural diagram of a display device according to some embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a display device 300 .
  • the display device 300 includes a display panel 200 .
  • the above-mentioned display device 300 may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display device.
  • OLED Organic Light Emitting Diode, organic light emitting diode
  • the display device 300 also includes a frame, a display driver IC (Integrated Circuit), and other electronic accessories.
  • a display driver IC Integrated Circuit
  • the above-mentioned display device 300 may be any display device that displays images, whether moving (eg, video) or fixed (eg, still images), and whether text or text. More specifically, it is contemplated that the display devices of the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants, etc.
  • PDA handheld or portable computer
  • GPS receiver/navigator camera
  • MP4 video player video player
  • video camera game console
  • watch clock
  • calculator TV monitor
  • flat panel display computer monitor
  • automotive monitor e.g., odometer display, etc.
  • navigator cockpit controller and/or display
  • display of camera view e.g., display of rear view camera in vehicle
  • electronic photo electronic billboard or sign
  • projector construction Structure
  • packaging and aesthetic structure for example, for the display of an image of a piece of jewelry
  • Figure 2 is a structural diagram of a display panel according to some embodiments of the present disclosure.
  • the above-mentioned display panel 200 includes a substrate 000 , a plurality of pixel driving circuits 100 disposed on one side of the substrate 000 , and a plurality of pixel driving circuits 100 disposed far away from the substrate 000 . Multiple light-emitting devices O on one side. A plurality of pixel driving circuits 100 are coupled to a plurality of light emitting devices O.
  • the above-mentioned substrate 000 may be a flexible substrate or a rigid substrate.
  • the material of the substrate 000 may be dimethylsiloxane, PI (Polyimide, polyimide), PET (Polyethylene Terephthalate, polyethylene terephthalate). Alcohol ester) and other highly elastic materials.
  • the material of the substrate 000 may be glass or the like.
  • the above-mentioned plurality of pixel driving circuits 100 and the plurality of light-emitting devices O may be coupled in one-to-one correspondence.
  • one pixel driving circuit 100 may be coupled with multiple light-emitting devices O, or multiple pixel driving circuits 100 may be coupled with one light-emitting device O.
  • the present disclosure schematically illustrates the structure of the display panel 200 by taking a pixel driving circuit 100 coupled to a light-emitting device O as an example.
  • the pixel driving circuit 100 may generate a driving signal.
  • Each light-emitting device O can emit light under the driving action of the driving signal generated by the corresponding pixel driving circuit 100.
  • the light emitted by the multiple light-emitting devices O cooperates with each other, so that the display panel 200 realizes the display function.
  • the above-mentioned light-emitting device O may be an OLED light-emitting device.
  • FIG. 3 is a structural diagram of a pixel driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is a simulation diagram of brightness changes of a light-emitting device driven by a pixel driving circuit according to some embodiments of the present disclosure.
  • some embodiments of the present disclosure provide a pixel driving circuit 100 , including: a driving sub-circuit 10 , a writing sub-circuit 20 and a compensation sub-circuit 30 .
  • the driving sub-circuit 10 is coupled to the first node N1, the second node N2 and the third node N3.
  • the driving subcircuit 10 is configured to transmit the voltage from the second node N2 to the third node N3 under the control of the voltage of the first node N1.
  • the compensation sub-circuit 30 is coupled to the first node N1, the third node N3 and the compensation control terminal G0.
  • the compensation sub-circuit 30 is configured to, during the writing phase, transmit the voltage of the third node N3 to the first node N1 under the control of the compensation signal received from the compensation control terminal G0, thereby controlling the driving sub-circuit to turn on.
  • the compensation subcircuit 30 includes a first transistor group T1.
  • the first transistor group T1 includes at least two first transistors T11 connected in series.
  • the first transistor T11 may be an oxide semiconductor thin film transistor.
  • the first transistor group T1 includes two first transistors T11 connected in series as an example.
  • the first first transistor is T11A
  • the second (last) first transistor is T11B. It can be understood that in other embodiments, the first transistor group T1 may include first transistors T11 with other values connected in series.
  • the gates of all the first transistors T11 in the first transistor group T1 are coupled to the first scan signal terminal Gate1.
  • the first electrode of the first first transistor T11A in the first transistor group T1 is coupled to the first node N1
  • the second electrode of the last first transistor T11B in the first transistor group T1 is coupled to the third node N3.
  • a fourth node N4 is formed between the second electrode of the first first transistor T11A in the first transistor group T1 and the first electrode of the second first transistor T11B in the first transistor group T1.
  • the writing subcircuit 20 is coupled to the second node N2 , the first scanning signal terminal Gate1 and the data signal terminal Data.
  • the writing subcircuit 20 is configured to, when writing In the stage, under the control of the raster scanning signal received from the first scanning signal terminal Gate1, the data signal received at the data signal terminal Gate1 is transmitted to the second node N2.
  • the effective signal of the raster scanning signal received by the first scanning signal terminal Gate1 and the effective signal of the compensation signal received by the compensation control terminal G0 are at least partially simultaneous.
  • the effective signal of the raster scanning signal received by the first scanning signal terminal Gate1 is synchronized with the effective signal of the compensation signal received by the compensation control terminal G0.
  • the raster scanning signal received by the first scanning signal terminal Gate1 is multiplexed into the compensation signal received by the compensation control terminal G0.
  • FIG. 3 takes the raster scanning signal received by the first scanning signal terminal Gate1 as an example of multiplexing the compensation signal received by the compensation control terminal G0 as an example.
  • the writing sub-circuit 20 can be turned on under the control of the raster scanning signal received by the first scanning signal terminal Gate1, so that the writing sub-circuit 20 transmits the data signal received at the data signal terminal Data to the second node. N2, the data signal becomes a compensation signal after passing through the driving subcircuit 10.
  • the compensation signal is transmitted to the first node N1 through the compensation subcircuit 30, that is, the writing of the compensation signal is completed, and the threshold voltage Vth of the driving subcircuit 10 is also achieved. compensation.
  • each sub-pixel in the display panel 200 is driven by multiple thin film transistors (TFTs) to emit light.
  • TFT thin film transistors
  • TFT driving technology can improve display speed, contrast and brightness, and improve resolution.
  • TFT has a hysteresis effect.
  • the hysteresis effect of TFT is an uncertainty in the electrical characteristics of TFT under a certain bias voltage. That is, the current flowing through the TFT is not only related to the current bias voltage, but also related to the current bias voltage.
  • the hysteresis effect of TFT is related to the gate dielectric of TFT, semiconductor material and the interface state trap between the two. During the light-emitting stage, the hysteresis effect of TFT will cause the current to decrease within a frame, which is perceived as flicker by the human eye. This phenomenon affects the display quality of the display panel 200 .
  • One lighting cycle includes a refresh frame and at least one hold frame.
  • One lighting cycle is one display frame, that is, one display screen.
  • the refresh frame includes a reset phase, a writing phase and a first lighting phase.
  • the holding frame includes a lighting adjustment phase and a second lighting phase.
  • the inventor of the present disclosure has found through research that in the refresh frame, the voltages of the first node N1 and the fourth node N4 are basically the same; in the hold frame, the voltage of the fourth node N4 is pulled up by the voltage of the first scan signal terminal Gate1, resulting in the fourth The voltage of node N4 may be greater than the voltage of first node N1.
  • the fourth node N4 When the voltage of the fourth node N4 is greater than the voltage of the first node N1, the fourth node N4 will leak current to the first node N1, which will cause the voltage of the first node N1 to be unstable.
  • the brightness retention rate of the light-emitting device within one frame is lowered. When the brightness retention rate within one frame is reduced to a range that is observable by the human eye, screen flickering is likely to occur.
  • the pixel driving circuit 100 includes: a driving subcircuit 10 , a writing subcircuit 20 and a compensation subcircuit 30 .
  • This disclosure conducts simulation verification on the voltage of the first node N1 and the voltage of the fourth node N4, and obtains the calculation results as shown in Figure 4 and Table 1.
  • each light-emitting period shown in Table 1 includes three holding frames.
  • the data of the last holding frame in a light-emitting period is used as an example for illustration.
  • Table 1 is a table of changes in the voltage of the first node N1 in the pixel driving circuit 100 and the voltage of the anode of the light-emitting device O.
  • the first transistor group T1 includes at least two serially connected A transistor T11 is turned on, and the voltage of the fourth node N4 is equal to the voltage of the first node N1.
  • the first transistor group T1 includes at least two series connected The first transistor T11 is turned off.
  • the scanning signal provided at the first scanning signal terminal Gate1 When the voltage changes from low voltage to high voltage, the voltage of the fourth node N4 is pulled up under the coupling effect of the capacitor Cgs or the capacitor Cgd.
  • FIG. 5 is a structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure.
  • FIG. 6 is a structural diagram of a pixel driving circuit according to yet another embodiment of the present disclosure.
  • a pixel driving circuit 100 continue to refer to FIG. 3, FIG. 5 and FIG. 6, and further include an adjustment sub-circuit 40.
  • the adjustment subcircuit 40 is coupled to the second node N2 and/or the third node N3, and is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the adjustment subcircuit 40 is configured to, in the light emission adjustment stage , under the control of the scan signal transmitted from the second scan signal terminal Gate2, the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2 and/or the third node N3.
  • transmitting the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 and/or the third node N3 includes the following three methods:
  • the first type Please continue to refer to Figure 3, and transmit the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2.
  • the adjustment subcircuit 40 is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2 under the control of the scanning signal transmitted from the second scanning signal terminal Gate2. Since no data refresh is performed in the previous stage of the light emission adjustment stage, the potential of the first scanning signal terminal Gate1 is relatively high.
  • the voltage of the fourth node N4 is pulled up by the voltage of the first scan signal terminal Gate1, so that the voltage of the fourth node N4 may be greater than the voltage of the first node N1.
  • the voltage of the second node N2 is adjusted using the reference voltage signal received at the first reference voltage signal terminal Vinit3. Due to the gate-source capacitance existing between the gate and the source of the driving transistor of the driving sub-circuit 10, when the voltage of the second node N2 changes, the voltage of the first node N1 changes synchronously under the coupling effect of the gate-source capacitance, Therefore, the influence of the fourth node N4 on the voltage of the first node N1 can be compensated.
  • the voltage of the first node N1 is in dynamic balance, improving the potential stability of the first node N1, making the brightness retention rate of the light-emitting device O higher in one frame, improving the brightness change in the next light-emitting stage, and improving The flickering phenomenon of the light-emitting device O and the display panel 200 is eliminated.
  • Second type Please continue to refer to FIG. 5 and transmit the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the third node N3.
  • the adjustment subcircuit 40 is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the third node N3 under the control of the scanning signal transmitted from the second scanning signal terminal Gate2. Since no data refresh is performed in the previous stage of the light emission adjustment stage, the potential of the first scanning signal terminal Gate1 is relatively high.
  • the voltage of the fourth node N4 is pulled up by the voltage of the first scan signal terminal Gate1, so that the voltage of the fourth node N4 may be greater than the voltage of the first node N1. Since no data refresh is performed in the previous stage of the light emission adjustment stage, the potential of the first scanning signal terminal Gate1 is relatively high.
  • the voltage of the fourth node N4 is pulled up by the voltage of the first scan signal terminal Gate1, so that the voltage of the fourth node N4 may be greater than the voltage of the first node N1.
  • the voltage of the third node N3 is adjusted using the reference voltage signal received at the first reference voltage signal terminal Vinit3. Due to the gate-drain capacitance existing between the gate and drain of the driving transistor of the driving sub-circuit 10, when the voltage of the third node N3 changes, the voltage of the first node N1 changes synchronously under the coupling effect of the gate-drain capacitance, Therefore, the influence of the fourth node N4 on the voltage of the first node N1 can be compensated.
  • the voltage of the first node N1 is in dynamic balance, the potential stability of the first node N1 is improved, the brightness retention rate of the light-emitting device O within one frame is higher, and the brightness change in the next light-emitting stage is improved.
  • the flickering phenomenon of the light-emitting device O and the display panel 200 is improved.
  • the adjustment subcircuit 40 is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2 and the third node N3 under the control of the scan signal transmitted from the second scan signal terminal Gate2.
  • the voltage of the second node N2 and the third node N3 is adjusted using the reference voltage signal received at the first reference voltage signal terminal Vinit3. Due to the gate-to-drain capacitance present between the gate and drain of the drive transistor of the drive subcircuit 10, there is a gate-source capacitance between the gate and the source. When the voltages of the second node N2 and the third node N3 change, under the coupling effect of the gate-source capacitance and the gate-drain capacitance, the voltage of the first node N1 changes synchronously, thereby compensating the impact of the fourth node N4 on the first node N1. influence of voltage.
  • the voltage of the first node N1 is in dynamic balance, the potential stability of the first node N1 is improved, the brightness retention rate of the light-emitting device O within one frame is higher, and the brightness change in the next light-emitting stage is improved.
  • the flickering phenomenon of the light-emitting device O and the display panel 200 is improved.
  • the adjustment subcircuit is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the scanning signal transmitted from the second scanning signal terminal Gate2 Under the control of the signal, the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2 and/or the third node N3.
  • the voltage of the second node N2 and the third node N3 is adjusted using the reference voltage signal received at the first reference voltage signal terminal Vinit3.
  • the gate and drain of the driving transistor of the driving subcircuit 10 have capacitances, when the voltage at the gate-source position of the driving transistor changes, the voltage of the gate can be adjusted synchronously under the action of capacitive coupling, that is, the voltage of the gate can be adjusted synchronously.
  • Figure 7 is a simulation diagram of the voltage changes of the first node voltage and the anode voltage of the light-emitting device in a pixel driving circuit according to some embodiments of the present disclosure in a high gray scale state.
  • Figure 8 is a simulation diagram of the voltage changes of the first node voltage and the anode voltage of the light-emitting device in a pixel driving circuit according to some embodiments of the present disclosure in a low gray scale state.
  • the display panel 200 includes a low gray level (eg, G0, G15, G30, etc.) state and a high gray level (eg, G110, G220, G255) state.
  • a low gray level eg, G0, G15, G30, etc.
  • a high gray level eg, G110, G220, G255
  • the voltage of the first node N1 in the pixel driving circuit 100 is higher than the voltage of the first node N1 in the pixel driving circuit 100 in the high grayscale state.
  • Some embodiments of the present disclosure perform simulation verification on the high gray-scale state and when the pixel driving circuit 100 includes the adjustment sub-circuit 40, the voltage of the first node N1 and the voltage of the anode of the light-emitting device O are simulated and verified; and for the high gray-scale state, When the pixel driving circuit 100 does not include a regulating sub-circuit, the voltage of the first node N1 and the voltage of the anode of the light-emitting device O are simulated and verified, and the calculation results are shown in Figure 7 .
  • Some embodiments of the present disclosure perform simulation verification on the voltage of the first node N1 and the voltage of the anode of the light-emitting device O when the pixel driving circuit 100 includes the adjustment sub-circuit 40 in a low gray-scale state.
  • simulation verification was performed on the voltage of the first node N1 and the voltage of the anode of the light-emitting device O when the pixel driving circuit 100 does not include an adjustment subcircuit in the low gray-scale state, and the calculation results are shown in Figure 8 . Referring to Figures 7 and 8, it is obvious that the difference between the voltage of the first node N1 and the voltage of the fourth node N4 is more obvious in the high gray scale state than in the low gray scale state.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 has a value ranging from -5V to 5V.
  • the voltage of the second node N2 is adjusted through the reference voltage signal received at the first reference voltage signal terminal Vinit3, and the voltage of the first node N1 is adjusted using capacitive coupling. Thereby, the potential stability of the first node N1 is improved, the brightness maintenance rate of the light-emitting device O within one frame is higher, and the flickering phenomenon of the light-emitting device O and the display panel 200 is improved.
  • the voltage value of the first node N1 in the pixel driving circuit 100 needs to be set lower in order to adjust the opening of the driving sub-circuit 10.
  • the difference between the voltage of the first node N1 and the voltage of the fourth node N4 is larger, so that the brightness of the light-emitting device within one frame is maintained. rate is lower. Therefore, the value range of the reference voltage signal received at the first reference voltage signal terminal Vinit3 is set to -5V ⁇ 5V.
  • the present disclosure conducts simulation verification on the voltage of the first node N1 and the voltage of the anode of the light-emitting device O,
  • the calculated results are shown in Table 2.
  • the pixel driving circuit 100 is not provided with the adjustment sub-circuit 40 .
  • the pixel driving circuit 100 includes an adjustment subcircuit 40 .
  • the change in the voltage of the first node N1 is 0.0713V, and the light emitting
  • the change in the anode voltage of device O is 0.064V.
  • the adjustment sub-circuit 40 is provided in the pixel driving circuit 100, the voltage change of the first node N1 can be reduced to 0.047V, reducing the voltage change by 0.027V, and the voltage change of the light-emitting device O can be reduced to 0.039V, reducing the voltage change. 0.025V.
  • the voltage of the first node N1 can be relatively stabilized, the brightness retention rate of the light-emitting device O can be improved, and the flickering phenomenon of the display panel 200 can be improved.
  • Table 2 is a table of changes in the voltage of the first node N1 and the anode of the light-emitting device O in the high gray scale state.
  • the voltage value of the first node N1 in the pixel driving circuit 100 needs to be set higher in order to adjust the opening of the driving sub-circuit 10. .
  • the value range of the reference voltage signal received at the first reference voltage signal terminal Vinit3 is set to -5V ⁇ 5V.
  • the reference voltage signal is written into the second node N2.
  • the potential difference between the second node N2 and the first node N1 is small and will not significantly affect the potential of the first node N1, that is, it will not greatly affect the first node N1.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is -5V, -3V, -1V, 1V, 3V or 5V. It can be understood that in other embodiments, the reference voltage signal received at the first reference voltage signal terminal Vinit3 may be other values in the range of -5V to 5V.
  • the present disclosure conducts simulation verification on the voltage of the first node N1 and the voltage of the anode of the light-emitting device O,
  • the calculated results are shown in Table 3.
  • the pixel driving circuit 100 is not provided with the adjustment sub-circuit 40 .
  • the pixel driving circuit 100 includes an adjustment subcircuit 40 .
  • Table 3 is a table of changes in the voltage of the first node N1 and the anode of the light-emitting device O in the low gray scale state.
  • the pixel driving circuit 100 sets the adjustment subcircuit 40 and sets the value range of the reference voltage signal received at the first reference voltage signal terminal Vinit3 to -5V to 5V. It can not only effectively improve the stability of the voltage of the first node N1 in the pixel driving circuit 100 in the high gray level state, but also maintain the stability of the voltage of the first node N1 in the pixel driving circuit 100 in the low gray level state. Therefore, no matter what state the display panel 200 is in, the flickering phenomenon can be effectively improved.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is approximately 2V.
  • the voltage value of the reference voltage signal received at the first reference voltage signal terminal Vinit3 may have a certain deviation.
  • the deviation value can be ⁇ 1, ⁇ 0.5, etc.
  • the pixel driving circuit 100 For the high gray scale state, and when the reference voltage signal received at the first reference voltage signal terminal Vinit3 is 2V, some embodiments of the present disclosure conduct simulation verification on the voltage of the first node N1 and the voltage of the anode of the light-emitting device O, The calculation results are shown in Table 4. Among them, before improvement, it is shown that the pixel driving circuit 100 is not provided with the adjustment sub-circuit 40 . After improvement, the pixel driving circuit 100 includes an adjustment subcircuit 40 .
  • Table 4 is a table of changes in the voltage of the second first node N1 and the anode of the light-emitting device O in the high grayscale state.
  • the above example only takes the reference voltage signal received at the first reference voltage signal terminal Vinit3 as 2V and 4V as an example.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 may be other values in the range of -5V to 5V.
  • the adjustment subcircuit 40 is further configured to, during the reset phase, control the scanning signal transmitted from the second scanning signal terminal Gate2 to adjust the voltage at the first reference voltage signal terminal.
  • the reference voltage signal received at Vinit3 is transmitted to the second node N2, and the second node N2 is reset.
  • the regulator sub-circuit 40 can be turned on under the control of the scanning signal transmitted by the second scanning signal terminal Gate2, so that the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second Node N2 resets the second node N2. It can effectively offset the hysteresis effect of the driving transistor in the driving subcircuit 10, improve the brightness retention rate within one frame, and thereby improve the flickering phenomenon of the display panel 200 at low frequencies.
  • FIG. 9 is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the regulating subcircuit 40 includes a second transistor T2.
  • the gate electrode of the second transistor T2 is coupled to the second scan signal terminal Gate2, the first electrode of the second transistor T2 is coupled to the second node N2, and the second electrode of the second transistor T2 is coupled to the first reference voltage signal terminal Vinit3. catch.
  • the scan signal transmitted by the second scan signal terminal Gate2 is a low level (effective level) signal
  • the second transistor T2 included in the adjustment subcircuit 40 transmits the low level signal by the second scan signal terminal Gate2. It is turned on under the control of the level signal.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2, and the second node N2 is reset. It can effectively offset the hysteresis effect of the driving transistor in the driving subcircuit 10, improve the brightness retention rate within one frame, and thereby improve the flickering phenomenon of the display panel 200 at low frequencies.
  • the driving sub-circuit 10 includes a driving transistor TD.
  • the gate electrode of the driving transistor TD is coupled to the first node N1, the first electrode of the driving transistor DT is coupled to the second node N2, and the second electrode of the driving transistor DT is coupled to the third node N3.
  • the driving transistor TD can be turned on under the control of the voltage of the first node N1 to transmit the electrical signal (such as a data signal) from the second node N2 transmitted to the third node N3.
  • the “effective level” in this disclosure refers to a level that enables the transistor to turn on.
  • the “effective level” is high level; when the transistor is a P-type transistor, the “effective level” is low level.
  • the writing sub-circuit 20 includes a third transistor T3.
  • the gate electrode of the third transistor T3 is coupled to the first scan signal terminal Gate1, the first electrode of the third transistor T3 is coupled to the data signal terminal Data, and the second electrode of the third transistor T3 is coupled to the second node N2.
  • the scanning signal transmitted by the first scanning signal terminal Gate1 is a low-level (effective level) signal
  • the third transistor T3 included in the writing sub-circuit 20 transmits a low-level signal at the first scanning signal terminal Gate1 is turned on under the control of , at this time, the data signal received at the data signal terminal Data is transmitted to the second node N2.
  • the data signal becomes a compensation signal after passing through the driving sub-circuit 10, and the compensation signal is transmitted to the first node N1 through the compensation sub-circuit 30, that is, the writing of the compensation signal is completed, and the compensation of the threshold voltage Vth is also realized.
  • the brightness maintenance rate within one frame is improved, thereby improving the flickering phenomenon of the display panel 200 at low frequencies.
  • the first scan signal terminal Gate1 is configured to control the third transistor T3 to turn on before controlling the first pole of the third transistor T3 to receive the data signal of the data signal terminal Data. At least 1 time.
  • the first pole of the third transistor T3 is reset at least once in order to improve the stability of the drive transistor TD included in the drive sub-circuit 10 .
  • the first scan signal terminal Gate1 is configured to control the third transistor T3 to turn on once before controlling the first pole of the third transistor T3 to receive the data signal from the data signal terminal Data. It can be understood that in other embodiments, the first scan signal terminal Gate1 is configured to control the third transistor T3 to turn on twice before controlling the first pole of the third transistor T3 to receive the data signal from the data signal terminal Data. Or more than twice.
  • the pixel driving circuit 100 further includes a second energy storage sub-circuit 60 .
  • the second energy storage sub-circuit 60 includes a second capacitor Cst.
  • the first plate of the second capacitor Cst is coupled to the first voltage terminal VDD, and the second plate of the second capacitor Cst is coupled to the first node N1.
  • the third transistor T3 included in the writing sub-circuit 20 is turned on under the control of the low-level signal transmitted by the first scan signal terminal Gate1.
  • the data signal received at the data signal terminal Data is transmitted to the second Node N2; at the same time, the data signal received at the data signal terminal Data is also transmitted to the second capacitor Cst to charge the second capacitor Cst.
  • the first transistor group T1 included in the compensation subcircuit 30 is turned on under the control of the low-level signal transmitted by the first scanning signal terminal Gate1.
  • the data signal received at the second node N2 is transmitted to the first node N1, and the The first node N1 performs compensation.
  • the potential of the first node N1 gradually rises to Vdata+Vth.
  • Vdata is the voltage value of the data signal provided by the data signal terminal Data
  • Vth is the threshold voltage of the driving transistor TD in the driving sub-circuit 10 .
  • FIG. 10 is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the pixel driving circuit 100 further includes a first storage sub-circuit 50 .
  • the first memory sub-circuit 50 is coupled to the first voltage terminal VDD and the second node N2.
  • the first storage sub-circuit 50 is configured to store and maintain the voltage of the second node N2.
  • the third transistor T3 included in the writing sub-circuit 20 is turned on under the control of the low-level signal transmitted by the first scan signal terminal Gate1.
  • the data signal received at the data signal terminal Data is transmitted to the second Node N2 also charges the first storage sub-circuit 50 at the same time.
  • the first storage sub-circuit 50 can maintain the voltage of the second node N2 to ensure the stability of the driving transistor TD included in the driving sub-circuit 10 .
  • the first storage sub-circuit 50 includes a first capacitor C1, a first plate of the capacitor is coupled to the first voltage terminal VDD, and a second plate of the first capacitor C1 is coupled to the second node N2.
  • the third transistor T3 included in the writing sub-circuit 20 is turned on under the control of the low-level signal transmitted by the first scan signal terminal Gate1.
  • the data signal received at the data signal terminal Data is transmitted to the second Node N2; at the same time, the data signal received at the data signal terminal Data is also transmitted to the first capacitor C1 to charge the first capacitor C1.
  • the regulator sub-circuit 40 is turned on under the control of the low-level signal transmitted from the second scan signal terminal Gate2
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2.
  • the regulating subcircuit 40 is turned off under the control of the high-level signal transmitted from the second scanning signal terminal Gate2, at this time, the first capacitor C1 can maintain the voltage of the second node N2, thereby maintaining the voltage of the first node N1. stability.
  • the pixel driving circuit 100 includes a first capacitor C1 and a second capacitor Cst.
  • C1 is the capacitance value of the first capacitor C1
  • Cst is the capacitance value of the second capacitor Cst.
  • the first capacitor C1 When the capacitance value C1 of the first capacitor C1 is equal to or approaches When , the first capacitor C1 can maintain the voltage of the second node N2, and at the same time, can prevent the first capacitor C1 from affecting the second capacitor Cst, and better maintain the stability of the first node N1.
  • the capacitance value C1 of the first capacitor C1 is equal to or approaches When , the influence of the first capacitor C1 on the second capacitor Cst can be prevented, and at the same time, the voltage of the second node N2 can be better stably maintained, thereby stabilizing the voltage of the first node N1.
  • the pixel driving circuit 100 further includes a first reset sub-circuit 70 .
  • the first reset sub-circuit 70 is coupled to the first node N1, the first reset signal terminal Reset1, and the first initialization signal terminal Vinit1; the first reset sub-circuit 70 is configured to, during the reset phase, receive the signal from the first reset signal. Under the control of the reset signal received at the terminal Reset1, the initialization signal received at the first initialization signal terminal Vinit1 is transmitted to the first node N1 to reset the first node N1.
  • the first reset sub-circuit 70 transmits the initialization signal received at the first initialization signal terminal Vinit1 to the first node N1 under the control of the reset signal received from the first reset signal terminal Reset1, to The first node N1 is reset to improve the stability of the driving transistor TD included in the driving sub-circuit 10 .
  • the first reset sub-circuit 70 is used to reset the first node N1
  • the adjustment sub-circuit 40 is used to reset the second node N2.
  • the initial state of the driving transistor TD before the writing stage is fixed, so that the driving transistor TD is in a stable state during the writing stage, and the hysteresis effect of the driving transistor TD is greatly improved.
  • the first reset sub-circuit 70 includes a fourth transistor group T4 , and the fourth transistor group T4 includes at least two fourth transistors T41 connected in series.
  • the fourth transistor group T4 includes two fourth transistors T41 connected in series as an example.
  • the first fourth transistor T41 is T41A
  • the second (last) fourth transistor T41 is T41B. It can be understood that in other embodiments, the fourth transistor group T4 may include fourth transistors T41 with other values connected in series.
  • the gates of all the fourth transistors T41 in the fourth transistor group T4 are coupled to the first reset signal terminal Reset1, and the first electrode of the first fourth transistor T41A in the fourth transistor group T4 is coupled to the first node N1. Then, the second pole of the last fourth transistor T41B in the fourth transistor group T4 is coupled to the first initialization signal terminal Vinit1.
  • the fourth transistor T41 included in the first reset sub-circuit 70 is turned on under the control of a low-level signal (valid signal) received from the first reset signal terminal Reset1, which is received and transmitted at the first initialization signal terminal.
  • the initialization signal received by Vinit1 is sent to the first node N1, and the first node N1 is reset.
  • the first reset signal terminal is configured to control at least one fourth transistor T41 to turn on at least once before controlling the second pole of at least one fourth transistor T41 to receive the first initialization signal from the first initialization signal terminal Vinit1.
  • the fourth transistor T41 is turned on at least once to reset the gate of the fourth transistor T41 so as to improve the stability of the fourth transistor T41 included in the first reset sub-circuit 70 .
  • the fourth transistor group T4 includes at least two fourth transistors T41 connected in series, the risk of leakage of the first node N1 from the fourth transistor T41 can be reduced, which is more conducive to ensuring the stability of the voltage of the first node N1 sex.
  • the pixel driving circuit 100 further includes a light emission control sub-circuit 80 .
  • the light-emitting control sub-circuit 80 is coupled to the first voltage terminal VDD, the enable signal terminal EM1, the second node N2, the third node N3 and the light-emitting device O.
  • the light-emitting control sub-circuit 80 is configured to cooperate with the driving sub-circuit 10 to transmit the driving signal to the light-emitting device O under the control of the enable signal from the enable signal terminal EM1.
  • the lighting control sub-circuit 80 cooperates with the driving sub-circuit 10 to transmit the electrical signal provided by the first voltage terminal VDD to the second voltage under the control of a low-level (effective level) signal from the enable signal terminal EM1.
  • the node N2 and the second node N2 transmit the electrical signal to the third node N3, and the third node N3 continues to transmit the electrical signal to the light emitting device O.
  • This electrical signal can cooperate with the electrical signal provided by the second voltage signal terminal Vss coupled to the light-emitting device O to drive the light-emitting device O to emit light normally to achieve display.
  • the lighting control sub-circuit 80 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is coupled to the enable signal terminal EM1, the first electrode of the fifth transistor T5 is coupled to the first voltage signal VDD terminal, and the second electrode of the fifth transistor T5 is coupled to the second node.
  • the gate of the sixth transistor T6 is coupled to the enable signal terminal EM1, the first electrode of the sixth transistor T6 is coupled to the third node N3, and the second electrode of the sixth transistor T6 is coupled to the light emitting device O.
  • the fifth transistor T5 and the sixth transistor T6 included in the light emission control sub-circuit 80 are turned on under the control of a low-level (effective level) signal from the enable signal terminal EM1, and the driving sub-circuit 10
  • the included driving transistor TD When the included driving transistor TD is turned on, the voltage signal provided by the first voltage signal VDD terminal can be transmitted to the light-emitting device O through the second node N2, the driving transistor TD, and the third node N3 in sequence.
  • the electrical signal can be connected to the light-emitting device O.
  • the electrical signals provided by the second voltage signal terminal Vss coupled to O cooperate with each other to drive the light-emitting device O to emit light normally to achieve display.
  • the pixel driving circuit 100 further includes a second reset sub-circuit 90 .
  • the second reset sub-circuit 90 is coupled to the second reset signal terminal Reset2, the second initialization signal terminal Vinit2, and the light-emitting device O; the second reset sub-circuit is configured to receive the reset signal from the second reset signal terminal Reset2. Under the control of , the initialization signal received at the second initialization signal terminal Vinit2 is transmitted to the light-emitting device O.
  • the second reset sub-circuit 90 transmits the initialization signal received at the second initialization signal terminal Vinit2 to the light-emitting device O under the control of the reset signal received from the second reset signal terminal Reset2, and the anode of the light-emitting device O Reset is performed to improve the stability of the light-emitting device O.
  • the second reset sub-circuit 90 includes a seventh transistor T7.
  • the gate electrode of the seventh transistor T7 is coupled to the second reset signal terminal Reset2, the first electrode of the seventh transistor T7 is coupled to the optical device O, and the second electrode of the seventh transistor T7 is coupled to the second initialization signal terminal Vinit2.
  • the seventh transistor T7 included in the second reset sub-circuit 90 is turned on under the control of the low level (effective level) signal received from the second reset signal terminal Reset2, and receives the second initialization signal terminal Vinit2.
  • the initialization signal is transmitted to the light-emitting device O.
  • the initialization signal received by the second initialization signal terminal Vinit2 can be a low-level signal, so that the signal can be used to reset the anode of the light-emitting device O and improve the stability of the light-emitting device O.
  • FIG. 11 is a structural diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the second reset signal terminal Reset2 and the second scan signal terminal Gate2 respond to the control of the same control signal.
  • FIG. 11 takes the second scanning signal terminal Gate2 being multiplexed as the second reset signal terminal Reset2 as an example.
  • the second scanning signal terminal Gate2 is multiplexed as the second reset signal terminal Reset2, which can simplify the structure of the pixel driving circuit 100 and help reduce the layout difficulty in the display panel 200.
  • the second reset signal terminal Reset2 and the second scanning signal terminal Gate2 respond to the control of the same control signal.
  • the second reset signal terminal Reset2 can reset the anode of the light-emitting device O multiple times within one frame, further improving the Stability of light-emitting device O.
  • the initialization signal received by the second initialization signal terminal Gate2 is inverted with the enable signal received by the enable signal terminal EM1 .
  • the initialization signal received by the second initialization signal terminal Gate2 is inverse phase with the enable signal received by the enable signal terminal EM1. It can be understood that the initialization signal received by the second initialization signal terminal Gate2 and the enable signal received by the enable signal terminal EM1 are alternately set.
  • the initialization signal received by the second initialization signal terminal Gate2 is a low-level signal, and at this time, the enable signal received by the enable signal terminal EM1 is a high-level signal.
  • the initialization signal received by the second initialization signal terminal Gate2 is a high-level signal, and at this time, the enable signal received by the enable signal terminal EM1 is a low-level signal.
  • the second initialization signal terminal Gate2 may be a signal terminal EM2 that is inverted from the enable signal received by the enable signal terminal EM1.
  • the signal terminal EM2 and the second initialization signal terminal Gate2 are the same signal terminal.
  • the signal terminal EM2 can be improved from the enable signal terminal EM1, and the internal structure of the display panel 200 will be described in detail later. Therefore, the above structure can also simplify the structure of the pixel driving circuit 100 and help reduce the layout difficulty in the display panel 200 .
  • Some embodiments of the present disclosure also provide a driving method for a pixel driving circuit, which is applied to the pixel driving circuit 100 in any of the above embodiments.
  • Figure 12 is a timing diagram of a pixel driving circuit according to some embodiments of the present disclosure. In some embodiments, see Figure 12, as well as Figure 9.
  • the pixel driving circuit 100 includes: a driving subcircuit 10, a writing subcircuit 20, a compensation subcircuit 30, a light emission control subcircuit and an adjustment subcircuit 40.
  • the driving sub-circuit 10 is coupled to the first node N1, the second node N2 and the third node N3.
  • the writing sub-circuit 20 is coupled to the second node N2, the first scanning signal terminal Gate1 and the data signal terminal Data.
  • the compensation sub-circuit 30 is coupled to the first node N1, the third node N3, and the compensation control terminal G0.
  • the light-emitting control sub-circuit 80 is coupled to the first voltage terminal VDD, the enable signal terminal EM1, the second node N2, the third node N3 and the light-emitting device O.
  • the adjustment subcircuit 40 is coupled to the second node N2 and/or the third node N3, and is coupled to the second scanning signal terminal Gate2 and the first reference voltage signal terminal Vinit3.
  • the driving method includes: multiple light emission periods F.
  • One lighting period F (one frame) includes a refresh frame F1 and at least one holding frame F2.
  • One lighting cycle (one frame) is one display frame, that is, one display screen.
  • the refresh frame F1 includes a reset phase P1, a writing phase P2, and a first lighting phase P3.
  • the holding frame F2 includes a lighting adjustment phase P4 and a second lighting phase P5.
  • the writing subcircuit 20 transmits the data signal received at the data signal terminal Data to the second node N2 under the control of the raster scanning signal received from the first scanning signal terminal Gate1; the driving subcircuit 10 transmits the data signal from the second node N2 to the third node N3; the compensation subcircuit 30 transmits the voltage of the third node N3 to the first node N1.
  • the effective signal of the raster scanning signal received by the first scanning signal terminal Gate1 and the effective signal of the compensation signal received by the compensation control terminal G0 are at least partially simultaneous.
  • the effective signal of the raster scanning signal received by the first scanning signal terminal Gate1 is synchronized with the effective signal of the compensation signal received by the compensation control terminal G0.
  • the raster scanning signal received by the first scanning signal terminal Gate1 is multiplexed into the compensation signal received by the compensation control terminal G0.
  • the drive signal is transmitted to the light-emitting device O, and the voltage signal provided by the first voltage terminal VDD is transmitted to the light-emitting device O to drive the light-emitting device O to emit light.
  • the adjustment subcircuit 40 under the control of the scan signal transmitted from the second scan signal terminal Gate2, transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 and/or Or the third node N3.
  • the adjustment subcircuit 40 transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 under the control of the scan signal transmitted from the second scan signal terminal Gate2.
  • the adjustment subcircuit 40 transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the third node N3 under the control of the scan signal transmitted from the second scan signal terminal Gate2.
  • the adjustment subcircuit 40 transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 and the third node under the control of the scan signal transmitted from the second scan signal terminal Gate2. N3.
  • the light-emitting control sub-circuit 80 cooperates with the driving sub-circuit 10 to control the signal from the enable signal terminal EM1 and the first node N1.
  • a voltage signal provided by a voltage terminal is transmitted to the light-emitting device O to drive the light-emitting device O to emit light.
  • the adjustment sub-circuit 40 is turned on under the control of the low-level (effective level) signal transmitted from the second scanning signal terminal Gate2.
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2 and/or the third node N3. Since data refresh is not performed during the first light-emitting phase P3, the potential of the first scanning signal terminal Gate1 is relatively high.
  • the voltage of the fourth node N4 is pulled up by the voltage of the first scan signal terminal Gate1, so that the voltage of the fourth node N4 may be greater than the voltage of the first node N1.
  • the voltage of the second node N2 and/or the third node N3 is adjusted using the reference voltage signal received at the first reference voltage signal terminal Vinit3. Due to the capacitance existing between the gate and the drain of the driving transistor of the driving sub-circuit 10, when the voltage of the second node N2 and/or the third node N3 changes, under the coupling effect of the capacitance, the voltage of the first node N1 The voltage changes synchronously, so that the influence of the fourth node N4 on the voltage of the first node N1 can be compensated.
  • the voltage of the first node N1 is in dynamic balance, improving the potential stability of the first node N1, making the brightness retention rate of the light-emitting device O higher in one frame, and improving the brightness in the second light-emitting stage P5.
  • the changes improve the flickering phenomenon of the light-emitting device O and the display panel 200.
  • one lighting period F1 (one frame) includes a refresh frame F1 and at least one holding frame F2.
  • Figure 12 takes a holding frame F2 as an example for illustration.
  • the timing within the holding frame F2 is the same as the timing of holding frame F2 in FIG. 12 .
  • the timing of the three holding frames F2 can be understood as repeating the holding frames F2 in FIG. 12 three times.
  • one light-emitting period F may include other values of holding frames F2, and the specific number of holding frames F2 may be set according to the driving state of the display panel 200.
  • the display panel 200 when the display panel 200 is driven at a low frequency, the number of frames F2 held in one light-emitting period F is greater than the number of frames F2 held in one light-emitting period F when the display panel 200 is driven at a high frequency. Based on this, since the display panel 200 maintains a large number of frames F2 when driven at a low frequency, the display panel is more likely to flicker during display.
  • the regulator subcircuit 40 transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 . Perform at least one reset.
  • FIG. 12 takes as an example the use of the regulator sub-circuit 40 to reset the second node N2 during the reset phase P1.
  • the regulator sub-circuit 40 is turned on under the control of the low-level (effective-level) signal transmitted from the second scanning signal terminal Gate2, and transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3. to the second node N2.
  • the initial state of the driving transistor TD before the writing phase is fixed, so that the driving transistor TD can be in a stable state during the writing phase, and the hysteresis effect of the driving transistor TD can be greatly improved.
  • the pixel driving method can, on the one hand, transmit the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second node N2 through the adjustment sub-circuit 40 during the light emission adjustment stage P4. .
  • the voltage change of the second node N2 is used to compensate the voltage change of the first node N1, so that the voltage of the first node N1 is in dynamic balance, and the potential stability of the first node N1 is improved, so that within one frame
  • the brightness retention rate of the light-emitting device O is relatively high, which improves the flickering phenomenon of the light-emitting device O and the display panel 200 .
  • the second node N2 can also be reset through the regulating subcircuit 40, so that the initial state of the driving transistor TD before the writing phase is fixed, so that the driving transistor TD can be stabilized during the writing phase. state, which greatly improves the hysteresis effect of the driving transistor TD.
  • the writing phase P2 includes the process of resetting the voltage of the first node N1 multiple times and writing the data signal to the first node N1, which can better make the driving transistor TD in a stable state and can better improve the hysteresis. effect.
  • FIG. 13 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the second node N2 is reset multiple times.
  • the second node N2 is reset multiple times through the regulating subcircuit 40. Can be reset more completely. It is more conducive to keeping the driving transistor TD in a stable state during the writing phase, and better improving the hysteresis effect of the driving transistor TD.
  • FIG. 13 takes as an example that the second node N2 is reset three times during the reset phase P1.
  • the number of times the second node N2 is reset during the reset phase P1 may be 2, 3 or 4 times.
  • FIG. 14 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the first reset sub-circuit 70 receives the first reset signal from the first reset signal terminal Reset1. Under the control of the reset signal, the initialization signal received at the first initialization signal terminal Vinit1 is transmitted to the first node N1.
  • the low-level (effective-level) signal received by the first reset signal terminal Reset1 is earlier than the low-level (effective-level) signal received by the first reset signal terminal Reset1.
  • the reset holding time of the driving transistor TD can be made longer, so that the hysteresis effect can be more completely improved.
  • FIG. 15 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure. In some embodiments, please refer to FIG. 15 .
  • the adjustment sub-circuit 40 controls the signal from the second scan signal terminal. Under the control of the scan signal transmitted by Gate2, the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2, and the second node N2 is reset.
  • the third transistor T3 in the writing sub-circuit 20 is turned on, and the data signal provided by the data signal terminal Data is written into the second node N2.
  • the data signal of the second node N2 is driven
  • the driving transistor TD in the sub-circuit 10 is written to the third node N3, and the data signal of the third node N3 compensates the first node N1 through the first transistor group T1 in the compensation sub-circuit 30.
  • the potential of the first node N1 gradually rises to Vdata+Vth.
  • Vdata is the voltage value of the data signal provided by the data signal terminal Data
  • Vth is the threshold voltage of the driving transistor TD in the driving sub-circuit 10 .
  • the voltage of the second node N2 will be changed. Therefore, by refreshing the second node N2 again after completing the above process, the voltage value stored in the driving transistor TD can be the same each time, which is beneficial to improving the hysteresis effect of the driving transistor TD. This allows the pixel driving circuit 100 to turn on the brightness for approximately the same time each time, thereby improving the display effect of the display panel.
  • the first storage sub-circuit 50 is charged.
  • the first storage sub-circuit 50 discharges to the second node N2 to compensate the voltage of the second node N2.
  • the third transistor T3 included in the writing sub-circuit 20 is turned on under the control of the low-level signal transmitted by the first scanning signal terminal Gate1.
  • the data received at the data signal terminal Data The data signal is transmitted to the second node N2; at the same time, the data signal received at the data signal terminal Data is also transmitted to the first capacitor C1 to charge the first capacitor C1.
  • the regulator sub-circuit 40 is turned on under the control of the low-level signal transmitted from the second scan signal terminal Gate2
  • the reference voltage signal received at the first reference voltage signal terminal Vinit3 is transmitted to the second node N2.
  • the regulating subcircuit 40 is turned off under the control of the high-level signal transmitted from the second scanning signal terminal Gate2, at this time, the first capacitor C1 can maintain the voltage of the second node N2, thereby maintaining the voltage of the first node N1. stability.
  • the regulation subcircuit 40 under the control of the scanning signal transmitted from the second scanning signal terminal Gate2, transmits the reference voltage signal received at the first reference voltage signal terminal Vinit3 to the second Node N2; at the same time, the second reset sub-circuit 90, under the control of the second reset signal received from the second reset signal terminal Reset2, will transmit to the light-emitting device O at the second initialization signal terminal Vinit2.
  • the second reset signal terminal Reset2 and the second scan signal terminal Gate2 are turned on or off synchronously in response to the control of the same control signal.
  • the second scan signal terminal Gate2 can be multiplexed as the second reset signal terminal Reset2.
  • the adjustment sub-circuit 40 and the second reset sub-circuit 90 are turned on at the same time, that is, the second node N2 is switched on at the same time. and the light-emitting device O are reset at least once, so that the initial state of the driving transistor TD before the writing stage is fixed, so that the driving transistor TD is in a stable state during the writing stage, and the stability of the light-emitting device O is improved, thereby improving the display panel 200 The flickering screen phenomenon.
  • the adjustment sub-circuit 40 and the second reset sub-circuit 90 are turned on at the same time, that is, the second node is switched on at the same time.
  • N2 and the light-emitting device O are refreshed, and the voltage change of the second node N2 is used to compensate the voltage change of the first node N1, so that the voltage of the first node N1 can be approximately in a dynamic equilibrium state.
  • the light-emitting device O can also be refreshed again.
  • the brightness of the light-emitting device O can be better stabilized.
  • Figure 16 is a timing diagram of yet another pixel driving circuit according to some embodiments of the present disclosure.
  • the lighting control sub-circuit 80 communicates with the driving sub-circuit 10 under the control of the enable signal from the enable signal terminal EM1 cooperate to transmit the driving signal to the light-emitting device O.
  • the second reset sub-circuit 90 transmits the initialization signal received at the second initialization signal terminal Vinit2 to the light-emitting device O under the control of the reset signal received from the second reset signal terminal Reset2.
  • the initialization signal received by the second initialization signal terminal Gate2 and the enable signal received by the enable signal terminal EM1 are alternately set.
  • the control terminal EM2 which is inverted with the enable signal terminal EM1 replaces the second reset signal terminal Reset2.
  • the enable signal terminal EM1 provides a low level and the control terminal EM2 provides a high level; or the enable signal terminal EM1 provides a high level and the control terminal EM2 provides a low level.
  • the lighting control sub-circuit 80 and the second reset sub-circuit 90 are turned on alternately.
  • the enable signal terminal EM1 provides a high level (inactive level) signal
  • the control terminal EM2 provides a low level (valid level) signal.
  • the light-emitting control sub-circuit 80 is turned off under the high-level control of the enable signal terminal EM1
  • the second reset sub-circuit 90 is turned on under the low-level control of the control terminal EM2, and will be connected to the second initialization signal terminal Vinit2.
  • the received initialization signal is transmitted to the light-emitting device O, and the anode of the light-emitting device O is reset.
  • the enable signal terminal EM1 provides a low level (effective level) signal
  • the control terminal EM2 provides a high level (inactive level) signal.
  • the second reset sub-circuit 90 is turned off under the control of the high-level signal of the control terminal EM2
  • the light-emitting control sub-circuit 80 is turned on under the control of the low-level signal of the enable signal terminal EM1, cooperating with the driving sub-circuit. , driving the light-emitting device O to emit light.
  • the enable signal terminal EM1 provides a high level (inactive level) signal
  • the control terminal EM2 provides a low level (effective level) signal.
  • the light-emitting control sub-circuit 80 is turned off under the high-level control of the enable signal terminal EM1
  • the second reset sub-circuit 90 is turned on under the low-level control of the control terminal EM2, and will be connected to the second initialization signal terminal Vinit2.
  • the received initialization signal is transmitted to the light-emitting device O, and the potential of the anode of the light-emitting device O is refreshed.
  • FIG. 17 is a film structure diagram of a pixel driving circuit located in a sub-pixel area in a display panel according to some embodiments of the present disclosure.
  • Figures 17A to 17D are structural diagrams of some film layers in Figure 17 respectively. It can be understood that the equivalent circuit diagram corresponding to the pixel driving circuit in Figure 17 is as shown in Figure 9.
  • the display panel 200 includes a substrate 000 and a first gate conductive layer G1.
  • the first gate conductive layer G1 is located on one side of the substrate 000.
  • the first gate conductive layer G1 includes a second scanning signal line Gate2 extending along the first direction X.
  • the pixel driving circuit 100 includes a second transistor T2 and a seventh transistor T7.
  • the second scanning signal line Gate2 includes a first part M1 and a second part M2.
  • the first part M1 is multiplexed as the gate of the second transistor T2
  • the second part M2 is multiplexed as the gate of the seventh transistor T7.
  • the above arrangement enables the gate electrode of the second transistor T2 and the gate electrode of the seventh transistor T7 to be electrically connected to the second scanning signal line Gate2.
  • the second scanning signal line Gate2 connected to the gate of the third transistor T3 is multiplexed as the second reset signal terminal Reset2 connected to the gate of the seventh transistor T7.
  • the gate of the second transistor T2 and the gate of the seventh transistor T7 can be driven by a gate driving circuit, and the electrical signal provided by the gate driving circuit is transmitted to the gate of the second transistor T2 through the second scanning signal line Gate2. and the gate of the seventh transistor T7 to control the turn-on and turn-off of the second transistor T2 and the seventh transistor T7.
  • the use of one gate driving circuit can be reduced, which facilitates the layout within the display panel 200 and helps achieve a narrow frame of the display panel 200 .
  • the manufacturing process of the pixel driving circuit 100 can also be simplified, thereby simplifying the manufacturing process of the display panel 200 .
  • the first gate conductive layer G1 also includes a first scanning signal line Gate1.
  • the first scanning signal line Gate1 extends along the first direction X.
  • the pixel driving circuit 100 includes a first transistor T11 and a fourth transistor T4.
  • the first scanning signal line Gate1 includes a third part M3 and a fourth part M4.
  • the third part M3 is multiplexed as the gate of the first transistor T11
  • the fourth part M4 is multiplexed as the gate of the fourth transistor T4.
  • the first gate conductive layer G1 also includes an enable signal line EM1, and the enable signal line EM1 extends along the first direction X.
  • the pixel driving circuit 100 includes a fifth transistor T5 and a sixth transistor T6.
  • the enable signal line EM1 includes a fifth part M5 and a sixth part M6.
  • the fifth part M5 is multiplexed as the gate of the fifth transistor T5
  • the sixth part M6 is multiplexed as the gate of the sixth transistor T6.
  • the first gate conductive layer G1 also includes a first reset signal line Reset1.
  • the first reset signal line Reset1 extends along the first direction X.
  • the pixel driving circuit 100 includes a fourth transistor T4.
  • the first reset signal line Reset1 includes a seventh part M7, and the seventh part M7 is multiplexed as the gate of the fourth transistor T4.
  • the above arrangement can simplify the manufacturing process of the pixel driving circuit 100, thereby simplifying the manufacturing process of the display panel 200.
  • the above description takes the first gate conductive layer G1 and includes the first reset signal line Reset1, the first scanning signal line Gate1, the enable signal line EM1 and the second scanning signal line Gate2 along the second direction Y as an example.
  • the second direction Y intersects the first direction X.
  • the second direction Y is perpendicular to the first direction X.
  • the first gate conductive layer G1 may also include other wiring arrangements according to actual requirements within the display panel 200 .
  • the first gate conductive layer G1 may also include a lower plate of the second capacitor Cst.
  • the first gate conductive layer G1 may further include a gate electrode of the driving transistor TD. And/or, part of the lower plate of the second capacitor Cst is multiplexed as the gate of the driving transistor TD. All of them can simplify the manufacturing process of the pixel driving circuit 100, thereby simplifying the manufacturing process of the display panel 200.
  • the material of the first gate conductive layer G1 includes conductive metal.
  • the conductive metal may include at least one of aluminum, copper, and molybdenum, and the present disclosure is not limited thereto.
  • FIG. 18 is a film structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure.
  • FIG. 19 is a film structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure.
  • FIG. 20 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in yet another display panel according to some embodiments of the present disclosure. It can be understood that the equivalent circuit diagram corresponding to the pixel driving circuit in FIG. 18, FIG. 19 and FIG. 20 is as shown in FIG. 11.
  • the display panel 200 further includes an active layer POLY, a second gate conductive layer G2 and a first source-drain conductive layer SD1 .
  • the active layer POLY is located between the substrate 000 and the first gate conductive layer G1.
  • the material of the active layer Poly may include amorphous silicon, single crystal silicon, polycrystalline silicon or metal oxide semiconductor materials.
  • a first gate insulating layer is disposed between the active layer Poly and the first gate conductive layer G1, and the first gate insulating layer electrically insulates the active layer Poly and the first gate conductive layer G1.
  • the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the first gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • the orthographic projection of the active layer Poly on the substrate overlaps with the orthographic projection of the first gate conductive layer G1 on the substrate.
  • the part of the active layer Poly covered by the first gate conductive layer G1 constitutes the active part (channel part) of each transistor, and the part of the active layer Poly not covered by the first gate conductive layer G1 is the conductive part. It forms part of the first pole or the second pole of each transistor.
  • the second gate conductive layer G2 is located on the side of the first gate conductive layer G1 away from the active layer POLY.
  • the second gate conductive layer G2 may be made of the same material as the first gate conductive layer G1. It can be understood that in other embodiments, the materials of the second gate conductive layer G2 and the first gate conductive layer G1 may be different. The embodiments of the present disclosure do not limit this.
  • a second gate insulating layer may be disposed between the second gate conductive layer G2 and the first gate conductive layer G1.
  • the second gate insulating layer electrically insulates the second gate conductive layer G2 and the first gate conductive layer G1.
  • the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the second gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • the first source-drain conductive layer SD1 is located on the side of the second gate conductive layer G2 away from the active layer POLY.
  • a third gate insulating layer is provided between the second gate conductive layer G2 and the first source-drain conductive layer SD1, and the third insulating layer makes the electrical connection between the second gate conductive layer G2 and the first source-drain conductive layer SD1 insulation.
  • the material of the third gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide.
  • the material of the third gate insulating layer may include silicon dioxide, and the present disclosure is not limited thereto.
  • the display panel 200 may further include a shielding layer LS located between the substrate 000 and the active layer POLY.
  • the material of the active layer POLY is relatively sensitive to light. When it is exposed to light of different intensities, its electrical properties vary greatly. In order to avoid the problem that the active part of each transistor in the active layer POLY is affected by light during use.
  • a blocking layer LS is provided between the substrate 000 and the active layer POLY.
  • the shielding layer LS can be used to prevent external light from affecting the active part.
  • the shielding layer LS can provide a constant potential in the channel portion, which can be used to improve the negative bias problem of the threshold voltage (Vth), thereby mitigating the above aging process.
  • the constant potential may be the potential provided by the first voltage terminal VDD, the potential provided by the second voltage terminal VSS, or the potential provided by the reference voltage signal terminal Vinit (Vinit1, Vinit2 or Vinit3).
  • the shielding layer LS can provide a variable voltage in the channel portion, and the access method can be from the periphery of the display area of the display panel 200, or holes can be drilled inside the pixel area of the display panel 200 for electrical connection.
  • the pixel driving circuit 100 includes a first capacitor C1.
  • the first plate of the first capacitor C1 and the second plate of the first capacitor C1 are respectively located in the shielding layer LS, the active layer POLY, the first gate conductive layer G1, the second gate conductive layer G2 and the first source-drain conductive layer At least two layers in layer SD1.
  • first electrode plate of the first capacitor C1 can be located in any of the above-mentioned film layers, and the second electrode plate of the first capacitor C1 can be located in other film layers except the above-mentioned first electrode plate.
  • the structure of the first capacitor C1 will be described in detail below.
  • FIG. 18A is a structural diagram of the active layer in FIG. 18
  • FIG. 18B is a structural diagram of the shielding layer in FIG. 18 .
  • the two plates of the first capacitor C1 are respectively located in the active layer POLY and the shielding layer LS.
  • the pixel driving circuit 100 includes a third transistor T3 and a fifth transistor T5.
  • the active layer POLY includes the active part of the third transistor T3, the active part of the fifth transistor T5, and the first plate of the first capacitor C1; the first electrode of the first capacitor C1 The plate is located between the active part of the third transistor T3 and the active part of the fifth transistor T5.
  • the shielding layer LS includes a first part LS1 and a second part LS2.
  • the orthographic projection of the first part LS1 on the substrate 000 has an overlap with the active part of the drive transistor TD. Ensure the stability of the drive transistor TD.
  • the first part LS1 can be expanded to form the second part LS2. This makes the orthographic projection of the second part LS2 on the substrate 000 and the orthographic projection of the active layer POLY on the substrate 000 overlap.
  • the second part LS2 is multiplexed as the second plate of the first capacitor C1.
  • the number of film layers between the active layer POLY and the shielding layer LS is small, and there may even be a situation where only one insulation layer is included between the active layer POLY and the shielding layer LS.
  • Disposing the two plates of the first capacitor C1 in the active layer POLY and the shielding layer LS respectively is beneficial to increasing the capacitance value of the first capacitor C1.
  • the second part LS2 and the first part LS1 of the shielding layer LS can use the same mask to form a layer structure through a patterning process, which is beneficial to simplifying the manufacturing process of the display panel 200 .
  • the pixel driving circuit 100 in the display panel 200 shown in FIG. 18 has improved shielding layer LS and active layer POLY compared to the pixel driving circuit 100 in the display panel 200 shown in FIG. 17 .
  • the first gate conductive layer G1, the second gate conductive layer G2, and the first source-drain conductive layer SD1 please refer to the film layer structures shown in FIGS. 17B to 17D.
  • FIG. 19A is a structural diagram of the second gate conductive layer in FIG. 19 .
  • the two plates of the first capacitor C1 are respectively located in the active layer POLY and the second gate conductive layer G2.
  • the pixel driving circuit 100 includes a second capacitor Cst, a third transistor T3 and a fifth transistor T5.
  • the active layer POLY in the display panel 200 shown in FIG. 19 and FIG. 18 has the same structure. Therefore, you can continue to read the structure of the active layer POLY as shown in Figure 18A.
  • the active layer POLY includes the active part of the third transistor T3, the active part of the fifth transistor T5, and the first plate of the first capacitor C1; The first plate of the first capacitor C1 is located between the active part of the third transistor T3 and the active part of the fifth transistor T5.
  • the second gate conductive layer G2 includes the first plate of the second capacitor Cst; the second plate of the first capacitor C1 is in the same layer and is electrically connected to the first plate of the second capacitor Cst.
  • the second plate of the first capacitor C1 and the first plate of the second capacitor Cst are on the same layer and are electrically connected.
  • the second plate of the first capacitor C1 can be an extended part of the first plate of the second capacitor Cst.
  • the second plate of the first capacitor C1 and the first plate of the second capacitor Cst can use the same film formation process. A film layer used to form a specific pattern is formed, and the layer structure is formed through a patterning process using the same mask. Therefore, the manufacturing process of the display panel 200 can be simplified.
  • the second gate conductive layer G2 may also include a first initialization signal line Vinit1 and a second initialization signal line Vinit2.
  • the structure of the first gate conductive layer G1 and the first source-drain conductive layer SD1 in the display panel 200 shown in FIG. 19 please refer to the film structure shown in FIG. 17B and FIG. 17D .
  • FIG. 20A is a structural diagram of the first gate-source conductive layer in FIG. 20 .
  • the two plates of the first capacitor C1 are respectively located in the active layer POLY and the first source-drain conductive layer SD1.
  • the pixel driving circuit 100 includes a second transistor T2, a third transistor T3, and a fifth transistor T5.
  • the active layer POLY in the display panel 200 shown in FIG. 20 and FIG. 18 has the same structure. Therefore, you can continue to read the structure of the active layer POLY as shown in Figure 18A.
  • the active layer POLY includes the active part of the third transistor T3, the active part of the fifth transistor T5, and the first plate of the first capacitor C1; The first plate of the first capacitor C1 is located between the active part of the third transistor T3 and the active part of the fifth transistor T5.
  • the first source-drain conductive layer SD1 includes the first electrode of the second transistor T2, the second electrode of the third transistor T3, and the second plate of the first capacitor C1; The second plate is located between the first electrode of the second transistor T2 and the second electrode of the third transistor T3.
  • the second plate of the first capacitor C1 is located between the first electrode of the second transistor T2 and the second electrode of the third transistor T3. Since the first electrode of the second transistor T2 and the second electrode of the third transistor T3 need to be electrically connected, that is, a conductive portion needs to be provided between the first electrode of the second transistor T2 and the second electrode of the third transistor T3. Thus, the area of the conductive portion can be enlarged, thereby forming the second plate of the first capacitor C1.
  • the second plate of the first capacitor C1, the first electrode of the second transistor T2, and the second electrode of the third transistor T3 can use the same film formation process to form a film layer for forming a specific pattern, and use the same mask to pass through it once The layer structure formed by the patterning process. Therefore, the manufacturing process of the display panel 200 can be simplified.
  • Figure 21 is a film layer structure diagram of a pixel driving circuit located in a sub-pixel area in another display panel according to some embodiments of the present disclosure.
  • Figures 21A to 21F are respectively structural diagrams of some film layers in Figure 21. It can be understood that the equivalent circuit diagram corresponding to the pixel driving circuit in Figure 21 is as shown in Figure 9.
  • the pixel driving circuit 100 includes a second transistor T2 and a seventh transistor T7.
  • the display panel 200 includes: a substrate 000, an active layer POLY, a first gate conductive layer Gate1, a second gate conductive layer Gate2, a first source-drain conductive layer SD1, a second source-drain conductive layer SD2, and a third source-drain conductive layer. SD3.
  • the pixel driving circuit 100 includes a second transistor T2 and a seventh transistor T7.
  • the third source-drain conductive layer SD3 includes a second scanning signal line Gate2 and a second reset signal line Reset (EM2).
  • the second scanning signal line Gate2 and the second reset signal line Reset (EM2) are arranged along the first direction X extending in the second direction Y.
  • the second scanning signal line Gate2 is located on one side of the second reset signal line Reset (EM2) closer to the second transistor T2 and the seventh transistor T7.
  • the second source-drain conductive layer SD2 also includes a first connection part L1 and a second connection part L2.
  • One end of the first connection portion L1 is connected to the gate of the second transistor T2 through a via hole, and the other end of the first connection portion L1 is connected to the second scanning signal line Gate2 through a via hole.
  • the gate of the second transistor T2 is coupled to the second scanning signal line Gate2 for transmitting the scanning signal received at the second scanning signal line Gate2 to the gate of the second transistor T2 and controlling its on or off.
  • One end of the second connection portion L2 is connected to the gate of the seventh transistor T7 through a via hole, and the other end of the second connection portion L2 is connected to the second reset signal line Reset (EM2) through the via hole.
  • the seventh transistor T7 is coupled to the second reset signal line Reset (EM2). It is used to transmit the reset signal received at the second reset signal line Reset (EM2) to the gate of the seventh transistor T7 to control its on or off.
  • the pixel driving circuit 100 includes a first transistor T11, a third transistor T3, and a fourth transistor T41.
  • the first gate conductive layer G1 includes a first reset signal line Reset1 and a first scanning signal line Gate1.
  • the first reset signal line Reset1 extends along the first direction X.
  • the first reset signal line Reset1 includes a first sub-portion H1, and the first sub-portion H1 is multiplexed as the gate of the fourth transistor T41.
  • the first scanning signal line Gate1 includes a second sub-section H2 and a third sub-section H3.
  • the second sub-section H2 is multiplexed as the gate electrode of the first transistor T11
  • the third sub-section H3 is multiplexed as the gate electrode of the third transistor T3. .
  • the above arrangement can simplify the manufacturing process of the pixel driving circuit 100, thereby simplifying the manufacturing process of the display panel 200.
  • Figure 22 is a structural diagram of another display panel according to some embodiments of the present disclosure.
  • the display panel 200 includes a display area AA and a peripheral area BB at least partially surrounding the display area AA.
  • the pixel driving circuit 100 and the light-emitting device O in any of the above embodiments can be disposed in the display area AA.
  • the gate driving circuit GOA used to drive the pixel driving circuit 100 may be provided in the peripheral area BB.
  • the gate driving circuit GOA may include a first gate driving circuit Gate1GOA, a second gate driving circuit Gate2GOA, and a third gate driving circuit EM1GOA.
  • the first gate driving circuit Gate1GOA is used to provide a scanning signal to the first gate signal terminal Gate1.
  • the first gate signal terminal Gate1 transmits the scanning signal to the gate of the first transistor T11 and the gate of the third transistor T3. , controlling the turn-on and turn-off of the first transistor T11 and the third transistor T3.
  • the second gate driving circuit Gate2GOA is used to provide a scanning signal to the second gate signal terminal Gate2.
  • the second gate signal terminal Gate2 transmits the scanning signal to the gate of the second transistor T2 and controls the conduction of the second transistor T2. On and off.
  • the second gate signal terminal Gate2 transmits the scan signal to the gate of the second transistor T2 and the gate of the seventh transistor T7 to control the on and off of the second transistor T2 and the seventh transistor T7.
  • the third gate drive circuit EM GOA is used to provide an enable signal to the enable signal terminal EM1, and the enable signal terminal EM1 transmits the enable signal to the gate of the fifth transistor T5 and the gate of the sixth transistor T6, The turn-on and turn-off of the fifth transistor T5 and the sixth transistor T6 are controlled.
  • Figure 23 is a circuit structure diagram of a shift register according to some embodiments of the present disclosure
  • Figure 24 is a timing diagram of the shift register in Figure 23.
  • Some embodiments of the present disclosure provide a gate driving circuit. Please refer to FIG. 23 and FIG. 24 .
  • the gate driving circuit GOA includes a plurality of shift registers Q1 arranged in cascade.
  • Shift register Q1 includes transistors T10, T11, T12, T13, T14, T15, T16, T17, capacitors C4 and C5.
  • the clock signal received at the clock signal terminal CK is low level, which turns on the transistor T10.
  • the transistor T10 transmits the upper-level initial scanning signal GSTV to the fifth node N5.
  • the upper-level initial scanning signal GSTV is low level, therefore, the fifth node N5 is low level.
  • the transistor T11 is turned on, and the transistor T11 transmits the voltage signal provided by the voltage signal terminal VGL to the sixth node N6.
  • the transistor T12 Under the control of the fifth node N5, the transistor T12 is turned on, and the transistor T12 transmits the clock signal received at the clock signal terminal CK to the sixth node N6; wherein, the voltage signal provided by the voltage signal terminal VGL is low level, and the clock signal The signal terminal is low level during the charging stage t1, therefore, the sixth node N6 is low level.
  • the transistor T13 Under the control of the sixth node N6, the transistor T13 is turned on, and the transistor T13 transmits the voltage signal provided by the voltage signal terminal VGH to the seventh node N7.
  • the voltage signal provided by the voltage signal terminal VGH is high level, so the seventh node N7 is high level.
  • the clock signal provided by the clock signal terminal CB is at a high level. Under the control of the clock signal provided by the clock signal terminal CB, the transistor T14 is turned off. Therefore, the high level of the seventh node N7 cannot be written to the fifth node N5.
  • the voltage signal provided by the voltage signal terminal VGL is low level, thereby controlling the transistor T15 to be turned on, and the signal of the fifth node N5 can be written to the eighth node N8. Therefore, the eighth node N8 is low level.
  • the sixth node N6 is at a low level, thereby controlling the transistor T17 to be turned on, and the transistor T17 transmits the voltage signal provided by the voltage signal terminal VGH to the initial scanning signal output terminal OUT.
  • the eighth node N8 is at a low level, thereby controlling the transistor T16 to turn on, and the transistor T16 transmits the clock signal provided by the clock signal terminal CB to the initial scan signal output terminal OUT.
  • the clock signal received at the clock signal terminal CK is high level, and the control transistor T10 is turned off. Therefore, the upper-level initial scanning signal GSTV cannot be transmitted to the fifth node N5, and the fifth node N5 remains low. flat.
  • the clock signal received at the clock signal terminal CK is at a high level, and the control transistor T11 is turned off, and the voltage signal received at the voltage signal terminal VGL cannot be transmitted to the sixth node N6.
  • the fifth node N5 remains low, thereby controlling the transistor T12 to turn on.
  • the transistor T12 transmits the clock signal received at the clock signal terminal CK to the sixth node N6.
  • the clock signal received at the clock signal terminal CK is high in the output stage. level, therefore, the sixth node N6 is at a high level, thereby controlling the transistor T17 to be turned off, so that the voltage signal received at the voltage signal terminal VGH cannot be transmitted to the initial scanning signal output terminal OUT.
  • the sixth node N6 is at a high level. Therefore, the transistor T13 is turned off, and the voltage signal received at the voltage signal terminal VGH cannot be transmitted to the seventh node N7.
  • the clock signal received at the clock signal terminal CB is low level, thereby controlling the transistor T14 to turn on, and the transistor T14 writes the low level of the fifth node N5 into the seventh node N7.
  • the fifth node N5 is low level. Since the transistor T15 is turned on, the low level of the fifth node N5 can be written to the eighth node N8.
  • the eighth node N8 is low level, thereby controlling the transistor T16 to turn on.
  • the transistor T16 will The clock signal received at the clock signal terminal CB is transmitted to the initial scan signal output terminal OUT.
  • the clock signal received at the clock signal terminal CB is low level in the output stage t2. Therefore, the initial scan signal OUT is low level in the output stage t2. . Since the level of the initial scanning signal output terminal OUT changes from high level to low level, under the control of capacitor C4, the level of eighth node N8 further decreases, thereby further turning on transistor T16.
  • the clock signal received at the clock signal terminal CK is low level, thereby controlling the transistor T10 to turn on.
  • the transistor T10 transmits the upper stage initial scanning signal GSTV to the fifth node N5.
  • the scanning signal GSTV is high level, therefore, the fifth node N5 is high level.
  • the transistor T15 is turned on, and the low level of the fifth node N5 is written to the eighth node N8, and the eighth node N8 is a high level, thereby controlling the transistor T16 to be turned off.
  • the fifth node N5 is at a high level, thereby controlling the transistor T12 to be turned off.
  • the clock signal received at the clock signal terminal CB is at a high level, thereby controlling the transistor T14 to be turned off.
  • the sixth node N6 is at a low level, thereby controlling the transistor T13 to be turned on.
  • the transistor T13 transmits the voltage signal received at the voltage signal terminal VGH to the seventh node N7, and the seventh node N7 is at a high level.
  • the clock signal received at the clock signal terminal CK is low level, thereby controlling the transistor T11 to turn on.
  • the transistor T11 transmits the voltage signal received at the voltage signal terminal VGL to the sixth node N6.
  • the voltage signal received at the voltage signal terminal VGL is Low level, therefore, the sixth node N6 is low level, thereby controlling the transistor T17 to turn on.
  • the transistor T17 transmits the voltage signal received at the voltage signal terminal VGL to the initial scanning signal output terminal OUT, and the voltage signal received at the voltage signal terminal VGL The voltage signal is high level.
  • the clock signal received at the clock signal terminal CK is high level, the transistor T10 is turned off, and the upper stage initial scanning signal GSTV cannot be transmitted to the fifth node N5.
  • the sixth node N6 is low level, and then the control transistor T13 is turned on.
  • the clock signal received at the clock signal terminal CB is low level, and the transistor T14 is turned on. Therefore, the voltage signal received at the voltage signal terminal VGH passes through the transistor in turn.
  • T13 and transistor T14 write to the fifth node N5, and the voltage signal received at the voltage signal terminal VGH is high level. Therefore, the fifth node N5 is high level.
  • the transistor T15 is turned on, and the level of the fifth node N5 is written into the eighth node N8.
  • the eighth node N8 is at a high level, and then the transistor T16 is controlled to be turned off. Therefore, the clock signal received at the clock signal terminal CB cannot be written.
  • Initial scan signal output terminal OUT is
  • the clock signal received at the clock signal terminal CK is at a high level, the transistor T11 is turned off, and the voltage signal received at the voltage signal terminal VGL cannot be transmitted to the sixth node N6.
  • the fifth node N5 is at a high level, thereby controlling the transistor T12 to be turned off.
  • the sixth node N6 remains low, so the transistor T17 is turned on.
  • the transistor T17 transmits the voltage signal received at the voltage signal terminal VGH to the initial scanning signal output terminal OUT.
  • the voltage signal received at the voltage signal terminal VGH is high level. Therefore, the initial scanning signal OUT is high level in the second pull-up phase t320.
  • the first gate driving circuit Gate1GOA in the display panel 200 may adopt the structure of the gate driving circuit GateGOA described above.
  • the initial scan signal output terminal OUT can be connected to the first gate signal terminal Gate1 to provide the scan signal for the first gate signal terminal Gat1.
  • the second gate driving circuit Gate2GOA in the display panel 200 may adopt the structure of the gate driving circuit GateGOA described above.
  • the initial scan signal output terminal OUT can be connected to the second gate signal terminal Gate2 to provide the scan signal to the second gate signal terminal Gate2.
  • shift register circuit shown in Figure 23 only uses eight transistors and two capacitors as an example. In other embodiments, other GOA circuits that can achieve the same or similar functions can also be applied. This disclosure does not limit this (such as the above-mentioned first gate driving circuit Gate1GOA or the second gate driving circuit Gate2GOA).
  • FIG. 25 is a circuit structure diagram of yet another shift register according to some embodiments of the present disclosure
  • FIG. 26 is a timing diagram of the shift register in FIG. 25 .
  • Some embodiments of the present disclosure provide a gate driving circuit. Please refer to FIG. 25 and FIG. 26 .
  • the gate driving circuit GOA includes a plurality of shift registers Q2 arranged in cascade.
  • the third gate driving circuit EM GOA includes a plurality of shift registers Q2 arranged in cascade.
  • Shift register Q2 includes transistors T20, T21, T22, T23, T24, T25, T26, T27, T28, T29, T30, T31, capacitors C6, C7, and C8.
  • the transistor T20 In the first stage t1, under the control of the low-level signal received at the clock signal terminal CK, the transistor T20 is turned on.
  • the signal input terminal STV provides a signal in a high-level state and is written to the ninth node N9 through the transistor T20.
  • the ninth node N9 is in a high-level state, and the transistor T21 and the transistor T27 are in a cut-off state; at the same time, at the voltage signal terminal Under the control of the low-level signal provided by VGL, the transistor T31 is turned on, and the high-level signal of the ninth node N9 is written to the eleventh node N11.
  • the eleventh node N11 is in a high-level state, and the transistor T29 is turned off. state.
  • the transistor T22 Under the control of the low-level signal received at the clock signal terminal CK, the transistor T22 is turned on, and the low-level signal provided by the voltage signal terminal VGL is written into the tenth node N10.
  • the tenth node N10 is in a low-level state, and the transistor T24 conduction.
  • the transistor T30 Under the control of the low-level signal provided by the voltage signal terminal VGL, the transistor T30 is turned on, the low-level signal of the tenth node N10 is written to the gate of the transistor T25, and the transistor T25 is turned on.
  • the transistor T26 Under the control of the high-level signal received at the clock signal line CB, the transistor T26 is turned off, the twelfth node N12 is in a floating state, and the twelfth node N12 maintains the high level of the previous stage (the last stage of the previous cycle). level state, transistor T28 is turned off. As a result, the signal output terminal OUT1 is in a floating state, and the signal output terminal OUT1 maintains the low level state of the previous stage (the last stage of the previous cycle), that is, the signal output terminal OUT1 outputs a low level signal.
  • the transistor T23 under the control of the low-level signal received at the clock signal line CB, the transistor T23 is turned on, and under the control of the low-level signal at the tenth node N10, the transistor T24 is turned on, and the voltage signal terminal VGH provides The high-level signal is written into the ninth node N9 and the eleventh node N11, and charges the capacitor C6. Therefore, since the ninth node N9 is in a high-level state, the transistor T21 will immediately switch to the off-state; the eleventh node N11 is in a high-level state, and the transistor T29 is off.
  • the transistor T26 under the control of the low-level signal received at the clock signal line CB, the transistor T26 is turned on, and the low-level signal received at the clock signal line CB is written to the thirteenth node N13 through the transistor T25.
  • the voltage at the tenth node N10 is pulled down to a lower level. Since the transistor T25 and the transistor T26 are turned on, the low-level signal received at the clock signal line CB is written to the twelfth node N12 through the transistor T25 and the transistor T26, and the transistor T28 is turned on.
  • the high-level signal provided by the voltage signal line VGH is written to the signal output terminal OUT1 through the transistor T28, that is, the signal output terminal OUT1 outputs a high-level signal.
  • the ninth node N9 is in a high level state and the transistor T27 is turned off; the eleventh node N11 is in a high level state and the transistor T29 is turned off.
  • the tenth node N10 is in a low level state, the transistor T25 is turned on, the high level signal received at the clock signal line CB is written to the twelfth node N12 through the transistor T25 and the transistor T26, and the transistor T28 is turned off.
  • the signal output terminal OUT1 Since the transistor T28 and the transistor T29 are both in the off state, the signal output terminal OUT1 is in a floating state, and the signal output terminal OUT1 maintains the high level state of the previous stage (the last stage of the previous cycle), that is, the signal output terminal OUT1 outputs high level signal.
  • the transistor T27 and the transistor T29 are in a cut-off state.
  • the transistor T23 is turned on, and the transistor T26 is turned on.
  • the transistor T25 is turned on.
  • the low-level signal received at the clock signal line CB is written to the twelfth node N12 through the transistor T25 and the transistor T26, and the transistor T28 is turned on. Therefore, the high-level signal provided by the voltage signal line VGH is written to the signal output terminal OUT1 through the transistor T28, that is, the signal output terminal OUT1 outputs a high-level signal.
  • the transistor T20 is turned on.
  • the signal input terminal STV provides a low-level signal and is written to the ninth node N9 through the transistor T20.
  • the ninth node N9 is in a low-level state and the transistor T21 is turned on; at the same time, the low-level signal received at the clock signal terminal CK
  • the transistor T22 is turned on, and the low-level signal provided by the voltage signal terminal VGL is written into the tenth node N10.
  • the tenth node N10 is in a low-level state, the transistor T24 is turned on, and the transistor T25 is turned on.
  • the high-level signal received at the clock signal line CB is written to the twelfth node N12 through the transistor T25 and the transistor T26, and the transistor T28 is turned off.
  • the eleventh node N11 is in a low level state, and the transistor T27 and the transistor T29 are in a conductive state.
  • the low-level signal provided by the voltage signal terminal VHL is transmitted to the signal output terminal OUT1, that is, the signal output terminal OUT1 outputs a low-level signal.
  • the transistor T21 is turned on.
  • the high-level signal provided by the clock signal terminal CK is written to the tenth node N10 through the transistor T21, the transistor T24 is turned off, and the transistor T25 is turned off. Since the ninth node N9 is in a low-level state, the transistor T27 is turned on, the high-level signal provided by the voltage signal terminal VGH is written to the twelfth node N12, and the transistor T28 is turned off.
  • the eleventh node N11 is in a low level state, and the transistor T29 is turned on. Therefore, the low-level signal provided by the voltage signal terminal VHL is transmitted to the signal output terminal OUT1, that is, the signal output terminal OUT1 outputs a low-level signal.
  • the signal output unit OUT1 of the shift register Q2 in the third gate drive circuit EM GOA can be connected to the enable signal terminal EM1 to provide an enable signal for the enable signal terminal EM1.
  • shift register circuit shown in Figure 25 only uses ten transistors and three capacitors as an example. In other embodiments, other GOA circuits that can achieve the same or similar functions can also be applied. Therefore, this disclosure does not limit this.
  • Figure 27 is a circuit structure diagram of a shift register according to some embodiments of the present disclosure.
  • the output control subcircuit U can be connected in series to the output terminal OUT1 of the shift register Q2 shown in Figure 25, and the signal output from the output terminal OUT1 is inverted and then transmitted through the output terminal OUT2.
  • the output control subcircuit U includes a transistor T40, a transistor T41, a transistor T42, a transistor T43, a transistor T44, and a capacitor C9.
  • the circuit of the shift register Q2 shown in Figure 27 can be driven with reference to the timing shown in Figure 26 .
  • the second reset signal terminal Reset2 may be the signal terminal EM2.
  • the signal terminal EM2 and the enable signal terminal EM1 are inverted.
  • the output terminal OUT2 of the shift register Q2 shown in FIG. 25 can be coupled with the signal terminal OUT2. Therefore, the output terminal OU1 of the shift register Q2 can be used to provide a signal terminal for the enable signal terminal EM1 and at the same time, the inverted signal can be transmitted to the signal terminal EM2 through the output terminal OUT2.
  • the output terminal OUT1 may be coupled to the signal terminal EM2, and the output terminal OUT2 may be coupled to the enable signal terminal.
  • this disclosure takes the output control sub-circuit U shown in Figure 27 as an example. In other embodiments, other circuits that can achieve the inversion effect can be applied here, and this disclosure does not limit this. .

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

公开了一种像素驱动电路，包括驱动子电路、写入子电路、补偿子电路及调节子电路。驱动子电路与第一节点、第二节点及第三节点耦接。写入子电路与第二节点、第一扫描信号端及数据信号端耦接。补偿子电路与第一节点、第三节点及补偿控制端耦接。调节子电路与第二节点和/或第三节点、第二扫描信号端及第一参考电压信号端耦接，调节子电路被配置为，在发光调节阶段，在来自第二扫描信号端传输的扫描信号的控制下，将在第一参考电压信号端处接收的参考电压信号传输至第二节点和/或第三节点。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板。
背景技术
AMOLED(Active-matrix Organic Light-Emitting Diode，有源矩阵有机发光二极管)显示面板具有自发光、超薄、反应速度快、对比度高、视角广等诸多优点，是目前受到广泛关注的一种显示器件。
AMOLED显示面板包括多个像素驱动电路和多个发光元件，像素驱动电路用于驱动对应的发光元件发光，实现显示功能。
发明内容
一方面，提供一种像素驱动电路。包括：驱动子电路、写入子电路、补偿子电路及调节子电路。所述驱动子电路，与第一节点、第二节点及第三节点耦接。所述驱动子电路被配置为，在所述第一节点的电压的控制下，将来自所述第二节点的电压传输至所述第三节点。所述写入子电路，与所述第二节点、第一扫描信号端及数据信号端耦接。所述写入子电路被配置为，在写入阶段，在来自所述第一扫描信号端接收的栅扫描信号的控制下，将在所述数据信号端处接收的数据信号传输至所述第二节点。所述补偿子电路，与所述第一节点、第三节点及补偿控制端耦接。所述补偿子电路被配置为，在写入阶段，在来自所述补偿控制端接收的补偿信号的控制下，将所述第三节点的电压传输至所述第一节点。所述调节子电路，与所述第二节点和/或所述第三节点耦接、且与第二扫描信号端及第一参考电压信号端耦接。所述调节子电路被配置为，在发光调节阶段，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点和/或所述第三节点。
在一些实施例中，所述调节子电路还被配置为，在复位阶段，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点复位。
在一些实施例中，所述调节子电路包括第二晶体管。所述第二晶体管的栅极和所述第二扫描信号端耦接。所述第二晶体管的第一极和所述第二节点耦接，所述第二晶体管的第二极和所述第一参考电压信号端耦接。
在一些实施例中，所述驱动子电路包括驱动晶体管。所述驱动晶体管的 栅极与所述第一节点耦接。所述驱动晶体管的第一极与所述第二节点耦接，所述驱动晶体管的第二极与所述第三节点耦接。
在一些实施例中，所述写入子电路包括第三晶体管。所述第三晶体管的栅极与所述第一扫描信号端耦接。所述第三晶体管的第一极与所述数据信号端耦接，所述第三晶体管的第二极与所述第二节点耦接。
在一些实施例中，所述第一扫描信号端被配置为，在控制所述第三晶体管的第一极接收所述数据信号端的数据信号之前，控制所述第三晶体管开启至少1次。
在一些实施例中，所述像素驱动电路还包括第一存储子电路。所述第一存储子电路，与所述第一电压端和所述第二节点耦接。所述第一存储子电路包括第一电容。所述第一电容的第一极板与所述第一电压端耦接，所述第一电容的第二极板与第二节点耦接。
在一些实施例中，所述像素驱动电路还包括：第二储能子电路。所述第二储能子电路包括第二电容。所述第二电容的第一极板与所述第一电压端耦接，所述第二电容的第二极板与所述第一节点耦接。其中，
Figure PCTCN2022103187-appb-000001
C1为所述第一电容的电容值，Cst为所述第二电容的电容值。
在一些实施例中，所述像素驱动电路还包括：第一复位子电路。所述第一复位子电路，与所述第一节点、第一复位信号端、及第一初始化信号端耦接。所述第一复位子电路被配置为，在复位阶段，在来自所述第一复位信号端接收的复位信号的控制下，将在所述第一初始化信号端接收的初始化信号传输至所述第一节点，对所述第一节点复位。
在一些实施例中，所述第一复位子电路包括第四晶体管组，所述第四晶体管组包括串联的至少两个第四晶体管。所述第四晶体管组中的所有第四晶体管的栅极均与所述第一复位信号端耦接，所述第四晶体管组中的第一个第四晶体管的第一极与所述第一节点耦接，所述第四晶体管组中的最后一个第四晶体管的第二极与所述第一初始化信号端耦接。所述第一复位信号端被配置为，在控制所述至少一个第四晶体管的第二极接收所述第一初始化信号端的第一初始化信号之前，控制至少一个第四晶体管开启至少1次。
在一些实施例中，所述像素驱动电路还包括：发光控制子电路。所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接；所述发光控制子电路被配置为，在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号。
在一些实施例中，所述发光控制子电路包括第五晶体管和第六晶体管。所述第五晶体管的栅极与使所述能信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接，所述第五晶体管的第二极与所述第二节点耦接。所述第六晶体管的栅极与使所述能信号端耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述发光器件耦接。
在一些实施例中，所述像素驱动电路还包括第二复位子电路。所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及发光器件耦接；所述第二复位子电路被配置为，在来自所述第二复位信号端接收的复位信号的控制下，将在所述第二初始化信号端接收的初始化信号传输至所述发光器件。
在一些实施例中，所述第二复位子电路包括第七晶体管。所述第七晶体管的栅极与第二复位信号端耦接，所述第七晶体管的第一极与所述光学器件耦接，所述第七晶体管的第二极与所述第二初始化信号端耦接。
在一些实施例中，所述第二复位信号端和所述第二扫描信号端响应于同一个控制信号的控制。
在一些实施例中，所述第二初始化信号端接收的初始化信号与所述使能信号端接收的使能信号反相。
在一些实施例中，所述第一参考电压信号端处接收的参考电压信号的取值范围为-5V～5V。
在一些实施例中，所述第一参考电压信号端处接收的参考电压信号大约为2V。
另一方面，提供一种像素驱动电路的驱动方法。所述像素驱动电路包括：驱动子电路、写入子电路、补偿子电路、发光控制子电路及调节子电路。所述驱动子电路，与第一节点、第二节点及第三节点耦接。所述写入子电路，与所述第二节点、第一扫描信号端及数据信号端耦接。所述补偿子电路，与所述第一节点、第三节点及所述补偿控制端耦接。所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接。所述调节子电路，与所述第二节点和/或所述第三节点耦接、且第二扫描信号端及第一参考电压信号端耦接。所述驱动方法包括：多个发光周期，一个发光周期包括复位阶段、写入阶段、第一发光阶段、发光调节阶段和第二发光阶段。在所述写入阶段，所述写入子电路，在来自所述第一扫描信号端接收的栅扫描信号的控制下，将在所述数据信号端处接收的数据信号传输至所述第二节点；所述驱动子电路将来自所述第二节点的数据信号传输至第三节点； 所述补偿子电路将所述第三节点的电压传输至所述第一节点。在所述第一发光阶段，在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号，所述第一电压端提供的电压信号传输至所述发光器件，以驱动所述发光器件发光。在所述发光调节阶段，所述调节子电路，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点和/或所述第三节点。在所述第二发光阶段，发光控制子电路，在来自所述使能信号端的信号的控制下，以及在所述第一节点的控制下，所述发光控制子电路与所述驱动子电路配合，将所述第一电压端提供的电压信号传输至所述发光器件，以驱动所述发光器件发光。
在一些实施例中，在所述复位阶段，所述调节子电路将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点进行至少一次复位。
在一些实施例中，对所述第二节点进行多次复位。
在一些实施例中，对所述第二节点进行2～4次复位。
在一些实施例中，像素驱动电路还包括第一复位子电路。
所述第一复位子电路，与所述第一节点、第一复位信号端、及第一初始化信号端耦接。在所述复位阶段，所述调节子电路对所述第二节点进行复位后，所述第一复位子电路，在来自所述第一复位信号端接收的第一复位信号的控制下，将在所述第一初始化信号端接收的初始化信号传输至所述第一节点。
在一些实施例中，在所述写入阶段，将在所述数据信号端处接收的数据信号传输至所述第一节点后，所述调节子电路，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点进行复位。
在一些实施例中，所述像素驱动电路还包括第一存储子电路。所述第一存储子电路，与所述第一电压端和所述第二节点耦接。在所述写入阶段，对所述第一存储电路充电。在所述第一发光阶段，所述第一存储电路放电至所述第二节点，补偿所述第二节点的电压。
在一些实施例中，所述像素驱动电路还包括第二复位子电路。所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及所述发光器件耦接；所述第二复位信号端和所述第二扫描信号端响应于同一个控制信号的控制。在所述复位阶段和所述发光调节阶段，所述调节子电路，将在所述第一 参考电压信号端处接收的参考电压信号传输至所述第二节点；同时所述第二复位子电路，在来自所述第二复位信号端接收的第二复位信号的控制下，将在所述第二初始化信号端传输至所述发光器件。
在一些实施例中，所述像素驱动电路还包括发光控制子电路和第二复位子电路。所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接。所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及所述发光器件耦接。所述第二初始化信号端接收的初始化信号与所述使能信号端接收的使能信号反相。在所述第一发光阶段，所述发光控制子电路在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号。在所述复位阶段和所述发光调节阶段，所述第二复位子电路在来自所述第二复位信号端接收的复位信号的控制下，将在所述第二初始化信号端接收的初始化信号传输至所述发光器件。
另一方面，提供一种显示面板。所述显示面板包括：如上述任一实施例所述的像素驱动电路。以及，与所述像素驱动电路电连接的发光器件。
在一些实施例中，所述显示面板包括：衬底和第一栅导电层。所述第一栅导电层位于所述衬底的一侧。所述第一栅导电层包括第二扫描信号线，所述第二扫描信号线沿第一方向延伸。所述像素驱动电路包括第二晶体管和所述第七晶体管。所述第二扫描信号线包括第一部分和第二部分；所述第一部分复用为所述第二晶体管的栅极，所述第二部分复用为第七晶体管的栅极。
在一些实施例中，所述显示面板还包括：遮挡层、有源层、第二栅导电层及第一源漏导电层。所述遮挡层位于所述衬底靠近所述第一栅导电层的一侧；所述有源层位于所述遮挡层和所述第一栅导电层之间。所述第二栅导电层位于所述第一栅导电层远离所述有源层的一侧。所述第一源漏导电层位于所述第二栅导电层远离所述有源层的一侧。所述像素驱动电路包括第一电容。所述第一电容的第一极板和所述第一电容的第二极板，分别位于所述遮挡层、有源层、所述第一栅导电层、所述第二栅导电层和所述第一源漏导电层中中至少两层。
在一些实施例中，所述像素驱动电路包括第二电容、第三晶体管和第五晶体管。所述有源层包括所述第三晶体管的有源部、所述第五晶体管的有源部、以及所述第一电容的第一极板；所述第一电容的第一极板位于所述第三晶体管的有源部和所述第五晶体管的有源部之间。所述第二栅导电层包括第二电容的第一极板；所述第一电容的第二极板与所述第二电容的第一极板同 层且电连接。
在一些实施例中，所述像素驱动电路包括第二晶体管、第三晶体管和第五晶体管。所述有源层包括所述第三晶体管的有源部、所述第五晶体管的有源部、以及所述第一电容的第一极板，所述第一电容的第一极板位于所述第三晶体管的有源部和所述第五晶体管的有源部之间；所述第一源漏导电层包括所述第二晶体管的第一极、所述第三晶体管的第二极、以及所述第一电容的第二极板，所述第一电容的第二极板位于所述第二晶体管的第一极和所述第三晶体管的第二极之间。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为本公开一些实施例的一种显示装置的结构图；
图2为本公开一些实施例的一种显示面板的结构图；
图3为本公开一些实施例的一种像素驱动电路的结构图；
图4为本公开一些实施例的一种像素驱动电路驱动的发光器件的亮度变化的仿真图；
图5为本公开又一些实施例的一种像素驱动电路的结构图；
图6为本公开又一些实施例的一种像素驱动电路的结构图；
图7为本公开一些实施例的一种像素驱动电路，高灰阶状态下，第一节点的电压、发光器件阳极电压的电压变化的仿真图；
图8为本公开一些实施例的一种像素驱动电路，低灰阶状态下，第一节点的电压、发光器件阳极电压的电压变化的仿真图；
图9为本公开一些实施例的又一种像素驱动电路的结构图；
图10为本公开一些实施例的又一种像素驱动电路的结构图；
图11为本公开一些实施例的又一种像素驱动电路的结构图；
图12为本公开一些实施例的又一种像素驱动电路的时序图；
图13为本公开一些实施例的又一种像素驱动电路的时序图；
图14为本公开一些实施例的又一种像素驱动电路的时序图；
图15为本公开一些实施例的又一种像素驱动电路的时序图；
图16为本公开一些实施例的又一种像素驱动电路的时序图；
图17为本公开一些实施例的一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图17A～图17D分别为图17中的一些膜层的结构图；
图18为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图18A为图18中的有源层的结构图；
图18B为图18中的遮挡层的结构图；
图19为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图19A为图19中的第二栅导电层的结构图；
图20为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图20A为图20中的第一栅源导电层的结构图；
图21本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图21A～图21F分别为图21中的一些膜层的结构图；
图22为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图；
图23为本公开一些实施例的一种移位寄存器的电路结构图；
图24为图23中的移位寄存器的时序图；
图25为本公开一些实施例的又一种移位寄存器的电路结构图；
图26为图25中的移位寄存器的时序图；
图27为本公开一些实施例的又一种移位寄存器的电路结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、 “一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差 (即，测量系统的局限性)所确定。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例提供的电路结构(例如像素驱动电路)中，电路结构所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(Metal Oxide Semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例提供的电路结构中，所采用的各晶体管的第一极为源极和漏极中一者，各晶体管的第二极为源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
本公开的实施例提供的电路结构中，第一节点、第二节点等节点并非表示实际存在的部件，而是表示电路图中相关耦接的汇合点，也就是说，这些节点是由电路图中相关耦接的汇合点等效而成的节点。
本公开的实施例中提供的电路结构所包括的晶体管，可以均为N型晶体管，或者可以均为P型晶体管，或者一部分为N型晶体管，另一部分为P型晶体管。在本公开中，“有效电平”指的是，能够使得晶体管导通的电平。其中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可以在高电平信号的控制下导通。
下面，以本公开的实施例中提供的电路结构所包括的晶体管均为P型晶体管为例，进行示意性说明。
在本公开中，P型晶体管可以在低电平信号的控制下导通，N型晶体管可 以在高电平信号的控制下导通。
图1为本公开一些实施例的一种显示装置的结构图。请参阅图1所示，本公开的一些实施例提供了一种显示装置300，该显示装置300包括：显示面板200。
在一些示例中，上述显示装置300例如可以是OLED(Organic Light Emitting Diode，有机发光二极管)显示装置。
示例性的，显示装置300还包括框架、显示驱动IC(Integrated Circuit，集成电路)以及其他电子配件等。
示例性的，上述显示装置300可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何显示装置中。更明确地说，预期所述实施例的显示装置可实施应用在多种电子中或与多种电子装置关联，所述多种电子装置例如(但不限于)移动电话、无线装置、个人数据助理(PDA)、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。
图2为本公开一些实施例的一种显示面板的结构图。
在一些实施例中，请参阅图2所示，上述显示面板200包括衬底000、设置在衬底000一侧的多个像素驱动电路100、设置在该多个像素驱动电路100远离衬底000一侧的多个发光器件O。多个像素驱动电路100与多个发光器件O耦接。
示例性的，上述衬底000可以为柔性衬底，也可以为刚性衬底。
例如，在衬底000为柔性衬底的情况下，衬底000的材料可以为二甲基硅氧烷、PI(Polyimide，聚酰亚胺)、PET(Polyethylene Terephthalate，聚对苯二甲酸乙二醇酯)等具有高弹性的材料。
又如，在衬底000为刚性衬底的情况下，衬底000的材料可以为玻璃等。
在一些示例中，上述多个像素驱动电路100和多个发光器件O可以一一对应耦接。在另一些示例中，一个像素驱动电路100可以与多个发光器件O耦接，或者，多个像素驱动电路100可以与一个发光器件O耦接。
下面，本公开以一个像素驱动电路100与一个发光器件O耦接为例，对显示面板200的结构进行示意性说明。
示例性的，显示面板200中，像素驱动电路100可以生成驱动信号。各发光器件O可以在相应的像素驱动电路100所生成的驱动信号的驱动作用下发出光，多个发光器件O发出的光相互配合，从而使得显示面板200实现显示功能。
示例性的，上述发光器件O可以为OLED发光器件。
图3为本公开一些实施例的一种像素驱动电路的结构图。图4为本公开一些实施例的一种像素驱动电路驱动的发光器件的亮度变化的仿真图。
请参阅图3所示，本公开的一些实施例提供了一种像素驱动电路100，包括：驱动子电路10、写入子电路20和补偿子电路30。
驱动子电路10与第一节点N1、第二节点N2及第三节点N3耦接。驱动子电路10被配置为，在第一节点N1的电压的控制下，将来自第二节点N2的电压传输至第三节点N3。
补偿子电路30，与第一节点N1、第三节点N3及补偿控制端G0耦接。补偿子电路30被配置为，在写入阶段，在来自补偿控制端G0接收的补偿信号的控制下，将第三节点N3的电压传输至第一节点N1，从而控制驱动子电路打开。示例性的，补偿子电路30包括第一晶体管组T1。第一晶体管组T1包括串联的至少两个第一晶体管T11。第一晶体管T11可以为氧化物半导体薄膜晶体管。
其中，图3以第一晶体管组T1包括串联的两个第一晶体管T11为例进行示意。第一个第一晶体管为T11A，第二个(最后一个)第一晶体管为T11B。可以理解的是，在另一些实施例中，第一晶体管组T1可以包括串联其他数值的第一晶体管T11。
第一晶体管组T1中的所有第一晶体管T11的栅极均与第一扫描信号端Gate1耦接。第一晶体管组T1中的第一个第一晶体管T11A的第一极与第一节点N1耦接，第一晶体管组T1中的最后一个第一晶体管T11B的第二极与第三节点N3耦接。第一晶体管组T1中的第一个第一晶体管T11A的第二极与第一晶体管组T1中的第二个第一晶体管T11B的第一极之间形成第四节点N4。
在一些示例中，请继续参阅图3所示，写入子电路20与第二节点N2、第一扫描信号端Gate1及数据信号端Data耦接，写入子电路20被配置为，在写入阶段，在来自第一扫描信号端Gate1接收的栅扫描信号的控制下，将在数据信号端Gate1处接收的数据信号传输至第二节点N2。
可以理解的时，采用上述设置方式，在写入阶段，第一扫描信号端Gate1 接收的栅扫描信号的有效信号与补偿控制端G0接收的补偿信号的有效信号至少部分同时进行。示例性的，第一扫描信号端Gate1接收的栅扫描信号的有效信号与补偿控制端G0接收的补偿信号的有效信号同步进行。例如，第一扫描信号端Gate1接收的栅扫描信号复用为补偿控制端G0接收的补偿信号。其中，图3以第一扫描信号端Gate1接收的栅扫描信号复用为补偿控制端G0接收的补偿信号为例进行示意。
基于此，可以使得写入子电路20在第一扫描信号端Gate1接收的栅扫描信号的控制下导通，这样写入子电路20将在数据信号端Data处接收的数据信号传输至第二节点N2，该数据信号经驱动子电路10后变为补偿信号，该补偿信号经补偿子电路30传输至第一节点N1，即补偿信号写入完成，也实现了对驱动子电路10的阈值电压Vth的补偿。
需要说明的是，显示面板200中的每个子像素由多个薄膜晶体管(TFT)驱动发光，采用TFT驱动技术可以提升显示速度、对比度和亮度、提高分辨率。但是，TFT存在磁滞效应现象，TFT的磁滞效应是在一定的偏压下，TFT电特性表现出来的一种不确定性，即流过TFT的电流不仅与当前的偏压有关，还与上一时刻TFT所处的状态。TFT的磁滞效应与TFT的栅介质、半导体材料以及两者之间的界面态陷阱有关，在发光阶段，TFT的磁滞效应会造成会引起一帧内电流下降的趋势，人眼察觉为闪烁现象从而影响显示面板200的显示品质。
一个发光周期(一帧)包括一个刷新帧和至少一个保持帧。一个发光周期(一帧)为一个显示帧，也即一个显示画面。刷新帧包括复位阶段、写入阶段及第一发光阶段。保持帧包括发光调节阶段和第二发光阶段。本公开发明人经研究发现，在刷新帧，第一节点N1和第四节点N4的电压基本相同；在保持帧，第四节点N4的电压被第一扫描信号端Gate1电压拉高，导致第四节点N4的电压可能大于第一节点N1的电压。而在第四节点N4的电压大于第一节点N1的电压时，第四节点N4会向第一节点N1漏流，从而会导致第一节点N1的电压无法稳定。使一帧内发光器件的亮度保持率较低，在一帧内的亮度保持率降低到人眼可观察的范围内时，则容易出现闪屏的现象。
在像素驱动电路100包括：驱动子电路10、写入子电路20和补偿子电路30时。本公开对第一节点N1的电压和第四节点N4的电压，进行了仿真验证，得到计算结果如图4和表1所示。
其中，表1所示的每个发光周期均包括三个保持帧，以一个发光周期内最后一个保持帧的数据为例进行示意。
表1为像素驱动电路100中第一节点N1的电压和发光器件O阳极的电压变化表。
Figure PCTCN2022103187-appb-000002
在第一扫描信号端Gate1提供的扫描信号为低电压信号(有效信号)时，在第一扫描信号端Gate1提供的低电压信号的控制下，第一晶体管组T1包括的串联的至少两个第一晶体管T11导通，第四节点N4的电压等于第一节点N1的电压。
在第一扫描信号端Gate1提供的扫描信号变为高电压信号(无效信号)时，在第一扫描信号端Gate1提供的高电压信号的控制下，第一晶体管组T1包括的串联的至少两个第一晶体管T11关闭。此时，由于第一晶体管组中的第一晶体管T1的栅极和源极之间存在的电容Cgs或者栅极和漏极之间存在的电容Cgd，在第一扫描信号端Gate1提供的扫描信号的电压从低电压变为高电压时，在电容Cgs或者电容Cgd的耦合作用下，第四节点N4的电压被拉高。而在第四节点N4的电压被拉高时，会导致第一节点N1的电压无法稳定，使一帧内发光器件的亮度保持率较低，导致低频下显示面板200出现闪屏现象。
图5为本公开又一些实施例的一种像素驱动电路的结构图。图6为本公开又一些实施例的一种像素驱动电路的结构图。
基于此，本公开一些实施例提供的一种像素驱动电路100，继续参阅图3、图5和图6所示，还包括调节子电路40。调节子电路40与第二节点N2和/或第三节点N3耦接、且与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接，调节子电路40被配置为，在发光调节阶段，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和/或第三节点N3。
其中，“将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和/或第三节点N3”包括以下三种方式：
第一种：请继续参阅图3所示，将在第一参考电压信号端Vinit3处接收 的参考电压信号传输至第二节点N2。
通过设置调节子电路40，调节子电路与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接。在发光调节阶段，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2。由于在发光调节阶段的上一阶段未进行数据刷新，第一扫描信号端Gate1的电位较高。第四节点N4的电压被第一扫描信号端Gate1电压拉高，导致第四节点N4的电压可能大于第一节点N1的电压。
由此利用第一参考电压信号端Vinit3处接收的参考电压信号调节第二节点N2的电压。由于驱动子电路10的驱动晶体管的栅极和源极之间存在的栅源电容，在第二节点N2的电压改变时，在栅源电容的耦合作用下，第一节点N1的电压同步改变，从而可以补偿第四节点N4对第一节点N1的电压的影响。在发光调节阶段使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善下一次发光阶段时的亮度变化，改善了发光器件O及显示面板200的闪屏现象。
第二种：请继续参阅图5所示，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第三节点N3。
通过设置调节子电路40，调节子电路与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接。在发光调节阶段，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第三节点N3。由于在发光调节阶段的上一阶段未进行数据刷新，第一扫描信号端Gate1的电位较高。第四节点N4的电压被第一扫描信号端Gate1电压拉高，导致第四节点N4的电压可能大于第一节点N1的电压。由于在发光调节阶段的上一阶段未进行数据刷新，第一扫描信号端Gate1的电位较高。第四节点N4的电压被第一扫描信号端Gate1电压拉高，导致第四节点N4的电压可能大于第一节点N1的电压。
由此利用第一参考电压信号端Vinit3处接收的参考电压信号调节第三节点N3的电压。由于驱动子电路10的驱动晶体管的栅极和漏极之间存在的栅漏电容，在第三节点N3的电压改变时，在栅漏电容的耦合作用下，第一节点N1的电压同步改变，从而可以补偿第四节点N4对第一节点N1的电压的影响。在发光调节阶段，使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善下一次发光阶段时的亮度变化，改善了发光器件O及显示面板200的闪屏现象。
第三种：请继续参阅图6所示，将在第一参考电压信号端Vinit3处接收 的参考电压信号传输至第二节点N2和第三节点N3。
通过设置调节子电路40，调节子电路与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接。在发光调节阶段，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和第三节点N3。
由此利用第一参考电压信号端Vinit3处接收的参考电压信号调节第二节点N2和第三节点N3的电压。由于驱动子电路10的驱动晶体管的栅极和漏极之间存在的栅漏电容，栅极和源极之间存在栅源电容。在第二节点N2和第三节点N3的电压改变时，在栅源电容和栅漏电容的耦合作用下，第一节点N1的电压同步改变，从而可以补偿第四节点N4对第一节点N1的电压的影响。在发光调节阶段，使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善下一次发光阶段时的亮度变化，改善了发光器件O及显示面板200的闪屏现象。
综上所述，本公开一些实施例所提供的像素驱动电路100，调节子电路与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和/或第三节点N3。由此利用第一参考电压信号端Vinit3处接收的参考电压信号调节第二节点N2和第三节点N3的电压。由于驱动子电路10的驱动晶体管的栅极和元漏极存在电容，在驱动晶体管栅源位置处的电压变化时，在电容耦合的作用下，可以同步调节栅极的电压，也即同步调节第一节点N1的电压。从而可以补偿第四节点N4对第一节点N1的电压的影响。使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善了发光器件O及显示面板200的闪屏现象。
图7为本公开一些实施例的一种像素驱动电路，高灰阶状态下，第一节点的电压、发光器件阳极电压的电压变化的仿真图。图8为本公开一些实施例的一种像素驱动电路，低灰阶状态下，第一节点的电压、发光器件阳极电压的电压变化的仿真图。
示例性的，显示面板200包括低灰阶(例如：G0、G15、G30等)状态和高灰阶(例如：G110、G220、G255)状态。在低灰阶状态时，像素驱动电路100中的第一节点N1的电压，高于高灰阶状态时，像素驱动电路100中的第一节点N1的电压。
本公开的一些实施例对高灰阶状态，且像素驱动电路100包括调节子电 路40时，第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证；并且对高灰阶状态，且像素驱动电路100不包括调节子电路时，第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证，得到计算结果如图7所示。本公开的一些实施例对低灰阶状态，且像素驱动电路100包括调节子电路40时，第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证。并且对低灰阶状态，且像素驱动电路100不包括调节子电路时，第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证，得到计算结果如图8所示。参阅图7和图8所示，显而易见，高灰阶状态相比低灰阶状态，第一节点N1电压和第四节点N4电压的差异较为明显。
在一些实施例中，继续参阅图3所示，第一参考电压信号端Vinit3处接收的参考电压信号的取值范围为-5V～5V。
通过第一参考电压信号端Vinit3处接收的参考电压信号调节第二节点N2的电压，利用电容耦合，调节第一节点N1电压。从而提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善了发光器件O及显示面板200的闪屏现象。
在一些示例中，针对高灰阶状态时，为了满足显示面板200高灰阶状态的需求，需设置像素驱动电路100中第一节点N1的电压值低一些，以便调节驱动子电路10的打开情况。而在第一节点N1电压较低，而第四节点N4电压升高的情况下，导致第一节点N1电压和第四节点N4的电压的差值更大，使一帧内发光器件的亮度保持率较低。由此，设置第一参考电压信号端Vinit3处接收的参考电压信号的取值范围为-5V～5V。将参考电压信号写入第二节点N2，利用第二节点N2的电压变化量调节第一节点N1的电压，从而补偿第四节点对第一节点N1的电压的影响，使得第一节点N1处于动态平衡的状态。提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善了发光器件O及显示面板200的闪屏现象。
示例性的，针对高灰阶状态，且第一参考电压信号端Vinit3处接收的参考电压信号为4V时，本公开对第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证，得到计算结果如表2所示。其中，改善前表示为像素驱动电路100未设置调节子电路40。改善后表示为像素驱动电路100包括调节子电路40。
根据表2所示，在第一参考电压信号端Vinit3处接收的参考电压信号为4V时，在像素驱动电路100未设置调节子电路40时，第一节点N1电压的变化量为0.0713V，发光器件O阳极电压的变化量为0.064V。而在像素驱动电 路100设置调节子电路40时，第一节点N1电压的变化量可以降至0.047V，减少电压变化量0.027V，发光器件O的电压变化量降至0.039V，减少电压变化量0.025V。可以相对稳定第一节点N1的电压，以及提高发光器件O的亮度保持率，改善了及显示面板200的闪屏现象。
表2为高灰阶状态时第一种第一节点N1的电压和发光器件O阳极的电压变化表。
Figure PCTCN2022103187-appb-000003
在一些示例中，针对低灰阶状态时，为了满足显示面板200低灰阶状态的需求，需设置像素驱动电路100中第一节点N1的电压值高一些，以便调节驱动子电路10的打开情况。而在第一节点N1电压较高时，第四节点N4电压升高并不会导致第一节点N1电压和第四节点N4的电压的差值更大。也即在低灰阶状态时，显示面板200的闪屏现象不明显。在此基础上，设置第一参考电压信号端Vinit3处接收的参考电压信号的取值范围为-5V～5V。将参考电压信号写入第二节点N2，第二节点N2与第一节点N1的电位差值较小，并不会较为明显的影响第一节点N1的电位，也即不会太大影响第一节点N1电压的保持率。
示例性的，第一参考电压信号端Vinit3处接收的参考电压信号为-5V、-3V、-1V、1V、3V或者5V。可以理解的是，在另外一些实施例中，第一参考电压信号端Vinit3处接收的参考电压信号可以为在-5V～5V这个范围内的其他数值。
示例性的，针对低灰阶状态，且第一参考电压信号端Vinit3处接收的参考电压信号为4V时，本公开对第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证，得到计算结果如表3所示。其中，改善前表示为像素驱动电路100未设置调节子电路40。改善后表示为像素驱动电路100包括调节子电路40。
表3为低灰阶状态时第一种第一节点N1的电压和发光器件O阳极的电压变化表。
Figure PCTCN2022103187-appb-000004
根据表3所示，在第一参考电压信号端Vinit3处接收的参考电压信号为4V时，在像素驱动电路100未设置调节子电路40时，第一节点N1电压的变化量为0.017V，发光器件O阳极电压的变化量为0.005V。而在像素驱动电路100设置调节子电路40时，依旧保持原有的电压变化量。所以在像素驱动电路100设置调节子电路40时，可以保持第一节点N1的稳定性，提高发光器件O的亮度保持率。
综上，本公开一些实施例所提供的像素驱动电路100，通过设置调节子电路40，且设置第一参考电压信号端Vinit3处接收的参考电压信号的取值范围为-5V～5V。既可以有效改善高灰阶状态时，像素驱动电路100中第一节点N1电压的稳定性，又可以保持低灰阶状态时，像素驱动电路100中第一节点N1电压的稳定性。从而无论显示面板200处于什么状态时，都可以有效改善闪屏现象。
在一些实施例中，继续参阅图3所示，第一参考电压信号端Vinit3处接收的参考电压信号大约为2V。
可以理解为，第一参考电压信号端Vinit3处接收的参考电压信号的电压值可以存在一定的偏差。例如，偏差值可以为±1、±0.5等。
针对高灰阶状态，且第一参考电压信号端Vinit3处接收的参考电压信号为2V时，本公开的一些实施例对第一节点N1的电压和发光器件O阳极的电压，进行了仿真验证，得到计算结果如表4所示。其中，改善前表示为像素驱动电路100未设置调节子电路40。改善后表示为像素驱动电路100包括调节子电路40。
根据表4所示，在第一参考电压信号端Vinit3处接收的参考电压信号为 2V时，在像素驱动电路100未设置调节子电路40时，第一节点N1电压的变化量为0.0713V，发光器件O阳极电压的变化量为0.064V。而在像素驱动电路100设置调节子电路40时，第一节点N1电压的变化量可以降至0.0298V，减少电压变化量0.0415V，发光器件O的电压变化量降至0.027V，减少电压变化量0.037V。相对于在第一参考电压信号端Vinit3处接收的参考电压信号为4V时，设置为2V可以有效的降低第一节点N1电压和发光器件O阳极电压的变化量，从而可以更好的改善显示面板200的闪屏现象。
表4为高灰阶状态时第二种第一节点N1的电压和发光器件O阳极的电压变化表。
Figure PCTCN2022103187-appb-000005
其中，上述仅以第一参考电压信号端Vinit3处接收的参考电压信号为2V、4V时为例进行示意。在另外一些实施例中，第一参考电压信号端Vinit3处接收的参考电压信号可以为-5V～5V范围内的其他数值。
在一些实施例中，继续参阅图3所示，调节子电路40还被配置为，在复位阶段，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2，对第二节点N2复位。
采用上述设置方式，在复位阶段，可以使得调节子电路40在第二扫描信号端Gate2传输的扫描信号的控制下导通，使得第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2，对第二节点N2复位。可以有效抵消驱动子电路10中驱动晶体管的磁滞效应，提升一帧内亮度保持率，进而改善低频下显示面板200的闪屏现象。
图9为本公开一些实施例的又一种像素驱动电路的结构图。在一些实施例中，请参阅图9所示，调节子电路40包括第二晶体管T2。
第二晶体管T2的栅极和第二扫描信号端Gate2耦接，第二晶体管T2的 第一极和第二节点N2耦接，第二晶体管T2的第二极和第一参考电压信号端Vinit3耦接。
示例性的，在复位阶段，第二扫描信号端Gate2传输的扫描信号为低电平(有效电平)信号，调节子电路40所包括的第二晶体管T2在第二扫描信号端Gate2传输的低电平信号的控制下导通，此时第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2，对第二节点N2复位。可以有效抵消驱动子电路10中驱动晶体管的磁滞效应，提升一帧内亮度保持率，进而改善低频下显示面板200的闪屏现象。
在一些实施例中，请继续参阅图9所示，驱动子电路10包括驱动晶体管TD。
驱动晶体管TD的栅极与第一节点N1耦接，驱动晶体管DT的第一极与第二节点N2耦接，驱动晶体管DT的第二极与第三节点N3耦接。
示例性的，在第一节点N1的电压为有效电平的情况下，驱动晶体管TD可以在第一节点N1的电压的控制下导通，将来自第二节点N2的电信号(例如数据信号)传输至第三节点N3。
需要说明的是，本公开中的“有效电平”指的是能够使得晶体管导通的电平。在晶体管为N型晶体管的情况下，“有效电平”则为高电平；在晶体管为P型晶体管的情况下，“有效电平”则为低电平。以下各实施例与此相同，不再赘述。
在一些实施例中，请继续参阅图9所示，写入子电路20包括第三晶体管T3。
第三晶体管T3的栅极与第一扫描信号端Gate1耦接，第三晶体管T3的第一极与数据信号端Data耦接，第三晶体管T3的第二极与第二节点N2耦接。
示例性的，第一扫描信号端Gate1传输的扫描信号为低电平(有效电平)信号，写入子电路20所包括的第三晶体管T3在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时数据信号端Data处接收的数据信号传输至第二节点N2。以及，该数据信号经驱动子电路10后变为补偿信号，该补偿信号经补偿子电路30传输至第一节点N1，即补偿信号写入完成，也实现了阈值电压Vth的补偿。提升一帧内亮度保持率，进而改善低频下显示面板200的闪屏现象。
在一些实施例中，请继续参阅图9所示，第一扫描信号端Gate1被配置为，在控制第三晶体管T3的第一极接收数据信号端Data的数据信号之前，控制第三晶体管T3开启至少1次。
在控制第三晶体管T3的第一极接收数据信号端Data的数据信号之前，对第三晶体管T3的第一极进行至少1次复位，便于提高驱动子电路10所包括的驱动晶体管TD的稳定性。
在一些实施例中，第一扫描信号端Gate1被配置为，在控制第三晶体管T3的第一极接收数据信号端Data的数据信号之前，控制第三晶体管T3开启一次。可以理解的是，在另一些实施例中，第一扫描信号端Gate1被配置为，在控制第三晶体管T3的第一极接收数据信号端Data的数据信号之前，控制第三晶体管T3开启两次或两次以上。
在一些实施例中，请继续参阅图9所示，像素驱动电路100还包括第二储能子电路60。
示例性的，第二储能子电路60包括第二电容Cst。
第二电容Cst的第一极板与第一电压端VDD耦接，第二电容Cst的第二极板与第一节点N1耦接。
示例性的，写入子电路20所包括的第三晶体管T3在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时数据信号端Data处接收的数据信号传输至第二节点N2；同时数据信号端Data处接收的数据信号也传输至第二电容Cst，对第二电容Cst进行充电。补偿子电路30所包括的第一晶体管组T1在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时第二节点N2处接收的数据信号传输至第一节点N1，对第一节点N1进行补偿。第一节点N1的电位逐渐上升至Vdata+Vth。其中，Vdata为数据信号端Data提供的数据信号的电压值，Vth为驱动子电路10中的驱动晶体管TD的阈值电压。在第一节点N1的电位为Vdata+Vth时，完成充电过程。后续，利用第二电容Cst放电保持驱动子电路10所包括的驱动晶体管TD持续导通，确保发光器件O发光。
图10为本公开一些实施例的又一种像素驱动电路的结构图。在一些实施例中，请参阅图10所示，像素驱动电路100还包括第一存储子电路50。第一存储子电路50与第一电压端VDD和第二节点N2耦接。第一存储子电路50被配置为，存储并保持第二节点N2的电压。
示例性的，写入子电路20所包括的第三晶体管T3在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时数据信号端Data处接收的数据信号传输至第二节点N2，同时也对第一存储子电路50充电。在第一发光阶段，第一存储子电路50可以保持第二节点N2的电压，确保驱动子电路10所包括的驱动晶体管TD的稳定性。
第一存储子电路50包括第一电容C1，电容的第一极板与第一电压端VDD耦接，第一电容C1的第二极板与第二节点N2耦接。
示例性的，写入子电路20所包括的第三晶体管T3在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时数据信号端Data处接收的数据信号传输至第二节点N2；同时数据信号端Data处接收的数据信号也传输至第一电容C1，对第一电容C1充电。当调节子电路40在来自第二扫描信号端Gate2传输的低电平信号的控制下导通，此时第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2。在调节子电路40在来自第二扫描信号端Gate2传输的高电平信号的控制下关断时，此时，第一电容C1可以保持第二节点N2的电压，从而保持第一节点N1电压的稳定性。
在一些实施例中，请继续参阅图10所示，像素驱动电路100包括第一电容C1和第二电容Cst。
Figure PCTCN2022103187-appb-000006
C1为第一电容C1的电容值，Cst为第二电容Cst的电容值。
当第一电容C1的电容值C1等于或趋近于
Figure PCTCN2022103187-appb-000007
时，第一电容C1可以实现对第二节点N2的电压的保持，同时可以防止第一电容C1对第二电容Cst影响，更好的保持第一节点N1的稳定性。当第一电容C1的电容值C1等于或趋近于
Figure PCTCN2022103187-appb-000008
时，可以防止第一电容C1对第二电容Cst影响，同时可以更好的稳定保持第二节点N2的电压，从而稳定第一节点N1的电压。
示例性的，
Figure PCTCN2022103187-appb-000009
或
Figure PCTCN2022103187-appb-000010
在一些实施例中，请继续参阅图10所示，像素驱动电路100还包括第一复位子电路70。
第一复位子电路70，与第一节点N1、第一复位信号端Reset1、及第一初始化信号端Vinit1耦接；第一复位子电路70被配置为，在复位阶段，在来自第一复位信号端Reset1接收的复位信号的控制下，将在第一初始化信号端Vinit1接收的初始化信号传输至第一节点N1，对第一节点N1复位。
示例性的，在复位阶段，第一复位子电路70在来自第一复位信号端Reset1接收的复位信号的控制下，将在第一初始化信号端Vinit1接收的初始化信号传输至第一节点N1，对第一节点N1进行复位，便于提高驱动子电路10所包括的驱动晶体管TD的稳定性。
示例性的，在复位阶段，利用第一复位子电路70对第一节点N1进行复位，利用调节子电路40对第二节点N2进行复位。使得驱动晶体管TD在写入阶段之前的初始状态固定，便于在写入阶段时使驱动晶体管TD处于稳定状 态，较大程度的改善驱动晶体管TD的迟滞效应。
在一些实施例中，请继续参阅图10所示，第一复位子电路70包括第四晶体管组T4，第四晶体管组T4包括串联的至少两个第四晶体管T41。
其中，图10以第四晶体管组T4包括串联的两个第四晶体管T41为例进行示意。第一个第四晶体管T41为T41A，第二个(最后一个)第四晶体管T41为T41B。可以理解的是，在另一些实施例中，第四晶体管组T4可以包括串联其他数值的第四晶体管T41。
第四晶体管组T4中的所有第四晶体管T41的栅极均与第一复位信号端Reset1耦接，第四晶体管组T4中的第一个第四晶体管T41A的第一极与第一节点N1耦接，第四晶体管组T4中的最后一个第四晶体管T41B的第二极与第一初始化信号端Vinit1耦接。
示例性的，第一复位子电路70所包括的第四晶体管T41在来自第一复位信号端Reset1接收的低电平信号(有效信号)的控制下导通，接收并传输在第一初始化信号端Vinit1接收的初始化信号至第一节点N1，对第一节点N1进行复位。
第一复位信号端被配置为，在控制至少一个第四晶体管T41的第二极接收第一初始化信号端Vinit1的第一初始化信号之前，控制至少一个第四晶体管T41开启至少1次。至少1次开启第四晶体管T41以便对第四晶体管T41的栅极进行复位，便于提高第一复位子电路70所包括的第四晶体管T41的稳定性。
需要说明的是，在第四晶体管组T4包括串联的至少两个第四晶体管T41时，可以降低第一节点N1从第四晶体管T41漏电的风险，更有利于保证第一节点N1的电压的稳定性。
在一些实施例中，请继续参阅图10所示，像素驱动电路100还包括发光控制子电路80。
发光控制子电路80，与第一电压端VDD、使能信号端EM1、第二节点N2、第三节点N3以及发光器件O耦接。发光控制子电路80被配置为，在来自使能信号端EM1的使能信号的控制下，与驱动子电路10配合，向发光器件O传输驱动信号。
示例性的，发光控制子电路80在来自使能信号端EM1的低电平(有效电平)信号控制下，与驱动子电路10配合，将第一电压端VDD提供的电信号传输至第二节点N2、第二节点N2将电信号传输至第三节点N3，第三节点N3继续将电信号传输至发光器件O。该电信号可以与发光器件O耦接的第二 电压信号端Vss提供的电信号相互配合，驱动发光器件O正常发光，实现显示。
在一些实施例中，请继续参阅图10所示，发光控制子电路80包括第五晶体管T5和第六晶体管T6。
第五晶体管T5的栅极与使能信号端EM1耦接，第五晶体管T5的第一极与第一电压信号VDD端耦接，第五晶体管T5的第二极与第二节点耦接。
第六晶体管T6的栅极与使能信号端EM1耦接，第六晶体管T6的第一极与第三节点N3耦接，第六晶体管T6的第二极与发光器O件耦接。
示例性的，发光控制子电路80所包括的第五晶体管T5和第六晶体管T6在来自使能信号端EM1的低电平(有效电平)信号的控制下导通，且驱动子电路10所包括的驱动晶体管TD导通的情况下，第一电压信号VDD端提供的电压信号可以依次经过第二节点N2、驱动晶体管TD、第三节点N3传输至发光器件O，该电信号可以与发光器件O耦接的第二电压信号端Vss提供的电信号相互配合，驱动发光器件O正常发光，实现显示。
在一些实施例中，请继续参阅图10所示，像素驱动电路100还包括第二复位子电路90。
第二复位子电路90，与第二复位信号端Reset2、第二初始化信号端Vinit2、以及发光器件O耦接；第二复位子电路被配置为，在来自第二复位信号端Reset2接收的复位信号的控制下，将在第二初始化信号端Vinit2接收的初始化信号传输至发光器件O。
示例性的，第二复位子电路90在来自第二复位信号端Reset2接收的复位信号的控制下，将在第二初始化信号端Vinit2接收的初始化信号传输至发光器件O，对发光器件O的阳极进行复位，提高发光器件O的稳定性。
在一些实施例中，请继续参阅图10所示，第二复位子电路90包括第七晶体管T7。
第七晶体管T7的栅极与第二复位信号端Reset2耦接，第七晶体管T7的第一极与光学器件O耦接，第七晶体管T7的第二极与第二初始化信号端Vinit2耦接。
示例性的，第二复位子电路90所包括第七晶体管T7，在来自第二复位信号端Reset2接收的低电平(有效电平)信号的控制下导通，将第二初始化信号端Vinit2接收的初始化信号传输至发光器件O。第二初始化信号端Vinit2接收的初始化信号可以为低电平信号，便于利用该信号对发 光器件O的阳极进行复位，提高发光器件O的稳定性。
图11为本公开一些实施例的又一种像素驱动电路的结构图。在一些实施例中，请参阅图11所示，第二复位信号端Reset2和第二扫描信号端Gate2响应于同一个控制信号的控制。
示例性的，图11以第二扫描信号端Gate2复用为第二复位信号端Reset2为例进行示意。一方面，第二扫描信号端Gate2复用为第二复位信号端Reset2，可以简化像素驱动电路100的结构，有利于降低显示面板200内的布局难度。另一方面，第二复位信号端Reset2和第二扫描信号端Gate2响应于同一个控制信号的控制，第二复位信号端Reset2可以在一帧内对发光器件O的阳极进行多次复位，进一步提高发光器件O的稳定性。
在一些实施例中，请继续参阅图10所示，第二初始化信号端Gate2接收的初始化信号与使能信号端EM1接收的使能信号反相。
示例性的，第二初始化信号端Gate2接收的初始化信号与使能信号端EM1接收的使能信号反相。可以理解为，第二初始化信号端Gate2接收的初始化信号与使能信号端EM1接收的使能信号交替设置。例如，第二初始化信号端Gate2接收的初始化信号为低电平信号，此时使能信号端EM1接收的使能信号为高电平信号。或者，第二初始化信号端Gate2接收的初始化信号为高电平信号，此时使能信号端EM1接收的使能信号为低电平信号。由此可以保证在使能信号端EM1接收的使能信号控制发光控制子电路80导通之前，对发光器件O的阳极进行复位，便于提高发光器件O的稳定性。
例如，第二初始化信号端Gate2可以为与使能信号端EM1接收的使能信号反相的信号端EM2。此时，信号端EM2和第二初始化信号端Gate2为同一信号端。此时，信号端EM2可以对使能信号端EM1改进得到，后文针对显示面板200内部结构会详细阐述。由此，上述结构还可以简化像素驱动电路100的结构，有利于降低显示面板200内的布局难度。
本公开一些实施例还提供了一种像素驱动电路的驱动方法，该驱动方法应用于上述任一实施例中的像素驱动电路100。
图12为本公开一些实施例的一种像素驱动电路的时序图。在一些实施例中，请参阅图12，以及图9所示。
像素驱动电路100包括：驱动子电路10、写入子电路20、补偿子电路30、发光控制子电路及调节子电路40。驱动子电路10与第一节点N1、第二节点N2及第三节点N3耦接。写入子电路20与第二节点N2、第一扫描信号端Gate1及数据信号端Data耦接。补偿子电路30与第一节点N1、第三节点 N3、补偿控制端G0耦接。发光控制子电路80，与第一电压端VDD、使能信号端EM1、第二节点N2、第三节点N3以及发光器件O耦接。调节子电路40与第二节点N2和/或第三节点N3耦接、且与第二扫描信号端Gate2及第一参考电压信号端Vinit3耦接。
驱动方法包括：多个发光周期F。一个发光周期F(一帧)包括一个刷新帧F1和至少一个保持帧F2。一个发光周期(一帧)为一个显示帧，也即一个显示画面。刷新帧F1包括复位阶段P1、写入阶段P2和第一发光阶段P3。保持帧F2包括发光调节阶段P4和第二发光阶段P5。
在写入阶段P2，写入子电路20，在来自第一扫描信号端Gate1接收的栅扫描信号的控制下，将在数据信号端Data处接收的数据信号传输至第二节点N2；驱动子电路10将来自第二节点N2的数据信号传输至第三节点N3；补偿子电路30将第三节点N3的电压传输至第一节点N1。
示例性的，在写入阶段P2，第一扫描信号端Gate1接收的栅扫描信号的有效信号与补偿控制端G0接收的补偿信号的有效信号至少部分同时进行。示例性的，第一扫描信号端Gate1接收的栅扫描信号的有效信号与补偿控制端G0接收的补偿信号的有效信号同步进行。例如，第一扫描信号端Gate1接收的栅扫描信号复用为补偿控制端G0接收的补偿信号。
在第一发光阶段P3，在来自使能信号端EM1的使能信号的控制下，与驱动子电路10配合，向发光器件O传输驱动信号，第一电压端VDD提供的电压信号传输至发光器件O，以驱动发光器件O发光。
在发光调节阶段P4，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和/或第三节点N3。
示例性的，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2。
示例性的，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第三节点N3。
示例性的，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和第三节点N3。
在第二发光阶段P5，发光控制子电路80，在来自使能信号端EM1的信 号的控制下，以及在第一节点N1的控制下，发光控制子电路80与驱动子电路10配合，将第一电压端提供的电压信号传输至发光器件O，以驱动发光器件O发光。
本公开一些实施例所提供的像素驱动电路100，通过在发光调节阶段P4，调节子电路40在来自第二扫描信号端Gate2传输的低电平(有效电平)信号的控制下导通，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2和/或第三节点N3。由于在第一发光阶段P3未进行数据刷新，第一扫描信号端Gate1的电位较高。第四节点N4的电压被第一扫描信号端Gate1电压拉高，导致第四节点N4的电压可能大于第一节点N1的电压。
由此，利用第一参考电压信号端Vinit3处接收的参考电压信号调节第二节点N2和/或第三节点N3的电压。由于驱动子电路10的驱动晶体管的栅极和元漏极之间存在的电容，在第二节点N2和/或第三节点N3的电压改变时，在电容的耦合作用下，第一节点N1的电压同步改变，从而可以补偿第四节点N4对第一节点N1的电压的影响。在发光调节阶段P4使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善在第二发光阶段P5时的亮度变化，改善了发光器件O及显示面板200的闪屏现象。
其中，一个发光周期F1(一帧)包括一个刷新帧F1和至少一个保持帧F2。图12以包括一个保持帧F2为例进行示意。当一个发光周期F包括多个保持帧F2时，对于保持帧F2内的时序与图12中保持帧F2的时序相同。例如，当一个发光周期F包括一个刷新帧F1和三个保持帧F2时，三个保持帧F2的时序可以理解为重复三次图12中的保持帧F2。在另一些实施例中，一个发光周期F内可以包括其他数值的保持帧F2，具体保持帧F2的数量可以根据显示面板200的驱动状态设置。例如，显示面板200低频驱动时，一个发光周期F内保持帧F2的数量，多于显示面板200高频驱动时一个发光周期F内保持帧F2的数量。也是基于此，由于显示面板200低频驱动时保持帧F2的数量较多，导致显示面板在显示时更容易出现闪烁的现象。
在一些实施例中，请继续参阅图12所示，在复位阶段P1，调节子电路40将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2，对第二节点N2进行至少一次复位。
示例性的，图12以在复位阶段P1，利用调节子电路40对第二节点N2进行一次复位为例进行示意。在复位阶段P1，调节子电路40在来自第二扫描信号端Gate2传输的低电平(有效电平)信号的控制下导通，将在第一参考电 压信号端Vinit3处接收的参考电压信号传输至第二节点N2。使得驱动晶体管TD在写入阶段之前的初始状态固定，便于在写入阶段时使驱动晶体管TD处于稳定状态，较大程度的改善驱动晶体管TD的迟滞效应。
综上，本公开一些实施例提供的像素驱动方法，一方面，可以在发光调节阶段P4，通过调节子电路40将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2。在电容耦合作用下，利用第二节点N2的电压变化量补偿第一节点N1的电压变化量，使得第一节点N1的电压处于动态平衡，提高第一节点N1的电位稳定性，使一帧内发光器件O的亮度保持率较高，改善了发光器件O及显示面板200的闪屏现象。另一方面，还可以在复位阶段P1，通过调节子电路40对第二节点N2进行复位，使得驱动晶体管TD在写入阶段之前的初始状态固定，便于在写入阶段时使驱动晶体管TD处于稳定状态，较大程度的改善驱动晶体管TD的迟滞效应。
需要说明的是，写入阶段P2包括多次复位第一节点N1电压和将数据信号写入第一节点N1的过程，可以更好的使得驱动晶体管TD处于稳定的状态，可以更好的改善迟滞效应。
图13为本公开一些实施例的又一种像素驱动电路的时序图。在一些示例中，参阅图13所示，在复位阶段P1，对第二节点N2进行多次复位。
在复位阶段P1，通过调节子电路40对第二节点N2进行多次复位。可以复位的更彻底。更有利于在写入阶段时使驱动晶体管TD处于稳定状态，更好的改善驱动晶体管TD的迟滞效应。
示例性的，继续参阅图13所示。在复位阶段P1，对第二节点N2进行2～4次复位。其中，图13以在复位阶段P1，对第二节点N2进行3次复位为例进行示意。
当在复位阶段P1对第二节点N2复位的次数等于或趋近于2次时，既可以实现对第二节点N2进行复位，又可以防止复位次数过多导致影响了占空比而影响显示效果的问题。当在复位阶段P1对第二节点N2复位的次数等于或趋近于4次时，可以在尽量不影响占空比的同时更彻底的对第二节点N2的复位。
示例性的，在复位阶段P1对第二节点N2复位的次数可以为2次、3次或4次。
图14为本公开一些实施例的又一种像素驱动电路的时序图。在一些实施例中，请参阅图14所示，在复位阶段P1，调节子电路40对第二节点N2进行复位后，第一复位子电路70，在来自第一复位信号端Reset1接收的第一 复位信号的控制下，将在第一初始化信号端Vinit1接收的初始化信号传输至第一节点N1。
示例性的，在复位阶段P1，第一复位信号端Reset1接收的低电平(有效电平)信号早于第一复位信号端Reset1接收的低电平(有效电平)信号。使得调节子电路40相比于第一复位子电路70提前导通。也即先通过调节子电路40对第二节点N2进行复位，再通过第一复位子电路70对第一节点N1进行复位。相对于图12所示的同时复位的情况，可以使得驱动晶体管TD的复位保持时间更长一些，从而可以更彻底的改善迟滞效应。
图15为本公开一些实施例的又一种像素驱动电路的时序图。在一些实施例中，请参阅图15所示，在写入阶段P2，将在数据信号端Data处接收的数据信号传输至第一节点N1后，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2，对第二节点N2进行复位。
示例性的，在写入阶段P2中，写入子电路20中的第三晶体管T3导通，将数据信号端Data提供的数据信号写入第二节点N2，第二节点N2的数据信号经过驱动子电路10中的驱动晶体管TD写入第三节点N3，第三节点N3的数据信号经过补偿子电路30中的第一晶体管组T1对第一节点N1进行补偿。第一节点N1的电位逐渐上升至Vdata+Vth。其中，Vdata为数据信号端Data提供的数据信号的电压值，Vth为驱动子电路10中的驱动晶体管TD的阈值电压。
而上述写入过程中，会改变第二节点N2的电压。由此，在完成上述过程后再次对第二节点N2进行刷新，可以使驱动晶体管TD每次存储的电压数值相同，有利于改善驱动晶体管TD存在迟滞效应的问题。使得像素驱动电路100每次开启亮度的时间大致相同，提高显示面板的显示效果。
在一些实施例中，继续参阅图12，以及结合图10所示。在写入阶段P2，对第一存储子电路50充电。在第一发光阶段P3，第一存储子电路50放电至第二节点N2，补偿第二节点N2的电压。
示例性的，在写入阶段P2，写入子电路20所包括的第三晶体管T3在第一扫描信号端Gate1传输的低电平信号的控制下导通，此时数据信号端Data处接收的数据信号传输至第二节点N2；同时数据信号端Data处接收的数据信号也传输至第一电容C1，对第一电容C1充电。当调节子电路40在来自第二扫描信号端Gate2传输的低电平信号的控制下导通，此时第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2。在调节子电路40在来自第 二扫描信号端Gate2传输的高电平信号的控制下关断时，此时，第一电容C1可以保持第二节点N2的电压，从而保持第一节点N1电压的稳定性。
在一些实施例中，继续参阅图12，以及结合图11所示。在复位阶段P1和发光调节阶段P4，调节子电路40，在来自第二扫描信号端Gate2传输的扫描信号的控制下，将在第一参考电压信号端Vinit3处接收的参考电压信号传输至第二节点N2；同时第二复位子电路90，在来自第二复位信号端Reset2接收的第二复位信号的控制下，将在第二初始化信号端Vinit2传输至发光器件O。
示例性的，第二复位信号端Reset2和第二扫描信号端Gate2响应于同一个控制信号的控制同步导通或者关断。例如，第二扫描信号端Gate2可以复用为第二复位信号端Reset2。
在复位阶段P1，在第二扫描信号端Gate2提供的低电平(有效电平)信号的控制下，调节子电路40和第二复位子电路90同时导通，也即同时对第二节点N2和发光器件O进行至少一次复位，使得驱动晶体管TD在写入阶段之前的初始状态固定，便于在写入阶段时使驱动晶体管TD处于稳定状态，以及提高发光器件O的稳定性，改善显示面板200的闪屏现象。
在发光调节阶段P4，在第二扫描信号端Gate2提供的低电平(有效电平)信号的控制下，调节子电路40和第二复位子电路90同时导通，也即同时对第二节点N2和发光器件O进行刷新，利用第二节点N2的电压变化量补偿第一节点N1的电压变化量，使得第一节点N1的电压可以大致处于动态平衡状态。而此时，也可以再次对发光器件O进行刷新，相对于仅在复位阶段P1对发光器件O阳极复位一次的方案，可以更好的稳定发光器件O的亮度。
图16为本公开一些实施例的又一种像素驱动电路的时序图。在一些实施例中，请参阅图16，以及结合图9所示，在第一发光阶段P3，发光控制子电路80在来自使能信号端EM1的使能信号的控制下，与驱动子电路10配合，向发光器件O传输驱动信号。
在复位阶段P1和发光调节阶段P4，第二复位子电路90在来自第二复位信号端Reset2接收的复位信号的控制下，将在第二初始化信号端Vinit2接收的初始化信号传输至发光器件O。
可以理解为，第二初始化信号端Gate2接收的初始化信号与使能信号端EM1接收的使能信号交替设置。示例性的，与使能信号端EM1反相的控制端EM2替换第二复位信号端Reset2。例如，使能信号端EM1提供低电平，控制端EM2提供高电平；或者使能信号端EM1提供高电平，控制端EM2 提供低电平。
采用上述设置方式，使得发光控制子电路80和第二复位子电路90交替打开。
在复位阶段P1，在使能信号端EM1提供高电平(无效电平)信号，控制端EM2提供低电平(有效电平)信号。此时，发光控制子电路80在使能信号端EM1的高电平控制下断开，第二复位子电路90在控制端EM2的低电平控制下导通，将在第二初始化信号端Vinit2接收的初始化信号传输至发光器件O，对发光器件O的阳极进行复位。
在第一发光阶段P3，在使能信号端EM1提供低电平(有效电平)信号，控制端EM2提供高电平(无效电平)信号。此时，第二复位子电路90在控制端EM2的高电平信号的控制下断开，发光控制子电路80在使能信号端EM1的低电平的控制下导通，与驱动子电路配合，驱动发光器件O发光。
在发光调节阶段P4，在使能信号端EM1提供高电平(无效电平)信号，控制端EM2提供低电平(有效电平)信号。此时，发光控制子电路80在使能信号端EM1的高电平控制下断开，第二复位子电路90在控制端EM2的低电平控制下导通，将在第二初始化信号端Vinit2接收的初始化信号传输至发光器件O，对发光器件O的阳极的电位进行刷新。
图17为本公开一些实施例的一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图。图17A～图17D分别为图17中的一些膜层的结构图。可以理解地，图17中像素驱动电路对应的等效电路图如前面图9所示。
请参阅图17所示。显示面板200包括衬底000和第一栅导电层G1。第一栅导电层G1位于衬底000的一侧。
请参阅图17B所示，第一栅导电层G1包括第二扫描信号线Gate2，第二扫描信号线Gate2沿第一方向X延伸。
像素驱动电路100包括第二晶体管T2和第七晶体管T7。
第二扫描信号线Gate2包括第一部分M1和第二部分M2，第一部分M1复用为第二晶体管T2的栅极，第二部分M2复用为第七晶体管T7的栅极。
上述设置方式，使得第二晶体管T2的栅极和第七晶体管T7的栅极均与第二扫描信号线Gate2电连接。第三晶体管T3的栅极连接的第二扫描信号线Gate2复用为第七晶体管T7的栅极所连接的第二复位信号端Reset2。使第二晶体管T2的栅极和第七晶体管T7的栅极可以利用一个栅极驱动电路驱动，通过第二扫描信号线Gate2将栅极驱动电路提供的电信号传输至第二晶体管 T2的栅极和第七晶体管T7的栅极，控制第二晶体管T2和第七晶体管T7的导通和关断。由此，可以减少一个栅极驱动电路的使用，便于显示面板200内的布局，有利于实现显示面板200窄边框。同时，还可以简化像素驱动电路100的制备流程，从而简化显示面板200的制备工艺流程。
示例性的，请继续参阅图17B所示，第一栅导电层G1还包括第一扫描信号线Gate1，第一扫描信号线Gate1沿第一方向X延伸。
像素驱动电路100包括第一晶体管T11和第四晶体管T4。
第一扫描信号线Gate1包括第三部分M3和第四部分M4，第三部分M3复用为第一晶体管T11的栅极，第四部分M4复用为第四晶体管T4的栅极。
示例性的，请继续参阅图17B所示，第一栅导电层G1还包括使能信号线EM1，使能信号线EM1沿第一方向X延伸。
像素驱动电路100包括第五晶体管T5和第六晶体管T6。
使能信号线EM1包括第五分部M5和第六部分M6，第五部分M5复用为第五晶体管T5的栅极，第六部分M6复用为第六晶体管T6的栅极。
示例性的，请继续参阅图17B所示，第一栅导电层G1还包括第一复位信号线Reset1，第一复位信号线Reset1沿第一方向X延伸。
像素驱动电路100包括第四晶体管T4。
第一复位信号线Reset1包括第七部分M7，第七部分M7复用为第四晶体管T4的栅极。
上述设置方式，可以简化像素驱动电路100的制备流程，从而简化显示面板200的制备工艺流程。
示例性的，上述以第一栅导电层G1，沿第二方向Y包括第一复位信号线Reset1、第一扫描信号线Gate1、使能信号线EM1和第二扫描信号线Gate2为例进行示意。第二方向Y和第一方向X相交。例如，第二方向Y和第一方向X垂直。在另一些实施例中，可以根据实际显示面板200内的需求，第一栅导电层G1还可以包括其他的走线设置。
例如，第一栅导电层G1还可以包括第二电容Cst的下极板。第一栅导电层G1还可以包括驱动晶体管TD的栅极。和/或，第二电容Cst的下极板的部分复用为驱动晶体管TD的栅极。均可以简化像素驱动电路100的制备流程，从而简化显示面板200的制备工艺流程。
示例性的，第一栅导电层G1的材料包括导电金属。该导电金属可以包括铝、铜、钼中的至少一种，本公开不限于此。
图18为本公开一些实施例的又一种显示面板中位于一个子像素区 域内的像素驱动电路的膜层结构图。图19为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图。图20为本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图。可以理解地，图18、图19和图20中像素驱动电路对应的等效电路图如前面图11所示。在一些实施例中，请参阅图18、图19和图20所示，显示面板200还包括有源层POLY、第二栅导电层G2和第一源漏导电层SD1。
有源层POLY位于衬底000和第一栅导电层G1之间。
示例性的，有源层Poly的材料可以包括非晶硅、单晶硅、多晶硅或金属氧化物半导体材料。
示例性的，有源层Poly和第一栅导电层G1之间设有第一栅绝缘层，第一栅绝缘层使有源层Poly和第一栅导电层G1电绝缘。例如，第一栅绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第一栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
需要说明的是，有源层Poly在衬底上的正投影与第一栅导电层G1在衬底上的正投影具有交叠。其中，有源层Poly中被第一栅导电层G1覆盖的部分构成各个晶体管的有源部(沟道部)，有源层Poly中未被第一栅导电层G1覆盖的部分为导电部，构成各晶体管的第一极或第二极的一部分。
第二栅导电层G2位于第一栅导电层G1远离有源层POLY的一侧。
示例性的，第二栅导电层G2可以与第一栅导电层G1材料可以相同。可以理解的是，在另一些实施例中，第二栅导电层G2可以与第一栅导电层G1材料可以不同。本公开的实施例对此不做限制。
示例性的，第二栅导电层G2可以与第一栅导电层G1之间设有第二栅绝缘层。第二栅绝缘层使第二栅导电层G2和第一栅导电层G1电绝缘。例如，第二栅绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第二栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
第一源漏导电层SD1位于第二栅导电层G2远离有源层POLY的一侧。
示例性的，第二栅导电层G2和第一源漏导电层SD1之间设置有第三栅绝缘层，第三绝缘层使第二栅导电层G2和第一源漏导电层SD1之间电绝缘。例如，第三栅绝缘层的材料包括氮化硅、氮氧化硅和氧化硅的无机绝缘材料中的任一种。第三栅绝缘层的材料可以包括二氧化硅，本公开不限于此。
示例性的，显示面板200还可以包括遮挡层LS，遮挡层LS位于衬底000和有源层POLY之间。
需要说明的是，有源层POLY的材料对光照比较敏感，当其受到不同强度光照时，其电学特性差异比较大。为避免有源层POLY中各个晶体管的有源部在使用过程中因光照而受到影响的问题。本公开在衬底000和有源层POLY之间设有遮挡层LS，遮挡层LS在衬底000上的正投影与有源层POLY在衬底000上的正投影具有交叠。可以利用遮挡层LS避免外部光线对有源部产生影响。
示例性的，示例性的，由于有源层POLY的材料在不断工作中，栅极加电会使其H2O、F离子、H原子产生扩散，导致晶体管的阈值电压(Vth)负偏，从而导致晶体管的寿命下降，也会导致显示面板200呈现显示画面的灰阶不均的问题。为避免上述问题，遮挡层LS可以在沟道部给一个恒定的电位，该电位可以用于改善阈值电压(Vth)负偏的问题，从而缓解上述老化过程。该恒定的电位可以为第一电压端VDD提供的电位，也可以为第二电压端VSS提供的电位，还可以为参考电压信号端Vinit(Vinit1、Vinit2或Vinit3)提供的电位。或者，遮挡层LS可以在沟道部给一个变电压，接入方式可以从显示面板200的显示区周边接入，也可以在显示面板200的像素区域内部打孔进行电连接。
基于上述设置方式，像素驱动电路100包括第一电容C1。
第一电容C1的第一极板和第一电容C1的第二极板，分别位于遮挡层LS、有源层POLY、第一栅导电层G1、第二栅导电层G2和第一源漏导电层SD1中至少两层。
可以理解的是，第一电容C1的第一极板可以位于上述任意一个膜层中，第一电容C1的第二极板位于除上述包括第一极板的其他膜层中。以下将对第一电容C1的结构进详细阐述。
图18A为图18中的有源层的结构图，图18B为图18中的遮挡层的结构图。示例性的，请参阅图18、图18A和图18B所示，第一电容C1的两个极板分别位于有源层POLY和遮挡层LS中。
像素驱动电路100包括第三晶体管T3和第五晶体管T5。
请继续参阅图18A所示，有源层POLY包括第三晶体管T3的有源部、第五晶体管T5的有源部、以及第一电容C1的第一极板；第一电容C1的第一极板位于第三晶体管T3的有源部和第五晶体管T5的有源部之间。
请继续参阅图18B所示，遮挡层LS包括第一部分LS1和第二部分LS2。第一部分LS1在衬底000上的正投影与驱动晶体管TD的有源部具有交叠。保证驱动晶体管TD的稳定性。在此基础上，可以将第一部分LS1外扩形成 第二部分LS2。使得第二部分LS2在衬底000上的正投影和有源层POLY在衬底000上的正投影具有交叠。此时，第二部分LS2复用为第一电容C1的第二极板。
上述设置方式，一方面，有源层POLY和遮挡层LS之间的膜层数量较少，甚至可能存在有源层POLY和遮挡层LS之间仅包括一个绝缘层的情况。将第一电容C1的两个极板分别设置在有源层POLY和遮挡层LS中，有利于增大第一电容C1的电容值。另一方面，遮挡层LS的第二部分LS2和第一部分LS1可以利用同一掩模板通过一次构图工艺形成的层结构，有利于简化显示面板200的制作工艺。
其中，图18所示显示面板200中的像素驱动电路100相对于图17所示显示面板200中的像素驱动电路100，改进了遮挡层LS和有源层POLY。对于第一栅导电层G1、第二栅导电层G2和第一源漏导电层SD1的结构可以参阅图17B～图17D所示的膜层结构。
图19A为图19中的第二栅导电层的结构图。示例性的，请参阅图19和图19A所示，第一电容C1的两个极板分别位于有源层POLY和第二栅导电层G2中。
像素驱动电路100包括第二电容Cst、第三晶体管T3和第五晶体管T5。
图19和图18所示的显示面板200内有源层POLY的结构相同。所以对于有源层POLY的结构可以继续阅图18A所示，有源层POLY包括第三晶体管T3的有源部、第五晶体管T5的有源部、以及第一电容C1的第一极板；第一电容C1的第一极板位于第三晶体管T3的有源部和第五晶体管T5的有源部之间。
请继续参阅图19A所示，第二栅导电层G2包括第二电容Cst的第一极板；第一电容C1的第二极板与第二电容Cst的第一极板同层且电连接。
上述设置方式，第一电容C1的第二极板与第二电容Cst的第一极板同层且电连接。第一电容C1的第二极板可以为第二电容Cst的第一极板外扩的一部分，第一电容C1的第二极板与第二电容Cst的第一极板可以采用同一成膜工艺形成用于形成特定图形的膜层，利用同一掩模板通过一次构图工艺形成的层结构。由此，可以利于简化显示面板200的制作工艺。
示例性的，第二栅导电层G2还可以包括第一初始化信号线Vinit1和第二初始化信号线Vinit2。
其中，图19所示显示面板200中的于第一栅导电层G1和第一源漏导电层SD1的结构可以参阅图17B和图17D所示的膜层结构。
图20A为图20中的第一栅源导电层的结构图。示例性的，请参阅图20和18A所示，第一电容C1的两个极板分别位于有源层POLY和第一源漏导电层SD1中。
像素驱动电路100包括第二晶体管T2、第三晶体管T3和第五晶体管T5。
图20和图18所示的显示面板200内有源层POLY的结构相同。所以对于有源层POLY的结构可以继续阅图18A所示，有源层POLY包括第三晶体管T3的有源部、第五晶体管T5的有源部、以及第一电容C1的第一极板；第一电容C1的第一极板位于第三晶体管T3的有源部和第五晶体管T5的有源部之间。
请继续参阅图20A所示，第一源漏导电层SD1包括第二晶体管T2的第一极、第三晶体管T3的第二极、以及第一电容C1的第二极板；第一电容C1的第二极板位于第二晶体管T2的第一极和第三晶体管T3的第二极之间。
上述设置方式，第一电容C1的第二极板位于第二晶体管T2的第一极和第三晶体管T3的第二极之间。由于第二晶体管T2的第一极和第三晶体管T3的第二极需实现电连接，也即在第二晶体管T2的第一极和第三晶体管T3的第二极之间需设置导电部。由此，可以扩增该导电部的面积，由此形成第一电容C1的第二极板。使第一电容C1的第二极板、第二晶体管T2的第一极和第三晶体管T3的第二极可以采用同一成膜工艺形成用于形成特定图形的膜层，利用同一掩模板通过一次构图工艺形成的层结构。由此，可以利于简化显示面板200的制作工艺。
图21本公开一些实施例的又一种显示面板中位于一个子像素区域内的像素驱动电路的膜层结构图，图21A～图21F分别为图21中的一些膜层的结构图。可以理解地，图21中像素驱动电路对应的等效电路图如前面图9所示。
在一些实施例中，请参阅图21，以及图9所示。像素驱动电路100包括第二晶体管T2和第七晶体管T7。
显示面板200包括：衬底000、有源层POLY、第一栅导电层Gate1、第二栅导电层Gate2、第一源漏导电层SD1、第二源漏导电层SD2、第三源漏导电层SD3。
像素驱动电路100包括第二晶体管T2和第七晶体管T7。
请继续参阅图21，以及结合图21F所示，第三源漏导电层SD3包括第二扫描信号线Gate2和第二复位信号线Reset(EM2)。第二扫描信号线Gate2和第二复位信号线Reset(EM2)沿第一方向X延伸第二方向Y排布。第二 扫描信号线Gate2位于第二复位信号线Reset(EM2)更靠近第二晶体管T2和第七晶体管T7和一侧。
请继续参阅图21，以及结合21E所示，第二源漏导电层SD2还包括第一连接部L1和第二连接部L2。第一连接部L1的一端通过过孔和第二晶体管T2的栅极连接，第一连接部L1的另一端通过过孔和第二扫描信号线Gate2连接。实现第二晶体管T2的栅极和第二扫描信号线Gate2耦接，用于将第二扫描信号线Gate2处接收的扫描信号传输至第二晶体管T2的栅极，控制其导通或关断。第二连接部L2的一端通过过孔和第七晶体管T7的栅极连接，第二连接部L2的另一端通过过孔和第二复位信号线Reset(EM2)连接。实现第七晶体管T7和第二复位信号线Reset(EM2)耦接。用于将第二复位信号线Reset(EM2)处接收的复位信号传输至第七晶体管T7的栅极，控制其导通或关断。
示例性的，像素驱动电路100包括第一晶体管T11、第三晶体管T3和第四晶体管T41。第一栅导电层G1包括第一复位信号线Reset1和第一扫描信号线Gate1，第一复位信号线Reset1沿第一方向X延伸。第一复位信号线Reset1包括第一子部H1，第一子部H1复用为第四晶体管T41的栅极。第一扫描信号线Gate1包括第二子部H2和第三子部H3，第二子部H2复用为第一晶体管T11的栅极，第三子部H3复用为第三晶体管T3的栅极。
上述设置方式，可以简化像素驱动电路100的制备流程，从而简化显示面板200的制备工艺流程。
图22为本公开一些实施例的又一种显示面板的结构图。在一些实施例中，请参阅图22所示，显示面板200包括显示区AA和至少部分围绕显示区AA的周边区BB。
上述任一实施例的像素驱动电路100和发光器件O，可以设置于显示区AA。
用于驱动像素驱动电路100的栅极驱动电路GOA，可以设置于周边区BB。示例性的，栅极驱动电路GOA可以包括第一栅极驱动电路Gate1GOA，第二栅极驱动电路Gate2GOA、第三栅极驱动电路EM1GOA。
第一栅极驱动电路Gate1GOA，用于为第一栅极信号端Gate1提供扫描信号，第一栅极信号端Gate1将该扫描信号传输至第一晶体管T11的栅极和第三晶体管T3的栅极，控制第一晶体管T11和第三晶体管T3的导通和关断。
第二栅极驱动电路Gate2GOA，用于为第二栅极信号端Gate2提供扫描 信号，第二栅极信号端Gate2将该扫描信号传输至第二晶体管T2的栅极，控制第二晶体管T2的导通和关断。或者，第二栅极信号端Gate2将该扫描信号传输至第二晶体管T2的栅极和第七晶体管T7的栅极，控制第二晶体管T2和第七晶体管T7的导通和关断。
第三栅极驱动电路EM GOA，用于为使能信号端EM1提供使能信号，使能信号端EM1将该使能信号传输至第五晶体管T5的栅极和第六晶体管T6的栅极，控制第五晶体管T5和第六晶体管T6的导通和关断。
图23为本公开一些实施例的一种移位寄存器的电路结构图，图24为图23中的移位寄存器的时序图。本公开的一些实施例提供了一种栅极驱动电路，请参阅图23和图24所示，栅极驱动电路GOA包括多个级联设置的移位寄存器Q1。
移位寄存器Q1包括晶体管T10、晶体管T11、晶体管T12、晶体管T13、晶体管T14、晶体管T15、晶体管T16、晶体管T17、电容C4和电容C5。
在充电阶段t1，在时钟信号端CK处所接收的时钟信号为低电平，进而使得晶体管T10导通，晶体管T10将上一级初始扫描信号GSTV传输至第五节点N5，上一级初始扫描信号GSTV为低电平，因此，第五节点N5为低电平。在时钟信号端CK处所接收的时钟信号的控制下，晶体管T11导通，晶体管T11将电压信号端VGL提供的电压信号传输至第六节点N6。在第五节点N5的控制下，晶体管T12导通，晶体管T12将在时钟信号端CK处所接收的时钟信号传输至第六节点N6；其中，电压信号端VGL提供的电压信号为低电平，时钟信号端在充电阶段t1为低电平，因此，第六节点N6为低电平。
在第六节点N6的控制下，晶体管T13导通，晶体管T13将电压信号端VGH提供的电压信号传输至第七节点N7，电压信号端VGH提供的电压信号为高电平，因此第七节点N7为高电平。而时钟信号端CB提供的时钟信号为高电平，时钟信号端CB提供的时钟信号的控制下，晶体管T14断开，因此，第七节点N7的高电平无法写入第五节点N5。
电压信号端VGL提供的电压信号为低电平，进而控制晶体管T15导通，第五节点N5的信号可以写入第八节点N8，因此，第八节点N8为低电平。
第六节点N6为低电平，进而控制晶体管T17导通，晶体管T17将电压信号端VGH提供的电压信号传输至初始扫描信号输出端OUT。第八节点N8为低电平，以此控制晶体管T16导通，晶体管T16将时钟信号端CB提供的时钟信号传输至初始扫描信号输出端OUT。
在输出阶段t2，时钟信号端CK处所接收的时钟信号为高电平，进而控 制晶体管T10断开，因此，上一级初始扫描信号GSTV无法传输至第五节点N5，第五节点N5保持低电平。
时钟信号端CK处所接收的时钟信号为高电平，进而控制晶体管T11断开，电压信号端VGL处接收的电压信号无法传输至第六节点N6。而第五节点N5保持低电平，进而控制晶体管T12导通，晶体管T12将时钟信号端CK处所接收的时钟信号传输至第六节点N6，时钟信号端CK处所接收的时钟信号在输出阶段为高电平，因此，第六节点N6为高电平，进而控制晶体管T17断开，使得电压信号端VGH处接收的电压信号无法传输至初始扫描信号输出端OUT。
第六节点N6为高电平，因此，晶体管T13断开，电压信号端VGH处接收的电压信号无法传输至第七节点N7。时钟信号端CB处接收的时钟信号为低电平，进而控制晶体管T14打开，晶体管T14将第五节点N5的低电平写入第七节点N7。
第五节点N5为低电平，由于晶体管T15导通，第五节点N5的低电平可以写入第八节点N8，第八节点N8为低电平，进而控制晶体管T16导通，晶体管T16将时钟信号端CB处接收的时钟信号传输至初始扫描信号输出端OUT，时钟信号端CB处接收的时钟信号在输出阶段t2为低电平，因此，初始扫描信号OUT在输出阶段t2为低电平。由于初始扫描信号输出端OUT的电平由高电平变化至低电平，在电容C4的控制下，第八节点N8的电平进一步降低，进而使得晶体管T16进一步打开。
在第一上拉阶段t310，时钟信号端CK处接收的时钟信号为低电平，进而控制晶体管T10导通，晶体管T10将上一级初始扫描信号GSTV传输至第五节点N5，上一级初始扫描信号GSTV为高电平，因此，第五节点N5为高电平。而晶体管T15导通，进而将第五节点N5的低电平写入第八节点N8，第八节点N8为高电平，以此控制晶体管T16断开。
第五节点N5为高电平，进而控制晶体管T12断开。时钟信号端CB处接收的时钟信号为高电平，进而控制晶体管T14断开。第六节点N6为低电平，进而控制晶体管T13导通，晶体管T13将电压信号端VGH处接收的电压信号传输至第七节点N7，第七节点N7为高电平。
时钟信号端CK处接收的时钟信号为低电平，进而控制晶体管T11导通，晶体管T11将电压信号端VGL处接收的电压信号传输至第六节点N6，电压信号端VGL处接收的电压信号为低电平，因此，第六节点N6为低电平，进而控制晶体管T17导通，晶体管T17将电压信号端VGL处接收的电压信号传 输至初始扫描信号输出端OUT，电压信号端VGL处接收的电压信号为高电平。
在第二上拉阶段t320，时钟信号端CK处接收的时钟信号为高电平，晶体管T10断开，上一级初始扫描信号GSTV无法传输至第五节点N5。而第六节点N6为低电平，进而控制晶体管T13导通，时钟信号端CB处接收的时钟信号为低电平，晶体管T14导通，因此，电压信号端VGH处接收的电压信号依次通过晶体管T13和晶体管T14写入第五节点N5，电压信号端VGH处接收的电压信号为高电平，因此，第五节点N5为高电平。晶体管T15导通，将第五节点N5的电平写入第八节点N8，第八节点N8为高电平，进而控制晶体管T16断开，因此，时钟信号端CB处接收的时钟信号无法写入初始扫描信号输出端OUT。
时钟信号端CK处接收的时钟信号为高电平，晶体管T11断开，电压信号端VGL处接收的电压信号无法传输至第六节点N6。第五节点N5为高电平，进而控制晶体管T12断开。第六节点N6保持低电平，因此晶体管T17导通，晶体管T17将电压信号端VGH处接收的电压信号传输至初始扫描信号输出端OUT，电压信号端VGH处接收的电压信号为高电平，因此初始扫描信号OUT在第二上拉阶段t320为高电平。
示例性的，显示面板200中的第一栅极驱动电路Gate1GOA可以采用上述栅极驱动电路Gate GOA的结构。例如，可以将初始扫描信号输出端OUT连接至第一栅极信号端Gate1，为第一栅极信号端Gat1提供扫描信号。
示例性的，显示面板200中的第二栅极驱动电路Gate2GOA时可以采用上述栅极驱动电路Gate GOA的结构。例如，可以将初始扫描信号输出端OUT连接至第二栅极信号端Gate2，为第二栅极信号端Gate2提供扫描信号。
需要说明的是，图23所示的移位寄存器的电路仅以八个晶体管、两个电容为例进行示意，在另外一些实施例中，能实现相同或相似功能的其他GOA电路也可以应用于此(如上述第一栅极驱动电路Gate1GOA或第二栅极驱动电路Gate2GOA)，本公开对此不作限制。
图25为本公开一些实施例的又一种移位寄存器的电路结构图，图26为图25中的移位寄存器的时序图。本公开的一些实施例提供了一种栅极驱动电路，请参阅图25和图26所示，栅极驱动电路GOA包括多个级联设置的移位寄存器Q2。
示例性的，第三栅极驱动电路EM GOA包括多个级联设置的移位寄存器Q2。
移位寄存器Q2包括晶体管T20、晶体管T21、晶体管T22、晶体管T23、晶体管T24、晶体管T25、晶体管T26、晶体管T27、晶体管T28、晶体管T29、晶体管T30、晶体管T31、电容C6、电容C7和电容C8。
第一阶段t1，在时钟信号端CK处接收的低电平信号的控制下，晶体管T20导通。信号输入端STV提供处于高电平状态的信号通过晶体管T20写入至第九节点N9，第九节点N9处于高电平状态，晶体管T21和晶体管T27处于截止状态；与此同时，在电压信号端VGL的提供的低电平信号的控制下，晶体管T31导通，第九节点N9的高电平信号写入至第十一节点N11，第十一节点N11处于高电平状态，晶体管T29处于截止状态。在时钟信号端CK处接收的低电平信号的控制下，晶体管T22导通，电压信号端VGL提供的低电平信号写入第十节点N10，第十节点N10处于低电平状态，晶体管T24导通。与此同时，在电压信号端VGL的提供的低电平信号的控制下，晶体管T30导通，第十节点N10的低电平信号写入至晶体管T25的栅极，晶体管T25导通。在时钟信号线CB处接收的高电平信号的控制下，晶体管T26截止，第十二节点N12处于浮接状态，第十二节点N12维持前一阶段(前一周期的最后一个阶段)的高电平状态，晶体管T28截止。由此，信号输出端OUT1处于浮接状态，信号输出端OUT1维持前一阶段(前一周期的最后一个阶段)的低电平状态，即信号输出端OUT1输出低电平信号。
第二阶段t2，在时钟信号线CB处接收的低电平信号的控制下，晶体管T23导通，且在第十节点N10低电平信号的控制下晶体管T24导通，电压信号端VGH提供的高电平信号写入第九节点N9、第十一节点N11，并对电容C6进行充电。由此由于第九节点N9处于高电平状态，晶体管T21也会立即切换至截止状态；第十一节点N11处于高电平状态，晶体管T29截止。于此同时，在时钟信号线CB处接收的低电平信号的控制下，晶体管T26导通，时钟信号线CB处接收的低电平信号通过晶体管T25写入至第十三节点N13。在电容C7的自举作用下，第十节点N10处的电压被下拉至更低水平。由于晶体管T25和晶体管T26导通，时钟信号线CB处接收的低电平信号通过晶体管T25和晶体管T26写入至第十二节点N12，晶体管T28导通。电压信号线VGH提供的高电平信号通过晶体管T28写入至信号输出端OUT1，也即信号输出端OUT1输出高电平信号。
第三阶段t3，第九节点N9处于高电平状态，晶体管T27截止；第十一节点N11处于高电平状态，晶体管T29截止。第十节点N10处于低电平状态，晶体管T25导通，时钟信号线CB处接收的高电平信号通过晶体管T25和晶 体管T26写入至第十二节点N12，晶体管T28截止。由于晶体管T28和晶体管T29均处于截止状态，因此信号输出端OUT1处于浮接状态，信号输出端OUT1维持前一阶段(前一周期的最后一个阶段)的高电平状态，即信号输出端OUT1输出高电平信号。
第四阶段t4，由于第九节点和第十一节点N11处于高电平状态，晶体管T27和晶体管T29处于截止状态。于此同时，在时钟信号线CB处接收的低电平信号的控制下，晶体管T23导通，晶体管T26导通。由于第十节点N10处于低电平状态，晶体管T25导通。时钟信号线CB处接收的低电平信号通过晶体管T25和晶体管T26写入至第十二节点N12，晶体管T28导通。因此，电压信号线VGH提供的高电平信号通过晶体管T28写入至信号输出端OUT1，也即信号输出端OUT1输出高电平信号。
第五阶段t5，在时钟信号端CK处接收的低电平信号的控制下，晶体管T20导通。信号输入端STV提供处于低电平信号通过晶体管T20写入至第九节点N9，第九节点N9处于低电平状态，晶体管T21导通；与此同时，在时钟信号端CK处接收的低电平信号的控制下，晶体管T22导通，电压信号端VGL提供的低电平信号写入第十节点N10，第十节点N10处于低电平状态，晶体管T24导通，晶体管T25导通。此时，时钟信号线CB处接收的高电平信号通过晶体管T25和晶体管T26写入至第十二节点N12，晶体管T28截止。于此同时，第十一节点N11处于低电平状态，晶体管T27和晶体管T29处于导通状态。电压信号端VHL提供的低电平信号传输至信号输出端OUT1，也即信号输出端OUT1输出低电平信号。
第六阶段t6，在时钟信号线CB处接收的低电平信号的控制下，第十一节点N11的电压在电容C6的自举作用下被下拉，第九节点N9和第十一节点N11处于低电平状态，晶体管T21导通。时钟信号端CK提供的高电平信号通过晶体管T21写入至第十节点N10，晶体管T24截止，晶体管T25截止。由于第九节点N9处于低电平状态，晶体管T27导通，电压信号端VGH提供的高电平信号写入至第十二节点N12，晶体管T28截止。第十一节点N11处于低电平状态，和晶体管T29导通。由此，电压信号端VHL提供的低电平信号传输至信号输出端OUT1，也即信号输出端OUT1输出低电平信号。
示例性的，第三栅极驱动电路EM GOA中移位寄存器Q2的信号输出单OUT1可以连接至使能信号端EM1，为使能信号端EM1提供使能信号。
需要说明的是，图25所示的移位寄存器的电路仅以十个晶体管、三个电容为例进行示意，在另外一些实施例中，能实现相同或相似功能的其他GOA 电路也可以应用于此，本公开对此不作限制。
图27为本公开一些实施例的一种移位寄存器的电路结构图。请参阅图27所示，可以在图25所示移位寄存器Q2的输出端OUT1串接输出控制子电路U，将输出端OUT1输出的信号反相后，通过输出端OUT2传输。输出控制子电路U包括晶体管T40、晶体管T41、晶体管T42、晶体管T43、晶体管T44、电容C9。其中，图27所示移位寄存器Q2的电路可以参考图26所示的时序进行驱动。
继续结合图10所示的像素驱动电路100，第二复位信号端Reset2可以为信号端EM2。信号端EM2和使能信号端EM1反相。在此基础上，可以利用图25所示的移位寄存器Q2的输出端OUT2与信号端OUT2耦接。由此，可以利用移位寄存器Q2的输出端OU1为使能信号端EM1提供信号端的同时将反相后的信号通过输出端OUT2传输至信号端EM2。无需单独另设栅极驱动电路为信号端EM2提供控制信号，由此可以便于显示面板200内部布局，以及便于实现显示面板200窄边框。
或者，也可以设置输出端OUT1与信号端EM2耦接，输出端OUT2与使能信号端耦接。
需要说明的是，本公开以图27所示的输出控制子电路U为例进行示意，在另外一些实施例中，其他可以实现反相效果的电路均可以应用于此，本公开对此不作限制。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (32)

  1. 一种像素驱动电路，包括：驱动子电路、写入子电路、补偿子电路及调节子电路；
    所述驱动子电路，与第一节点、第二节点及第三节点耦接，所述驱动子电路被配置为，在所述第一节点的电压的控制下，将来自所述第二节点的电压传输至所述第三节点；
    所述写入子电路，与所述第二节点、第一扫描信号端及数据信号端耦接，所述写入子电路被配置为，在写入阶段，在来自所述第一扫描信号端接收的栅扫描信号的控制下，将在所述数据信号端处接收的数据信号传输至所述第二节点；
    所述补偿子电路，与所述第一节点、第三节点及补偿控制端耦接，所述补偿子电路被配置为，在写入阶段，在来自所述补偿控制端接收的补偿信号的控制下，将所述第三节点的电压传输至所述第一节点；
    所述调节子电路，与所述第二节点和/或所述第三节点耦接、且与第二扫描信号端及第一参考电压信号端耦接，所述调节子电路被配置为，在发光调节阶段，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点和/或所述第三节点。
  2. 根据权利要求1所述的像素驱动电路，其中，
    所述调节子电路还被配置为，在复位阶段，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点复位。
  3. 根据权利要求1或2所述的像素驱动电路，其中，
    所述调节子电路包括第二晶体管；
    所述第二晶体管的栅极和所述第二扫描信号端耦接，所述第二晶体管的第一极和所述第二节点耦接，所述第二晶体管的第二极和所述第一参考电压信号端耦接。
  4. 根据权利要求1～3中任一项所述的像素驱动电路，其中，
    所述驱动子电路包括驱动晶体管；
    所述驱动晶体管的栅极与所述第一节点耦接，所述驱动晶体管的第一极与所述第二节点耦接，所述驱动晶体管的第二极与所述第三节点耦接。
  5. 根据权利要求1～4中任一项所述的像素驱动电路，其中，
    所述写入子电路包括第三晶体管；
    所述第三晶体管的栅极与所述第一扫描信号端耦接，所述第三晶体管的第一极与所述数据信号端耦接，所述第三晶体管的第二极与所述第二节点耦接。
  6. 根据权利要求5所述的像素驱动电路，其中，
    所述第一扫描信号端被配置为，在控制所述第三晶体管的第一极接收所述数据信号端的数据信号之前，控制所述第三晶体管开启至少1次。
  7. 根据权利要求1～6所述的像素驱动电路，还包括：第一存储子电；所述第一存储子电路，与所述第一电压端和所述第二节点耦接；
    所述第一存储子电路包括第一电容，所述第一电容的第一极板与所述第一电压端耦接，所述第一电容的第二极板与第二节点耦接。
  8. 根据权利要求7所述的像素驱动电路，还包括：第二储能子电路；
    所述第二储能子电路包括第二电容；
    所述第二电容的第一极板与所述第一电压端耦接，所述第二电容的第二极板与所述第一节点耦接；
    其中，
    Figure PCTCN2022103187-appb-100001
    C1为所述第一电容的电容值，Cst为所述第二电容的电容值。
  9. 根据权利要求1～8中任一项所述的像素驱动电路，还包括：第一复位子电路；
    所述第一复位子电路，与所述第一节点、第一复位信号端、及第一初始化信号端耦接；所述第一复位子电路被配置为，在复位阶段，在来自所述第一复位信号端接收的复位信号的控制下，将在所述第一初始化信号端接收的初始化信号传输至所述第一节点，对所述第一节点复位。
  10. 根据权利要求9所述的像素驱动电路，其中，
    所述第一复位子电路包括第四晶体管组，所述第四晶体管组包括串联的至少两个第四晶体管；
    所述第四晶体管组中的所有第四晶体管的栅极均与所述第一复位信号端耦接，所述第四晶体管组中的第一个第四晶体管的第一极与所述第一节点耦接，所述第四晶体管组中的最后一个第四晶体管的第二极与所述第一初始化信号端耦接；
    所述第一复位信号端被配置为，在控制所述至少一个第四晶体管的第二极接收所述第一初始化信号端的第一初始化信号之前，控制至少一个第四晶体管开启至少1次。
  11. 根据权利要求1～10中任一项所述的像素驱动电路，还包括：发光控制子电路；
    所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接；所述发光控制子电路被配置为，在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号。
  12. 根据权利要求11所述的像素驱动电路，其中，
    所述发光控制子电路包括第五晶体管和第六晶体管；
    所述第五晶体管的栅极与使所述能信号端耦接，所述第五晶体管的第一极与所述第一电压信号端耦接，所述第五晶体管的第二极与所述第二节点耦接；
    所述第六晶体管的栅极与使所述能信号端耦接，所述第六晶体管的第一极与所述第三节点耦接，所述第六晶体管的第二极与所述发光器件耦接。
  13. 根据权利要求12所述的像素驱动电路，还包括：第二复位子电路；
    所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及发光器件耦接；所述第二复位子电路被配置为，在来自所述第二复位信号端接收的复位信号的控制下，将在所述第二初始化信号端接收的初始化信号传输至所述发光器件。
  14. 根据权利要求13所述的像素驱动电路，其中，
    所述第二复位子电路包括第七晶体管；
    所述第七晶体管的栅极与第二复位信号端耦接，所述第七晶体管的第一极与所述光学器件耦接，所述第七晶体管的第二极与所述第二初始化信号端耦接。
  15. 根据权利要求13或14所述的像素驱动电路，其中，
    所述第二复位信号端和所述第二扫描信号端响应于同一个控制信号的控制。
  16. 根据权利要求13或14所述的像素驱动电路，其中，
    所述第二初始化信号端接收的初始化信号与所述使能信号端接收的使能信号反相。
  17. 根据权利要求1～16中任一项所述的像素驱动电路，其中，
    所述第一参考电压信号端处接收的参考电压信号的取值范围为-5V～5V。
  18. 根据权利要求17所述的像素驱动电路，其中，
    所述第一参考电压信号端处接收的参考电压信号大约为2V。
  19. 一种像素驱动电路的驱动方法，其中，所述像素驱动电路包括：驱动子电路、写入子电路、补偿子电路、发光控制子电路及调节子电路；
    所述驱动子电路，与第一节点、第二节点及第三节点耦接；
    所述写入子电路，与所述第二节点、第一扫描信号端及数据信号端耦接；
    所述补偿子电路，与所述第一节点、第三节点及补偿控制端耦接；
    所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接；
    所述调节子电路，与所述第二节点和/或所述第三节点耦接、且与第二扫描信号端及第一参考电压信号端耦接；
    所述驱动方法包括：多个发光周期，一个发光周期包括复位阶段、写入阶段、第一发光阶段、发光调节阶段和第二发光阶段；
    在所述写入阶段，所述写入子电路，在来自所述第一扫描信号端接收的栅扫描信号的控制下，将在所述数据信号端处接收的数据信号传输至所述第二节点；所述驱动子电路将来自所述第二节点的数据信号传输至第三节点；所述补偿子电路将所述第三节点的电压传输至所述第一节点；
    在所述第一发光阶段，在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号，所述第一电压端提供的电压信号传输至所述发光器件，以驱动所述发光器件发光；
    在所述发光调节阶段，所述调节子电路，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点和/或所述第三节点；
    在所述第二发光阶段，发光控制子电路，在来自所述使能信号端的信号的控制下，以及在所述第一节点的控制下，所述发光控制子电路与所述驱动子电路配合，将所述第一电压端提供的电压信号传输至所述发光器件，以驱动所述发光器件发光。
  20. 根据权利要求19所述的驱动方法，其中，
    在所述复位阶段，所述调节子电路将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点进行至少一次复位。
  21. 根据权利要求20所述的驱动方法，其中，对所述第二节点进行多次复位。
  22. 根据权利要求20或21所述的驱动方法，其中，对所述第二节点进行2～4次复位。
  23. 根据权利要求19～22中任一项所述的驱动方法，所述像素驱动电路 还包括：第一复位子电路；
    所述第一复位子电路，与所述第一节点、第一复位信号端、及第一初始化信号端耦接；
    在所述复位阶段，所述调节子电路对所述第二节点进行复位后，所述第一复位子电路，在来自所述第一复位信号端接收的第一复位信号的控制下，将在所述第一初始化信号端接收的初始化信号传输至所述第一节点。
  24. 根据权利要求19～23中任一项所述的驱动方法，其中，
    在所述写入阶段，将在所述数据信号端处接收的数据信号传输至所述第一节点后，所述调节子电路，在来自所述第二扫描信号端传输的扫描信号的控制下，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点，对所述第二节点进行复位。
  25. 根据权利要求19～24中任一项所述的驱动方法，所述像素驱动电路还包括：第一存储子电路；
    所述第一存储子电路，与所述第一电压端和所述第二节点耦接；
    在所述写入阶段，对所述第一存储电路充电；
    在所述第一发光阶段，所述第一存储电路放电至所述第二节点，补偿所述第二节点的电压。
  26. 根据权利要求19～25所述的驱动方法，所述像素驱动电路还包括：第二复位子电路；
    所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及所述发光器件耦接；所述第二复位信号端和所述第二扫描信号端响应于同一个控制信号的控制；
    在所述复位阶段和所述发光调节阶段，所述调节子电路，将在所述第一参考电压信号端处接收的参考电压信号传输至所述第二节点；同时所述第二复位子电路，在来自所述第二复位信号端接收的第二复位信号的控制下，将在所述第二初始化信号端传输至所述发光器件。
  27. 根据权利要求18～24所述的驱动方法，所述像素驱动电路还包括发光控制子电路和第二复位子电路；
    所述发光控制子电路，与第一电压端、使能信号端、所述第二节点、所述第三节点以及发光器件耦接；
    所述第二复位子电路，与第二复位信号端、第二初始化信号端、以及所述发光器件耦接；所述第二初始化信号端接收的初始化信号与所述使能信号端接收的使能信号反相；
    在所述第一发光阶段，所述发光控制子电路在来自所述使能信号端的使能信号的控制下，与所述驱动子电路配合，向所述发光器件传输驱动信号；
    在所述复位阶段和所述发光调节阶段，所述第二复位子电路在来自所述第二复位信号端接收的复位信号的控制下，将在所述第二初始化信号端接收的初始化信号传输至所述发光器件。
  28. 一种显示面板，包括：
    多个如上述权利要求1～18中任一项所述的像素驱动电路，以及，
    与所述像素驱动电路电连接的发光器件。
  29. 根据权利要求28所述的显示面板，包括：衬底和位于衬底一侧的第一栅导电层；
    所述第一栅导电层包括第二扫描信号线，所述第二扫描信号线沿第一方向延伸；
    所述像素驱动电路包括第二晶体管和所述第七晶体管；
    所述第二扫描信号线包括第一部分和第二部分；
    所述第一部分复用为所述第二晶体管的栅极，所述第二部分复用为第七晶体管的栅极。
  30. 根据权利要求29所述的显示面板，还包括：
    遮挡层，位于所述衬底靠近所述第一栅导电层的一侧；
    有源层，位于所述遮挡层和所述第一栅导电层之间；
    第二栅导电层，位于所述第一栅导电层远离所述有源层的一侧；
    第一源漏导电层，位于所述第二栅导电层远离所述有源层的一侧；
    所述像素驱动电路包括第一电容：
    所述第一电容的第一极板和所述第一电容的第二极板，分别位于所述遮挡层、有源层、所述第一栅导电层、所述第二栅导电层和所述第一源漏导电层中至少两层。
  31. 根据权利要求30所述的显示面板，其中，
    所述像素驱动电路包括第二电容、第三晶体管和第五晶体管；
    所述有源层包括所述第三晶体管的有源部、所述第五晶体管的有源部、以及所述第一电容的第一极板；所述第一电容的第一极板位于所述第三晶体管的有源部和所述第五晶体管的有源部之间；
    所述第二栅导电层包括第二电容的第一极板；所述第一电容的第二极板与所述第二电容的第一极板同层且电连接。
  32. 根据权利要求30所述的显示面板，其中，
    所述像素驱动电路包括第二晶体管、第三晶体管和第五晶体管；
    所述有源层包括所述第三晶体管的有源部、所述第五晶体管的有源部、以及所述第一电容的第一极板；所述第一电容的第一极板位于所述第三晶体管的有源部和所述第五晶体管的有源部之间；
    所述第一源漏导电层包括所述第二晶体管的第一极、所述第三晶体管的第二极、以及所述第一电容的第二极板；所述第一电容的第二极板位于所述第二晶体管的第一极和所述第三晶体管的第二极之间。
PCT/CN2022/103187 2022-06-30 2022-06-30 像素驱动电路及其驱动方法、显示面板 WO2024000547A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2022/103187 WO2024000547A1 (zh) 2022-06-30 2022-06-30 像素驱动电路及其驱动方法、显示面板
CN202280002087.9A CN117678010A (zh) 2022-06-30 2022-06-30 像素驱动电路及其驱动方法、显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2022/103187 WO2024000547A1 (zh) 2022-06-30 2022-06-30 像素驱动电路及其驱动方法、显示面板

Publications (1)

Publication Number Publication Date
WO2024000547A1 true WO2024000547A1 (zh) 2024-01-04

Family

ID=89383878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/103187 WO2024000547A1 (zh) 2022-06-30 2022-06-30 像素驱动电路及其驱动方法、显示面板

Country Status (2)

Country Link
CN (1) CN117678010A (zh)
WO (1) WO2024000547A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110648631A (zh) * 2019-09-30 2020-01-03 昆山国显光电有限公司 像素电路、方法、显示面板及装置
CN111489701A (zh) * 2020-05-29 2020-08-04 上海天马有机发光显示技术有限公司 阵列基板及其驱动方法、显示面板和显示装置
CN112102785A (zh) * 2020-10-15 2020-12-18 厦门天马微电子有限公司 像素电路、显示面板及其驱动方法和显示装置
CN112397026A (zh) * 2020-12-04 2021-02-23 上海天马有机发光显示技术有限公司 像素驱动电路、显示面板及其驱动方法
CN113593478A (zh) * 2021-08-12 2021-11-02 武汉华星光电半导体显示技术有限公司 显示面板
CN114078430A (zh) * 2021-12-09 2022-02-22 武汉华星光电半导体显示技术有限公司 像素电路及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110648631A (zh) * 2019-09-30 2020-01-03 昆山国显光电有限公司 像素电路、方法、显示面板及装置
CN111489701A (zh) * 2020-05-29 2020-08-04 上海天马有机发光显示技术有限公司 阵列基板及其驱动方法、显示面板和显示装置
CN112102785A (zh) * 2020-10-15 2020-12-18 厦门天马微电子有限公司 像素电路、显示面板及其驱动方法和显示装置
CN112397026A (zh) * 2020-12-04 2021-02-23 上海天马有机发光显示技术有限公司 像素驱动电路、显示面板及其驱动方法
CN113593478A (zh) * 2021-08-12 2021-11-02 武汉华星光电半导体显示技术有限公司 显示面板
CN114078430A (zh) * 2021-12-09 2022-02-22 武汉华星光电半导体显示技术有限公司 像素电路及显示面板

Also Published As

Publication number Publication date
CN117678010A (zh) 2024-03-08

Similar Documents

Publication Publication Date Title
US11361713B1 (en) Display panel and display device
US20240112635A1 (en) Pixel circuit and driving method thereof, display panel and display apparatus
US10157571B2 (en) Display panel, method for driving the same and display device
US11817047B2 (en) Display panel and display device
US10255860B2 (en) Organic light emitting diode display
US8917224B2 (en) Pixel unit circuit and OLED display apparatus
WO2018095031A1 (zh) 像素电路及其驱动方法、以及显示面板
US9412302B2 (en) Pixel driving circuit, driving method, array substrate and display apparatus
EP3852095B1 (en) Pixel circuit and driving method therefor, and display device
US11029774B2 (en) Touch panel in which cathodes serve as touch sense electrodes and a touch screen formed using the touch panel
US10311783B2 (en) Pixel circuit, method for driving the same, display panel and display device
JP2023522803A (ja) シフトレジスタ回路及びその駆動方法、ゲート駆動回路、表示装置
WO2019109673A1 (zh) 像素电路及其驱动方法、显示面板和显示设备
US11355060B2 (en) Pixel circuit, method of driving pixel circuit, display panel and display device
US20220114972A1 (en) Pixel driving circuit and display panel
WO2023016138A1 (zh) 像素驱动电路及显示面板
US20050190126A1 (en) Current source circuit, display device using the same and driving method thereof
WO2021142871A1 (zh) 像素补偿电路及显示面板
WO2019047701A1 (zh) 像素电路及其驱动方法、显示装置
EP4336486A1 (en) Pixel driving circuit and display panel
CN112908259A (zh) Goa电路及显示面板
JP7090412B2 (ja) 画素回路、表示装置、画素回路の駆動方法および電子機器
CN114627817A (zh) 像素电路、像素驱动方法及显示装置
CN111402788A (zh) 一种像素电路和显示面板
CN108987453B (zh) 像素结构、驱动方法、像素电路和显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202280002087.9

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22948649

Country of ref document: EP

Kind code of ref document: A1