WO2023274357A1 - 一种微型发光元件及其制备方法 - Google Patents

一种微型发光元件及其制备方法 Download PDF

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WO2023274357A1
WO2023274357A1 PCT/CN2022/102752 CN2022102752W WO2023274357A1 WO 2023274357 A1 WO2023274357 A1 WO 2023274357A1 CN 2022102752 W CN2022102752 W CN 2022102752W WO 2023274357 A1 WO2023274357 A1 WO 2023274357A1
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dbr
layer
emitting element
electrode
etching
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PCT/CN2022/102752
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English (en)
French (fr)
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刘伟
刘伟文
彭绍文
林锋杰
周弘毅
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厦门乾照光电股份有限公司
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Publication of WO2023274357A1 publication Critical patent/WO2023274357A1/zh
Priority to US18/395,445 priority Critical patent/US20240128403A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body

Definitions

  • the invention relates to the field of light emitting diodes, in particular to a micro light emitting element and a preparation method thereof.
  • the ITO + electrode extension bar + DBR flip-chip structure is used, as shown in Figure 1 and Figure 2, so that the light emitted by the active layer needs to be reflected by a Bragg reflector (DBR) to improve the light output rate; among them, DBR High-temperature evaporation is used as the light reflection layer, and the DBR reflection layer is a TI3O5/SiO2 laminated optical design structure.
  • DBR Bragg reflector
  • the DBR reflection layer is a TI3O5/SiO2 laminated optical design structure.
  • the DBR reflective layer due to the low uniformity of the film thickness of the DBR reflective layer prepared by the conventional process on the flip-chip non-planar surface, especially the poor step coverage, the DBR reflective layer has limited reflection of light and affects the coating of subsequent electrodes. It will cause the metal of the electrode to break and affect the reliability of the LED chip.
  • the inventor specially designed a micro light-emitting element and its preparation method, and this case arose from it.
  • the purpose of the present invention is to provide a micro-light-emitting element and its preparation method to ensure the luminous efficiency of the micro-light-emitting element while solving the problem of limited light reflection and affecting subsequent electrode coating caused by the poor step coating of the DBR reflective layer. question.
  • a micro light-emitting element including a substrate and several LED array units arranged on the surface of the substrate and isolated from each other by grooves, the LED array units include:
  • An epitaxial stack the epitaxial stack includes a first-type semiconductor layer, an active region, and a second-type semiconductor layer stacked in sequence along a first direction, and a local area of the epitaxial stack is etched to part of the first A type semiconductor layer forms grooves and mesas; the first direction is perpendicular to the substrate, and is directed from the substrate to the epitaxial stack;
  • a DBR structure layer which includes a DBR adhesion layer, a DBR reflective layer, and a DBR sacrificial layer sequentially stacked along the surface of the epitaxial stack, and the DBR structure layer has parts exposing the electrode extension strips and the grooves respectively through holes on the surface;
  • a first electrode which is stacked on the through hole exposing the groove and electrically connected to the first type semiconductor layer
  • the second electrode is stacked on the through hole exposing the electrode extension strip and is electrically connected to the second type semiconductor layer.
  • the densities of the DBR sacrificial layer, the DBR reflective layer and the DBR adhesion layer increase sequentially, so that the etching rate decreases sequentially during etching, so that an inverted trapezoidal via hole with inclined sidewalls is formed through an etching process.
  • the inclined sidewall forms an included angle with the horizontal surface of the epitaxial stack, and the included angle ranges from 5° to 50°, inclusive.
  • the thickness ratio of the DBR reflective layer to the DBR sacrificial layer is 1:1 ⁇ 1:5; and the smaller the included angle, the greater the thickness of the DBR sacrificial layer.
  • a transparent conductive layer is provided on the mesa, and electrode extension strips are stacked on a surface of the transparent conductive layer facing away from the epitaxial stack.
  • the DBR adhesion layer is obtained by atomic layer deposition, and it includes at least one of Ti3O5, SiO2 and Al2O3.
  • the DBR sacrificial layer includes a spin-on-glass layer or an insulating film obtained by low-temperature deposition.
  • the DBR reflective layer includes a plurality of film layers with alternating high and low refractive indices, and the thickness of each film layer is a quarter of the wavelength of the light emitted by the micro-light-emitting element.
  • the electrode extension strips include at least one of Cr, Ni, Al, Ti, Pt, and Au.
  • the present invention also provides a preparation method of a miniature light-emitting element, the preparation method comprising the following steps:
  • a DBR structure layer on the surface of the epitaxial stack, which includes a DBR adhesion layer, a DBR reflective layer and a DBR sacrificial layer stacked in sequence;
  • the film densities of the DBR sacrificial layer, the DBR reflective layer and the DBR adhesion layer increase sequentially, so that the etching rate decreases sequentially during etching, thereby forming an inverted trapezoid with inclined sidewalls through the etching process described in step S08 through hole.
  • the formation of the sloped sidewall described in step S08 includes: firstly, using photoresist as a mask layer, exposing the required opening area through a photolithography and development process; secondly, etching the area corresponding to the opening area with an etching solution
  • the DBR sacrificial layer is used to form a lateral corrosion interface; then, the protrusion of the DBR structure layer formed by the existence of the electrode extension strips is completely etched by multi-stage ICP etching, thereby forming a DBR structure layer with a smooth cross section.
  • the ratio of CH x F y to O 2 changes in a gradient.
  • the ratio of CH x F y to O 2 transitions from an increasing gradient to a decreasing gradient.
  • the ratio of CH x F y to O 2 gradually decreases from 1:6 to 1:4 to 1:2, and then gradually increases from 1:2 to 1:4 to 1:6.
  • the micro light-emitting element provided by the present invention is provided with a DBR structure layer, which includes a DBR adhesion layer, a DBR reflective layer and a DBR sacrificial layer sequentially stacked along the surface of the epitaxial stack, and through the DBR adhesion layer Improve the structural coverage of the subsequent DBR reflective layer.
  • the inclined sidewall of the through hole forms an included angle with the horizontal surface of the epitaxial stack, and the value of the included angle ranges from 5° to 50°, so that the through hole for depositing the first electrode is relatively gentle, which can further completely eliminate The height difference between the DBR reflection layer above the electrode extension strip and the DBR reflection layer above the ITO caused by the presence of the electrode extension strip.
  • the thickness ratio of the DBR reflective layer to the DBR sacrificial layer is: 1:1 to 1:5; and the smaller the included angle, the greater the thickness of the DBR sacrificial layer; while protecting the DBR reflective layer, it can effectively eliminate the electrode expansion.
  • the DBR adhesion layer is obtained by atomic layer deposition, and it includes at least one of Ti 3 O 5 , SiO 2 and Al 2 O 3 , so that a film layer with high density and high adhesion can be obtained.
  • the present invention also provides a preparation method of the miniature light-emitting element. While realizing the above-mentioned beneficial effects of the micro-light-emitting element, the manufacturing process is simple and convenient, and it is convenient for production.
  • the formation of the oblique sidewall of the through hole includes: firstly, using photoresist as a mask layer, exposing the required opening area through a photolithography development process; secondly, etching the DBR sacrificial area corresponding to the opening area with an etching solution layer to form a lateral corrosion interface; then, the protrusion of the DBR structure layer formed by the existence of the electrode extension strips is completely etched by multi-stage ICP etching, thereby forming a DBR structure layer with a smooth cross section.
  • the etching angle of the DBR structure layer is formed into a gradual gentle slope by using multi-stage ICP etching to improve the metal coverage of the electrode.
  • FIG. 1 is a structural schematic diagram of a small and medium-sized LED chip in the prior art
  • Fig. 2 is a product effect diagram corresponding to the through hole for depositing electrodes shown in Fig. 1;
  • Fig. 3 is a schematic structural diagram of a micro light-emitting element provided by an embodiment of the present invention.
  • Figure 4.1 to Figure 4.9 are structural schematic diagrams corresponding to the steps of the preparation method of the micro light-emitting element provided by the embodiment of the present invention.
  • a micro light-emitting element includes a substrate 1 and several LED array units arranged on the surface of the substrate 1 and isolated from each other by grooves.
  • the LED array unit includes:
  • An epitaxial stack includes a first-type semiconductor layer 2, an active region 3, and a second-type semiconductor layer 4 sequentially stacked along a first direction, and a local area of the epitaxial stack is etched to part of the
  • the first type semiconductor layer 2 forms grooves 5.1 and mesas 5.2; the first direction is perpendicular to the substrate 1, and is directed from the substrate 1 to the epitaxial stack;
  • the DBR structure layer includes a DBR adhesive layer 8.1, a DBR reflective layer 8.2 and a DBR sacrificial layer 8.3 sequentially stacked along the surface of the epitaxial stack, and the DBR structure layer has exposed electrode extension strips 7 and the A through-hole in part of the surface of the groove 5.1;
  • the first electrode 9 is stacked on the through hole exposing the groove 5.1 and electrically connected to the first type semiconductor layer 2;
  • the second electrode 10 is stacked on the exposed through-hole of the electrode extension strip 7 and is electrically connected to the second-type semiconductor layer 4 .
  • the type of the substrate 1 is not limited in the micro light-emitting element of this embodiment, for example, the substrate 1 may be but not limited to a sapphire substrate 1, a silicon substrate 1, and the like.
  • the types of the first-type semiconductor layer 2, active region 3, and second-type semiconductor layer 4 of the epitaxial stack are not limited in the micro light-emitting element of this embodiment, for example, the first-type semiconductor Layer 2 may be but not limited to a gallium nitride layer, and correspondingly, the second-type semiconductor layer 4 may be but not limited to a gallium nitride layer.
  • the electrode extension strip 7 located on the mesa is directly electrically connected to the second type semiconductor layer 4 through a through hole, which can The electrode extension strip 7 is directly electrically connected to the second-type semiconductor layer 2, which is beneficial in actual work.
  • the current of the second electrode directly flows into the epitaxial stack; in the present application
  • the electrode extension strips can also be laminated on the surface of the transparent conductive layer, depending on the specific circumstances, which is not limited in this application.
  • the film density of the DBR sacrificial layer 8.3, DBR reflective layer 8.2 and DBR adhesion layer 8.1 increases sequentially, so that the etching rate decreases sequentially during etching, thereby passing The etching process forms inverted trapezoidal via holes with sloped sidewalls.
  • the inclined sidewall forms an included angle with the horizontal surface of the epitaxial stack, and the value of the included angle ⁇ ranges from 5° to 50°, including endpoint value.
  • the thickness ratio of the DBR reflective layer 8.2 to the DBR sacrificial layer 8.3 is: 1:1 to 1:5; and the smaller the included angle, the thicker the DBR sacrificial layer It should be noted that the embodiment of the present application does not limit the specific thickness values of the DBR reflective layer 8.2 and the DBR sacrificial layer 8.3, as long as the aforementioned requirements are met, depending on the specific circumstances.
  • a transparent conductive layer 6 is provided on the mesa 5.2, and electrode extension strips 7 are stacked on the side of the transparent conductive layer 6 away from the epitaxial stack surface.
  • the electrode extension strip 7 may include the electrode extension strip 7 forming the mesa 5.2 and/or the electrode extension strip 7 forming the groove 5.1, respectively to serve as the second electrode 10 on the mesa.
  • the material of the transparent conductive layer 6 may be ITO, depending on the specific circumstances, and this application does not limit it.
  • the DBR adhesion layer 8.1 is obtained by atomic layer deposition, and includes at least one of Ti 3 O 5 , SiO 2 and Al 2 O 3 .
  • the DBR sacrificial layer 8.3 includes a spin-on-glass layer or an insulating film obtained by low-temperature deposition.
  • the DBR reflective layer 8.2 includes a plurality of film layers with alternating high and low refractive indices, and the thickness of each film layer is equal to the thickness of the light emitted by the micro-light-emitting element. a quarter of the wavelength.
  • the electrode extension strip 7 includes at least one of Cr, Ni, Al, Ti, Pt, and Au.
  • the embodiment of the present application also provides a method for preparing a micro light-emitting element, the preparation method comprising the following steps:
  • the type of the substrate 1 is not limited in the micro light-emitting element of this embodiment, for example, the substrate 1 may be but not limited to a sapphire substrate 1, a silicon substrate 1, and the like.
  • the epitaxial stack includes a first-type semiconductor layer 2, an active layer, and a second-type semiconductor layer 4 stacked sequentially on the surface of the substrate 1;
  • the type of the first-type semiconductor layer 2, the active region 3 and the second-type semiconductor layer 4 of the epitaxial stack may not be limited in the micro light-emitting element of this embodiment, for example, the first The first-type semiconductor layer 2 may be but not limited to a gallium nitride layer, and correspondingly, the second-type semiconductor layer 4 may be but not limited to a gallium nitride layer.
  • FIG. 4.3 by etching the epitaxial stack, part of the first-type semiconductor layer 2 is exposed, thereby forming several grooves 5.1 and mesas 5.2, and the grooves 5.1 are arranged opposite to the mesas 5.2;
  • Figure 4.3 only shows the epitaxial stack structure corresponding to a single LED array unit;
  • etching the epitaxial stack to form several grooves 5.1 and mesas 5.2 includes: using an inductively coupled plasma (ICP) process, and the etching gas includes: Cl 2 , Ar and O 2 .
  • ICP inductively coupled plasma
  • the etching gas includes: Cl 2 , Ar and O 2 .
  • this application does not limit it, and it depends on the specific circumstances.
  • deep etching is performed on the epitaxial stack to expose the surface of the substrate 1 to form several spaced apart epitaxial stacks; including: using an inductively coupled plasma (ICP) process , the etching gas includes: Cl 2 , Ar and O 2 .
  • ICP inductively coupled plasma
  • the etching gas includes: Cl 2 , Ar and O 2 .
  • this application does not limit it, and it depends on the specific circumstances.
  • the material of the transparent conductive layer 6 may be ITO, and its formation process may be an electron beam evaporation process, a sputtering evaporation process, etc., depending on the specific circumstances. Not limited.
  • the electrode extension bar 7 may include the electrode extension bar 7 forming the mesa 5.2 and/or the electrode extension bar 7 formed in the groove 5.1, respectively as the second electrode 10
  • the extended extension of the mesa 5.2, and the extended extension of the first electrode 9 in the groove 5.1 is that the number of electrode extension strips 7 can be one or more; the formation process can be an electron beam evaporation process, It depends on the specific situation, which is not limited in this application.
  • the electrode extension strip 7 on the mesa is directly electrically connected to the second-type semiconductor layer 4 through a through hole, so that the electrode extension strip 7 is directly connected to the second-type semiconductor layer 4.
  • the electrical connection of the type II semiconductor layer 4 is beneficial to the actual work.
  • the current of the second electrode directly flows into the epitaxial stack; in other embodiments of the present application, the electrode extension strip can also be Laminated on the surface of the transparent conductive layer, depending on the specific circumstances, the present application does not limit this.
  • the electrode extension strip 7 includes one or more combinations of Cr, Ni, Al, Ti, Pt, and Au.
  • S07 as shown in Figure 4.7, form a DBR structure layer on the surface of the epitaxial stack, which includes a DBR adhesion layer 8.1, a DBR reflection layer 8.2 and a DBR sacrificial layer 8.3 stacked in sequence;
  • the DBR adhesion layer 8.1 is obtained by atomic layer deposition, and it includes at least one of Ti 3 O 5 , SiO 2 and Al2O3, depending on the circumstances, the present application Not limited.
  • the DBR reflective layer 8.2 includes a plurality of film layers with alternating high and low refractive indices, and the thickness of each film layer is a quarter of the wavelength of the light emitted by the micro light-emitting element. .
  • the DBR sacrificial layer 8.3 includes a spin-on-glass layer or an insulating film obtained by low-temperature deposition.
  • the etching rates of the DBR sacrificial layer 8.3, the DBR reflective layer 8.2 and the DBR adhesion layer 8.1 are sequentially reduced.
  • the DBR structure layer has through holes that respectively expose part of the surface of the electrode extension bar 7 and the groove 5.1 through an etching process
  • the etching rate decreases sequentially during etching, so that the etching rate described in step S08
  • the etch process forms inverted trapezoidal vias with sloped sidewalls.
  • the formation of the sloped sidewall described in step S08 includes: first, using photoresist as a mask layer, and exposing the desired opening area through a photolithographic development process Secondly, the DBR sacrificial layer 8.3 corresponding to the opening area is etched by an etching solution to form a lateral etching interface; then, multi-stage ICP etching is used to make the DBR structure layer formed due to the existence of the electrode extension strip 7 protrude is fully etched, thereby forming a DBR structure layer with a smooth cross-section.
  • the inclined sidewall forms an included angle with the horizontal surface of the epitaxial stack, and the value of the included angle ⁇ ranges from 5° to 50°, including endpoint value.
  • the thickness ratio of the DBR reflective layer 8.2 to the DBR sacrificial layer 8.3 is: 1:1 to 1:5; and the smaller the included angle, the thicker the DBR sacrificial layer It should be noted that the embodiment of the present application does not limit the specific thickness values of the DBR reflective layer 8.2 and the DBR sacrificial layer 8.3, as long as the aforementioned requirements are met, depending on the specific circumstances.
  • the ratio of CH x F y to O 2 changes in a gradient.
  • the ratio of CH x F y to O 2 changes from increasing gradient to decreasing gradient.
  • the ratio of CH x F y to O 2 is gradually reduced from 1:6 to 1:4 to 1:2, and then from 1:2 to 1 :4 to 1:6 gradually increases.
  • CHF 3 gas is used as the etching process gas
  • O 2 is used as the auxiliary gas.
  • S09 as shown in Figure 4.9, form a first electrode 9 electrically connected to the first-type semiconductor layer 2 in the through hole exposing the groove 5.1; in the exposing the electrode extension strip 7
  • the through hole forms the second electrode 10 electrically connected to the second-type semiconductor layer 4 .
  • the first electrode 9 and/or the second electrode 10 includes one or more combinations of Cr, Ni, Al, Ti, Pt, Au and other metals.
  • the micro light-emitting element provided in the embodiment of the present application is provided with a DBR structure layer, which includes a DBR adhesive layer 8.1, a DBR reflective layer 8.2 and a DBR sacrificial layer 8.3 sequentially stacked along the surface of the epitaxial stack. , improve the structural coverage of the subsequent DBR reflective layer 8.2 through the DBR adhesive layer 8.1.
  • transparent conductive layer 6 forms a smooth mesa 5.2, thereby making the first electrode 9 and/or the second electrode 10 Basically at the same height to improve the reliability of its push-pull force and avoid the risk of electrode drop; and through the inclined side wall of the through hole, it is beneficial to the subsequent coating of the first electrode 9 and increases the first electrode 9 and the DBR structure layer
  • the contact area is small, so that good adhesion can be formed between the DBR structure layer and the electrode; thereby ensuring the reliability of the light-emitting element.
  • the inclined sidewall of the through hole forms an included angle with the horizontal surface of the epitaxial stack, and the value of the included angle ranges from 5° to 50°, so that the through hole for depositing the first electrode is relatively gentle, which can further completely eliminate
  • the height difference between the DBR reflection layer 8.2 above the electrode extension strip 7 and the DBR reflection layer 8.2 above the ITO is caused by the existence of the electrode extension strip 7 .
  • the thickness ratio of the DBR reflective layer to the DBR sacrificial layer is: 1:1 to 1:5; and the smaller the included angle, the greater the thickness of the DBR sacrificial layer; while protecting the DBR reflective layer, it can effectively eliminate the electrode expansion.
  • the DBR adhesion layer is obtained by atomic layer deposition, and it includes at least one of Ti 3 O 5 , SiO 2 and Al 2 O 3 , so that a film layer with high density and high adhesion can be obtained.
  • the embodiment of the present application also provides a method for preparing a micro-light-emitting element. While realizing the above-mentioned beneficial effects of the micro-light-emitting element, the manufacturing process is simple and convenient, and it is convenient for production.
  • the formation of the oblique sidewall of the through hole includes: firstly, using photoresist as a mask layer, exposing the required opening area through a photolithography development process; secondly, etching the DBR sacrificial area corresponding to the opening area with an etching solution Layer 8.3, forming a lateral etching interface; then, the protrusion of the DBR structure layer formed by the existence of the electrode extension strip 7 is completely etched by multi-stage ICP etching, thereby forming a DBR structure layer with a smooth cross section.
  • the etching angle of the DBR structure layer is formed into a gradual gentle slope by using multi-stage ICP etching to improve the metal coverage of the electrodes.

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Abstract

本发明提供了一种微型发光元件及其制备方法，其DBR结构层包括依次层叠的DBR黏附层、DBR反射层和DBR牺牲层，通过DBR黏附层改善后续DBR反射层的结构披覆性；并利用所述DBR牺牲层、DBR反射层及DBR黏附层的蚀刻速率依次降低的设置，通过刻蚀工艺形成具有斜侧壁的通孔，消除位于电极扩展条上方的DBR反射层与位于ITO上方的DBR反射层的高度差，形成平滑的台面，进而使得电极基本处于同一高度以提升其推拉力可靠性，避免掉电极的风险；且通过通孔的斜侧壁设置，有利于后续第一电极的披覆，并增大第一电极与DBR结构层的接触面积，使得DBR结构层与电极之间能够形成良好的黏附；进而保证发光元件的可靠性。

Description

一种微型发光元件及其制备方法
本申请要求于2021年07月01日提交中国专利局、申请号为202110740250.9、发明名称为“一种微型发光元件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及发光二极管领域，尤其涉及一种微型发光元件及其制备方法。
背景技术
随着半导体发光技术的不断发展，LED的应用日新月异，特别是LED在显示技术的发展。同时，由于LED显示屏的高分辨率的需要，LED芯片的间距及芯片的尺寸也越来越小，如Mini-LED等，然而小尺寸的LED芯片面临着发光效率低的技术难点。
目前，大多采用ITO+电极扩展条+DBR倒装结构，如图1、图2所示，使有源层发出的光需通过布拉格反射镜(DBR)良好的镜面反射来提高出光率；其中，DBR作为光反射层采用高温蒸镀，DBR反射层为TI3O5/SiO2叠层光学设计结构。然而，由于常规工艺制备获得的DBR反射层在倒装非平面上的膜厚度均一性不高，尤其是台阶披覆性差，致使DBR反射层对光的反射有限，并影响后续电极的披覆，导致电极的金属断裂，影响LED芯片的可靠性等。其次，由于电极扩展条的存在，使位于电极扩展条上方的DBR反射层与位于ITO上方的DBR反射层存在明显的高度差，如此导致后续蒸镀电极时存在明显高度差，使 倒装芯片电极扩展条上方的电极成为施力点，存在掉电极风险；最后，如图2中的A标记处所示，对DBR反射层进行ICP干法蚀刻形成用于承载电极的通孔时，由于ICP各项异性蚀刻，使得DBR刻蚀角度陡直不利于后续电极的披覆，容易导致电极的金属断裂，严重影响芯片可靠性。
有鉴于此，本发明人专门设计了一种微型发光元件及其制备方法，本案由此产生。
发明内容
本发明的目的在于提供一种微型发光元件及其制备方法，以保证微型发光元件发光效率的同时，解决因DBR反射层的台阶披覆性差所导致的光反射受限及影响后续电极披覆的问题。
为了实现上述目的，本发明采用的技术方案如下：
一种微型发光元件，包括衬底及及设置于所述衬底表面且通过沟槽相互隔离的若干个LED阵列单元，所述LED阵列单元包括：
外延叠层，所述外延叠层包括沿第一方向依次堆叠的第一型半导体层、有源区以及第二型半导体层，且所述外延叠层的局部区域蚀刻至部分所述的第一型半导体层形成凹槽及台面；所述第一方向垂直于所述衬底，并由所述衬底指向所述外延叠层；
电极扩展条，其层叠于所述台面；
DBR结构层，其包括沿所述外延叠层的表面依次层叠的DBR黏附层、DBR反射层和DBR牺牲层，且所述DBR结构层具有分别裸露所述电极扩展条和所述凹槽的部分表面的通孔；
第一电极，其层叠于所述裸露所述凹槽的通孔与所述第一型半导体层电连接；
第二电极，其层叠于所述裸露所述电极扩展条的通孔与所述第二型半导体层电连接。
优选地，所述DBR牺牲层、DBR反射层及DBR黏附层的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过刻蚀工艺形成具有斜侧壁的倒梯形通孔。
优选地，所述斜侧壁与所述外延叠层的水平表面形成夹角，且夹角的取值范围为5°～50°，包括端点值。
优选地，DBR反射层与DBR牺牲层的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大。
优选地，在所述台面设有透明导电层，且电极扩展条层叠于所述透明导电层背离所述外延叠层的一侧表面。
优选地，所述DBR黏附层通过原子层沉积而获得，且其包括Ti3O5、SiO2及Al2O3中的至少一种。
优选地，所述DBR牺牲层包括旋涂玻璃层或通过低温沉积而获得的绝缘膜。
优选地，所述DBR反射层包括复数个高低折射率交替的膜层，且各所述膜层的厚度为所述微型发光元件所射出光线的波长的四分之一。
优选地，所述电极扩展条包括Cr、Ni、Al、Ti、Pt、Au中的至少一种。
本发明还提供了一种微型发光元件的制备方法，所述制备方法包括如下步骤：
S01、提供一衬底；
S02、生长外延叠层，所述外延叠层包括在所述衬底表面依次堆叠的第一型半导体层、有源层和第二型半导体层；
S03、通过蚀刻所述外延叠层，使部分所述第一型半导体层裸露，从而形成若干个凹槽及台面，所述凹槽与台面相对设置；
S04、通过深蚀刻所述外延叠层至裸露所述衬底表面，形成若干个间隔排布的外延叠层；
S05、在各所述独立的外延叠层的台面沉积透明导电层；
S06、在透明导电层表面形成电极扩展条；
S07、在所述外延叠层的表面形成DBR结构层，其包括依次层叠的DBR黏附层、DBR反射层和DBR牺牲层；
S09、通过刻蚀工艺使所述DBR结构层具有分别裸露所述电极扩展条和所述凹槽的部分表面的通孔；
S09、在所述裸露所述凹槽的通孔内形成与所述第一型半导体层电连接的第一电极；在所述裸露所述电极扩展条的通孔形成与所述第二型半导体层电连接的第二电极。
优选地，所述DBR牺牲层、DBR反射层及DBR黏附层的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过步骤S08所述的刻蚀工艺形成具有斜侧壁的倒梯形通孔。
优选地，步骤S08所述的斜侧壁的形成包括：首先，采用光刻胶作为掩膜层，通过光刻显影工艺裸露所需开孔区域；其次，通过腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层，形成侧向腐蚀界面；然后，采用多段式ICP刻蚀使因所 述电极扩展条的存在所形成的DBR结构层凸起被完全蚀刻，从而形成具有平滑截面的DBR结构层。
优选地，所述多段式ICP刻蚀采用CH xF y气体作为蚀刻工艺气体，并采用O 2或Ar作为辅助气体，其中，X+Y＝4。
优选地，所述多段式ICP刻蚀过程中，所述CH xF y与O 2的比例呈梯度变化。
优选地，所述CH xF y与O 2的比例由梯度递增过渡至梯度递减。
优选地，所述CH xF y与O 2的比例从1:6至1:4至1:2逐渐降低后，再从1:2至1:4至1:6逐渐上升。
经由上述的技术方案可知，本发明提供的微型发光元件，通过设置DBR结构层，其包括沿所述外延叠层的表面依次层叠的DBR黏附层、DBR反射层和DBR牺牲层，通过DBR黏附层改善后续DBR反射层的结构披覆性。其次，通过在DBR反射层表面设置DBR牺牲层，使腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层时可形成侧向腐蚀界面并避免过度刻蚀损坏DBR反射层；进一步地，利用所述DBR牺牲层、DBR反射层及DBR黏附层的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过刻蚀工艺形成具有斜侧壁的倒梯形通孔；，消除位于电极扩展条上方的DBR反射层与位于ITO(即透明导电层)上方的DBR反射层的高度差，形成平滑的台面，进而使得第一电极和/或第二电极基本处于同一高度以提升其推拉力可靠性，避免掉电极的风险；且通过通孔的斜侧壁设置，有利于后续第一电极的披覆，并增大第一电极与DBR结构层的接触面积，使得DBR结构层与电极之间能够形成良好的黏附；进而保证发光元件的可靠性。
通孔的斜侧壁与所述外延叠层的水平表面形成夹角，且夹角的取值范围为 5°～50°，使沉积所述第一电极的通孔较为平缓，可进一步彻底消除因电极扩展条的存在所引起的位于电极扩展条上方的DBR反射层与位于ITO上方的DBR反射层的高度差。
进一步地，DBR反射层与DBR牺牲层的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大；在保护DBR反射层的同时，有效消除因电极扩展条的存在所引起的位于电极扩展条上方的DBR反射层与位于ITO上方的DBR反射层的高度差。
此外，所述DBR黏附层通过原子层沉积而获得，且其包括Ti 3O 5、SiO 2及Al 2O 3中的至少一种，可以得到高致密性、高粘附性的膜层。
本发明还提供了一种微型发光元件的制备方法，在实现上述微型发光元件的有益效果的同时，其工艺制作简单便捷，便于生产化。
同时，所述通孔斜侧壁的形成包括：首先，采用光刻胶作为掩膜层，通过光刻显影工艺裸露所需开孔区域；其次，通过腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层，形成侧向腐蚀界面；然后，采用多段式ICP刻蚀使因所述电极扩展条的存在所形成的DBR结构层凸起被完全蚀刻，从而形成具有平滑截面的DBR结构层。通过DBR牺牲层形成侧向腐蚀后，采用多段式ICP刻蚀使DBR结构层的刻蚀角度形成渐变式缓坡，改善电极的金属覆盖性。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创 造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为现有技术中小尺寸LED芯片的结构示意图；
图2为图1所示的用于沉积电极的通孔所对应的产品效果图；
图3为本发明实施例所提供的微型发光元件的结构示意图；
图4.1至图4.9为本发明实施例所提供的微型发光元件的制备方法步骤所对应的结构示意图；
图中符号说明：1、衬底，2、第一型半导体层，3、有源区，4、第二型半导体层，5.1、凹槽，5.2、台面，6、透明导电层，7、电极扩展条，8.1、DBR黏附层，8.2、DBR反射层，8.3、DBR牺牲层，9、第一电极，10、第二电极，θ、通孔斜侧壁与外延叠层水平表面所形成的夹角。
具体实施方式
为使本发明的内容更加清晰，下面结合附图对本发明的内容作进一步说明。本发明不局限于该具体实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图3所示，一种微型发光元件，包括衬底1及及设置于所述衬底1表面且通过沟槽相互隔离的若干个LED阵列单元，所述LED阵列单元包括：
外延叠层，所述外延叠层包括沿第一方向依次堆叠的第一型半导体层2、有源区3以及第二型半导体层4，且所述外延叠层的局部区域蚀刻至部分所述的第一型半导体层2形成凹槽5.1及台面5.2；所述第一方向垂直于所述衬底1，并由所述衬底1指向所述外延叠层；
电极扩展条7，其层叠于所述台面5.2；
DBR结构层，其包括沿所述外延叠层的表面依次层叠的DBR黏附层8.1、DBR反射层8.2和DBR牺牲层8.3，且所述DBR结构层具有分别裸露所述电极扩展条7和所述凹槽5.1的部分表面的通孔；
第一电极9，其层叠于所述裸露所述凹槽5.1的通孔与所述第一型半导体层2电连接；
第二电极10，其层叠于所述裸露所述电极扩展条7的通孔与所述第二型半导体层4电连接。
需要说明的是，衬底1的类型在本实施例的微型发光元件不受限制，例如，所述衬底1可以是但不限于蓝宝石衬底1、硅衬底1等。另外，所述外延叠层的第一型半导体层2、有源区3以及第二型半导体层4的类型在本实施例的微型发光元件也可以不受限制，例如，所述第一型半导体层2可以是但不限于氮化镓层，相应地，所述第二型半导体层4可以是但不限于氮化镓层。
值得一提的是，在上述实施例中，值得一提的是，在上述实施例中，所述位于台面的电极扩展条7通过通孔与所述第二型半导体层4直接电连接，可以使得所述电极扩展条7直接与所述第二型半导体层2电连接，有利于在实际工作中，所述LED芯片中，第二电极的电流直接流入所述外延叠层；在本申请的其他实施例中，所述电极扩展条还可层叠于透明导电层表面，具体视情况而定，本申请对此并不做限定。
在上述实施例的基础上，在本申请一个实施例中，所述DBR牺牲层8.3、DBR反射层8.2及DBR黏附层8.1的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过刻蚀工艺形成具有斜侧壁的倒梯形通孔。
在上述实施例的基础上，在本申请一个实施例中，所述斜侧壁与所述外延叠层的水平表面形成夹角，且夹角θ的取值范围为5°～50°，包括端点值。
在上述实施例的基础上，在本申请一个实施例中，DBR反射层8.2与DBR牺牲层8.3的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大；需要说明的是，本申请实施例不限定DBR反射层8.2与DBR牺牲层8.3的厚度具体值，只要满足前述要求即可，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，在所述台面5.2设有透明导电层6，且电极扩展条7层叠于所述透明导电层6背离所述外延叠层的一侧表面。
值得一提的是，在上述实施例中，电极扩展条7可以包括形成台面5.2的电极扩展条7和/或形成凹槽5.1的电极扩展条7，分别以作为所述第二电极10在台面5.2的扩展延伸，和所述第一电极9在凹槽5.1的扩展延伸；需要的是，电极扩展条7的数量可以是一条或多条，具体视情况而定，本申请对此并不做限定。
值得一提的是，在上述实施例中，透明导电层6的材料可以是ITO，具体视情况而定，本申请对此并不做限定。
在上述实施例的基础上，在本申请一个实施例中，所述DBR黏附层8.1通过原子层沉积而获得，且其包括Ti 3O 5、SiO 2及Al 2O 3中的至少一种。
在上述实施例的基础上，在本申请一个实施例中，所述DBR牺牲层8.3包括旋涂玻璃层或通过低温沉积而获得的绝缘膜。
在上述实施例的基础上，在本申请一个实施例中，所述DBR反射层8.2包括复数个高低折射率交替的膜层，且各所述膜层的厚度为所述微型发光元件 所射出光线的波长的四分之一。
在上述实施例的基础上，在本申请一个实施例中，所述电极扩展条7包括Cr、Ni、Al、Ti、Pt、Au中的至少一种。
本申请实施例还提供了一种微型发光元件的制备方法，所述制备方法包括如下步骤：
S01、如图4.1所示，提供一衬底1；
需要说明的是，衬底1的类型在本实施例的微型发光元件不受限制，例如，所述衬底1可以是但不限于蓝宝石衬底1、硅衬底1等。
S02、如图4.2所示，生长外延叠层，所述外延叠层包括在所述衬底1表面依次堆叠的第一型半导体层2、有源层和第二型半导体层4；
需要说明的是，所述外延叠层的第一型半导体层2、有源区3以及第二型半导体层4的类型在本实施例的微型发光元件也可以不受限制，例如，所述第一型半导体层2可以是但不限于氮化镓层，相应地，所述第二型半导体层4可以是但不限于氮化镓层。
S03、如图4.3所示，通过蚀刻所述外延叠层，使部分所述第一型半导体层2裸露，从而形成若干个凹槽5.1及台面5.2，所述凹槽5.1与台面5.2相对设置；其中，图4.3仅示意了单个LED阵列单元所对应的外延叠层结构；
在本申请的一个实施例中，对所述外延叠层的进行刻蚀形成若干个凹槽5.1及台面5.2包括：利用电感耦合等离子体(ICP)工艺，刻蚀气体包括：Cl 2、Ar和O 2。但本申请对此并不做限定，具体视情况而定。
S04、如图4.4所示，通过深蚀刻所述外延叠层至裸露所述衬底1表面，形成若干个间隔排布的外延叠层；其中，图4.4仅示意了单个LED阵列单元所 对应的外延叠层结构；
在本申请的一个实施例中，对所述外延叠层的进行深蚀刻至裸露所述衬底1表面，形成若干个间隔排布的外延叠层；包括：利用电感耦合等离子体(ICP)工艺，刻蚀气体包括：Cl 2、Ar和O 2。但本申请对此并不做限定，具体视情况而定。
S05、如图4.5所示，在各所述独立的外延叠层的台面5.2沉积透明导电层6；
值得一提的是，在上述实施例中，透明导电层6的材料可以是ITO，其形成工艺可以是电子束蒸镀工艺、溅射蒸镀等工艺，具体视情况而定，本申请对此并不做限定。
S06、如图4.6所示，在透明导电层6表面形成电极扩展条7；
值得一提的是，在上述实施例中，电极扩展条7可以包括形成台面5.2的电极扩展条7和/或形成于凹槽5.1内的电极扩展条7，分别以作为所述第二电极10在台面5.2的扩展延伸，和所述第一电极9在凹槽5.1的扩展延伸；需要的是，电极扩展条7的数量可以是一条或多条；其形成工艺可以是电子束蒸镀工艺，具体视情况而定，本申请对此并不做限定。
值得一提的是，在上述实施例中，所述位于台面的电极扩展条7通过通孔与所述第二型半导体层4直接电连接，可以使得所述电极扩展条7直接与所述第二型半导体层4电连接，有利于在实际工作中，所述LED芯片中，第二电极的电流直接流入所述外延叠层；在本申请的其他实施例中，所述电极扩展条还可层叠于透明导电层表面，具体视情况而定，本申请对此并不做限定。
在本申请的一个实施例中，所述电极扩展条7包括Cr、Ni、Al、Ti、Pt、 Au中的一种或多种组合。
S07、如图4.7所示，在所述外延叠层的表面形成DBR结构层，其包括依次层叠的DBR黏附层8.1、DBR反射层8.2和DBR牺牲层8.3；
在本申请的一个实施例中，所述DBR黏附层8.1通过原子层沉积而获得，且其包括Ti 3O 5、SiO 2及Al2O3中的至少一种，具体视情况而定，本申请对此并不做限定。
在本申请的一个实施例中，所述DBR反射层8.2包括复数个高低折射率交替的膜层，且各所述膜层的厚度为所述微型发光元件所射出光线的波长的四分之一。
在本申请的一个实施例中，所述DBR牺牲层8.3包括旋涂玻璃层或通过低温沉积而获得的绝缘膜。
在本申请的一个实施例中，所述DBR牺牲层8.3、DBR反射层8.2及DBR黏附层8.1的蚀刻速率依次降低。
S08、如图4.8所示，通过刻蚀工艺使所述DBR结构层具有分别裸露所述电极扩展条7和所述凹槽5.1的部分表面的通孔；
在上述实施例的基础上，在本申请一个实施例中，具体可通过在表面旋涂光刻胶定向对准蚀刻。
在本申请的一个实施例中，由于所述DBR牺牲层8.3、DBR反射层8.2及DBR黏附层8.1的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过步骤S08所述的刻蚀工艺形成具有斜侧壁的倒梯形通孔。在上述实施例的基础上，在本申请一个实施例中，步骤S08所述的斜侧壁的形成包括：首先，采用光刻胶作为掩膜层，通过光刻显影工艺裸露所需开孔区域；其次，通过腐 蚀溶液蚀刻开孔区域所对应的DBR牺牲层8.3，形成侧向腐蚀界面；然后，采用多段式ICP刻蚀使因所述电极扩展条7的存在所形成的DBR结构层凸起被完全蚀刻，从而形成具有平滑截面的DBR结构层。
在上述实施例的基础上，在本申请一个实施例中，所述斜侧壁与所述外延叠层的水平表面形成夹角，且夹角θ的取值范围为5°～50°，包括端点值。
在上述实施例的基础上，在本申请一个实施例中，DBR反射层8.2与DBR牺牲层8.3的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大；需要说明的是，本申请实施例不限定DBR反射层8.2与DBR牺牲层8.3的厚度具体值，只要满足前述要求即可，具体视情况而定。
在上述实施例的基础上，在本申请一个实施例中，所述多段式ICP刻蚀采用CH xF y气体作为蚀刻工艺气体，并采用O 2或Ar作为辅助气体，其中，X+Y＝4。
在上述实施例的基础上，在本申请一个实施例中，所述多段式ICP刻蚀过程中，所述CH xF y与O 2的比例呈梯度变化。
在上述实施例的基础上，在本申请一个实施例中，所述CH xF y与O 2的比例由梯度递增过渡至梯度递减。
在上述实施例的基础上，在本申请一个实施例中，所述CH xF y与O 2的比例从1:6至1:4至1:2逐渐降低后，再从1:2至1:4至1:6逐渐上升。
在上述实施例的基础上，在本申请一个实施例中，采用CHF 3气体作为蚀刻工艺气体，并采用O 2作为辅助气体。
S09、如图4.9所示，在所述裸露所述凹槽5.1的通孔内形成与所述第一型半导体层2电连接的第一电极9；在所述裸露所述电极扩展条7的通孔形成与所述第二型半导体层4电连接的第二电极10。
在上述实施例的基础上，在本申请一个实施例中，第一电极9和/或第二电极10包括Cr、Ni、Al、Ti、Pt、Au等金属中一种或多种组合。
经由上述的技术方案可知，本申请实施例提供的微型发光元件，通过设置DBR结构层，其包括沿所述外延叠层的表面依次层叠的DBR黏附层8.1、DBR反射层8.2和DBR牺牲层8.3，通过DBR黏附层8.1改善后续DBR反射层8.2的结构披覆性。其次，通过在DBR反射层8.2表面设置DBR牺牲层8.3，使腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层8.3时可形成侧向腐蚀界面并避免过度刻蚀损坏DBR反射层8.2；进一步地，利用所述DBR牺牲层8.3、DBR反射层8.2及DBR黏附层8.1的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过刻蚀工艺形成具有斜侧壁的倒梯形通孔；消除位于电极扩展条7上方的DBR反射层8.2与位于ITO(即透明导电层6)上方的DBR反射层8.2的高度差，形成平滑的台面5.2，进而使得第一电极9和/或第二电极10基本处于同一高度以提升其推拉力可靠性，避免掉电极的风险；且通过通孔的斜侧壁设置，有利于后续第一电极9的披覆，并增大第一电极9与DBR结构层的接触面积，使得DBR结构层与电极之间能够形成良好的黏附；进而保证发光元件的可靠性。
通孔的斜侧壁与所述外延叠层的水平表面形成夹角，且夹角的取值范围为5°～50°，使沉积所述第一电极的通孔较为平缓，可进一步彻底消除因电极扩展条7的存在所引起的位于电极扩展条7上方的DBR反射层8.2与位于ITO上方的DBR反射层8.2的高度差。
进一步地，DBR反射层与DBR牺牲层的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大；在保护DBR反射层的同时，有效消除因电极扩展 条的存在所引起的位于电极扩展条上方的DBR反射层与位于ITO上方的DBR反射层的高度差。
此外，所述DBR黏附层通过原子层沉积而获得，且其包括Ti 3O 5、SiO 2及Al 2O 3中的至少一种，可以得到高致密性、高粘附性的膜层。
本申请实施例还提供了一种微型发光元件的制备方法，在实现上述微型发光元件的有益效果的同时，其工艺制作简单便捷，便于生产化。
同时，所述通孔斜侧壁的形成包括：首先，采用光刻胶作为掩膜层，通过光刻显影工艺裸露所需开孔区域；其次，通过腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层8.3，形成侧向腐蚀界面；然后，采用多段式ICP刻蚀使因所述电极扩展条7的存在所形成的DBR结构层凸起被完全蚀刻，从而形成具有平滑截面的DBR结构层。通过DBR牺牲层8.3形成侧向腐蚀后，采用多段式ICP刻蚀使DBR结构层的刻蚀角度形成渐变式缓坡，改善电极的金属覆盖性。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (13)

  1. 一种微型发光元件，包括衬底及及设置于所述衬底表面且通过沟槽相互隔离的若干个LED阵列单元，其特征在于，所述LED阵列单元包括：
    外延叠层，所述外延叠层包括沿第一方向依次堆叠的第一型半导体层、有源区以及第二型半导体层，且所述外延叠层的局部区域蚀刻至部分所述的第一型半导体层形成凹槽及台面；所述第一方向垂直于所述衬底，并由所述衬底指向所述外延叠层；
    电极扩展条，其层叠于所述台面；
    DBR结构层，其包括沿所述外延叠层的表面依次层叠的DBR黏附层、DBR反射层和DBR牺牲层，且所述DBR结构层具有分别裸露所述电极扩展条和所述凹槽的部分表面的通孔；
    第一电极，其层叠于所述裸露所述凹槽的通孔与所述第一型半导体层电连接；
    第二电极，其层叠于所述裸露所述电极扩展条的通孔与所述第二型半导体层电连接。
  2. 根据权利要求1所述的微型发光元件，其特征在于，所述DBR牺牲层、DBR反射层及DBR黏附层的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过刻蚀工艺形成具有斜侧壁的倒梯形通孔。
  3. 根据权利要求2所述的微型发光元件，其特征在于，所述斜侧壁与所述外延叠层的水平表面形成夹角，且夹角的取值范围为5°～50°，包括端点值。
  4. 根据权利要求3所述的微型发光元件，其特征在于，DBR反射层与DBR牺牲层的厚度比为：1：1～1：5；且夹角越小，DBR牺牲层的厚度越大。
  5. 根据权利要求1所述的微型发光元件，其特征在于，在所述台面设有透明导电层，且电极扩展条层叠于所述透明导电层背离所述外延叠层的一侧表面。
  6. 根据权利要求1所述的微型发光元件，其特征在于，所述DBR黏附层通过原子层沉积而获得，且其包括Ti 3O 5、SiO 2及Al 2O 3中的至少一种。
  7. 根据权利要求1所述的微型发光元件，其特征在于，所述DBR牺牲层包括旋涂玻璃层或通过低温沉积而获得的绝缘膜。
  8. 一种微型发光元件的制备方法，其特征在于，所述制备方法包括如下步骤：
    S01、提供一衬底；
    S02、生长外延叠层，所述外延叠层包括在所述衬底表面依次堆叠的第一型半导体层、有源层和第二型半导体层；
    S03、通过蚀刻所述外延叠层，使部分所述第一型半导体层裸露，从而形成若干个凹槽及台面，所述凹槽与台面相对设置；
    S04、通过深蚀刻所述外延叠层至裸露所述衬底表面，形成若干个间隔排布的外延叠层；
    S05、在各所述独立的外延叠层的台面沉积透明导电层；
    S06、在透明导电层表面形成电极扩展条；
    S07、在所述外延叠层的表面形成DBR结构层，其包括依次层叠的DBR黏附层、DBR反射层和DBR牺牲层；
    S08、通过刻蚀工艺使所述DBR结构层具有分别裸露所述电极扩展条和所述凹槽的部分表面的通孔；
    S09、在所述裸露所述凹槽的通孔内形成与所述第一型半导体层电连接的第一电极；在所述裸露所述电极扩展条的通孔形成与所述第二型半导体层电连接的第二电极。
  9. 根据权利要求8所述的微型发光元件的制备方法，其特征在于，所述DBR牺牲层、DBR反射层及DBR黏附层的膜层致密性依次上升，使得蚀刻时蚀刻速率依次降低，从而通过步骤S08所述的刻蚀工艺形成具有斜侧壁的倒梯形通孔。
  10. 根据权利要求9所述的微型发光元件的制备方法，其特征在于，步骤S08所述的斜侧壁的形成包括：首先、采用光刻胶作为掩膜层，通过光刻显影工艺裸露所需开孔区域；其次，通过腐蚀溶液蚀刻开孔区域所对应的DBR牺牲层，形成侧向腐蚀界面；然后，采用多段式ICP刻蚀使因所述电极扩展条的存在所形成的DBR结构层凸起被完全蚀刻，从而形成具有平滑截面的的DBR结构层。
  11. 根据权利要求10所述的微型发光元件的制备方法，其特征在于，所述多段式ICP刻蚀采用CH xF y气体作为蚀刻工艺气体，并采用O 2或Ar作为辅助气体，其中，X+Y＝4。
  12. 根据权利要求11所述的微型发光元件的制备方法，其特征在于，所述多段式ICP刻蚀过程中，所述CH xF y与O 2的比例呈梯度变化。
  13. 根据权利要求12所述的微型发光元件的制备方法，其特征在于，所述CH xF y与O 2的比例由梯度递增过渡至梯度递减。
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