WO2023272589A1 - 用于驱动显示面板的方法 - Google Patents

用于驱动显示面板的方法 Download PDF

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Publication number
WO2023272589A1
WO2023272589A1 PCT/CN2021/103599 CN2021103599W WO2023272589A1 WO 2023272589 A1 WO2023272589 A1 WO 2023272589A1 CN 2021103599 W CN2021103599 W CN 2021103599W WO 2023272589 A1 WO2023272589 A1 WO 2023272589A1
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Prior art keywords
signal
circuit
driving
display panel
time period
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PCT/CN2021/103599
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English (en)
French (fr)
Inventor
单冬晓
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/103599 priority Critical patent/WO2023272589A1/zh
Priority to PCT/CN2022/083384 priority patent/WO2023273444A1/zh
Priority to CN202280000570.3A priority patent/CN116034416A/zh
Priority to US17/790,011 priority patent/US20240185796A1/en
Publication of WO2023272589A1 publication Critical patent/WO2023272589A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • Embodiments of the present disclosure generally relate to display technologies, and in particular, relate to a method for driving a display panel.
  • FIG. 1 is a block diagram showing the structure of an exemplary OLED display panel.
  • an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display panel may include a pixel circuit 1, a gate driving circuit 2, and a source driving circuit 3.
  • the gate driving circuit 2 and the source driving circuit 3 respectively provide scanning signals, data signals and the like to the pixel circuit 1 .
  • the pixel circuit 1 may include a plurality of pixel units in an array, wherein each pixel unit may include an OLED element.
  • the OLED panel may further include a light emission control driving circuit 4 that outputs a light emission control signal to the pixel circuit 1 .
  • the light emission control driving circuit 4 can cooperate with the gate driving circuit 2 to drive the pixel circuit 1 .
  • OLED panels Compared with liquid crystal display (Liquid Crystal Display, LCD) panels, OLED panels use more thin-film transistors (Thin-Film Transistor, TFT), and the circuit is more complicated.
  • TFT Thin-Film Transistor
  • each transistor in the pixel circuit may be in an unstable state, resulting in problems such as flickering images and/or circuit short circuits.
  • An object of the present disclosure is to provide an improved method for driving a display panel, so as to solve the above-mentioned problems or other problems that may occur during the power-on process of the display panel.
  • the display panel includes a pixel circuit, a gate driving circuit, and a source driving circuit.
  • the method for driving the display panel may include: providing an inactive start signal to the gate driving circuit and/or the light emission control driving circuit during the first period of time; and providing the first power signal and the first power supply signal to the pixel circuit during the second period of time. a second power supply signal; and providing an effective start signal to the gate drive circuit and/or the light emission control drive circuit during a third period of time.
  • the power terminal of the pixel circuit is grounded.
  • the source driving circuit is made to output a ground signal during the first time period.
  • the method for driving the gate driving circuit includes: providing the third power supply signal and the fourth power supply signal to the gate driving circuit; providing a clock signal to the gate driving circuit; and The gate drive circuit provides an invalid first enable signal.
  • the first activation signal remains inactive during the first time period and the second time period.
  • the method for driving the display panel further includes: making the source driver circuit provide the display data signal to the pixel circuit during the third time period.
  • the display panel further includes a light emission control driving circuit for outputting a light emission control signal to the pixel circuit.
  • the method for driving the display panel further includes: driving the light emission control driving circuit during the first time period.
  • the method for driving the light emission control drive circuit includes: providing a third power supply signal and a fourth power supply signal to the power supply terminal of the light emission control drive circuit; providing a clock signal to the light emission control drive circuit ; and providing an invalid second startup signal to the light-emitting control driving circuit.
  • the method for driving a display panel further includes: causing the source driver circuit to provide a display data signal to the pixel circuit during a third time period.
  • the first startup signal provided to the source driving circuit and the second startup signal provided to the light emission control driving circuit remain ineffective.
  • the second enabling signal remains inactive until the first enabling signal of the gate driving circuit becomes active.
  • the first start signal provided to the source driving circuit and the second start signal provided to the light emission control driving circuit remain ineffective.
  • the second activation signal remains inactive.
  • the pixel circuit is supplied with a display data signal corresponding to displaying black.
  • the pixel circuit includes a driving power supply terminal and a reference power supply terminal.
  • the method for driving the pixel circuit includes: providing the first power supply signal and the second power supply signal to the driving power supply terminal; and supplying power to the reference power supply terminal.
  • the first time period includes the duration of at least one display frame
  • the second time period includes the duration of at least one display frame
  • the first time period does not overlap with the second time period.
  • the display panel further includes a multiplexing circuit provided between the source driving circuit and the pixel circuit.
  • the multiplexing circuit is turned on.
  • Another aspect of the present disclosure further provides a display panel configured to provide a pixel circuit with the display panel driving method described in any one of the above embodiments.
  • an improved power-on sequence is provided for the display panel, which can avoid problems such as flickering of the display screen or circuit short circuit caused by the unstable state of the internal circuit of the display panel during the power-on process.
  • FIG. 1 is a block diagram showing the structure of an exemplary OLED display panel.
  • FIG. 2 is an exemplary flowchart illustrating a method for driving a display panel according to an embodiment of the present disclosure.
  • FIG. 3 is a block diagram showing the structure of another exemplary OLED display panel.
  • Fig. 4(a) is a circuit diagram of an exemplary pixel unit.
  • FIG. 4( b ) is a timing diagram of an exemplary pixel unit in FIG. 4( a ).
  • FIG. 5( a ) is a circuit diagram of an exemplary gate drive circuit.
  • FIG. 5( b ) is a timing diagram of an exemplary gate driving circuit in FIG. 5( a ).
  • Fig. 6(a) is a circuit diagram of an exemplary light emission control driving circuit.
  • FIG. 6( b ) is an exemplary timing diagram of the light emission control driving circuit in FIG. 6( a ).
  • FIG. 7( a ) is a circuit diagram of another exemplary pixel unit.
  • FIG. 7( b ) is a timing diagram of an exemplary pixel unit in FIG. 7( a ).
  • FIG. 8( a ) is a flowchart illustrating sub-steps of the method shown in FIG. 2 .
  • FIG. 8( b ) is a flowchart illustrating additional steps of the method shown in FIG. 2 .
  • FIG. 8( c ) is a flowchart illustrating additional steps of the method shown in FIG. 2 .
  • FIG. 8( d ) is an exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • FIG. 9 is another exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is an exemplary test signal waveform diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • FIG. 11 is a block diagram showing the structure of another exemplary OLED display panel.
  • FIG. 12( a ) is a circuit diagram of an exemplary pixel unit in FIG. 11 .
  • FIG. 12( b ) is a timing diagram of an exemplary pixel unit in FIG. 12( a ).
  • FIG. 13( a ) is a circuit diagram of an exemplary additional gate drive circuit in FIG. 11 .
  • FIG. 13( b ) is a timing diagram of an exemplary additional gate drive circuit in FIG. 13( a ).
  • FIG. 14 is an exemplary timing diagram corresponding to a method for powering on the OLED display panel in FIG. 11 according to an embodiment of the present disclosure.
  • FIG. 2 is an exemplary flowchart illustrating a method for driving a display panel according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure can be applied to the OLED display panel as shown in FIG. 1 , and any other suitable display panels. Therefore, embodiments of the present disclosure also include such a display panel to which this method is applied.
  • the method for driving a display panel shown in FIG. 2 may include: step S101, providing an invalid startup signal to the gate drive circuit and/or light emission control drive circuit during a first period of time; step S102, providing an invalid startup signal during a second period of time , providing the first power signal and the second power signal to the pixel circuit; and step S103 , providing a valid start signal to the gate drive circuit and/or the light emission control drive circuit in a third time period.
  • the display panel can enter a normal display process. That is, in a normal display process, the gate drive circuit periodically (for example, with a display frame as a cycle) drives the pixel circuit (makes the transistor in the pixel circuit turn on or off according to a predetermined timing), and the source driver periodically Display data is provided to the pixel circuit, so that the OLED in the pixel circuit operates corresponding to the display data of each display frame (for example, emits light with a corresponding brightness), so that the OLED display panel can display the image picture of each frame.
  • the gate drive circuit periodically (for example, with a display frame as a cycle) drives the pixel circuit (makes the transistor in the pixel circuit turn on or off according to a predetermined timing), and the source driver periodically Display data is provided to the pixel circuit, so that the OLED in the pixel circuit operates corresponding to the display data of each display frame (for example, emits light with a corresponding brightness), so that the OLED display panel can display the image picture of each frame.
  • the power terminal in the pixel circuit may be grounded. According to such a method, the transistor in the pixel circuit can be more reliably in the cut-off state, the anti-interference ability in the power-on process can be improved, and problems such as flickering of the display screen or circuit short circuit can be effectively prevented.
  • the source driving circuit may be made to output a ground signal during the first time period.
  • the pixel circuit receives the ground signal instead of the display data signal, which can further prevent the interference signal during the power-on process from being input to the pixel circuit as display data, and can effectively prevent problems such as flickering of the display screen or circuit short circuit.
  • the first time period does not overlap with the second time period. According to such an approach, it can be ensured that after the gate drive circuit is initialized (that is, after the pixel circuit can be driven completely according to the predetermined display timing), power supply and/or display data are provided to the pixel circuit. This can more effectively prevent problems such as flickering of the display screen or short circuit of the circuit.
  • the first time period includes the duration of at least one display frame
  • the second time period includes the duration of at least one display frame.
  • the method for driving a display panel described in the embodiments of the present disclosure will be further described in conjunction with an exemplary circuit structure of an exemplary OLED display panel. It should be understood that the following circuit structures are merely exemplary, rather than methods described for the embodiments of the present disclosure. The method for driving a display panel described in the embodiments of the present disclosure can be applied to the transformation and improvement of the following circuit structures.
  • FIG. 3 is a block diagram showing the structure of another exemplary OLED display panel.
  • the pixel circuit 1 includes a plurality of pixel units in an array, which can be recorded as the first row (Line[1]) to the yth row (Line[y]), and the first column (Row[1]) to column x (Row[x]).
  • x, y are positive integers.
  • OLED display panels can use a so-called line scan mode of operation.
  • the gate driving circuit 2 and the light emission control driving circuit 4 sequentially scan each row of pixel units, and correspondingly, the source driving circuit 3 sequentially provides data signals to each row of scanned pixel units.
  • the gate drive circuit 2 first outputs a valid reset signal (RST[1]), so that the pixel unit of the first row (Line[1]) are reset. Then, the gate driving circuit 2 outputs a valid gate driving signal (GATE[1]), so that the data signal provided by the source driving circuit 3 can be written into the pixel units of the first row (Line[1]).
  • the effective gate driving signal (GATE[1]) can also be used as a reset signal (RST[2]) of the pixel unit in the second row (Line[2]).
  • the luminescence control driving circuit 4 outputs an effective luminescence control signal (EM[1]), so that the OLEDs in the pixel units of the first row (Line[1]) work corresponding to their respective display data (for example, generate respective corresponding brightness).
  • EM[1] effective luminescence control signal
  • the display state can last until the end of the display frame.
  • the second row (Line[2]) pixel unit to the yth row (Line[y]) pixel unit will be scanned in the same way.
  • an "effective" signal refers to a signal that can make subsequent circuit elements (such as transistors) enter an operating state (such as conduction). Accordingly, specific properties (eg, amplitude) of the "active" signal may vary corresponding to the differences in subsequent circuit elements. For example, for an N-type transistor, the effective signal may be a relatively high-level voltage signal. For a P-type transistor, the effective signal may be a relatively low-level voltage signal.
  • an "invalid" signal refers to a signal that cannot make subsequent circuit elements (such as transistors) enter an operating state (such as conduction), that is, will keep subsequent circuit elements (such as transistors) off.
  • the OLED display panel further includes a multiplexing circuit disposed between the source driving circuit and the pixel circuit.
  • the output of the source driver circuit 3 may be coupled to a multiplexing circuit 31 .
  • the display data provided by the source driver 3 can be respectively provided to pixel units in different columns via the multiplexing circuit.
  • signals for displaying data may be provided to odd columns and even columns respectively.
  • MUX1 When MUX1 is active, the switching elements in the multiplexing circuit 31 corresponding to the pixel units in odd columns can be turned on, so that the output of the source driver circuit 3 is transmitted to the pixel units in odd columns.
  • the switching elements in the multiplexing circuit 31 corresponding to the pixel units of the even columns can be turned on, so that the output of the source driving circuit 3 is transmitted to the pixel units of the even columns.
  • the multiplexing of the source driving circuit 3 can be realized, the circuit components required in the source driving circuit 3 are reduced, and the occupied area and cost are correspondingly reduced.
  • the switching signals MUX1 and MUX2 can have completely opposite waveforms, that is, they are either provided to odd columns or even columns at the same time, so as to realize the multiplexing of the output of the source driving circuit 3 . Therefore, in the following description, only MUX may be used to represent such a plurality of switching signals having a fixed waveform relationship.
  • the OLED display panel in FIG. 3 can be, for example, an AMOLED (Active-matrix organic light-emitting diode, active-matrix organic light-emitting diode) panel, specifically an LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) AMOLED display panel.
  • AMOLED Active-matrix organic light-emitting diode, active-matrix organic light-emitting diode
  • LTPS Low Temperature Poly-Silicon, low temperature polysilicon
  • 2A source-level multiplexing circuit is used (the switching elements (such as thin film transistors) driven by Mux1 and Mux2 are P-channel), and some models of panels may not have a Mux circuit.
  • FIG. 4(a) is a circuit diagram of an exemplary pixel unit.
  • FIG. 4( b ) is a timing diagram of an exemplary pixel unit in FIG. 4( a ).
  • the pixel unit shown in FIG. 4( a ) may include an eleventh transistor T11 to a seventeenth transistor T17 and an eleventh capacitor C11 . In addition, it is described that the pixel unit is located in the Nth row.
  • the control electrode of the eleventh transistor T11 is used to input the reset signal Reset (N), the first electrode is coupled to the first reference power supply terminal VREFN (also called the initialization power supply terminal, and may be at a low level), the second The two electrodes are coupled to the control electrode of the thirteenth transistor T13 and the first electrode of the twelfth transistor T12.
  • the control electrode of the twelfth transistor T12 is used to input the gate driving signal Gate, and the second electrode is coupled to the second electrode of the thirteenth transistor T13 and the first electrode of the sixteenth transistor T16 .
  • the first pole of the thirteenth transistor T13 is coupled to the first pole of the fourteenth transistor T14 and the second pole of the fifteenth transistor T15 .
  • the control electrode of the fourteenth transistor T14 is used for inputting the gate driving signal Gate, and the second electrode is used for inputting the display data signal Vdata.
  • the control pole of the fifteenth transistor T15 is used for inputting the light emission control signal EM, and the first pole is coupled to the power supply terminal for inputting the first driving power supply ELVDD (that is, provided as the first power supply signal) level).
  • the control electrode of the sixteenth transistor T16 is used to input the light emission control signal EM, and the second electrode is coupled to the first electrode (which may be an anode) of the OLED.
  • the control electrode of the seventeenth transistor T17 is used to input the reset signal Reset (N+1) of the pixel circuit in the next row (may be the same as the gate drive signal Gate), the first electrode is coupled to the first reference power supply terminal VREFN, The second pole is coupled with the first pole of the OLED.
  • the second electrode (which may be the cathode) of the OLED is coupled to the power terminal (which may input a low level) for inputting the second driving power ELVSS (that is, provided as the second power signal).
  • a first end of the eleventh capacitor C11 is coupled to the power end for inputting the first driving power ELVDD, and a second end is coupled to the control electrode of the thirteenth transistor T13.
  • the control electrode of the transistor may be the gate, the first electrode may be either the source or the drain, and the second electrode may be the other of the source or the drain. Furthermore, the first poles of different transistors may be of different types and the second poles may be of different types.
  • the lighting control signal remains inactive (invalid means that the signal cannot turn on the transistor, or turn off the transistor).
  • the reset signal Reset(N) is valid (valid means that the signal can turn on the transistor), so that the voltage of the corresponding node in the corresponding pixel circuit is reset, or initialized, or set as a reference voltage.
  • the gate driving signal Gate is active, so that the data signal Data (ie, Vdata) is written.
  • the light emission control signal is valid, and the reset signal Reset(N) and the gate driving signal Gate are invalid.
  • the OLED operates (for example, emits light with a predetermined brightness) corresponding to the data signal Data.
  • the duration of the high level of the light emission control signal EM is longer than the time period 2H shown in the figure and covers the low level of the reset signal Reset and the gate drive signal Gate in the time periods t1 and t2 .
  • the reset signal Reset(N) may be the gate driving signal Gate(N ⁇ 1) of the previous row.
  • FIG. 5( a ) is a circuit diagram of an exemplary gate drive circuit.
  • FIG. 5( b ) is a timing diagram of an exemplary gate driving circuit in FIG. 5( a ).
  • the gate drive circuit can be composed of the shift register units shown in Fig. 5(a) connected in series step by step. That is, the gate driving circuit works in the form of a shift register, and the shift register units of each level sequentially output the above-mentioned reset signal and gate driving signal (also collectively referred to as row scanning signals) to the pixel circuit.
  • such a shift register unit may include: the twenty-first transistor T21 to the twenty-eighth transistor T28, the twenty-first capacitor C21 to the twenty-eighth Two capacitors C22.
  • the control pole of the twenty-first transistor T21 is used to input the first clock signal GCK
  • the first pole is used to input the first start signal GSTV
  • the second pole is connected with the control pole of the twenty-second transistor T22
  • the twenty-seventh transistor T22 The second pole of the transistor T27 is coupled to the first pole of the twenty-eighth transistor T28.
  • the first pole of the twenty-second transistor T22 is used to input the first clock signal GCK
  • the second pole is connected with the second pole of the twenty-third transistor T23, the control pole of the twenty-fourth transistor T24, the twenty-sixth transistor
  • the control pole of T26 is coupled.
  • the control electrode of the twenty-third transistor T23 is used for inputting the first clock signal GCK, and the first electrode is coupled to the power terminal for inputting the low level VL (ie, provided as the fourth power signal).
  • the first pole of the twenty-fourth transistor T24 is coupled to the power terminal for inputting a high level VH (that is, provided as a third power signal), and the second pole is connected to the first pole of the twenty-fifth transistor T25. coupled and used to output the gate driving signal GO.
  • the control electrode of the twenty-fifth transistor T25 is coupled to the second electrode of the twenty-eighth transistor T28, and the second electrode is used for inputting the second clock signal GCB.
  • the first pole of the twenty-sixth transistor T26 is coupled to the power terminal for inputting the high level VH, and the second pole is coupled to the first pole of the twenty-seventh transistor T27.
  • the gate of the twenty-seventh transistor T27 is used to input the second clock signal GCB.
  • the control electrode of the twenty-eighth transistor T28 is coupled to the power terminal for inputting the low level VL.
  • the twenty-first capacitor C21 is coupled between the control electrode and the first electrode of the twenty-fourth transistor T24.
  • the twenty-second capacitor C22 is coupled between the control electrode and the first electrode of the twenty-fifth transistor T25.
  • the high level VH may be a positive voltage with a predetermined magnitude
  • the low level VL may be a negative voltage with a predetermined magnitude
  • the first start signal GSTV is valid, so that the corresponding first The shift register unit of the row pixel unit starts to work.
  • the states of the first start signal GSTV, the first clock signal GCK, and the second clock signal GCB change according to a predetermined timing, so that the valid gate driving signal GO1 is output for the first row of pixel units during the time period t2.
  • the gate drive signal GO1 is also used as the start signal of the next-stage shift register unit (for example, corresponding to the second row of pixel units), so that the next-stage shift register unit outputs a valid gate drive signal in the time period t3 GO2 for the next row of pixel units.
  • the shift register units at all levels work sequentially to complete the output of the gate driving signals of all rows.
  • the circuit structures of the shift register units in two adjacent rows are exactly the same, and all stages can share two clock signals GCK and GCB.
  • FIG. 6(a) is a circuit diagram of an exemplary light emission control driving circuit.
  • FIG. 6( b ) is an exemplary timing diagram of the light emission control driving circuit in FIG. 6( a ).
  • the light emission control drive circuit can be composed of the shift register units shown in FIG. 6( a ) in series. That is, the light emission control driving circuit also works in the form of a shift register, and the shift register units of each stage sequentially output the above light emission control signal (which may also belong to the row scanning signal) to the pixel circuit.
  • such a shift register unit may mainly include: a thirty-first transistor T31 to a thirty-eighth transistor T38, a thirty-first capacitor C31 to a third Thirteen capacitors C33.
  • the control pole of the thirty-first transistor T1 is used to input the third clock signal ECK
  • the first pole is used to input the second start signal ESTV
  • the second pole is connected to the control pole of the thirty-third transistor T33
  • the thirty-fifth The control electrode of the transistor T35 is coupled to the control electrode of the thirty-eighth transistor T38.
  • the control pole of the thirty-second transistor T32 is used to input the third clock signal ECK
  • the first pole is coupled to the power terminal for inputting the low level VL
  • the second pole is connected to the second pole of the thirty-third transistor T33
  • the control electrode of the thirty-sixth transistor T36 is coupled.
  • the first pole of the thirty-third transistor T33 is used to input the third clock signal ECK.
  • the control pole of the thirty-fourth transistor T34 is coupled to the second pole of the thirty-seventh transistor T37 and the second pole of the thirty-eighth transistor T38, and the first pole is coupled to the power terminal for inputting a high level VH , the second pole is coupled to the first pole of the thirty-fifth transistor T35, and is used for outputting the light emission control signal EM.
  • the second pole of the thirty-fifth transistor T35 is coupled to the power terminal for inputting the low level VL.
  • the first pole of the thirty-sixth transistor T36 is coupled to the power terminal for inputting the low level VL, and the second pole is coupled to the first pole of the thirty-seventh transistor T37.
  • the control electrode of the thirty-seventh transistor T37 is used to input the fourth clock signal ECB.
  • the first pole of the thirty-eighth transistor T38 is coupled to the power terminal for inputting the high level VH.
  • the first terminal of the thirty-first capacitor C31 is coupled to the control electrode of the thirty-fifth transistor T35, and the second terminal is used for inputting the fourth clock signal ECB.
  • the thirty-second capacitor C32 is coupled between the control electrode and the first electrode of the thirty-fourth transistor T34.
  • the first terminal of the thirty-third capacitor C33 is coupled to the control electrode of the thirty-sixth transistor T36, and the second terminal is used for inputting the fourth clock signal ECB.
  • the second start signal ESTV is invalid, so that the pixel unit corresponding to the first row
  • the shift register unit outputs an invalid lighting control signal.
  • the first enable signal GSTV changes to be valid later, and the states of the third clock signal ECK and the fourth clock signal ECB change according to a predetermined timing, so that the continuously valid light emission control signal EO1 is output for the first row of pixel units.
  • the luminescence control signal EO1 is simultaneously used as an activation signal for the next-stage shift register unit (for example, corresponding to the second row of pixel units), so that the next-stage shift register unit will output an effective luminescence control signal EO2 for use in The pixel unit of the next row.
  • the shift register units at all levels work sequentially to complete the output of the light-emitting control signals of all rows.
  • circuits shown in Fig. 4(a), Fig. 5(a) and Fig. 6(a) can cooperate with each other. However, it should be understood that any one or more of the circuits may be replaced by circuits of other structures having the same function.
  • FIG. 7( a ) is a circuit diagram of another exemplary pixel unit.
  • FIG. 7( b ) is a timing diagram of an exemplary pixel unit in FIG. 7( a ).
  • the pixel unit shown in FIG. 7( a ) may include a forty-first transistor T41 to a forty-seventh transistor T47 and a forty-first capacitor C41 . In addition, it is also described that the pixel unit is located in the Nth row.
  • the control pole of the forty-first transistor T41 is used to input the reset signal Reset (N), the first pole is coupled to the first reference power supply terminal VREFN, the second pole is coupled to the first pole of the forty-second transistor T42, The control electrode of the forty-third transistor T43.
  • the control electrode of the forty-second transistor T42 is used to input the gate driving signal Gate, and the second electrode is coupled to the second electrode of the forty-third transistor T43 and the first electrode of the forty-sixth transistor T46.
  • the first pole of the forty-third transistor T43 is coupled to the second pole of the forty-seventh transistor T47 and a power terminal for inputting the first driving power ELVDD.
  • the control electrode of the forty-fourth transistor T44 is used to input the gate drive signal Gate, the first electrode is used to input the display data signal Vdata, and the second electrode is coupled to the first electrode of the forty-fifth transistor T45 and the fourth electrode. Seventeen is the first pole of the transistor T47.
  • the control electrode of the forty-fifth transistor T45 is used for inputting the light emission control signal EM, and the second electrode is coupled to the second reference power supply terminal VREFP (also referred to as an initialization power supply terminal, and may input a high level).
  • the control electrode of the forty-sixth transistor T46 is used to input the light emission control signal EM, and the second electrode is coupled to the first electrode of the OLED.
  • the gate of the forty-seventh transistor T47 is used to input the reset signal Reset(N).
  • the second electrode (which may be the cathode) of the OLED is coupled to the power terminal (which may input a low level) for inputting the second driving power ELVSS.
  • the first terminal of the forty-first capacitor C41 is coupled to the second terminal of the forty-fourth transistor T44, and the second terminal is coupled to the second terminal of the forty-first transistor T41.
  • FIG. 7(b) The working sequence of FIG. 7(b) may be exactly the same as that of FIG. 4(b), and its description is omitted.
  • all the transistors are P-type (or called P-channel) transistors, and the corresponding effective signal is a signal of a relatively low level (for example, 0V or negative voltage) as an example. It should be understood that some or all transistors can also be replaced by N-type without changing the overall function of the circuit, and the effective signal corresponding to the replaced part or all transistors will be a relatively high level (for example, a positive signal with a predetermined amplitude voltage) signal.
  • the method shown in FIG. 2 may have additional steps, or each step in FIG. 2 may have further details.
  • FIG. 8( a ) is a flowchart illustrating sub-steps of the method shown in FIG. 2 .
  • the method for driving the gate drive circuit includes: step S1011, supplying power to the power supply terminal of the gate drive circuit (for example, providing a third power supply signal, the fourth power supply signal); step S1012, providing a clock signal to the gate driving circuit; and step S1013, providing an invalid first start signal to the gate driving circuit.
  • the pixel circuit includes a driving power supply terminal and a reference power supply terminal.
  • the method for driving the pixel circuit includes: step S1021, supplying power to the driving power terminal (for example, providing a first power signal and a second power signal); and step S1022, supplying power to the reference power terminal.
  • FIG. 8( b ) is a flowchart illustrating additional steps of the method shown in FIG. 2 .
  • the method for driving the display panel further includes: Step S104, driving the light emission control driving circuit during the first period of time.
  • the method for driving the light emission control driving circuit may include: Step S1041, supplying power to the power supply terminal of the light emission control driving circuit (for example, providing a third power signal, a fourth power signal) ; Step S1042, providing a clock signal to the light emission control driving circuit; and Step S1043, providing an invalid second startup signal to the light emission control driving circuit.
  • FIG. 8( c ) is a flowchart illustrating additional steps of the method shown in FIG. 2 .
  • the method for driving a display panel further includes: step S105 , causing the source driver circuit to provide a display data signal to the pixel circuit in a third time period.
  • the first activation signal and the second activation signal remain inactive.
  • the second enabling signal remains inactive until the first enabling signal of the gate driving circuit becomes active.
  • FIG. 8( d ) is an exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • the first time period may include at least the first frame 1st frame.
  • power is supplied to the power supply terminal of the gate driving circuit, and two supply voltages VH and VL are provided (for example, high level and low level can be provided respectively).
  • the clock signal GCLK provided by the gate driving circuit may represent the first clock signal GCK and the second clock signal GCB mentioned above.
  • An inactive first enable signal GSTV is provided to the gate drive circuit.
  • the first activation signal may remain inactive.
  • the second time period may include at least the second frame 2nd frame.
  • the first enable signal GSTV may remain inactive.
  • GOA supplies power to VH and VL. Except for the GOA input signal (STV, CLK) (ESTV, GSTV can be collectively referred to as STV; ECLK, GCLK can be collectively referred to as CLK) to determine the output high level or low level according to the specific GOA circuit design, other power supplies and signals on the panel maintain output
  • STV GOA input signal
  • CLK GOA input signal
  • ECLK, GCLK can be collectively referred to as CLK
  • GOA power on the power supply VH and VL of the gate drive circuit and/or light emission control drive circuit (hereinafter referred to as GOA), and use a frame Time to initialize the drive circuit;
  • 2GOA is a multi-level cascade architecture
  • the output of the previous stage is the input of the subsequent stage
  • the output status of each level after GOA is powered on is uncertain (possible output status: VH, VL or even a certain voltage between VH and VL)
  • the transistors in the pixel circuit may be in an undesired on state, such as powering on the pixel circuit-related power supplies (VREFN, ELVDD, ELVSS) without additional operations, and/or providing display data signals (Source), and different power supplies may form
  • VREFN, ELVDD, ELVSS pixel circuit-related power supplies
  • Source display data signals
  • different power supplies may form The path causes a short circuit. What's more, when current flows through the OLED device, there will be a momentary flickering phenomenon. Therefore, at the beginning of GOA power-on, it is necessary to determine the status of all levels of GOA; since all levels of GOA are cascaded connections, the operation of determining the output status of each level requires a
  • the multiplexing circuit may be kept on or switched normally (that is, the Mux outputs a low level or normally outputs an alternating high and low level).
  • the multiplexing circuit can also be kept turned on.
  • the signal output from the source driver circuit to the pixel circuit in this frame can be a grounded signal GND, and the switching signal Mux can output low level or normal output.
  • the P-type transistor as a switch it is turned on when the output is low, allowing the data signal to pass through.
  • Normal output refers to the output during normal display, same as 4th Frame. Mux outputs low level or normal output, so that the GND output by the source driver circuit (Source Driver) can reach the pixel circuit, and realize the purpose that as many lines in the panel as possible connected to the source driver circuit can be discharged to GND.
  • the first start signal GSTV and the second start ESTV output high level (inactive), the clock signal GCLK of the gate drive circuit and the clock signal ECLK of the luminescence control drive circuit (which can represent the above-mentioned third clock signal ECK, fourth clock signal ECB ) is the same as the clock signal input to the gate drive circuit (Gate GOA) and the light emission control drive circuit (EM GOA) during normal display.
  • GATE GOA gate drive circuit
  • EM GOA light emission control drive circuit
  • the second start signal ESTV of the light emission control driving signal and the clock signal ECLK maintain the state in the GOA initialization frame.
  • the first start signal GSTV and the clock signal GCLK of the gate driving signal maintain the state in the GOA initialization frame.
  • the voltage of the data signal Source and the state of the switching signal Mux in this frame may not be specified. If the power-on speed of some power supply is too slow (the power-on time is late or the rise time is long), the frame can be changed from one frame to multiple frames to wait for the power-on to complete.
  • the state of the gate of each transistor (eg, TFT) of the pixel circuit is determined, and the relevant power supply of the pixel circuit can be powered on.
  • the pixel power supply ELVDD, ELVSS, and VREFN are powered on (some pixel circuits are powered on together with the pixel power supply VREFP, etc.).
  • the source driver for providing display data can also start to work, but it does not necessarily provide the pixel circuit with a data signal for normal display.
  • the first start signal GSTV and the clock signal GCLK of the gate driving signal, the clock signal ECLK of the light emission control driving signal, the switching signal Mux and the data signal Source can be output normally.
  • the pixel circuit has not written a data signal in the last frame, so the light emission control EM of the pixel circuit cannot be pulled low (effective) at the beginning of this frame, otherwise flicker may occur. Therefore, the second starting signal ESTV of the light emission control driving signal needs to be kept at a high level (invalid) at the beginning of this frame until the second starting signal ESTV is pulled down in a display frame during normal display and then the second starting signal ESTV is activated. Signal ESTV pulled low. That is, during normal display, the second starting signal ESTV is at low level for two periods of time in one frame, and in this frame, the first period of low level of the second starting signal ESTV needs to be pulled high, and then pulled down for the second period of time.
  • the working state of the first starting signal GSTV in the GOA initialization frame can also be the same as the state of the normal display, that is, the same as the 4th frame (4th frame).
  • FIG. 9 is another exemplary timing diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • the first activation signal and the second activation signal remain inactive.
  • the second activation signal remains inactive.
  • a display data signal corresponding to displaying black is provided to the pixel circuit.
  • both the power-on of the OLED panel and the initialization frame of the GOA can be the same as those shown in Fig. 8(d).
  • the main difference from that shown in Figure 8 is that the first start signal GSTV of the gate drive circuit can be in the same state as in normal display, and has a stage of being pulled low (effective) . That is, it is possible to cause a display data signal to be written to the pixel circuit.
  • the written display data signal can be configured as a voltage that enables the thirteenth transistor T13 to be turned off (for example, corresponding to displaying black). It can also prevent screen flickering, circuit short circuit, etc.
  • the frame can be changed from one frame to multiple frames to wait for the power-on to complete.
  • the difference from Figure 8(d) is that since the pixel circuit has written display data (such as black) in the previous frame, at the beginning of this frame, the pixel
  • the writing control signal EM of the circuit can be normally pulled down (effective), that is, the second enable signal ESTV of the writing control driving circuit can also work normally.
  • the working state of the first start signal GSTV in the GOA initialization frame can also be the same as the state during normal display, that is, the same as the 4th frame (4th frame).
  • the clock signal GCLK of the gate drive circuit can work normally in this frame (same as the 4th frame (4th frame)), but it can also not work (for example, depending on the composition of the gate drive circuit, keep high level or low level).
  • FIG. 10 is an exemplary test signal waveform diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure.
  • FIG. 10 may correspond to the power-on sequence shown in FIG. 9 .
  • SPIMOSI in FIG. 10 corresponds to I/F.
  • the falling edge of TE indicates the beginning of a new frame, and the rising edge indicates the end of the previous frame.
  • SWIRE in FIG. 10 is a signal for providing the first driving power ELVDD and the second driving power ELVSS to the pixel circuit. Once SWIRE is pulled high, the first driving power ELVDD and the second driving power ELVSS start to supply power immediately.
  • the display data signal SRC (namely, source) may be coupled to an interference signal in the first frame (1st frame), resulting in voltage fluctuations (glitch), and if the display process is started directly at this time, it may cause The screen flickers, etc.
  • the gate driving circuit and the like are initialized, which can effectively avoid such a phenomenon.
  • the normal display process starts, and start signals such as ESTV can be output normally.
  • not supplying power to the pixel circuit may also refer to not fully supplying power to the pixel circuit, that is, partially supplying power.
  • the first reference power supply terminal VREFN can be already in the power-on state in the first frame 1st frame.
  • This setting of partial power supply can also play a certain role in avoiding flickering of the display screen or short circuit of the circuit caused by the unstable state of the internal circuit of the display panel.
  • the situation that no power is supplied to the pixel circuit in the first frame 1st frame will be a more preferred implementation manner.
  • FIG. 11 is a block diagram showing the structure of another exemplary OLED display panel.
  • the structure in Figure 11 can be used for LTPO (Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide) AMOLED panels.
  • LTPO Low Temperature Polycrystalline Oxide, low temperature polycrystalline oxide
  • the gate drive circuit (PGate GOA) is used to provide the required additional gate drive signal PGATE and reset signal PRST to the pixel circuit.
  • FIG. 12( a ) is a circuit diagram of an exemplary pixel unit in FIG. 11 .
  • FIG. 12( b ) is a timing diagram of an exemplary pixel unit in FIG. 12( a ).
  • the LTPO pixel circuit is shown in Figure 12(a).
  • the eleventh transistor T1 and the twelfth transistor T2 are replaced by N-channel transistors (for example, indium gallium zinc oxide thin film transistors, indium gallium zinc oxide thin film transistor, IGZO TFT), and these two TFTs are driven separately using an additional gate drive circuit (PGate GOA).
  • PGate GOA additional gate drive circuit
  • the required additional reset signal Preset is further provided.
  • the required additional gate driving signal PGate is further provided.
  • the remaining signals are the same as those in Figure 4(b).
  • FIG. 13( a ) is a circuit diagram of an exemplary additional gate drive circuit in FIG. 11 .
  • FIG. 13( b ) is a timing diagram of an exemplary additional gate drive circuit in FIG. 13( a ).
  • the shift register unit of such an additional gate drive circuit may include: the fifty-first transistor T51 to the sixty-third transistor T63, the fifty-first Capacitor C51 to fifty-third capacitor C53.
  • the control pole of the fifty-first transistor T51 is used to input the fifth clock signal GCK', the first pole is coupled to the second pole of the sixty-third transistor T63, and the second pole is coupled to the control pole of the fifty-second transistor T52 , and the first pole of the sixty-second transistor T62 is coupled.
  • the first pole of the fifty-second transistor T52 is used to input the fifth clock signal GCK'
  • the second pole is connected with the second pole of the fifty-third transistor T53
  • the control pole of the fifty-fifth transistor T55 the sixty-first The first pole of the transistor T61 is coupled.
  • the control electrode of the fifty-third transistor T53 is used for inputting the fifth clock signal GCK'
  • the first electrode is coupled to the power terminal for inputting the low level VL.
  • the control electrode of the fifty-fourth transistor T54 is coupled to the control electrode of the fifty-eighth transistor T58, the control electrode of the sixtieth transistor T60, and the second electrode of the sixty-second transistor T62, and the first electrode is used to input the second electrode of the sixth transistor T62.
  • the second pole of the sixth clock signal GCB' is coupled to the second pole of the fifty-fifth transistor T55.
  • a first pole of the fifty-fifth transistor T55 is coupled to a power supply terminal for inputting a high level VH.
  • the control pole of the fifty-sixth transistor T56 is coupled to the second pole of the sixty-first transistor T61, the first pole is used to input the sixth clock signal GCB', and the second pole is coupled to the gate of the fifty-seventh transistor T57 first pole.
  • the control electrode of the fifty-seventh transistor T57 is used to input the sixth clock signal GCB', and the second electrode is coupled to the first electrode of the fifty-eighth transistor T58 and the control electrode of the fifty-ninth transistor T59.
  • the second electrode of the fifty-eighth transistor T58 is used to input the sixth clock signal GCB'.
  • the first pole of the fifty-ninth transistor T59 is used to input the sixth clock signal GCB', the second pole is coupled to the first pole of the sixtieth transistor T60, and is used to output the auxiliary gate drive signal PGox(x can represent the number of rows).
  • the second pole of the sixtieth transistor T60 is coupled to a power terminal for inputting a low level VL.
  • the control electrode of the sixty-first transistor T61 is coupled to the power terminal for inputting the low level VL.
  • the control electrode of the sixty-second transistor T62 is coupled to the power terminal for inputting the low level VL.
  • the control electrode of the sixty-third transistor T63 is used to input the sixth clock signal GCB', and the first electrode is coupled to the auxiliary gate driving signal PGox-1 output from the previous row (x may represent the row number).
  • the fifty-first capacitor C51 is coupled between the control electrode and the second electrode of the fifty-sixth transistor T56.
  • the fifty-second capacitor C52 is coupled between the control electrode and the first electrode of the fifty-ninth transistor T59.
  • the fifty-third capacitor C53 is coupled between the control electrode and the second electrode of the fifty-fourth transistor T54.
  • FIG. 14 is an exemplary timing diagram corresponding to a method for powering on the OLED display panel in FIG. 11 according to an embodiment of the present disclosure.
  • the startup signal PGSTV and the clock signal PGCLK of the additional gate driving circuit can be inverted from the startup signal GSTV and the clock signal GCLK of the gate driving circuit respectively. That is, in each time period, when the activation signal GSTV of the gate driving circuit is active, the activation signal PGSTV of the additional gate driving circuit is also in an active state.
  • an improved power-on sequence is provided for the OLED display panel, which can avoid problems such as flickering of the display screen or circuit short circuit caused by unstable internal circuit state of the display panel during the power-on process.
  • problems such as flickering of the display screen or circuit short circuit caused by unstable internal circuit state of the display panel during the power-on process.
  • problems such as a splash screen at power-on and internal circuit short circuit can be avoided at the moment of power-on.

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Abstract

提供了一种用于驱动显示面板的方法。显示面板（1）包括像素电路、栅极驱动电路（2）、以及源极驱动电路（3）。用于驱动显示面板的方法可以包括：在第一时间段，向栅极驱动电路（2）和/或发光控制驱动电路（4）提供无效的启动信号；在第二时间段，对像素电路提供第一电源信号和第二电源信号；以及在第三时间段内，向栅极驱动电路（2）和/或发光控制驱动电路（4）提供有效的启动信号。对显示面板提供了改进的上电时序，可以在上电过程中避免由于显示面板内部电路状态不稳定而导致的显示画面闪烁，或者电路短路等问题。

Description

用于驱动显示面板的方法 技术领域
本公开的实施例一般涉及显示技术，尤其涉及一种用于驱动显示面板的方法。
背景技术
本部分仅仅用于提供背景技术以促进本公开的更好的理解。因此，本部分的陈述将从这个角度阅读并且不涉及什么在现有技术中或者什么不在现有技术中的承认。
图1是示出了示例性的OLED显示面板的结构的框图。
如图1所示，作为显示面板的非限制性示例，有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板可以包括像素电路1、栅极驱动电路2、以及源极驱动电路3。栅极驱动电路2、以及源极驱动电路3分别为像素电路1提供扫描信号、数据信号等。像素电路1可以包括阵列状的多个像素单元，其中每个像素单元可以包括OLED元件。
此外，作为可选的部分，根据像素电路的具体结构的不同，OLED面板还可能包括向像素电路1输出发光控制信号的发光控制驱动电路4。发光控制驱动电路4可以与栅极驱动电路2配合，以对于像素电路1进行驱动。
OLED面板相较于液晶显示器(Liquid Crystal Display，LCD)面板而言，使用了更多的薄膜晶体管(Thin-Film Transistor，TFT)，电路更为复杂。
更为复杂的电路可能会导致更多潜在的问题。例如，在对于OLED显示面板上电的过程中，像素电路中的各个晶体管可能会处于不稳定的状态而导致呈现闪烁的画面、和/或电路短路等问题。
发明内容
本发明内容对于本公开的方面进行了简要的描述，这些方面将在具体实施方式中进一步描述。本发明内容并不标识要求保护的主题的关键特征或基本特征，其也不限制要求保护的主题的范围。
本公开的一个目的在于提供改进的用于驱动显示面板的方法，以解决显示面板在上电的过程中可能出现的上述问题或者其它问题。
本公开的一个方面提供了一种用于驱动显示面板的方法。显示面板包括像素电路、栅极驱动电路、以及源极驱动电路。用于驱动显示面板的方法可以包括：在第一时间段，向栅极驱动电路和/或发光控制驱动电路提供无效的启动信号；以及在第二时间段，对像素电路提供第一电源信号和第二电源信号；以及在第三时间段内，向栅极驱动电路和/或发光控制驱动电路提供有效的启动信号。
在本公开的实施例中，在第一时间段，将像素电路的电源端接地。
在本公开的实施例中，在第一时间段，使源极驱动电路输出接地信号。
在本公开的实施例中，在第一时间段，驱动栅极驱动电路的方法包括：对栅极驱动电路提供第三电源信号、第四电源信号；对栅极驱动电路提供时钟信号；以及对栅极驱动电路提供无效的第一启动信号。
在本公开的实施例中，在第一时间段以及第二时间段，使第一启动信号保持无效。
在本公开的实施例中，用于驱动显示面板的方法还包括：在第三时间段，使源极驱动电路向像素电路提供显示数据信号。
在本公开的实施例中，显示面板还包括用于向像素电路输出发光控制信号的发光控制驱动电路。用于驱动显示面板的方法还包括：在第一时间段，驱动发光控制驱动电路。
在本公开的实施例中，在第一时间段，驱动发光控制驱动电路的方法包括：对发光控制驱动电路的电源端提供第三电源信号、第四电源信号；对发光控制驱动电路提供时钟信号；以及对发光控制驱动电路提供无效的第二启动信号。
在本公开的实施例中，用于驱动显示面板的方法，还包括：在第三时间段，使源极驱动电路向像素电路提供显示数据信号。在第一时间段以及第二时间段，对源极驱动电路提供的第一启动信号以及对发光控制驱动电路提供的第二启动信号保持无效。在第三时间段，第二启动信号在栅极驱动电路的第一启动信号变为有效之前保持无效。
在本公开的实施例中，在第一时间段，对源极驱动电路提供的第一启动信号以及对发光控制驱动电路提供的第二启动信号保持无效。在第二时间段，第二启动信号保持无效。
在本公开的实施例中，在第二时间段，对像素电路提供对应于显示黑色 的显示数据信号。
在本公开的实施例中，像素电路包括驱动电源端以及参考电源端。在第二时间段，驱动像素电路的方法包括：对驱动电源端提供第一电源信号、第二电源信号；以及对参考电源端供电。
在本公开的实施例中，第一时间段包括至少一个显示帧的持续时间，第二时间段包括至少一个显示帧的持续时间。
在本公开的实施例中，第一时间段与第二时间段不重叠。
在本公开的实施例中，显示面板还包括被设置在源极驱动电路和像素电路之间的复用电路。在使源极驱动电路输出接地信号的情况下，复用电路被导通。
本公开的另一个方面还提供了一种显示面板，配置为向像素电路提供上述实施例中任一项所述的显示面板驱动方法。
根据本公开的实施例，对显示面板提供了改进的上电时序，可以在上电过程中避免由于显示面板内部电路状态不稳定而导致的显示画面闪烁，或者电路短路等问题。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是示出了示例性的OLED显示面板的结构的框图。
图2是示出了根据本公开的实施例的用于驱动显示面板的方法的示例性的流程图。
图3是示出了另一个示例性的OLED显示面板的结构的框图。
图4(a)是一个示例性的像素单元的电路图。
图4(b)是示例性的图4(a)中的像素单元的时序图。
图5(a)是示例性的栅极驱动电路的电路图。
图5(b)是示例性的图5(a)中的栅极驱动电路的时序图。
图6(a)是示例性的发光控制驱动电路的电路图。
图6(b)是示例性的图6(a)中的发光控制驱动电路的时序图。
图7(a)是另一个示例性的像素单元的电路图。
图7(b)是示例性的图7(a)中的像素单元的时序图。
图8(a)是示出图2中所示的方法的子步骤的流程图。
图8(b)是示出图2中所示的方法的附加步骤的流程图。
图8(c)是示出图2中所示的方法的附加步骤的流程图。
图8(d)是对应于根据本公开的实施例的用于驱动显示面板的方法的一个示例性的时序图。
图9是对应于根据本公开的实施例的用于驱动显示面板的方法的另一个示例性的时序图。
图10是对应于根据本公开的实施例的用于驱动显示面板的方法的一个示例性的测试信号波形图。
图11是示出了另一个示例性的OLED显示面板的结构的框图。
图12(a)是示例性的图11中的像素单元的电路图。
图12(b)是示例性的图12(a)中的像素单元的时序图。
图13(a)是示例性的图11中的附加栅极驱动电路的电路图。
图13(b)是示例性的图13(a)中的附加栅极驱动电路的时序图。
图14是对应于根据本公开的实施例的用于对图11中的OLED显示面板上电的方法的示例性的时序图。
具体实施方式
为使本公开实施例的技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的耦接，而是可以包括电性的耦接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改 变后，则该相对位置关系也可能相应地改变。
图2是示出了根据本公开的实施例的用于驱动显示面板的方法的示例性的流程图。
本公开的实施例可以应用于如图1所示的OLED显示面板，以及其它任何合适的显示面板。因此，本公开的实施例也包含应用了该方法的这样的显示面板。
图2所示的用于驱动显示面板的方法可以包括：步骤S101，在第一时间段，向栅极驱动电路和/或发光控制驱动电路提供无效的启动信号；步骤S102，在第二时间段，对所述像素电路提供第一电源信号和第二电源信号；以及步骤S103，在第三时间段，向栅极驱动电路和/或发光控制驱动电路提供有效的启动信号。
根据本公开的实施例，在显示面板上电的过程中，在不同的时间段中进行栅极驱动电路的驱动、像素电路的供电、显示数据的提供等操作。通过这样的方式，可以防止像素电路中的晶体管状态不稳定时被驱动，进而有效防止显示画面闪烁，或者电路短路等问题。
在完成上述上电过程之后，显示面板就可以进入正常的显示过程。即，在正常的显示过程中，栅极驱动电路周期性地(例如，以显示帧为周期)驱动像素电路(按照预定时序使得像素电路中的晶体管导通或者截止)，源极驱动器周期性地向像素电路提供显示数据，使得像素电路中的OLED对应于每一显示帧的显示数据而操作(例如，以相应的亮度发光)，从而OLED显示面板能够显示每一帧的图像画面。
在本公开的实施例中，在第一时间段，可以将像素电路中的电源端接地。根据这样的方式，可以使得像素电路中的晶体管更可靠地处于截止状态，提高上电过程中的抗干扰的能力，有效防止显示画面闪烁，或者电路短路等问题。
在本公开的实施例中，在第一时间段，可以使源极驱动电路输出接地信号。根据这样的方式，像素电路接收到接地信号以代替显示数据信号，这可以进一步防止上电过程中的干扰信号被作为显示数据输入到像素电路，可以有效防止显示画面闪烁，或者电路短路等问题。
在本公开的实施例中，第一时间段与第二时间段不重叠。根据这样的方式，可以确保栅极驱动电路完成初始化之后(即，可以完全按照预定显示用 时序对于像素电路进行驱动之后)，再对于像素电路提供供电和/或提供显示数据。这可以更有效防止显示画面闪烁，或者电路短路等问题。
在本公开的实施例中，第一时间段包括至少一个显示帧的持续时间，第二时间段包括至少一个显示帧的持续时间。考虑到电源等各个电路模块都可能需要一段时间以进入稳定状态，根据这样的方式，可以确保上电过程完成后各个电路模块都进入了稳定的工作状态，而避免画面闪烁，或者电路短路等问题。
以下，将结合示例性的OLED显示面板的示例性的电路结构，对于本公开的实施例所述的用于驱动显示面板的方法进行进一步的说明。应当理解，下列电路结构仅仅是示例性的，而不是对于本公开的实施例所述的方法。本公开的实施例所述的用于驱动显示面板的方法可以应用于下列电路结构的变换和改进。
图3是示出了另一个示例性的OLED显示面板的结构的框图。
如图3所示，像素电路1包括阵列状的多个像素单元，可以记为第1行(Line[1])至第y行(Line[y])，第1列(Row[1])至第x列(Row[x])。x，y为正整数。
OLED显示面板可以使用所谓的行扫描工作模式。在一个显示帧中，栅极驱动电路2、发光控制驱动电路4依次扫描每一行像素单元，并且相应地源极驱动电路3依次向被扫描的每一行像素单元提供数据信号。
例如，以扫描第1行(Line[1])像素单元为例，栅极驱动电路2首先输出有效的复位信号(RST[1])，以使得第1行(Line[1])的像素单元都被复位。然后，栅极驱动电路2输出有效的栅极驱动信号(GATE[1])，使得源极驱动电路3提供的数据信号可以被写入第1行(Line[1])的像素单元。该有效的栅极驱动信号(GATE[1])同时可以作为第2行(Line[2])的像素单元的复位信号(RST[2])。然后，发光控制驱动电路4输出有效的发光控制信号(EM[1])，使得第1行(Line[1])的像素单元中的OLED对应于各自的显示数据而工作(例如，产生各自相应的亮度)。该显示状态可以持续到该显示帧的结束。
第2行(Line[2])像素单元直到第y行(Line[y])像素单元都将以同样的方式完成扫描。
应当理解，“有效”的信号是指可以使得后续的电路元件(例如晶体管) 进入工作状态(例如导通)的信号。因此，对应于后续电路元件的不同，该“有效”的信号的具体属性(例如，幅值)可以不同。例如，对于N型晶体管，有效的信号可以是为相对高电平的电压信号。而对于P型晶体管，有效的信号可以是相对低电平的电压信号。相应地，“无效”的信号是指不能使得后续的电路元件(例如晶体管)进入工作状态(例如导通)的信号，也就是说，将使得后续的电路元件(例如晶体管)保持截止。
此外，在本公开的实施例中，OLED显示面板还包括被设置在源极驱动电路和像素电路之间的复用电路。源极驱动电路3的输出可以耦接到复用电路31。在切换信号的控制下，源极驱动器3提供的显示数据可以经由复用电路分别提供到不同列的像素单元。例如，如图3所示，可以在切换信号MUX1，MUX2的控制下，分别向奇数列、偶数列提供显示数据的信号。MUX1有效时，可以使得复用电路31中的与奇数列的像素单元对应的开关元件导通，从而源极驱动电路3的输出被传输到奇数列的像素单元。而MUX2有效时，可以使得复用电路31中的与偶数列的像素单元对应的开关元件导通，从而源极驱动电路3的输出被传输到偶数列的像素单元。如此，可以实现源极驱动电路3的复用，减少了源极驱动电路3中所需要的电路元件并相应降低占用面积、成本等。
此外，在工作期间，切换信号MUX1，MUX2可以具有完全相反的波形，即同一时刻要么向奇数列提供，要么向偶数列提供，以实现源极驱动电路3的输出的复用。因此，在之后的描述中，也可以仅仅使用MUX来表示这样具有固定波形关系的多个切换信号。
作为非限制性的示例，图3中的OLED显示面板可以是例如AMOLED(Active-matrix organic light-emitting diode，主动矩阵有机发光二极体)面板，具体可以是LTPS(Low Temperature Poly-Silicon，低温多晶硅)AMOLED显示面板。根据图3的结构，可以具有以下特点：①使用类似移位寄存器的栅极驱动电路(Gate Driver on Array，GOA)来驱动像素的复位Reset、栅极Gate和发光控制EM信号。②采用源级复用电路(Mux1和Mux2驱动的开关元件(例如，薄膜晶体管)为P沟道)，部分型号面板也可以没有Mux电路。
图4(a)是一个示例性的像素单元的电路图。图4(b)是示例性的图4(a)中的像素单元的时序图。
图4(a)所示的像素单元可以包括第十一晶体管T11～第十七晶体管T17、第十一电容C11。此外，以该像素单元位于第N行进行说明。
第十一晶体管T11的控制极被用于输入复位信号Reset(N)，第一极耦接到第一参考电源端VREFN(也可以被称为初始化电源端，并且可以是低电平)，第二极与第十三晶体管T13的控制极、第十二晶体管T12的第一极耦接。第十二晶体管T12的控制极被用于输入栅极驱动信号Gate，第二极与第十三晶体管T13的第二极、第十六晶体管T16的第一极耦接。第十三晶体管T13的第一极与第十四晶体管T14的第一极、第十五晶体管T15的第二极耦接。第十四晶体管T14的控制极被用于输入栅极驱动信号Gate，第二极被用于输入显示数据信号Vdata。第十五晶体管T15的控制极被用于输入发光控制信号EM，第一极耦接到用于输入第一驱动电源ELVDD(即，作为第一电源信号而被提供)的电源端(可以输入高电平)。第十六晶体管T16的控制极被用于输入发光控制信号EM，第二极与OLED的第一极(可以是阳极)耦接。第十七晶体管T17的控制极被用于输入下一行的像素电路的复位信号Reset(N+1)(可以与栅极驱动信号Gate相同)，第一极耦接到第一参考电源端VREFN，第二极与OLED的第一极耦接。OLED的第二极(可以是阴极)与用于输入第二驱动电源ELVSS(即，作为第二电源信号而被提供)的电源端(可以输入低电平)耦接。第十一电容C11的第一端耦接到用于输入第一驱动电源ELVDD的电源端，第二端与第十三晶体管T13的控制极耦接。
晶体管的控制极可以是栅极，第一极可以是源极或者漏极中的任一个，而第二极可以是源极或者漏极中的另一个。此外，不同晶体管的第一极可以是不同的类型，第二极可以是不同的类型。
如图4(b)所示，在时间段t1，t2，发光控制信号保持无效(无效是指该信号不能使晶体管导通，或者说是使得晶体管截止)。在时间段t1，复位信号Reset(N)有效(有效是指该信号能够使晶体管导通)，使得相应像素电路中相应节点的电压被复位，或者被初始化，或者被设置为参考电压。在时间段t2，栅极驱动信号Gate有效，使得数据信号Data(即Vdata)被写入。在时间段t3之后，发光控制信号有效，复位信号Reset(N)、栅极驱动信号Gate无效。OLED对应于数据信号Data而工作(例如，以预定的亮度发光)。
如图4(b)所示，发光控制信号EM高电平持续时间大于图中所示的时 间段2H且包裹住时间段t1和t2内的复位信号Reset和栅极驱动信号Gate的低电平。
应当理解，该复位信号Reset(N)可以是上一行的栅极驱动信号Gate(N-1)。
图5(a)是示例性的栅极驱动电路的电路图。图5(b)是示例性的图5(a)中的栅极驱动电路的时序图。
栅极驱动电路可以由图5(a)中所示的移位寄存器单元逐级串联组成。即，栅极驱动电路采用移位寄存器的方式工作，各级的移位寄存器单元依次向像素电路输出上述的复位信号、栅极驱动信号(也可以统称为行扫描信号)。
如图5(a)所示，作为一个非限制性的示例，这样的移位寄存器单元可以包括：第二十一晶体管T21～第二十八晶体管T28、第二十一电容C21～第二十二电容C22。
第二十一晶体管T21的控制极被用于输入第一时钟信号GCK，第一极被用于输入第一启动信号GSTV，第二极与第二十二晶体管T22的控制极、第二十七晶体管T27的第二极、第二十八晶体管T28的第一极耦接。第二十二晶体管T22的第一极被用于输入第一时钟信号GCK，第二极与第二十三晶体管T23的第二极、第二十四晶体管T24的控制极、第二十六晶体管T26的控制极耦接。第二十三晶体管T23的控制极被用于输入第一时钟信号GCK，第一极耦接到用于输入低电平VL(即，作为第四电源信号而被提供)的电源端。第二十四晶体管T24的第一极耦接到用于输入高电平VH(即，作为第三电源信号而被提供)的电源端，第二极与第二十五晶体管T25的第一极耦接，且用于输出栅极驱动信号GO。第二十五晶体管T25的控制极与第二十八晶体管T28的第二极耦接，第二极被用于输入第二时钟信号GCB。第二十六晶体管T26的第一极耦接到用于输入高电平VH的电源端，第二极与第二十七晶体管T27的第一极耦接。第二十七晶体管T27的控制极被用于输入第二时钟信号GCB。第二十八晶体管T28的控制极耦接到用于输入低电平VL的电源端。
第二十一电容C21耦接在第二十四晶体管T24的控制极和第一极之间。第二十二电容C22耦接在第二十五晶体管T25的控制极和第一极之间。
例如，高电平VH可以是预定幅值的正电压，低电平VL可以是预定幅值的负电压。
如图5(b)所示，以该移位寄存器单元位于第一级(例如，对应于第一行像素单元)为例，在时间段t1，第一启动信号GSTV有效，使得对应于第一行像素单元的移位寄存器单元开始工作。第一启动信号GSTV、以及第一时钟信号GCK、第二时钟信号GCB的状态按照预定时序改变，使得在时间段t2，对于第一行像素单元输出有效的栅极驱动信号GO1。该栅极驱动信号GO1同时作为(例如，对应于第二行像素单元的)下一级移位寄存器单元的启动信号，使得下一级移位寄存器单元在时间段t3输出有效的栅极驱动信号GO2，以用于下一行的像素单元。以此类推，各级的移位寄存器单元依次工作，完成所有行的栅极驱动信号的输出。
相邻两行的移位寄存器单元的电路结构是完全相同，且所有级可以共用两个时钟信号GCK和GCB。
图6(a)是示例性的发光控制驱动电路的电路图。图6(b)是示例性的图6(a)中的发光控制驱动电路的时序图。
与栅极驱动电路类似地，发光控制驱动电路可以由图6(a)中所示的移位寄存器单元逐级串联组成。即，发光控制驱动电路也采用移位寄存器的方式工作，各级的移位寄存器单元依次向像素电路输出上述的发光控制信号(也可以属于行扫描信号)。
如图6(a)所示，作为一个非限制性的示例，这样的移位寄存器单元可以主要包括：第三十一晶体管T31～第三十八晶体管T38、第三十一电容C31～第三十三电容C33。
第三十一晶体管T1的控制极被用于输入第三时钟信号ECK，第一极被用于输入第二启动信号ESTV，第二极与第三十三晶体管T33的控制极、第三十五晶体管T35的控制极、第三十八晶体管T38的控制极耦接。第三十二晶体管T32的控制极被用于输入第三时钟信号ECK，第一极耦接到用于输入低电平VL的电源端，第二极与第三十三晶体管T33的第二极、第三十六晶体管T36的控制极耦接。第三十三晶体管T33的第一极被用于输入第三时钟信号ECK。第三十四晶体管T34的控制极与第三十七晶体管T37的第二极、第三十八晶体管T38的第二极耦接，第一极耦接到用于输入高电平VH的电源端，第二极与第三十五晶体管T35的第一极耦接，且用于输出发光控制信号EM。第三十五晶体管T35的第二极耦接到用于输入低电平VL的电源端。第三十六晶体管T36的第一极耦接到用于输入低电平VL的电源端， 第二极与第三十七晶体管T37的第一极耦接。第三十七晶体管T37的控制极被用于输入第四时钟信号ECB。第三十八晶体管T38的第一极耦接到用于输入高电平VH的电源端。
第三十一电容C31的第一端耦接到第三十五晶体管T35的控制极，第二端用于输入第四时钟信号ECB。第三十二电容C32耦接在第三十四晶体管T34的控制极和第一极之间。第三十三电容C33的第一端耦接到第三十六晶体管T36的控制极，第二端用于输入第四时钟信号ECB。
如图6(b)所示，以该移位寄存器单元位于第一级(例如，对应于第一行像素单元)为例，首先，第二启动信号ESTV无效，使得对应于第一行像素单元的移位寄存器单元输出无效的发光控制信号。第一启动信号GSTV在之后改变为有效，并且第三时钟信号ECK、第四时钟信号ECB的状态按照预定时序改变，使得对于第一行像素单元输出持续有效的发光控制信号EO1。该发光控制信号EO1同时作为(例如对应于第二行像素单元的)下一级移位寄存器单元的启动信号，使得下一级移位寄存器单元在之后输出有效的发光控制信号EO2，以用于下一行的像素单元。以此类推，各级的移位寄存器单元依次工作，完成所有行的发光控制信号的输出。
上述图4(a)、图5(a)、图6(a)中所示出的电路可以相互配合工作。然而，应当理解，其中的任意一个或者多个电路都可以被其它的结构的具有相同功能的电路替换。
图7(a)是另一个示例性的像素单元的电路图。图7(b)是示例性的图7(a)中的像素单元的时序图。
图7(a)所示的像素单元可以包括第四十一晶体管T41～第四十七晶体管T47、第四十一电容C41。此外，也以该像素单元位于第N行进行说明。
第四十一晶体管T41的控制极被用于输入复位信号Reset(N)，第一极耦接到第一参考电源端VREFN，第二极耦接到第四十二晶体管T42的第一极、第四十三晶体管T43的控制极。第四十二晶体管T42的控制极被用于输入栅极驱动信号Gate，第二极耦接到第四十三晶体管T43的第二极、第四十六晶体管T46的第一极。第四十三晶体管T43的第一极耦接到第四十七晶体管T47的第二极、以及用于输入第一驱动电源ELVDD的电源端。第四十四晶体管T44的控制极被用于输入栅极驱动信号Gate，第一极被用于输入显示数据信号Vdata，第二极耦接到第四十五晶体管T45的第一极以及第四十 七晶体管T47的第一极。第四十五晶体管T45的控制极被用于输入发光控制信号EM，第二极耦接到第二参考电源端VREFP(也可以被称为初始化电源端，并且可以是输入高电平)。第四十六晶体管T46的控制极被用于输入发光控制信号EM，第二极与OLED的第一极耦接。第四十七晶体管T47的控制极被用于输入复位信号Reset(N)。OLED的第二极(可以是阴极)与用于输入第二驱动电源ELVSS的电源端(可以输入低电平)耦接。第四十一电容C41的第一端耦接到第四十四晶体管T44的第二极，第二端与第四十一晶体管T41的第二极耦接。
图7(b)的工作时序可以和图4(b)完全相同，省略其描述。
以上，以所有晶体管都为P型(或者称为P沟道)晶体管，相对应的有效信号为相对低的电平(例如，0V或者负电压)的信号为例进行说明。应当理解，部分或者全部晶体管也可以被替换为N型而不改变电路的整体功能，被替换的这一部分或者全部晶体管对应的有效信号将为相对高的电平(例如，具有预定幅值的正电压)的信号。
根据所应用的OLED面板的具体结构，图2所示的方法可以具有附加的步骤，或者图2中的各个步骤可以具有进一步的细节。
图8(a)是示出图2中所示的方法的子步骤的流程图。
如图8(a)所示，在本公开的实施例中，在第一时间段，驱动栅极驱动电路的方法包括：步骤S1011，对栅极驱动电路的电源端供电(例如，提供第三电源信号、第四电源信号)；步骤S1012，对栅极驱动电路提供时钟信号；以及步骤S1013，对栅极驱动电路提供无效的第一启动信号。
在本公开的实施例中，像素电路包括驱动电源端以及参考电源端。在第二时间段，驱动像素电路的方法包括：步骤S1021，对驱动电源端供电(例如，提供第一电源信号、第二电源信号)；以及步骤S1022，对参考电源端供电。
图8(b)是示出图2中所示的方法的附加步骤的流程图。
如图8(b)所示，在本公开的实施例中，在显示面板还包括用于向像素电路输出发光控制信号的发光控制驱动电路的情况下，用于驱动显示面板的方法还包括：步骤S104，在第一时间段，驱动发光控制驱动电路。
在本公开的实施例中，在第一时间段，驱动发光控制驱动电路的方法可以包括：步骤S1041，对发光控制驱动电路的电源端供电(例如，提供第三 电源信号、第四电源信号)；步骤S1042，对发光控制驱动电路提供时钟信号；以及步骤S1043，对发光控制驱动电路提供无效的第二启动信号。
图8(c)是示出图2中所示的方法的附加步骤的流程图。
在本公开的实施例中，用于驱动显示面板的方法，还包括：步骤S105，在第三时间段，使源极驱动电路向像素电路提供显示数据信号。在第一时间段以及第二时间段，第一启动信号以及第二启动信号保持无效。在第三时间段，第二启动信号在栅极驱动电路的第一启动信号变为有效之前保持无效。
图8(d)是对应于根据本公开的实施例的用于驱动显示面板的方法的一个示例性的时序图。
如图8(d)所示，第一时间段可以至少包括第一帧1st frame。在该第一帧中，对栅极驱动电路的电源端开始供电，提供了两路供电电压VH和VL(例如，可以分别提供高电平，和低电平)。对于栅极驱动电路提供时钟信号GCLK，可以代表上述的第一时钟信号GCK以及第二时钟信号GCB。对栅极驱动电路提供无效的第一启动信号GSTV。
在本公开的实施例中，在第一时间段以及第二时间段，可以使第一启动信号保持无效。
如图8(d)所示，第二时间段可以至少包括第二帧2nd frame。在该第一帧和第二帧中，第一启动信号GSTV都可以保持无效。
具体而言，如图8(d)所示，从OLED面板开机直到显示可以大致分为以下阶段。
1.OLED面板经由接口(I/F)收到开始显示(Display on)的指令后，GOA供电VH和VL上电。除GOA输入信号(STV、CLK)(ESTV、GSTV可以统称为STV；ECLK、GCLK可以统称为CLK)根据具体GOA电路设计确定输出高电平或者低电平外，面板其他电源和信号均维持输出GND状态，防止在上电过程中像素电路可能形成的短路回路中出现电流；
2.进入上述上电方法中的第一时间段中的GOA初始化帧，栅极驱动电路、和/或发光控制驱动电路(以下，简称为GOA)的电源VH和VL上电，并使用一帧时间对驱动电路初始化；
①像素电路中除图4(a)、图7(a)所示的T3外，各个晶体管的栅极控制均需要由GOA来完成，故面板上电需要首先对GOA操作；
②GOA为多级级联架构，前级的输出为后级的输入，GOA上电后各级 输出状态不确定(可能输出状态：VH、VL甚至是VH与VL之间的某一电压)，造成像素电路中的晶体管可能处于不期望的开启状态，如不做额外操作就对像素电路相关电源(VREFN、ELVDD、ELVSS)上电，和/或提供显示数据信号(Source)，不同电源间可能形成通路造成短路。更甚，如此时有电流流过OLED器件，会出现瞬间闪屏现象。故GOA上电之初需要将GOA各级状态确定下来；由于GOA各级为级联连接，完成确定各级输出状态的操作需要一帧画面的刷新周期。
在本公开的实施例中，在第一时间段，复用电路可以保持导通或者正常切换(即，Mux输出低电平或者正常输出交替变化的高低电平)。或者，在源极驱动电路输出接地信号时，复用电路也可以保持被导通。
在该GOA初始化帧中，此帧中由源极驱动电路向像素电路输出的信号可以是接地的信号GND，切换信号Mux输出低电平或正常输出均可。对应于P型晶体管作为开关，那么输出低电平的时候为导通，允许数据信号通过。正常输出(toggle)指正常显示时的输出，同4th Frame。Mux输出低电平或正常输出，使得源极驱动电路(Source Driver)输出的GND均可达到像素电路，实现面板中可尽可能多的线路与源极驱动电路相连部分泄放到GND的目的，此时ELVDD、ELVSS、VREFP、VREFN电压也均为GND，故像素电路内绝大部分均为GND，无法在像素电路内形成不可控的电流。此时，输出低电平时更优，可以使GND由源极驱动电路灌入面板，防止闪烁。第一启动信号GSTV和第二启动ESTV输出高电平(无效)，栅极驱动电路的时钟信号GCLK和发光控制驱动电路的时钟信号ECLK(可以代表上述第三时钟信号ECK，第四时钟信号ECB)与正常显示时输入栅极驱动电路(Gate GOA)和发光控制驱动电路(EM GOA)的时钟信号相同。此帧完成后，例如图4(a)中的像素电路的TFT除第十三晶体管T13外，所有TFT的栅极状态均为高电平状态(无效)，TFT进入截止状态。
3.进入上述上电方法中的第二时间段中的像素电源上电帧，发光控制驱动信号的第二启动信号ESTV和时钟信号ECLK维持GOA初始化帧中的状态。栅极驱动信号的第一启动信号GSTV和时钟信号GCLK维持GOA初始化帧中的状态。此帧中，由于像素电路没有处于写入数据的状态，此帧数据信号Source的电压和切换信号Mux的状态可以不做规定。如有电源上电速度过慢(上电时间晚或上升时间长)，该帧可由一帧变为多帧，以等待上电完 成。
此时像素电路各个晶体管(例如，TFT)栅极状态确定，像素电路相关电源可以上电。像素电源ELVDD、ELVSS、VREFN上电(有些像素电路还有像素电源VREFP等一并上电)。用于提供显示数据的源极驱动器(以Source表示其输出)也可以开始工作，但并不一定向像素电路提供用于正常显示的数据信号。
4.进入开始显示帧，面板由此帧开始显示。栅极驱动信号的第一启动信号GSTV和时钟信号GCLK、发光控制驱动信号的时钟信号ECLK、切换信号Mux和数据信号Source可以正常输出。
此外，像素电路在上一帧中还未写入数据信号，因此，在此帧开始时像素电路的发光控制EM不能拉低(有效)，否则可能出现闪烁。故发光控制驱动信号的第二启动信号ESTV在此帧开始时，需要保持高电平(无效)，直至第二启动信号ESTV在正常显示时一显示帧内被拉低的位置再将第二启动信号ESTV拉低。即正常显示时，第二启动信号ESTV在一帧内有两段时间为低电平，而在此帧第二启动信号ESTV第一段低电平需要拉高，第二段时间内拉低。
5.上电完成之后，面板正常显示。
此外，由于第一启动信号GSTV低电平宽度很窄，如果栅极驱动电路的第一启动信号GSTV和时钟信号GCLK正常工作，则在一个显示帧的显示画面结束时，面板内所有行的栅极驱动信号Gate均为高电平(同第一启动信号GSTV始终拉高、时钟信号GCLK正常工作方式下一帧画面结束时面板内所有行栅极驱动信号Gate的状态)。故在GOA初始化帧中第一启动信号GSTV的工作状态也可以与正常显示时的状态相同，即与第4帧(4th frame)等相同。
图9是对应于根据本公开的实施例的用于驱动显示面板的方法的另一个示例性的时序图。
在本公开的实施例中，在第一时间段，第一启动信号以及第二启动信号保持无效。在第二时间段，第二启动信号保持无效。
在本公开的实施例中，在第二时间段，对像素电路提供对应于显示黑色的显示数据信号。
如图9所示，OLED面板开机以及GOA初始化帧都可以与图8(d)所 示相同。
在像素电源上电帧(2nd frame)中，与图8所示不同之处主要在于，栅极驱动电路的第一启动信号GSTV可以与正常显示时状态相同，具有被拉低(有效)的阶段。也就是说，可以使得显示数据信号被写入到像素电路。
相对应地，考虑到上电过程中像素电路各供电电压情况，被写入的显示数据信号可以被配置为可使得第十三晶体管T13关闭的电压(例如，对应于显示黑色)。同样可以防止画面闪烁、电路短路等。
如有电源上电速度过慢(上电时间晚或上升时间长)，该帧可由一帧变为多帧，以等待上电完成。
此外，在进入显示帧开始，即第三帧(3rd frame)，与图8(d)不同的是，由于像素电路在上一帧已写入显示数据(例如黑色)，在此帧开始时像素电路的写入控制信号EM就可以正常地被拉低(有效)，即写入控制驱动电路的第二启动信号ESTV也可以正常工作。
此外，与图8(d)相同地，在GOA初始化帧中第一启动信号GSTV的工作状态也可以与正常显示时的状态相同，即与第4帧(4th frame)等相同。
此外，由于像素电源上电帧(2nd Frame)中，栅极驱动电路的第一启动信号GSTV存在拉低的情况，显示数据信号Source的电压会被写入，并且强制要求写入黑数据。因此，栅极驱动电路的时钟信号GCLK在此帧即可正常工作(同第4帧(4th frame))，但是也可以不工作(例如，根据不同的栅极驱动电路组成，保持高电平或低电平)。
图10是对应于根据本公开的实施例的用于驱动显示面板的方法的一个示例性的测试信号波形图。
具体而言，图10可以对应于图9所示的上电时序。在图10中的SPIMOSI对应于I/F。TE的下降沿表示新一帧的开始，上升沿表示上一帧的结束。在图10中的SWIRE是用于向像素电路的提供第一驱动电源ELVDD，第二驱动电源ELVSS的信号，一旦SWIRE拉高后，第一驱动电源ELVDD，第二驱动电源ELVSS立即开始供电。
在图10中可以看出，显示数据信号SRC(即，source)在第一帧(1st frame)中可能会耦合到干扰信号，产生电压波动(毛刺)，此时如果直接开始显示过程，可能使得画面出现闪烁等现象。根据本公开的实施例，在第一帧(1st frame)中，不进行显示，而是对于栅极驱动电路等进行初始化，可 以有效避免这样的现象产生。
在初始化以及上电等过程都完成后，例如，图10中的第四帧(4th frame)，开始正常的显示过程，ESTV等启动信号可以正常输出。
此外，考虑到实际应用环境和需求，在本公开中所述的“不对像素电路供电”也可以指不对像素电路完全供电的情况，即，可以部分供电。例如，在图10中，由于测试对象中的芯片等的实际应用情况，可以使得第一参考电源端VREFN在第一帧1st frame中已经处于上电的状态。在避免由于显示面板内部电路状态不稳定而导致的显示画面闪烁，或者电路短路等方面，这种部分供电的设置同样可以起到一定的作用。当然，第一帧1st frame中完全不对像素电路供电的情况将是更优选的实施方式。
图11是示出了另一个示例性的OLED显示面板的结构的框图。
图11中的结构可以用于LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)AMOLED面板。相较图3所示的LTPS AMOLED面板而言，多出一个附加栅极驱动电路(PGate GOA)。该栅极驱动电路(PGate GOA)用于向像素电路提供所需要的附加的栅极驱动信号PGATE、复位信号PRST。
图12(a)是示例性的图11中的像素单元的电路图。图12(b)是示例性的图12(a)中的像素单元的时序图。
LTPO像素电路如图12(a)，相较图4，第十一晶体管T1和第十二晶体管T2被替换为N沟道晶体管(例如，铟镓锌氧化物薄膜晶体管，indium gallium zinc oxide thin film transistor，IGZO TFT)，并且这两个TFT单独使用附加栅极驱动电路(PGate GOA)驱动。
具体而言，图12(b)中，在时间段T1，进一步提供了所需要的附加复位信号Preset。在时间段T2，进一步提供了所需要的附加的栅极驱动信号PGate。其余信号与图4(b)中的信号时序相同。
图13(a)是示例性的图11中的附加栅极驱动电路的电路图。图13(b)是示例性的图13(a)中的附加栅极驱动电路的时序图。
如图13(a)所示，作为一个非限制性的示例，这样的附加栅极驱动电路的移位寄存器单元可以包括：第五十一晶体管T51～第六十三晶体管T63、第五十一电容C51～第五十三电容C53。第五十一晶体管T51的控制极被用于输入第五时钟信号GCK’，第一极与第六十三晶体管T63的第二极耦接，第二极与第五十二晶体管T52的控制极、第六十二晶体管T62的第一极耦 接。第五十二晶体管T52的第一极被用于输入第五时钟信号GCK’，第二极与第五十三晶体管T53的第二极、第五十五晶体管T55的控制极、第六十一晶体管T61的第一极耦接。第五十三晶体管T53的控制极被用于输入第五时钟信号GCK’，第一极耦接到用于输入低电平VL的电源端。第五十四晶体管T54的控制极与第五十八晶体管T58的控制极、第六十晶体管T60的控制极、第六十二晶体管T62的第二极耦接，第一极被用于输入第六时钟信号GCB’，第二极与第五十五晶体管T55的第二极耦接。第五十五晶体管T55的第一极耦接到用于输入高电平VH的电源端。第五十六晶体管T56的控制极耦接到第六十一晶体管T61的第二极，第一极被用于输入第六时钟信号GCB’，第二极耦接到第五十七晶体管T57的第一极。第五十七晶体管T57的控制极被用于输入第六时钟信号GCB’，第二极耦接到第五十八晶体管T58的第一极、第五十九晶体管T59的控制极。第五十八晶体管T58的第二极被用于输入第六时钟信号GCB’。第五十九晶体管T59的第一极被用于输入第六时钟信号GCB’，第二极与第六十晶体管T60的第一极耦接，且被用于输出辅助栅极驱动信号PGox(x可以表示行数)。第六十晶体管T60的第二极耦接到用于输入低电平VL的电源端。第六十一晶体管T61的控制极耦接到用于输入低电平VL的电源端。第六十二晶体管T62的控制极耦接到用于输入低电平VL的电源端。第六十三晶体管T63的控制极被用于输入第六时钟信号GCB’，第一极耦接到上一行输出的辅助栅极驱动信号PGox-1(x可以表示行数)。
第五十一电容C51耦接在第五十六晶体管T56的控制极和第二极之间。第五十二电容C52耦接在第五十九晶体管T59的控制极和第一极之间。第五十三电容C53耦接在第五十四晶体管T54的控制极和第二极之间。
图13(b)的时序与图5(b)相比较，其区别在于图13(b)中的附加栅极驱动电路的启动信号PGSTV、附加栅极驱动信号PGO(包括第一行的PGO1，第二行的PGO2)均为高电平有效。此外，图13(b)中的第五时钟信号GCK’、第六时钟信号GCB’的电平相对应进行调整。
图14是对应于根据本公开的实施例的用于对图11中的OLED显示面板上电的方法的示例性的时序图。
如图14所示，除了像素电路中的第十一晶体管T1和第十二晶体管T2的驱动信号极性变化而需要提供附加栅极驱动电路的启动信号PGSTV、时 钟信号PGCLK之外，与图9所示的时序没有其它区别。此外，附加栅极驱动电路的启动信号PGSTV、时钟信号PGCLK可以分别与栅极驱动电路的启动信号GSTV、时钟信号GCLK反向。也就是说，在各个时间段中，在栅极驱动电路的启动信号GSTV有效时，附加栅极驱动电路的启动信号PGSTV也为有效状态。
根据本公开的实施例，对OLED显示面板提供了改进的上电时序，可以在上电过程中避免由于显示面板内部电路状态不稳定而导致的显示画面闪烁，或者电路短路等问题。尤其是可在短时间(例如，两帧)完成面板上电的情况下，避免上电瞬间出现开机闪屏和内部电路短路等问题。
应当理解，以上仅为本公开的示例性的具体实施方式，本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种用于驱动显示面板的方法，其中，所述显示面板包括像素电路、栅极驱动电路、以及源极驱动电路，所述方法包括：
    在第一时间段，向所述栅极驱动电路和/或发光控制驱动电路提供无效的启动信号；
    在第二时间段，对所述像素电路提供第一电源信号和第二电源信号；以及
    在第三时间段内，向所述栅极驱动电路和/或发光控制驱动电路提供有效的启动信号。
  2. 根据权利要求1所述的用于驱动显示面板的方法，其中，在所述第一时间段，将所述像素电路的电源端接地。
  3. 根据权利要求1至2中任一项所述的用于驱动显示面板的方法，其中，在所述第一时间段，使所述源极驱动电路输出接地信号。
  4. 根据权利要求1至3中任一项所述的用于驱动显示面板的方法，其中，在所述第一时间段，驱动所述栅极驱动电路的方法包括：
    对所述栅极驱动电路的电源端提供第三电源信号、第四电源信号；
    对所述栅极驱动电路提供时钟信号；以及
    对所述栅极驱动电路提供无效的第一启动信号。
  5. 根据权利要求4所述的用于驱动显示面板的方法，其中，在所述第一时间段以及所述第二时间段，使所述第一启动信号保持无效。
  6. 根据权利要求1至5中任一项所述的用于驱动显示面板的方法，还包括：
    在第三时间段，使所述源极驱动电路向所述像素电路提供显示数据信号。
  7. 根据权利要求1至5中任一项所述的用于驱动显示面板的方法，其中，所述显示面板还包括用于向所述像素电路输出发光控制信号的所述发光控制驱动电路；
    所述方法还包括：在第一时间段，驱动所述发光控制驱动电路。
  8. 根据权利要求7所述的用于驱动显示面板的方法，其中，在第一时间段，驱动所述发光控制驱动电路的方法包括：
    对所述发光控制驱动电路的电源端提供第三电源信号、第四电源信号；
    对所述发光控制驱动电路提供时钟信号；以及
    对所述发光控制驱动电路提供无效的第二启动信号。
  9. 根据权利要求8所述的用于驱动显示面板的方法，还包括：
    在第三时间段，使所述源极驱动电路向所述像素电路提供显示数据信号；
    其中，在所述第一时间段以及所述第二时间段，对所述栅极驱动电路提供的第一启动信号以及对所述发光控制驱动电路提供的所述第二启动信号保持无效；以及
    其中，在所述第三时间段，所述第二启动信号在所述栅极驱动电路的第一启动信号变成有效之前保持无效。
  10. 根据权利要求8所述的用于驱动显示面板的方法，其中，在所述第一时间段，对所述栅极驱动电路提供的第一启动信号以及对所述发光控制驱动电路提供的所述第二启动信号保持无效；以及其中，在所述第二时间段，所述第二启动信号保持无效。
  11. 根据权利要求10所述的用于驱动显示面板的方法，其中，在所述第二时间段，对所述像素电路提供对应于显示黑色的显示数据信号。
  12. 根据权利要求1至11中任一项所述的用于驱动显示面板的方法，其中，所述像素电路包括驱动电源端以及参考电源端；以及
    其中，在所述第二时间段，驱动所述像素电路包括：
    对所述驱动电源端提供所述第一电源信号、所述第二电源信号；以及
    对所述参考电源端供电。
  13. 根据权利要求1至12中任一项所述的用于驱动显示面板的方法，其中，所述第一时间段包括至少一个显示帧的持续时间，所述第二时间段包括至少一个显示帧的持续时间。
  14. 根据权利要求1至13中任一项所述的用于驱动显示面板的方法，其中，所述第一时间段与所述第二时间段不重叠。
  15. 根据权利要求1至14中任一项所述的用于驱动显示面板的方法，其中，所述显示面板还包括被设置在所述源极驱动电路和所述像素电路之间的复用电路；
    其中，在使所述源极驱动电路输出接地信号的情况下，所述复用电路被导通。
  16. 一种显示面板，配置为向像素电路提供权1-15中任一项所述的显示面板驱动方法。
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