WO2023248718A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2023248718A1
WO2023248718A1 PCT/JP2023/019756 JP2023019756W WO2023248718A1 WO 2023248718 A1 WO2023248718 A1 WO 2023248718A1 JP 2023019756 W JP2023019756 W JP 2023019756W WO 2023248718 A1 WO2023248718 A1 WO 2023248718A1
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WIPO (PCT)
Prior art keywords
pad
connection
semiconductor device
transistor
transistors
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2023/019756
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English (en)
French (fr)
Japanese (ja)
Inventor
達志 金田
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2024528655A priority Critical patent/JPWO2023248718A1/ja
Priority to CN202380039835.5A priority patent/CN119183608A/zh
Priority to US18/861,731 priority patent/US20250301761A1/en
Priority to DE112023002758.7T priority patent/DE112023002758T5/de
Publication of WO2023248718A1 publication Critical patent/WO2023248718A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/20—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes
    • H10D80/251—FETs covered by H10D30/00, e.g. power FETs
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/20—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D1/00 - H10D48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes
    • H10D80/231—Diodes covered by H10D8/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H10W72/5475—Dispositions of multiple bond wires multiple bond wires connected to common bond pads at both ends of the wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • the present disclosure relates to a semiconductor device.
  • a power module in which a plurality of transistors are connected in parallel to ensure current capacity. Further, in order to suppress oscillation of the potential of the gate electrode of a transistor, a power module in which main electrodes such as source electrodes are connected between a plurality of transistors has been proposed (Patent Documents 1, 2, and 3).
  • a semiconductor device of the present disclosure includes a plurality of transistors that are electrically connected in parallel to each other and include a first pad, and a conductive member, the first pad being a source pad or an emitter pad, and the first pad being a source pad or an emitter pad;
  • the pad has a first connection region, a second connection region and a third connection region sandwiching the first connection region therebetween, and a first connection member that connects the first connection region and the conductive member. and a second connection member connecting the second connection regions of two of the plurality of transistors to each other, and the third connection regions of the two of the plurality of transistors to each other. and a third connecting member for connecting.
  • FIG. 1 is a top view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 3 is a schematic diagram showing the structure of a transistor.
  • FIG. 4 is a top view showing the semiconductor device according to the second embodiment.
  • FIG. 5 is a top view showing a semiconductor device according to a third embodiment.
  • FIG. 6 is a top view showing a semiconductor device according to a fourth embodiment.
  • FIG. 7 is a top view showing a semiconductor device according to a fifth embodiment.
  • FIG. 8 is a top view showing a semiconductor device according to a sixth embodiment.
  • FIG. 9 is a cross-sectional view showing a semiconductor device according to a sixth embodiment.
  • FIG. 10 is a diagram showing how to use the semiconductor device according to the sixth embodiment.
  • An object of the present disclosure is to provide a semiconductor device that can improve the stability of parallel operation between multiple transistors.
  • a semiconductor device includes a plurality of transistors that are electrically connected in parallel to each other and include a first pad, and a conductive member, and the first pad is a source pad or an emitter.
  • the first pad is a pad, and the first pad has a first connection area, a second connection area and a third connection area sandwiching the first connection area therebetween, and the first connection area and the conductive member are connected to each other.
  • a first connection member that connects the second connection regions of two of the plurality of transistors, and a second connection member that connects the second connection regions of two of the plurality of transistors; and a third connection member that connects the third connection regions of.
  • the current that has reached the first connection region flows to the first connection member, and the current that has reached the second connection region flows to the first connection member via the first connection region and reaches the third connection region.
  • the current flows through the first connection region to the first connection member.
  • the current that has reached the first pad flows to the first connection member via the first connection area sandwiched between the second connection area and the third connection area.
  • the second connection regions of the two transistors are connected to each other by a second connection member, and the third connection regions of the two transistors are connected to each other by a third connection member. If there is no second connection member or third connection member, a difference in potential between the second connection regions or a difference in potential between the third connection regions is likely to occur between the two transistors.
  • the second connection area has a first internal connection area and a second internal connection area separated from the first internal connection area, and the first internal connection area and the It may have a fourth connection member that connects the second internal connection area. In this case, it is easy to suppress the potential difference within each second connection region.
  • the second connecting member and the fourth connecting member may be integrated.
  • the second connecting member and the fourth connecting member can be formed continuously by stitch bonding, the frequency of cutting the bonding wire can be reduced, and damage to the transistor due to cutting can be suppressed.
  • the first pad may have a gap between the first internal connection area and the second internal connection area.
  • the gate wiring can be placed between the first internal connection region and the second internal connection region.
  • an insulating substrate may be provided, and the plurality of transistors may be mounted on the insulating substrate. In this case, it is easy to arrange multiple transistors close to each other.
  • a plurality of insulating substrates are provided, some of the plurality of transistors are mounted on each insulating substrate, and some of the transistors are mounted on a different insulating substrate. Between the two mounted transistors, the second connection regions may be connected to each other by the second connection member, and the third connection regions may be connected to each other by the third connection member. In this case, heat transfer between transistors mounted on different insulating substrates is suppressed.
  • the cross-sectional area perpendicular to the longitudinal direction of the second connecting member and the third connecting member is the same as the cross-sectional area perpendicular to the longitudinal direction of the first connecting member. May be equal. In this case, it is easy to form the first connection region, the second connection member, and the third connection member.
  • the transistor has a gate pad, a fifth connection member connected to the gate pad, and the second connection member and the third connection member.
  • a cross-sectional area perpendicular to the longitudinal direction of the fifth connecting member may be equal to a cross-sectional area perpendicular to the longitudinal direction of the fifth connecting member. In this case, it is easy to form the second connecting member, the third connecting member, and the fifth connecting member.
  • Any one of [1] to [8] may include a diode electrically connected in parallel to the plurality of transistors.
  • the diode can be used as a freewheeling diode.
  • the diode may be a silicon carbide diode. In this case, it is easy to realize a high breakdown voltage in the diode.
  • the transistor may be a silicon carbide transistor. In this case, it is easy to realize a high breakdown voltage in the transistor.
  • the first connection region, the second connection region, and the The three connection areas may be separated from each other. In this case, it is easy to reduce the potential difference between the first pads, and it is easy to suppress oscillation.
  • a semiconductor device includes a transistor including a first pad, an encapsulant that seals the transistor, and a first a second terminal connected to the first pad and extending from the sealing material in a second direction different from the first direction, the first pad being a source pad or It is an emitter pad.
  • connecting the second terminals can reduce the potential difference between the first pads and suppress oscillation. Therefore, the stability of parallel operation between a plurality of transistors can be improved.
  • [14] [13] may include a first wire connecting the first pad and the first terminal, and a second wire connecting the first pad and the second terminal. .
  • the first pad and the first terminal can be easily connected, and the first pad and the second terminal can be easily connected.
  • [15] [13] or [14] may include a third terminal connected to the first pad and extending from the sealing material in a direction opposite to the second terminal.
  • a third terminal connected to the first pad and extending from the sealing material in a direction opposite to the second terminal.
  • a third wire may be provided to connect the first pad and the third terminal.
  • the first pad and the third terminal can be easily connected.
  • the transistor may be a silicon carbide transistor. In this case, it is easy to realize a high breakdown voltage in the transistor.
  • the plane including the X1-X2 direction and the Y1-Y2 direction is the XY plane
  • the plane including the Y1-Y2 direction and the Z1-Z2 direction is the YZ plane
  • the plane including the Z1-Z2 direction and the X1-X2 direction is the ZX plane.
  • the Z1 direction is defined as an upward direction
  • the Z2 direction is defined as a downward direction.
  • planar view refers to viewing the object from the Z1 side.
  • FIG. 1 is a top view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view showing the semiconductor device according to the first embodiment.
  • FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG.
  • the semiconductor device 1 includes a heat sink 121, a housing 122, a source terminal 101, a drain terminal 102, a gate terminal 103, and a sense source terminal 104. and has.
  • the semiconductor device 1 further includes a first conductive layer 11 , a second conductive layer 12 , a third conductive layer 13 , a fourth conductive layer 14 , and an insulating substrate 123 .
  • the semiconductor device 1 further includes a plurality of transistors 200. The number of transistors 200 is not limited, and is four in one example.
  • Transistor 200 is a field effect transistor and has a silicon carbide substrate 210, a gate pad 231, a source pad 232, and a drain electrode 233.
  • the gate pad 231 and the source pad 232 are provided on the upper surface (Z1 side surface) of the transistor 200, and the drain electrode 233 is provided on the lower surface (Z2 side surface) of the transistor 200.
  • the source pad 232 has a first connection region 241, a second connection region 242, and a third connection region 243.
  • the first connection area 241 is on the Y2 side of the second connection area 242, and the third connection area 243 is on the Y2 side of the first connection area 241. Therefore, the second connection area 242 and the third connection area 243 sandwich the first connection area 241 therebetween.
  • Source pad 232 is an example of a first pad.
  • the heat sink 121 is, for example, a rectangular plate-shaped body with a uniform thickness when viewed from above.
  • the material of the heat sink 121 is a metal having high thermal conductivity, such as copper (Cu), copper alloy, or aluminum (Al).
  • the heat sink 121 is fixed to a cooler or the like using a thermal interface material (TIM) or the like.
  • the casing 122 is formed, for example, in a frame shape in a plan view, and the outer shape of the casing 122 is the same as the outer shape of the heat sink 121.
  • the material of the housing 122 is an insulator such as resin.
  • the housing 122 has a pair of side walls 191 and 192 that face each other, and a pair of end walls 193 and 194 that connect both ends of the side walls 191 and 192.
  • the side walls 191 and 192 are arranged parallel to the ZX plane, and the end walls 193 and 194 are arranged parallel to the YZ plane.
  • the side wall 191 is arranged on the Y1 side of the side wall 192, and the end wall 193 is arranged on the X1 side of the end wall 194.
  • a gate terminal 103 and a sense source terminal 104 are arranged on the upper surface (Z1 side surface) of the side wall portion 191.
  • the gate terminal 103 and the sense source terminal 104 are each made of a metal plate.
  • a source terminal 101 and a drain terminal 102 are arranged on the upper surface (Z1 side surface) of the end wall portion 193.
  • the drain terminal 102 is arranged on the Y1 side of the source terminal 101.
  • the source terminal 101 and the drain terminal 102 are each made of a metal plate.
  • an insulating substrate 123 is arranged on the Z1 side of the heat sink 121.
  • the first conductive layer 11, the second conductive layer 12, the third conductive layer 13, and the fourth conductive layer 14 are provided on the Z1 side surface of the insulating substrate 123.
  • a fifth conductive layer 15 is provided on the Z2 side surface of the insulating substrate 123.
  • the fifth conductive layer 15 is bonded to the heat sink 121 by a second bonding material 132.
  • the material of the insulating substrate 123 is, for example, silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), or aluminum nitride (AlN).
  • the material of the first conductive layer 11, the second conductive layer 12, the third conductive layer 13, the fourth conductive layer 14, and the fifth conductive layer 15 is, for example, copper.
  • the material of the second bonding material 132 is, for example, solder such as lead-free solder containing tin (Sn).
  • the first conductive layer 11 is an example of a conductive member.
  • the source terminal 101 is connected to the first conductive layer 11 and the drain terminal 102 is connected to the second conductive layer 12.
  • Gate terminal 103 is connected to third conductive layer 13
  • sense source terminal 104 is connected to fourth conductive layer 14 .
  • the semiconductor device 1 further includes a first bonding wire 161, a second bonding wire 162, a third bonding wire 163, a fourth bonding wire 164, and a fifth bonding wire 165.
  • the transistor 200 is provided on the second conductive layer 12.
  • the transistors 200 are arranged along the X1-X2 direction.
  • a first connection region 241 of the source pad 232 of the transistor 200 is connected to the first conductive layer 11 by a plurality of first bonding wires 161 .
  • a drain electrode 233 of the transistor 200 is bonded to the second conductive layer 12 by a first bonding material 131.
  • the material of the first bonding material 131 is, for example, solder such as lead-free solder containing tin (Sn).
  • a gate pad 231 of the transistor 200 is connected to the third conductive layer 13 by a fourth bonding wire 164.
  • the source pad 232 of the transistor 200 is also connected to the fourth conductive layer 14 by a fifth bonding wire 165.
  • second connection regions 242 are connected to each other by a second bonding wire 162, and third connection regions 243 are connected to each other by a third bonding wire 163.
  • the first bonding wire 161 is an example of a first connection member
  • the second bonding wire 162 is an example of a second connection member
  • the third bonding wire 163 is an example of a third connection member.
  • the fourth bonding wire 164 is an example of the fifth connection member.
  • FIG. 3 is a schematic diagram showing the configuration of the transistor 200.
  • transistor 200 mainly includes a silicon carbide substrate 210, a gate pad 231, a source pad 232, and a drain electrode 233.
  • Silicon carbide substrate 210 includes a silicon carbide single crystal substrate 211 and a silicon carbide epitaxial layer 212 on silicon carbide single crystal substrate 211.
  • Silicon carbide substrate 210 has a main surface 210A and a main surface 210B opposite to main surface 210A.
  • Silicon carbide epitaxial layer 212 constitutes main surface 210A
  • silicon carbide single crystal substrate 211 constitutes main surface 210B.
  • a plurality of transistor cells are provided in silicon carbide epitaxial layer 212.
  • Gate pad 231 and source pad 232 are provided on main surface 210A, and drain electrode 233 is provided on main surface 210B.
  • a current I flows from the drain electrode 233 to the source pad 232. Furthermore, within the source pad 232, the current I flows toward the first connection region 241 to which the first bonding wire 161 is connected. Then, a current I flows through the first bonding wire 161 through the first connection region 241 . The current I that has reached the first connection region 241 flows directly to the first bonding wire 161. Further, the current I that has reached the second connection area 242 flows to the first bonding wire 161 via the first connection area 241, and the current I that has reached the third connection area 243 flows through the first connection area 241. It flows into the first bonding wire 161.
  • the second bonding wire 162 and the third bonding wire 163 by providing the second bonding wire 162 and the third bonding wire 163, the potential difference between the source pads 232 can be reduced and oscillation can be suppressed. Therefore, the stability of parallel operation between the plurality of transistors 200 can be improved.
  • the plurality of transistors 200 are mounted on the insulating substrate 123, it is easy to arrange the plurality of transistors 200 close to each other.
  • transistor 200 is a silicon carbide transistor including silicon carbide substrate 210, high breakdown voltage can be easily achieved.
  • the cross-sectional areas perpendicular to the longitudinal direction of the second bonding wire 162 and the third bonding wire 163 are not limited, but may be equal to the cross-sectional area perpendicular to the longitudinal direction of the first bonding wire 161.
  • the first bonding wire 161, the second bonding wire 162, and the third bonding wire 163 can be formed without replacing the wires. Therefore, it is easy to form the first bonding wire 161, the second bonding wire 162, and the third bonding wire 163.
  • the cross-sectional area perpendicular to the longitudinal direction of the second bonding wire 162 and the third bonding wire 163 may be equal to the cross-sectional area perpendicular to the longitudinal direction of the fourth bonding wire 164.
  • the fourth bonding wire 164, the second bonding wire 162, and the third bonding wire 163 can be formed without replacing the wires. Therefore, it is easy to form the fourth bonding wire 164, the second bonding wire 162, and the third bonding wire 163.
  • FIG. 4 is a top view showing the semiconductor device according to the second embodiment.
  • the semiconductor device 2 includes a transistor 300 instead of the transistor 200.
  • the transistor 300 includes a gate pad 231, a source pad 332, a drain electrode 233, and a gate wiring (gate runner) 234.
  • the gate pad 231, the gate wiring 334, and the source pad 332 are provided on the upper surface (Z1 side surface) of the semiconductor device 1, and the drain electrode 233 is provided on the lower surface (Z2 side surface) of the semiconductor device 1.
  • the source pad 332 has a first connection region 341, a second connection region 342, and a third connection region 343.
  • the first connection area 341 is on the Y2 side of the second connection area 342, and the third connection area 343 is on the Y2 side of the first connection area 341. Therefore, the second connection area 342 and the third connection area 343 sandwich the first connection area 341 therebetween.
  • the source pad 332 includes a source pad 332A and a source pad 332B. Source pads 332A and 332B are separated from each other in the X1-X2 direction. Source pad 332A is on the X1 side of source pad 332B. First connection region 341, second connection region 342 and third connection region 343 span source pads 332A and 332B.
  • the second connection region 342 has a first internal connection region 351 within the source pad 332A and a second internal connection region 352 within the source pad 332B. The second internal connection area 352 is separate from the first internal connection area 351.
  • the source pad 332 has a gap 353 between the first interconnect region 351 and the second interconnect region 352 .
  • the first internal connection area 351 is located on the X1 side of the second internal connection area 352.
  • Source pad 332 is an example of a first pad.
  • the gate wiring 334 is provided between the source pads 332A and 332B, and extends along the Y1-Y2 direction. Gate wiring 334 is connected to gate pad 231. The gate wiring 334 is provided in the gap 353.
  • the other configuration of the transistor 300 is the same as that of the transistor 200.
  • the semiconductor device 2 further includes a sixth bonding wire 166.
  • a first internal connection region 351 and a second internal connection region 352 are connected within the transistor 200 by a sixth bonding wire 166 .
  • the sixth bonding wire 166 is an example of the fourth connection member.
  • the second embodiment also provides the same effects as the first embodiment. Further, since the first internal connection region 351 and the second internal connection region 352 are connected by the sixth bonding wire 166, it is easy to suppress the potential difference within the second connection region 342. Furthermore, since there is a gap 353 between the first internal connection area 351 and the second internal connection area 352, the gate wiring 334 can be placed between the first internal connection area 351 and the second internal connection area 352.
  • the second bonding wire 162 and the sixth bonding wire 166 may be integrated.
  • the second bonding wire 162 and the sixth bonding wire 166 may be formed by stitch bonding. In this case, the frequency of cutting the bonding wires when forming the second bonding wire 162 and the sixth bonding wire 166 can be reduced, and damage to the transistor 300 caused by cutting can be suppressed.
  • FIG. 5 is a top view showing a semiconductor device according to a third embodiment.
  • the semiconductor device 3 includes a transistor 400 instead of the transistor 300.
  • the transistor 400 includes a gate pad 231, a source pad 432, a drain electrode 233, and a gate wiring (gate runner) 434.
  • the gate pad 231, the gate wiring 434, and the source pad 432 are provided on the upper surface (Z1 side surface) of the semiconductor device 1, and the drain electrode 233 is provided on the lower surface (Z2 side surface) of the semiconductor device 1.
  • the source pad 432 has a first connection region 441, a second connection region 442, and a third connection region 443.
  • the first connection area 441 is on the Y2 side of the second connection area 442, and the third connection area 443 is on the Y2 side of the first connection area 441. Therefore, the second connection area 442 and the third connection area 443 sandwich the first connection area 441 therebetween.
  • the source pad 432 includes a source pad 432A, a source pad 432B, and a conduction region 432C.
  • Source pads 432A and 432B are separated from each other in the X1-X2 direction.
  • Source pad 432A is on the X1 side of source pad 432B.
  • First connection region 441, second connection region 442 and third connection region 443 span source pads 332A and 332B.
  • the conduction region 432C is connected to a corner of the source pad 432A on the X2 side and the Y2 side and a corner of the source pad 432B on the X1 side and the Y2 side, thereby making the source pads 432A and 432B conductive with each other.
  • the conductive region 432C is included in the third connection region 443.
  • the second connection region 442 has a first internal connection region 451 within the source pad 432A and a second internal connection region 452 within the source pad 432B.
  • the second internal connection area 452 is separate from the first internal connection area 451.
  • the source pad 432 has a gap 453 between the first internal connection area 451 and the second internal connection area 452 .
  • the first internal connection area 451 is on the X1 side of the second internal connection area 452.
  • Source pad 432 is an example of a first pad.
  • the gate wiring 434 is provided between the source pads 432A and 432B, and extends along the Y1-Y2 direction. Gate wiring 434 is connected to gate pad 231. The Y2 side end of the gate wiring 434 is located near the conduction region 432C, but is away from the conduction region 432C. The gate wiring 434 is provided in the gap 453.
  • the other configuration of the transistor 400 is the same as that of the transistor 300. Further, the other configurations of the third embodiment are the same as those of the second embodiment.
  • the third embodiment also provides the same effects as the first embodiment. Further, since the first internal connection region 451 and the second internal connection region 452 are connected by the sixth bonding wire 166, it is easy to suppress the potential difference within the second connection region 442. Furthermore, since there is a gap 453 between the first internal connection area 451 and the second internal connection area 452, the gate wiring 434 can be placed between the first internal connection area 451 and the second internal connection area 452.
  • FIG. 6 is a top view showing a semiconductor device according to a fourth embodiment.
  • the semiconductor device 4 includes a plurality of diodes 500 in addition to a plurality of transistors 200.
  • the number of diodes 500 is not limited, and is four in one example.
  • the semiconductor device 4 further includes a seventh bonding wire 167.
  • the diode 500 is a Schottky barrier diode and has an anode pad 532 and a cathode electrode (not shown).
  • the anode pad 532 is provided on the upper surface (Z1 side surface) of the diode 500
  • the cathode electrode is provided on the lower surface (Z2 side surface) of the diode 500.
  • the diode 500 is provided on the second conductive layer 12.
  • the diodes 500 are arranged along the X1-X2 direction.
  • Diode 500 is on the X1 side of transistor 200.
  • An anode pad 532 of the diode 500 is connected to the first conductive layer 11 by a plurality of seventh bonding wires 167 .
  • a cathode electrode of the diode 500 is bonded to the second conductive layer 12 by a third bonding material (not shown).
  • the material of the third bonding material is, for example, solder such as lead-free solder containing tin (Sn).
  • diode 500 can be used as a freewheeling diode.
  • diode 500 is a silicon carbide diode including a silicon carbide substrate, high breakdown voltage can be easily achieved.
  • FIG. 7 is a top view showing a semiconductor device according to a fifth embodiment.
  • the semiconductor device 5 includes insulating substrates 623 and 624 instead of the insulating substrate 123.
  • Insulating substrates 623 and 624 are arranged on the Z1 side of the heat sink 121 inside the housing 122.
  • the insulating substrate 623 is on the X1 side of the insulating substrate 624.
  • the first conductive layer 11, the second conductive layer 12, the third conductive layer 13, and the fourth conductive layer 14 are provided on the Z1 side surface of the insulating substrate 623 and the Z1 side surface of the insulating substrate 624.
  • the fifth conductive layer 15 is provided on the Z2 side surface of the insulating substrate 623 and the Z2 side surface of the insulating substrate 624.
  • the material of the insulating substrates 623 and 624 is, for example, silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), or aluminum nitride (AlN).
  • transistors 200 are provided on the second conductive layer 12 on the insulating substrate 623, and the other four transistors 200 are provided on the second conductive layer 12 on the insulating substrate 624.
  • the transistors 200 are arranged along the X1-X2 direction.
  • the semiconductor device 5 further includes an eighth bonding wire 168, a ninth bonding wire 169, a tenth bonding wire 170, and an eleventh bonding wire 171.
  • the first conductive layer 11 on the insulating substrate 623 and the first conductive layer 11 on the insulating substrate 624 are connected by a plurality of eighth bonding wires 168 .
  • the second conductive layer 12 on the insulating substrate 623 and the second conductive layer 12 on the insulating substrate 624 are connected by a plurality of ninth bonding wires 169.
  • the third conductive layer 13 on the insulating substrate 623 and the third conductive layer 13 on the insulating substrate 624 are connected by a tenth bonding wire 170.
  • the fourth conductive layer 14 on the insulating substrate 623 and the fourth conductive layer 14 on the insulating substrate 624 are connected by an eleventh bonding wire 171.
  • the source terminal 101 is connected to the first conductive layer 11 on the insulating substrate 623, and the drain terminal 102 is connected to the second conductive layer 12 on the insulating substrate 623.
  • the gate terminal 103 is connected to the third conductive layer 13 on the insulating substrate 624, and the sense source terminal 104 is connected to the fourth conductive layer 14 on the insulating substrate 624.
  • the other configuration of the fifth embodiment is the same as the configuration of the first embodiment.
  • the second connecting member and the third connecting member are not limited to bonding wires, but may be copper clips, ribbons, or the like.
  • FIG. 8 is a top view showing a semiconductor device according to a sixth embodiment.
  • FIG. 9 is a cross-sectional view showing a semiconductor device according to a sixth embodiment.
  • FIG. 9 corresponds to a cross-sectional view taken along line IX-IX in FIG.
  • the semiconductor device 6 includes a transistor 710, a sealing material 720, a first source terminal 731, a second source terminal 732, and a third source terminal 733. , a gate terminal 740 , a drain terminal 750 , and a die pad 760 .
  • the sealing material 720 is seen through.
  • the semiconductor device 6 further includes a first bonding wire 781, a second bonding wire 782, a third bonding wire 783, and a fourth bonding wire 784.
  • the first bonding wire 781, the second bonding wire 782, the third bonding wire 783, and the fourth bonding wire 784 are, for example, aluminum (Al) wires.
  • Transistor 710 is a field effect transistor and has a silicon carbide substrate 711, a gate pad 771, a source pad 772, and a drain electrode 773.
  • the gate pad 771 and the source pad 772 are provided on the upper surface (Z1 side surface) of the transistor 710, and the drain electrode 773 is provided on the lower surface (Z2 side surface) of the transistor 710.
  • Source pad 772 is an example of a first pad.
  • the drain terminal 750 is formed integrally with the die pad 760 and extends from the die pad 760 toward the Y2 side.
  • the first source terminal 731 is on the X1 side of the drain terminal 750 and extends parallel to the drain terminal 750.
  • Gate terminal 740 is on the X2 side of drain terminal 750 and extends parallel to drain terminal 750.
  • the second source terminal 732 is located on the X1 side of the die pad 760, away from the die pad 760, and extends along the X1-X2 direction.
  • the third source terminal 733 is located on the X2 side of the die pad 760, away from the die pad 760, and extends along the X1-X2 direction.
  • the transistor 710 is provided on the die pad 760.
  • a drain electrode 773 of the transistor 710 is bonded to the die pad 760 by a bonding material 790.
  • the material of the bonding material 790 is, for example, solder such as lead-free solder containing tin (Sn).
  • the source pad 772 of the transistor 710 is connected to the first source terminal 731 by a plurality of first bonding wires 781.
  • Source pad 772 of transistor 710 is also connected to second source terminal 732 by a second bonding wire 782 .
  • the source pad 772 of the transistor 710 is also connected to a third source terminal 733 by a third bonding wire 783.
  • the gate pad 771 of the transistor 710 is connected to the gate terminal 740 by a fourth bonding wire 784.
  • the first source terminal 731 is an example of a first terminal
  • the second source terminal 732 is an example of a second terminal
  • the third source terminal 733 is an example of a third terminal.
  • the first bonding wire 781 is an example of a first wire
  • the second bonding wire 782 is an example of a second wire
  • the third bonding wire 783 is an example of a third wire.
  • the sealing material 720 seals the transistor 710.
  • the sealing material 720 also seals the first bonding wire 781, the second bonding wire 782, the third bonding wire 783, and the fourth bonding wire 784.
  • the sealing material 720 connects the first source terminal 731 to the first bonding wire 781 , the second source terminal 732 to the second bonding wire 782 , and the third source terminal 733 to the third bonding wire 783 . Also seal the connection.
  • the sealing material 720 also seals the connection portion of the gate terminal 740 with the fourth bonding wire 784.
  • the first source terminal 731, gate terminal 740, and drain terminal 750 extend from the sealing material 720 toward the Y2 side.
  • the second source terminal 732 extends from the sealing material 720 toward the X1 side.
  • the third source terminal 733 extends from the sealing material 720 toward the X2 side.
  • the direction in which the first source terminal 731, gate terminal 740, and drain terminal 750 extend is an example of the first direction.
  • the direction in which the second source terminal 732 extends is an example of the second direction.
  • FIG. 10 is a diagram showing how to use the semiconductor device 6 according to the sixth embodiment.
  • a plurality of semiconductor devices 6 are used.
  • the plurality of semiconductor devices 6 are connected in parallel to each other.
  • the second source terminal 732 and the third source terminal 733 are connected between two semiconductor devices 6 among the plurality of semiconductor devices 6 .
  • the second source terminal 732 and the third source terminal 733 are connected to each other by welding, soldering, or screwing.
  • the source pad 772, the first source terminal 731, the second source terminal 732, and the third source terminal 733 are easily connected. can be connected to.
  • transistor 710 is a silicon carbide transistor including silicon carbide substrate 711, high breakdown voltage can be easily achieved.
  • the transistors 200, 300, 400, and 710 do not need to be field effect transistors, and may be, for example, insulated gate bipolar transistors (IGBT).
  • the emitter pad is used as the first pad.
  • the IGBT may be a silicon carbide IGBT.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
PCT/JP2023/019756 2022-06-24 2023-05-26 半導体装置 Ceased WO2023248718A1 (ja)

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CN202380039835.5A CN119183608A (zh) 2022-06-24 2023-05-26 半导体器件
US18/861,731 US20250301761A1 (en) 2022-06-24 2023-05-26 Semiconductor device
DE112023002758.7T DE112023002758T5 (de) 2022-06-24 2023-05-26 Halbleitervorrichtung

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JP (1) JPWO2023248718A1 (https=)
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JP7843721B2 (ja) * 2023-02-08 2026-04-10 三菱電機株式会社 半導体装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035983A (ja) * 1999-07-16 2001-02-09 Nec Kansai Ltd 半導体装置
JP2013012560A (ja) * 2011-06-29 2013-01-17 Hitachi Ltd パワー半導体モジュール
JP2016184667A (ja) * 2015-03-26 2016-10-20 住友電気工業株式会社 半導体装置
JP2022070377A (ja) * 2020-10-27 2022-05-13 三菱電機株式会社 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035983A (ja) * 1999-07-16 2001-02-09 Nec Kansai Ltd 半導体装置
JP2013012560A (ja) * 2011-06-29 2013-01-17 Hitachi Ltd パワー半導体モジュール
JP2016184667A (ja) * 2015-03-26 2016-10-20 住友電気工業株式会社 半導体装置
JP2022070377A (ja) * 2020-10-27 2022-05-13 三菱電機株式会社 半導体装置

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JPWO2023248718A1 (https=) 2023-12-28

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