WO2023243306A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

Info

Publication number
WO2023243306A1
WO2023243306A1 PCT/JP2023/018745 JP2023018745W WO2023243306A1 WO 2023243306 A1 WO2023243306 A1 WO 2023243306A1 JP 2023018745 W JP2023018745 W JP 2023018745W WO 2023243306 A1 WO2023243306 A1 WO 2023243306A1
Authority
WO
WIPO (PCT)
Prior art keywords
main surface
semiconductor device
base material
conductive portion
wiring board
Prior art date
Application number
PCT/JP2023/018745
Other languages
English (en)
Japanese (ja)
Inventor
昌明 松尾
開人 井上
英夫 原
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ローム株式会社 filed Critical ローム株式会社
Publication of WO2023243306A1 publication Critical patent/WO2023243306A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to a semiconductor device.
  • IPM Intelligent Power Module
  • Such a semiconductor device includes a plurality of semiconductor chips, a plurality of electrode sections, a heat dissipation layer, and a sealing resin section (see Patent Document 1).
  • a semiconductor chip is placed on a die pad portion of one of the electrode portions.
  • the plurality of electrode portions serve as conduction paths that connect the semiconductor chip to the outside.
  • Semiconductor chips include LSI chips such as control ICs.
  • An LSI chip has input/output for multiple types of control signals. As the number of control signals increases, it is necessary to increase the number of conduction paths to the LSI chip, but if these conduction paths are constructed from multiple electrode sections as in the past, the integration of semiconductor devices will become even higher. It may become difficult.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. Particularly, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that enables even higher integration.
  • a semiconductor device provided by a first aspect of the present disclosure includes a first base material having a first main surface and a first back surface facing opposite to each other in the thickness direction, and a first base material disposed on the first main surface.
  • a second base material having a first main surface conductive portion having conductivity, a second main surface facing the same side as the first main surface in the thickness direction, and a second back surface facing the same side as the first back surface.
  • a second main surface conductive part having electrical conductivity disposed on the second main surface; a switching element disposed on the first main surface and electrically connected to the first main surface conductive part; a driving device disposed on the second main surface, electrically connected to the second main surface conductive portion, and driving the switching element; and at least a portion of the first base material and the second base material. and a sealing resin that covers the entire switching element and the drive device.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a plan view showing the semiconductor device of FIG. 1.
  • FIG. 3 is a plan view showing the semiconductor device of FIG. 1, and is a view through the sealing resin.
  • FIG. 4 is a bottom view showing the semiconductor device of FIG. 1.
  • FIG. 5 is a cross-sectional view taken along line VV in FIG. 3.
  • FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. 7 is a plan view showing each wiring board of the semiconductor device of FIG. 1.
  • FIG. 8 is a flowchart showing one step of an example of the method for manufacturing the semiconductor device of FIG.
  • FIG. 9 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, and is a view through a sealing resin.
  • a thing A is formed on a thing B and "a thing A is formed on a thing B” mean “a thing A is formed on a thing B” unless otherwise specified.
  • "something A is placed on something B” and “something A is placed on something B” mean "something A is placed on something B” unless otherwise specified.
  • First embodiment: 1 to 7 show an example of a semiconductor device according to the present disclosure.
  • the semiconductor device A1 of this embodiment includes a plurality of leads 1, a wiring board 2, a wiring board 3, a plurality of semiconductor chips 4, a plurality of drive devices 5, a plurality of passive elements 6, a plurality of wires 7, and a sealing resin 8. It is equipped with In this embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used for applications such as air conditioners and motor control equipment, for example.
  • IPM Intelligent Power Module
  • FIG. 1 is a perspective view showing a semiconductor device A1.
  • FIG. 2 is a plan view showing the semiconductor device A1.
  • FIG. 3 is a plan view showing the semiconductor device A1, and is a view through the sealing resin 8. As shown in FIG. In addition, in FIG. 3, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line).
  • FIG. 4 is a bottom view showing the semiconductor device A1.
  • FIG. 5 is a cross-sectional view taken along line VV in FIG. 3.
  • FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. 7 is a plan view showing the wiring board 2 and the wiring board 3.
  • the thickness direction of the wiring board 2 is referred to as the thickness direction z
  • the direction along one side of the wiring board 2 perpendicular to the thickness direction z is referred to as the first direction y
  • the direction perpendicular to the thickness direction z and the first direction y is the second direction x.
  • the shape and dimensions of the semiconductor device A1 are not limited.
  • the wiring board 2 is mounted with a plurality of semiconductor chips 4 and a plurality of passive elements 6 (shunt resistors 6a to be described later), and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the first side y1 in the first direction y. has been done.
  • the plurality of semiconductor chips 4 are power transistors
  • the wiring board 2 is a power section board on which a power circuit is arranged.
  • the wiring board 2 includes a base material 21, a main surface conductive portion 22, and a back surface conductive portion 23.
  • the base material 21 is plate-shaped, and has a rectangular shape that is elongated in the second direction x when viewed in the thickness direction z (that is, in plan view).
  • the thickness dimension (dimension in the thickness direction z) of the base material 21 is, for example, about 0.1 mm to 1.0 mm. Note that the dimensions of the base material 21 are not limited.
  • the base material 21 is made of an insulating material.
  • the constituent material of the base material 21 is, for example, ceramics with excellent thermal conductivity, and in this embodiment, includes aluminum nitride (AlN). Note that the constituent material of the base material 21 is not limited to this.
  • the base material 21 has a main surface 211 and a back surface 212.
  • the main surface 211 and the back surface 212 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 211 is a surface facing the first side z1 in the thickness direction z.
  • a main surface conductive portion 22 is arranged on the main surface 211, and a plurality of semiconductor chips 4, a plurality of passive elements 6, and a plurality of leads 1 are mounted on the main surface 211.
  • the back surface 212 is a surface facing the second side z2 in the thickness direction z. On the back surface 212, a back conductive portion 23 is arranged.
  • the shapes of the main surface 211 and the back surface 212 are both rectangular. Note that the shape of the base material 21 is not limited.
  • the main surface conductive portion 22 is arranged on the main surface 211 of the base material 21.
  • the main surface conductive portion 22 is made of a conductive material.
  • the constituent material of the main surface conductive portion 22 is not particularly limited, and examples thereof include copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described.
  • the thickness dimension (dimension in the thickness direction z) T1 (see FIG. 6) of the main surface conductive portion 22 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness dimension T1 is approximately 0.25 mm. Note that the thickness dimension T1 is not limited.
  • the main surface conductive portion 22 includes a plurality of pads 221 and a plurality of wirings 222, as shown in FIG. 7, for example.
  • Each pad 221 has a rectangular shape, for example, and has the semiconductor chip 4, the passive element 6, the lead 1 (lead 11 described later), or the wire 7 (wires 71 and 72 described later) electrically connected.
  • the shape of the pad 221 is not limited.
  • Each pad 221 is spaced apart from each other.
  • Each of the plurality of wirings 222 is a conduction path that connects one of the pads 221 and one of the pads 221 to conduct them.
  • the shape of each wiring 222 is not limited.
  • the back conductive portion 23 is arranged on the back surface 212 of the base material 21.
  • the back conductive portion 23 is made of a conductive material.
  • the constituent material of the back conductive portion 23 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these.
  • the constituent material of the back surface conductive portion 23 is copper (Cu), as is the case with the main surface conductive portion 22.
  • the thickness dimension (dimension in the thickness direction z) of the back conductive portion 23 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more.
  • the thickness of the back conductive portion 23 is approximately 0.25 mm, similar to the thickness T1, but is not limited thereto.
  • the back surface conductive portion 23 covers the entire surface of the back surface 212. Note that the shape of the back conductive portion 23 is not limited. The back conductive portion 23 is exposed from the sealing resin 8, as shown in FIG.
  • the wiring board 2 is formed from a so-called DBC (Direct Bonded Copper) board.
  • the DBC board is a board in which copper foil is bonded to both sides of a ceramic plate.
  • the wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23.
  • the method for forming the wiring board 2 is not limited. Regardless of which method is used, it is necessary to form a copper layer of 0.2 mm or more.
  • the constituent material of the main surface conductive portion 22 and the back surface conductive portion 23 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
  • the wiring board 3 has a plurality of drive devices 5 and a plurality of passive elements 6 mounted thereon, and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the second side y2 in the first direction y.
  • the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y, and the wiring board 3 is located on the second side y2 of the first direction y with respect to the wiring board 2.
  • the wiring board 3 is a control unit board on which a control circuit for controlling the power circuit arranged on the wiring board 2 is arranged.
  • the wiring board 3 includes a base material 31, a main surface conductive portion 32, and a back surface conductive portion 33.
  • the base material 31 is plate-shaped and has a rectangular shape that is long in the second direction x when viewed in the thickness direction z.
  • the thickness dimension (dimension in the thickness direction z) of the base material 31 is, for example, about 0.1 mm to 1.0 mm, which is about the same as that of the base material 21. Note that the dimensions of the base material 31 are not limited.
  • the base material 31 is made of an insulating material.
  • the constituent material of the base material 31 is, for example, ceramics, and in this embodiment contains alumina (Al 2 O 3 ).
  • the base material 31 does not require as much thermal conductivity as the base material 21.
  • the base material 21 is made of ceramics made of aluminum nitride, and has higher thermal conductivity than the base material 31 made of ceramics made of alumina.
  • the constituent material of the base material 31 is not limited to this.
  • the constituent material of the base material 21 and the constituent material of the base material 31 may be the same.
  • the base material 31 has a main surface 311 and a back surface 312.
  • the main surface 311 and the back surface 312 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 311 is a surface facing the first side z1 in the thickness direction z.
  • a main surface conductive portion 32 is arranged on the main surface 311, and a plurality of drive devices 5, a plurality of passive elements 6, and a plurality of leads 1 are mounted thereon.
  • the back surface 312 is a surface facing the second side z2 in the thickness direction z.
  • On the back surface 312, a back conductive portion 33 is arranged.
  • the shapes of the main surface 311 and the back surface 312 are both rectangular. Note that the shape of the base material 31 is not limited.
  • the main surface conductive portion 32 is arranged on the main surface 311 of the base material 31.
  • the main surface conductive portion 32 is made of a conductive material.
  • the constituent material of the main surface conductive portion 32 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described.
  • the thickness dimension (dimension in the thickness direction z) T2 (see FIG. 6) of the main surface conductive part 32 is smaller than the thickness dimension T1, and has a thickness that allows finer processing than the main surface conductive part 22 by etching. be. In this embodiment, the thickness dimension T2 is, for example, about 0.1 mm. Note that the thickness dimension T2 is not limited.
  • the main surface conductive portion 32 includes a plurality of pads 321 and a plurality of wirings 322, as shown in FIG. 7, for example.
  • Each pad 321 has a rectangular shape, for example, and has a driving device 5, a passive element 6, a lead 1 (a lead 15 described later), or a wire 7 (wires 73 and 74 described later) electrically connected.
  • the shape of the pad 321 is not limited.
  • Each pad 321 is spaced apart from each other.
  • Each of the plurality of wirings 322 is a conduction path that connects one of the pads 321 and one of the pads 321 to conduct the two.
  • the shape of each wiring 322 is not limited. Note that a conductive plate-like member may be placed on the pad 321 to which the wire 7 is bonded in order to protect the pad 321 and the base material 31 from impact caused by wire bonding.
  • the back surface conductive part 33 is arranged on the back surface 312 of the base material 31.
  • the back conductive portion 33 is made of a conductive material.
  • the constituent material of the back conductive portion 33 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these.
  • the constituent material of the back conductive portion 33 is copper (Cu), as is the case with the main conductive portion 32 .
  • the thickness dimension (dimension in the thickness direction z) of the back conductive portion 33 is approximately the same as the thickness dimension T2, and is, for example, approximately 0.1 mm. Note that the thickness dimension of the back conductive portion 33 is not limited to this. In this embodiment, the back conductive portion 33 covers the entire back surface 312.
  • the shape of the back conductive portion 33 is not limited.
  • the back conductive portion 33 is exposed from the sealing resin 8, as shown in FIG.
  • the wiring board 3 does not need to include the back conductive portion 33.
  • the back surface 312 of the base material 31 may be exposed from the sealing resin 8, or the entire wiring board 3 may be covered with the sealing resin 8 (the wiring board 3 is not exposed from the sealing resin 8). good.
  • the wiring board 3 is formed from a so-called DBC board.
  • the DBC board is a board in which copper foil is bonded to both sides of a ceramic plate.
  • the copper foil of the DBC board is thinner than the copper foil of the DBC board for forming the wiring board 2.
  • the wiring board 3 is formed by patterning copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33.
  • the method of forming the wiring board 3 is not limited.
  • the wiring board 3 may be formed from a so-called DPC (Direct Plated Copper) board, which is a ceramic plate with copper plating on both sides.
  • DPC Direct Plated Copper
  • the wiring board 3 may be formed by disposing copper paste on both sides of a ceramic plate and firing the same.
  • the constituent material of the main surface conductive portion 32 and the back surface conductive portion 33 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
  • the plurality of leads 1 are configured to include metal.
  • the metal constituting the lead 1 is not particularly limited, and includes, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or alloys thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy). etc.).
  • the plurality of leads 1 may be plated with nickel (Ni).
  • the plurality of leads 1 may be formed, for example, by pressing a metal mold against a metal plate, or by patterning a metal plate by etching. Note that the method for forming the plurality of leads 1 is not limited.
  • the thickness of each lead 1 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. Each lead 1 is spaced apart from each other.
  • the plurality of leads 1 each include a plurality of leads 11, leads 12, leads 15, and leads 16.
  • the leads 11 and 12 constitute a conductive path to the semiconductor chip 4.
  • Leads 15 and 16 constitute a conduction path to drive device 5 or passive element 6.
  • the plurality of leads 11 are each arranged on the base material 21, and in this embodiment, are arranged on the main surface 211 closer to the first side y1 in the first direction y. Each lead 11 is bonded to a pad 221 of the main surface conductive portion 22 via a conductive bonding material 76 .
  • the conductive bonding material 76 may be any material that can conductively bond the leads 11 to the pads 221, such as silver paste, copper paste, solder, or the like. Note that the conductive bonding material 76 is not limited.
  • Each lead 11 is electrically connected to the semiconductor chip 4 via the main surface conductive portion 22 and the wire 71.
  • the plurality of leads 1 includes three leads 11. Note that the number and arrangement of leads 11 are not limited.
  • the structure of the lead 11 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 11 will be divided into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114.
  • the joint portion 111 has a main surface 111a and a back surface 111b.
  • the main surface 111a and the back surface 111b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 111a is a surface facing the first side z1 in the thickness direction z.
  • the back surface 111b is a surface facing the second side z2 in the thickness direction z.
  • the back surface 111b is bonded to the pad 221 of the main surface conductive portion 22 by a conductive bonding material 76.
  • the inclined connection portion 113 and the parallel connection portion 114 are covered with the sealing resin 8.
  • the inclined connection part 113 is connected to the joint part 111 and the parallel connection part 114 and is inclined with respect to the joint part 111 and the parallel connection part 114.
  • the parallel connecting portion 114 is connected to the inclined connecting portion 113 and the protruding portion 112 and is parallel to the joining portion 111 .
  • the protruding portion 112 is connected to the end of the parallel connection portion 114 and is a portion of the lead 11 that protrudes from the sealing resin 8 .
  • the protruding portion 112 protrudes to the side opposite to the joining portion 111 (y1 side) in the first direction y.
  • the protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent toward the side toward which the main surface 111a of the joint portion 111 faces in the thickness direction z.
  • the plurality of leads 12 are not arranged on the base material 21, but are arranged on the first side y1 of the base material 21 in the first direction y.
  • Each lead 12 does not include a portion corresponding to the joint portion 111 and the inclined connection portion 113 of the lead 11, but only includes a portion corresponding to the protrusion portion 112 and the parallel connection portion 114.
  • a wire 72 is electrically connected to a portion corresponding to the parallel connection portion 114.
  • Each lead 12 is electrically connected to the semiconductor chip 4 or the passive element 6 via the wire 72 and the main surface conductive portion 22.
  • the plurality of leads 1 includes six leads 12. Note that the configuration, number, and arrangement of the leads 12 are not limited to this.
  • the plurality of leads 15 are each arranged on the base material 31, and in this embodiment, are arranged on the main surface 311 closer to the second side y2 in the first direction y. Each lead 15 is bonded to a pad 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Each lead 15 is electrically connected to the drive device 5 or the passive element 6 via the main surface conductive portion 22 . In this embodiment, the plurality of leads 1 includes 18 leads 15. Note that the number and arrangement of leads 15 are not limited.
  • the structure of the lead 15 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 15 will be divided into a joining portion 151, a protruding portion 152, an inclined connecting portion 153, and a parallel connecting portion 154.
  • the joint portion 151 has a main surface 151a and a back surface 151b.
  • the main surface 151a and the back surface 151b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 151a is a surface facing the first side z1 in the thickness direction z.
  • the back surface 151b is a surface facing the second side z2 in the thickness direction z.
  • the back surface 151b is bonded to the pad 321 of the main surface conductive portion 32 by a conductive bonding material 76.
  • the inclined connection portion 153 and the parallel connection portion 154 are covered with the sealing resin 8.
  • the inclined connection portion 153 is connected to the joint portion 151 and the parallel connection portion 154 and is inclined with respect to the joint portion 151 and the parallel connection portion 154.
  • the parallel connecting portion 154 is connected to the inclined connecting portion 153 and the protruding portion 152 and is parallel to the joining portion 151.
  • the protruding portion 152 is connected to the end of the parallel connection portion 154 and is a portion of the lead 15 that protrudes from the sealing resin 8 .
  • the protruding portion 152 protrudes to the side opposite to the joining portion 151 (y2 side) in the first direction y.
  • the protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent toward the side toward which the main surface 151a of the joint portion 151 faces in the thickness direction z.
  • the plurality of leads 16 are not arranged on the base material 31, but are arranged on the first side x1 or the second side x2 of the base material 31 in the second direction x.
  • Each lead 16 has a similar configuration to lead 15.
  • a wire 74 is conductively bonded to a portion corresponding to the bonding portion 151 instead of being bonded to the pad 321 of the main surface conductive portion 32 .
  • Each lead 16 is electrically connected to the drive device 5 and the passive element 6 via the wire 74 and the main surface conductive portion 32.
  • the plurality of leads 1 includes four leads 16. Note that the configuration, number, and arrangement of the leads 16 are not limited to this.
  • the plurality of semiconductor chips 4 are switching elements and power transistors that control power.
  • the semiconductor chip 4 is constructed using a semiconductor material mainly composed of SiC (silicon carbide).
  • the semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like.
  • the semiconductor chip 4 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Note that the semiconductor chip 4 is not limited to a MOSFET, and may be an IGBT (Insulated Gate Bipolar Transistor) or the like. Although this embodiment shows a case where the semiconductor device A1 includes four semiconductor chips 4, this is just an example, and the number of semiconductor chips 4 is not limited.
  • Each semiconductor chip 4 has a rectangular plate shape when viewed in the thickness direction z, and includes an element main surface 41, an element rear surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45.
  • the element main surface 41 and the element back surface 42 face opposite sides in the thickness direction z.
  • the element main surface 41 is a surface facing the first side z1 in the thickness direction z.
  • the back surface 42 of the element is a surface facing the second side z2 in the thickness direction z.
  • a source electrode 43 and a gate electrode 44 are arranged on the main surface 41 of the element.
  • a drain electrode 45 is arranged on the back surface 42 of the element. Note that the shapes and arrangement of the source electrode 43, gate electrode 44, and drain electrode 45 are not limited.
  • Each semiconductor chip 4 is mounted on the wiring board 2, as shown in FIGS. 3 and 5.
  • Each semiconductor chip 4 is arranged on the main surface 211 of the base material 21.
  • the four semiconductor chips 4 are arranged side by side in the second direction x on the main surface 211 closer to the second side y2 in the first direction y.
  • the arrangement position of each drive device 5 is not limited.
  • each semiconductor chip 4 is bonded to a pad 221 of the main surface conductive portion 22 by a conductive bonding material 76 with the element back surface 42 facing the main surface 211.
  • the drain electrode 45 of the semiconductor chip 4 is electrically connected to the pad 221 by the conductive bonding material 76 .
  • the source electrode 43 of the semiconductor chip 4 is electrically connected to the adjacent pad 221 by a wire 71.
  • the semiconductor device A1 includes two bridge circuits each made up of two semiconductor chips 4.
  • the source electrode 43 and gate electrode 44 of the semiconductor chip 4 are electrically connected to the driving device 5 via the wire 73 and the main surface conductive portion 32 of the wiring board 3, respectively.
  • Each of the plurality of drive devices 5 is a so-called gate driver that outputs a drive signal to drive the corresponding semiconductor chip 4.
  • the drive device 5 is an insulated gate driver in which a low voltage side into which a signal is input is insulated from a high voltage side through which a drive signal is output.
  • the driving device 5 is not limited to an insulated gate driver.
  • the semiconductor device A1 includes four drive devices 5 corresponding to the number of semiconductor chips 4.
  • Each drive device 5 is mounted on the wiring board 3, as shown in FIGS. 3 and 5.
  • Each drive device 5 is arranged on the main surface 311 of the base material 31.
  • the four drive devices 5 are arranged at the center (or approximately at the center) of the main surface 311 in the first direction y and in line in the second direction x. Note that the arrangement position of each drive device 5 is not limited.
  • the drive device 5 is an SOP (Small Outline Package) type package.
  • the drive device 5 includes a plurality of terminals that protrude and extend on both sides of the first direction y. These terminals are conductively bonded to the pads 321 of the main surface conductive portion 32 by a conductive bonding material 76 .
  • the package type of the drive device 5 is not limited to the SOP type, and may be other types such as a QFP (Quad Flat Package) type or an SOJ (Small Outline J-lead Package) type. Further, the size, shape, number of terminals, etc. of the drive device 5 are not limited. Further, instead of the drive device 5, a drive chip may be directly disposed on the wiring board 3. The drive device 5 outputs a drive signal to the gate electrode 44 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73. Further, the driving device 5 receives the potential of the source electrode 43 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73.
  • the plurality of passive elements 6 are mounted on the wiring board 2 or the wiring board 3, as shown in FIGS. 3 and 5. Each passive element 6 is disposed on the main surface 211 of the base material 21 or the main surface 311 of the base material 31, and is electrically connected to the pad 221 of the main surface conductive part 22 or the pad 321 of the main surface conductive part 32. ing.
  • the passive element 6 is, for example, a resistor, a capacitor, a coil, a diode, or the like. Passive element 6 includes two shunt resistors 6a and a thermistor 6b.
  • the two shunt resistors 6a are mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21. Each shunt resistor 6a straddles the two pads 221 of the main surface conductive portion 22 and is electrically connected to each pad 221. An output current of a bridge circuit composed of two semiconductor chips 4 flows through each shunt resistor 6a, and a potential difference between both terminals is output.
  • the thermistor 6b is mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31.
  • the thermistor 6b straddles the two pads 321 of the main surface conductive portion 32 and is electrically connected to each pad 321.
  • Each pad 321 to which the thermistor 6b is bonded is electrically connected to the lead 15 via the pad 321 electrically connected by a wiring 322.
  • a predetermined current is passed through the thermistor 6b, and the thermistor 6b outputs a voltage signal according to the temperature of the wiring board 3.
  • Each passive element 6 is mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31. Each passive element 6 is electrically connected to a pad 321 of the main surface conductive portion 32 and electrically connected to the drive device 5 via the wiring 322 and the pad 321. Note that the type, arrangement position, and number of each passive element 6 are not limited.
  • the plurality of wires 7 each include a plurality of wires 71, 72, 73, and 74.
  • the plurality of wires 71 are electrically connected to the source electrode 43 of the semiconductor chip 4 and the pad 221.
  • each semiconductor chip 4 and the pad 221 are connected by two wires 71, but the number of wires 71 connecting each semiconductor chip 4 and the pad 221 is not limited.
  • the wire 71 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 71 are not limited.
  • the plurality of wires 72 are electrically connected to the pads 221 of the main surface conductive portion 22 and the leads 12 .
  • the number of wires 72 connecting pads 221 and leads 12 is not limited.
  • the wire 72 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 72 are not limited.
  • the plurality of wires 73 are electrically connected to the source electrode 43 or gate electrode 44 of the semiconductor chip 4 and the pad 321 of the main surface conductive portion 32 of the wiring board 3.
  • each semiconductor chip 4 and the pad 321 are connected by one wire 73, but the number of wires 73 connecting each semiconductor chip 4 and the pad 321 is not limited.
  • the wire 73 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 73 are not limited.
  • the plurality of wires 74 are electrically connected to the pads 321 of the main surface conductive portion 32 of the wiring board 3 and the leads 16 .
  • each pad 321 and each lead 16 are connected by one wire 74, but the number of wires 74 connecting each pad 321 and each lead 16 is not limited.
  • the wire 74 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 74 are not limited.
  • the sealing resin 8 seals a plurality of semiconductor chips 4 , a plurality of drive devices 5 , a plurality of passive elements 6 , a plurality of wires 7 , a portion of each of the plurality of leads 1 , and a portion of the wiring board 2 and the wiring board 3 . covering at least part of each part.
  • the material of the sealing resin 8 is not particularly limited, and insulating materials such as epoxy resin and silicone gel may be used as appropriate.
  • the sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83.
  • the main resin surface 81 and the resin back surface 82 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main resin surface 81 is a surface facing the first side z1 in the thickness direction z.
  • the resin back surface 82 is a surface facing the second side z2 in the thickness direction z.
  • Each resin side surface 83 is connected to the resin main surface 81 and the resin back surface 82, and faces the second direction x or the first direction y. As shown in FIG.
  • each of the plurality of leads 11 and leads 12 protrudes from the resin side surface 83 facing the first side y1 in the first direction y of the sealing resin 8.
  • Each of the plurality of leads 15 and leads 16 protrudes from the resin side surface 83 facing the second side y2 in the first direction y of the sealing resin 8.
  • the manufacturing method of this example includes a substrate forming process (step S1), a lead frame bonding process (step S2), a semiconductor chip mounting process (step S3), a drive device mounting process (step S4), a wire
  • the process includes a connecting process (step S5), a resin forming process (step S6), and a frame cutting process (step S7).
  • step S1 two types of DBC substrates are first prepared.
  • One DBC substrate is a substrate in which copper foils having a thickness of T1 are bonded to both sides of an aluminum nitride ceramic plate.
  • the other DBC substrate is a substrate in which copper foil having a thickness of T2 is bonded to both sides of an alumina ceramic plate.
  • the copper foil on one side of each DBC board is patterned by etching.
  • the aluminum nitride DBC substrate becomes the wiring board 2.
  • the patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23.
  • the alumina DBC board becomes the wiring board 3.
  • the patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33.
  • step S2 first, the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y.
  • a conductive bonding paste is placed on a predetermined pad 221 of the main surface conductive portion 22 and a predetermined pad 321 of the main surface conductive portion 32.
  • the conductive bonding paste is, for example, silver paste, copper paste, or solder.
  • a lead frame is prepared.
  • the lead frame includes a plurality of leads 1 and further has a frame to which the plurality of leads 1 are connected. Note that the shape of the lead frame and the like are not limited at all.
  • each of the plurality of leads 11 is made to face a predetermined pad 221 via a conductive bonding paste.
  • each of the plurality of leads 15 is made to face a predetermined pad 321 via a conductive bonding paste.
  • the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. As a result, each lead 11 is bonded to a predetermined pad 221 via the conductive bonding material 76, and each lead 15 is bonded to the pad 321 via the conductive bonding material 76.
  • step S3 first, a conductive bonding paste is placed at a predetermined position of a predetermined pad 221 on the main surface conductive portion 22 of the wiring board 2. Each semiconductor chip 4 is then attached to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the semiconductor chip 4 is bonded to the pad 221 via the conductive bonding material 76. Further, in a similar process, the shunt resistor 6a is bonded to the pad 221 via the conductive bonding material 76.
  • step S4 first, a conductive bonding paste is placed on a predetermined pad 321 of the main surface conductive portion 32 of the wiring board 3. Each terminal of each drive device 5 is then adhered to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the drive device 5 is bonded to the pad 321 via the conductive bonding material 76. Further, the thermistor 6b and other passive elements 6 are bonded to the pad 321 via the conductive bonding material 76 by a similar process.
  • a plurality of wires 71 and 72 are connected.
  • wires made of aluminum (Al) are sequentially connected by, for example, a wedge bonding method.
  • a plurality of wires 71 are obtained.
  • the plurality of wires 73 and 74 are connected.
  • wire materials made of gold (Au) are sequentially connected by, for example, a capillary bonding method.
  • a plurality of wires 72 are obtained.
  • step S6 for example, a part of the lead frame, the wiring boards 2 and 3, each of the plurality of semiconductor chips 4, the driving device 5, the passive element 6, and the wire 7 are surrounded by a mold. Next, a liquid resin material is injected into the space defined by the mold. Next, the sealing resin 8 is obtained by curing this resin material.
  • step S7 the lead frame is cut at an appropriate location exposed from the sealing resin 8. As a result, the plurality of leads 1 are divided from each other. Thereafter, the above-described semiconductor device A1 is obtained by performing a process such as bending the plurality of leads 1 as necessary.
  • the wiring board 3 includes the main surface conductive portion 32 disposed on the main surface 311 of the base material 31.
  • the driving device 5 is electrically connected to the pad 321 of the main surface conductive portion 32 .
  • the conduction path to the drive device 5 can be configured by the main surface conductive portion 32 disposed on the main surface 311 of the base material 31. Therefore, compared to, for example, a case where the conduction path is formed of metal leads, it is possible to make the conduction path thinner and more dense.
  • the semiconductor device A1 includes a wiring board 2 in addition to the wiring board 3.
  • the wiring board 2 includes a main surface conductive portion 22 disposed on the main surface 211 of the base material 21 .
  • the semiconductor chip 4 is bonded to the pad 221.
  • the thickness T1 of the main surface conductive portion 22 is larger than the thickness T2 of the main surface conductive portion 32, and is thick enough to maintain the heat dissipation effect of the heat generated by the semiconductor chip 4.
  • the thickness dimension T2 is smaller than the thickness dimension T1, and is a thickness that allows finer processing by etching.
  • the semiconductor device A1 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense.
  • the wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. Therefore, compared to the case where the main surface conductive portion 22 and the back surface conductive portion 23 are respectively formed on the base material 21, the manufacturing process can be simplified. The same applies to the wiring board 3.
  • the base material 21 of the wiring board 2 is an aluminum nitride ceramic plate.
  • the base material 31 of the wiring board 3 is an alumina ceramic plate. Therefore, the base material 21 has higher thermal conductivity than the base material 31. Thereby, the wiring board 2 can appropriately dissipate the heat generated by the semiconductor chip 4. Further, the material cost of the wiring board 3, which does not require as much heat dissipation as the wiring board 2, can be reduced.
  • the back conductive portion 33 of the wiring board 2 is exposed from the resin back surface 82. Therefore, the heat transmitted from the semiconductor chip 4 to the wiring board 2 can be radiated to the outside more efficiently.
  • the semiconductor device A1 includes a thermistor 6b mounted on the wiring board 3. Therefore, the semiconductor device A1 can detect the temperature of the wiring board 3.
  • the plurality of leads 11 are bonded to the pads 221 of the main surface conductive portion 22 via the conductive bonding material 76. Thereby, the plurality of leads 11 are firmly fixed to the wiring board 2. Further, it is possible to reduce the resistance between the plurality of leads 11 and the main surface conductive portion 22. Further, the plurality of leads 15 are bonded to the pads 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Thereby, the plurality of leads 15 are firmly fixed to the wiring board 3. Furthermore, the resistance between the plurality of leads 15 and the main surface conductive portion 32 can be reduced.
  • the base material 31 does not require as much thermal conductivity as the base material 21, it may be a substrate containing synthetic resin such as glass epoxy resin. That is, the wiring board 3 may be a so-called PCB (Printed Circuit Board) board. Further, the base material 31 may be a multilayer substrate in which a plurality of base materials are laminated.
  • PCB printed Circuit Board
  • FIG. 9 is a diagram for explaining a semiconductor device A2 according to a second embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view showing the semiconductor device A2, and corresponds to FIG. 5.
  • the semiconductor device A2 according to the second embodiment differs from the first embodiment in that the entire wiring board 3 is covered with a sealing resin 8.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment.
  • the wiring board 3 does not include the back conductive portion 33.
  • the wiring board 3 according to this embodiment is formed by etching and patterning the copper foil of a DBC board in which copper foil is bonded to only one side of a ceramic plate. Further, the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8. Unlike the wiring board 2 on which the semiconductor chip 4 is mounted, the wiring board 3 is not required to have much heat dissipation. Therefore, even if the wiring board 3 is not exposed from the resin back surface 82 and its heat dissipation is suppressed, it does not pose much of a problem.
  • the semiconductor device A2 since the semiconductor device A2 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A2 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A2, since the wiring board 3 does not include the back conductive portion 33, material costs can be suppressed.
  • the wiring board 3 is not exposed from the resin back surface 82, but the present invention is not limited to this.
  • the back surface 312 of the base material 31 may be exposed from the resin back surface 82.
  • FIG. 10 is a diagram for explaining a semiconductor device A3 according to a third embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view showing the semiconductor device A3, and corresponds to FIG. 5.
  • the semiconductor device A3 according to the third embodiment differs from the first embodiment in that the passive element 6 is also arranged on the back surface 312 of the base material 31 of the wiring board 3.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first and second embodiments described above may be combined arbitrarily.
  • the wiring board 3 has passive elements 6 arranged not only on the main surface 311 but also on the back surface 312.
  • the back conductive portion 33 includes pads 331 and wiring 332.
  • the pad 331 and the wiring 332 are formed by patterning the copper foil on the other side of the DBC substrate by etching.
  • the shape of the back conductive portion 33 is not limited.
  • the passive element 6 is conductively bonded to the pad 331 via a conductive bonding material 76 .
  • the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8, as in the second embodiment.
  • the passive element 6 disposed on the back surface 312 is also covered with the sealing resin 8.
  • the electronic components arranged on the back surface 312 are not limited to the passive element 6; for example, the driving device 5 may be arranged on the back surface 312.
  • the semiconductor device A3 since the semiconductor device A3 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense. , can be compatible.
  • the semiconductor device A3 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A3, since the passive elements 6 can be arranged on both sides of the wiring board 3, more passive elements 6 can be mounted. Furthermore, when the passive elements 6 mounted on the wiring board 3 do not change, the shape of the wiring board 3 viewed in the thickness direction z can be made smaller by arranging the passive elements 6 on both sides. Thereby, the semiconductor device A3 can be downsized.
  • FIG. 11 is a diagram for explaining a semiconductor device A4 according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view showing the semiconductor device A4, and corresponds to FIG. 5.
  • the semiconductor device A4 according to the fourth embodiment differs from the first embodiment in the arrangement method of the wiring board 2 and the wiring board 3.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to third embodiments described above may be combined arbitrarily.
  • the wiring board 2 has a larger dimension in the first direction y than that of the semiconductor device A1.
  • the wiring board 3 is disposed on the first side z1 of the wiring board 2 in the thickness direction z and closer to the second side y2 of the wiring board 2 in the first direction y.
  • the entire wiring board 3 overlaps the wiring board 2 when viewed in the thickness direction z.
  • the wiring board 3 does not include the back conductive portion 33, and the back surface 312 of the base material 31 is joined to the main surface 211 of the base material 21 of the wiring board 2.
  • the semiconductor device A4 since the semiconductor device A4 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A4 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, in the semiconductor device A4, since the wiring board 2 has a large dimension in the first direction y, the area of the back conductive portion 23 exposed from the resin back surface 82 is also large. Thereby, the semiconductor device A4 can more efficiently radiate heat transferred from the semiconductor chip 4 to the wiring board 2 to the outside.
  • FIG. 12 is a diagram for explaining a semiconductor device A5 according to a fifth embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing the semiconductor device A5, and is a partially enlarged view of the diagram corresponding to FIG. Note that in FIG. 12, the sealing resin 8 is omitted.
  • the semiconductor device A5 according to the fifth embodiment differs from the first embodiment in that a thermistor is also mounted on the wiring board 2. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to fourth embodiments described above may be combined arbitrarily.
  • the semiconductor device A5 further includes a thermistor 6c.
  • the thermistor 6c is mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21.
  • the main surface conductive portion 22 of the wiring board 2 includes two pads 221a.
  • the two pads 221a are arranged in the x direction at the center of the main surface 211 of the base material 21 in the second direction x, at the end of the second side y2 in the first direction y, and spaced apart from each other in the x direction.
  • the thermistor 6c straddles the two pads 221a and is electrically connected to each pad 221a.
  • two wires 75 are further provided.
  • the wire 75 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 75 are not limited.
  • Each wire 75 is electrically connected to the pad 221a and the pad 321 of the main surface conductive portion 32, respectively.
  • the pads 321 to which each wire 75 is bonded are electrically connected to the leads 15 via the pads 321 electrically connected by wiring 322, respectively. Note that the layout of the main surface conductive portion 32 is not described.
  • a predetermined current is passed through the thermistor 6c, and the thermistor 6c outputs a voltage signal according to the temperature of the wiring board 2.
  • the semiconductor device A5 since the semiconductor device A5 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A5 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, since the semiconductor device A5 includes the thermistor 6c, the temperature of the wiring board 2 can be detected.
  • the semiconductor device A5 includes only one thermistor 6c for detecting the temperature of the wiring board 2, but the present invention is not limited to this.
  • the semiconductor device A5 may include, for example, four thermistors 6c, and each thermistor 6c may be arranged adjacent to the semiconductor chip 4. In this case, each thermistor 6c can detect the temperature of the adjacent semiconductor chip 4.
  • the semiconductor device according to the present disclosure is not limited to the embodiments described above.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in design in various ways.
  • the present disclosure includes the embodiments described in the appendix below.
  • a first base material (21) having a first main surface (211) and a first back surface (212) facing oppositely to each other in the thickness direction (z); a first main surface conductive part (22) having electrical conductivity disposed on the first main surface; a second base material (31) having a second main surface (311) facing the same side as the first main surface in the thickness direction and a second back surface (312) facing the same side as the first back surface; a second main surface conductive part (32) having electrical conductivity disposed on the second main surface; a switching element (4) disposed on the first main surface and electrically connected to the first main surface conductive part; a drive device (5) disposed on the second main surface, electrically connected to the second main surface conductive part, and driving the switching element; a sealing resin (8) that covers at least a portion of the first base material and the second base material, and the entire switching element and the drive device; A semiconductor device (A1) comprising: Appendix 2.
  • the semiconductor device according to any one of appendices 1 to 6, wherein the second base material is disposed in a first direction (y) perpendicular to the thickness direction with respect to the first base material.
  • Appendix 8. further comprising a second back conductive portion (33) having conductivity disposed on the second back surface, The semiconductor device according to appendix 7, wherein the second back conductive portion is exposed from the sealing resin.
  • Appendix 9. (Third embodiment, FIG. 10) further comprising a backside electronic component (6) disposed on the second backside, The semiconductor device according to appendix 7, wherein the back side electronic component is covered with the sealing resin.
  • Appendix 10. (Fourth embodiment, FIG. 11) 7.
  • A1, A2, A3, A4, A5 Semiconductor device 1, 11, 12, 15, 16: Lead 111: Joint portion 111a: Main surface 111b: Back surface 112: Projecting portion 113: Inclined connection portion 114: Parallel connection portion 151: Joint portion 151a: Main surface 151b: Back surface 152: Protruding portion 153: Slanted connection portion 154: Parallel connection portion 2: Wiring board 21: Base material 211: Main surface 212: Back surface 22: Main surface conductive portion 221, 221a: Pad 222 : Wiring 23: Back conductive part 3: Wiring board 31: Base material 311: Main surface 312: Back surface 32: Main surface conductive part 321: Pad 322: Wiring 33: Back conductive part 331: Pad 332: Wiring 4: Semiconductor chip 41 : Element principal surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5: Drive device 6: Passive element 6a: Shunt resistor 6b, 6c: Thermistor 7,

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

La présente invention concerne un dispositif à semi-conducteur qui comprend : un premier substrat ayant une première surface principale ; une partie conductrice de la première surface principale disposée sur la première surface principale ; un second substrat ayant une seconde surface principale ; une partie conductrice de la seconde surface principale disposée sur la seconde surface principale ; un élément de commutation disposé sur la première surface principale et connecté de manière conductrice à la partie conductrice de la première surface principale ; un dispositif de commande disposé sur la seconde surface principale et connecté de manière conductrice à la partie conductrice de la seconde surface principale, et qui commande l'élément de commutation ; et une résine d'étanchéité qui recouvre au moins une partie du premier substrat et du second substrat, et la totalité de l'élément de commutation et du dispositif de commande.
PCT/JP2023/018745 2022-06-13 2023-05-19 Dispositif à semi-conducteur WO2023243306A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2022-095181 2022-06-13
JP2022095181 2022-06-13

Publications (1)

Publication Number Publication Date
WO2023243306A1 true WO2023243306A1 (fr) 2023-12-21

Family

ID=89191063

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2023/018745 WO2023243306A1 (fr) 2022-06-13 2023-05-19 Dispositif à semi-conducteur

Country Status (1)

Country Link
WO (1) WO2023243306A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098223A (ja) * 1995-06-16 1997-01-10 Mitsubishi Electric Corp 半導体パワーモジュールおよびその製造方法
JP2011054625A (ja) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd 回路装置
JP2013058726A (ja) * 2011-08-12 2013-03-28 Sanyo Electric Co Ltd 実装基板および実装基板を用いた回路装置
JP2013074254A (ja) * 2011-09-29 2013-04-22 Mitsubishi Electric Corp 半導体装置及びその製造方法
WO2014064822A1 (fr) * 2012-10-26 2014-05-01 株式会社日立産機システム Module semi-conducteur de puissance et dispositif de conversion de puissance l'utilisant
WO2015174198A1 (fr) * 2014-05-13 2015-11-19 三菱電機株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JP2022053848A (ja) * 2020-09-25 2022-04-06 富士電機株式会社 半導体装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098223A (ja) * 1995-06-16 1997-01-10 Mitsubishi Electric Corp 半導体パワーモジュールおよびその製造方法
JP2011054625A (ja) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd 回路装置
JP2013058726A (ja) * 2011-08-12 2013-03-28 Sanyo Electric Co Ltd 実装基板および実装基板を用いた回路装置
JP2013074254A (ja) * 2011-09-29 2013-04-22 Mitsubishi Electric Corp 半導体装置及びその製造方法
WO2014064822A1 (fr) * 2012-10-26 2014-05-01 株式会社日立産機システム Module semi-conducteur de puissance et dispositif de conversion de puissance l'utilisant
WO2015174198A1 (fr) * 2014-05-13 2015-11-19 三菱電機株式会社 Dispositif à semi-conducteur et son procédé de fabrication
JP2022053848A (ja) * 2020-09-25 2022-04-06 富士電機株式会社 半導体装置

Similar Documents

Publication Publication Date Title
KR102585450B1 (ko) 브레이징된 전기 전도성 층을 포함하는 칩 캐리어를 구비한 몰딩된 패키지
WO2021251126A1 (fr) Dispositif à semi-conducteurs
US7005734B2 (en) Double-sided cooling isolated packaged power semiconductor device
WO2021210402A1 (fr) Dispositif à semi-conducteurs
CN108735692B (zh) 半导体装置
US20080029875A1 (en) Hermetically sealed semiconductor device module
US20230163078A1 (en) Semiconductor device
WO2021200337A1 (fr) Dispositif électronique
WO2021200336A1 (fr) Dispositif électronique
JP2015005681A (ja) 半導体装置及びその製造方法
JP7238330B2 (ja) 半導体装置及び半導体装置の製造方法
JP2021190505A (ja) 半導体装置
JP2017107937A (ja) 電力用半導体装置
CN113228265A (zh) 半导体组件的电路构造
WO2021176996A1 (fr) Dispositif à semiconducteur et procédé de fabrication de dispositif à semiconducteur
JPH0738013A (ja) 複合ベース部材及び電力用半導体装置
JP2021158232A (ja) 半導体モジュール
JP2735912B2 (ja) インバータ装置
WO2021187018A1 (fr) Dispositif à semi-conducteur
WO2023243306A1 (fr) Dispositif à semi-conducteur
JP2019212809A (ja) 半導体装置
WO2021182016A1 (fr) Dispositif à semi-conducteur
JPH09213877A (ja) マルチチップモジュール半導体装置
WO2020184383A1 (fr) Dispositif semi-conducteur
WO2023053823A1 (fr) Dispositif à semi-conducteurs

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 23823607

Country of ref document: EP

Kind code of ref document: A1