WO2023243306A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2023243306A1
WO2023243306A1 PCT/JP2023/018745 JP2023018745W WO2023243306A1 WO 2023243306 A1 WO2023243306 A1 WO 2023243306A1 JP 2023018745 W JP2023018745 W JP 2023018745W WO 2023243306 A1 WO2023243306 A1 WO 2023243306A1
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WO
WIPO (PCT)
Prior art keywords
main surface
semiconductor device
base material
conductive portion
wiring board
Prior art date
Application number
PCT/JP2023/018745
Other languages
French (fr)
Japanese (ja)
Inventor
昌明 松尾
開人 井上
英夫 原
Original Assignee
ローム株式会社
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Publication of WO2023243306A1 publication Critical patent/WO2023243306A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure relates to a semiconductor device.
  • IPM Intelligent Power Module
  • Such a semiconductor device includes a plurality of semiconductor chips, a plurality of electrode sections, a heat dissipation layer, and a sealing resin section (see Patent Document 1).
  • a semiconductor chip is placed on a die pad portion of one of the electrode portions.
  • the plurality of electrode portions serve as conduction paths that connect the semiconductor chip to the outside.
  • Semiconductor chips include LSI chips such as control ICs.
  • An LSI chip has input/output for multiple types of control signals. As the number of control signals increases, it is necessary to increase the number of conduction paths to the LSI chip, but if these conduction paths are constructed from multiple electrode sections as in the past, the integration of semiconductor devices will become even higher. It may become difficult.
  • An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. Particularly, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that enables even higher integration.
  • a semiconductor device provided by a first aspect of the present disclosure includes a first base material having a first main surface and a first back surface facing opposite to each other in the thickness direction, and a first base material disposed on the first main surface.
  • a second base material having a first main surface conductive portion having conductivity, a second main surface facing the same side as the first main surface in the thickness direction, and a second back surface facing the same side as the first back surface.
  • a second main surface conductive part having electrical conductivity disposed on the second main surface; a switching element disposed on the first main surface and electrically connected to the first main surface conductive part; a driving device disposed on the second main surface, electrically connected to the second main surface conductive portion, and driving the switching element; and at least a portion of the first base material and the second base material. and a sealing resin that covers the entire switching element and the drive device.
  • FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure.
  • FIG. 2 is a plan view showing the semiconductor device of FIG. 1.
  • FIG. 3 is a plan view showing the semiconductor device of FIG. 1, and is a view through the sealing resin.
  • FIG. 4 is a bottom view showing the semiconductor device of FIG. 1.
  • FIG. 5 is a cross-sectional view taken along line VV in FIG. 3.
  • FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. 7 is a plan view showing each wiring board of the semiconductor device of FIG. 1.
  • FIG. 8 is a flowchart showing one step of an example of the method for manufacturing the semiconductor device of FIG.
  • FIG. 9 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, and is a view through a sealing resin.
  • a thing A is formed on a thing B and "a thing A is formed on a thing B” mean “a thing A is formed on a thing B” unless otherwise specified.
  • "something A is placed on something B” and “something A is placed on something B” mean "something A is placed on something B” unless otherwise specified.
  • First embodiment: 1 to 7 show an example of a semiconductor device according to the present disclosure.
  • the semiconductor device A1 of this embodiment includes a plurality of leads 1, a wiring board 2, a wiring board 3, a plurality of semiconductor chips 4, a plurality of drive devices 5, a plurality of passive elements 6, a plurality of wires 7, and a sealing resin 8. It is equipped with In this embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used for applications such as air conditioners and motor control equipment, for example.
  • IPM Intelligent Power Module
  • FIG. 1 is a perspective view showing a semiconductor device A1.
  • FIG. 2 is a plan view showing the semiconductor device A1.
  • FIG. 3 is a plan view showing the semiconductor device A1, and is a view through the sealing resin 8. As shown in FIG. In addition, in FIG. 3, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line).
  • FIG. 4 is a bottom view showing the semiconductor device A1.
  • FIG. 5 is a cross-sectional view taken along line VV in FIG. 3.
  • FIG. 6 is a partially enlarged view of FIG. 5.
  • FIG. 7 is a plan view showing the wiring board 2 and the wiring board 3.
  • the thickness direction of the wiring board 2 is referred to as the thickness direction z
  • the direction along one side of the wiring board 2 perpendicular to the thickness direction z is referred to as the first direction y
  • the direction perpendicular to the thickness direction z and the first direction y is the second direction x.
  • the shape and dimensions of the semiconductor device A1 are not limited.
  • the wiring board 2 is mounted with a plurality of semiconductor chips 4 and a plurality of passive elements 6 (shunt resistors 6a to be described later), and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the first side y1 in the first direction y. has been done.
  • the plurality of semiconductor chips 4 are power transistors
  • the wiring board 2 is a power section board on which a power circuit is arranged.
  • the wiring board 2 includes a base material 21, a main surface conductive portion 22, and a back surface conductive portion 23.
  • the base material 21 is plate-shaped, and has a rectangular shape that is elongated in the second direction x when viewed in the thickness direction z (that is, in plan view).
  • the thickness dimension (dimension in the thickness direction z) of the base material 21 is, for example, about 0.1 mm to 1.0 mm. Note that the dimensions of the base material 21 are not limited.
  • the base material 21 is made of an insulating material.
  • the constituent material of the base material 21 is, for example, ceramics with excellent thermal conductivity, and in this embodiment, includes aluminum nitride (AlN). Note that the constituent material of the base material 21 is not limited to this.
  • the base material 21 has a main surface 211 and a back surface 212.
  • the main surface 211 and the back surface 212 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 211 is a surface facing the first side z1 in the thickness direction z.
  • a main surface conductive portion 22 is arranged on the main surface 211, and a plurality of semiconductor chips 4, a plurality of passive elements 6, and a plurality of leads 1 are mounted on the main surface 211.
  • the back surface 212 is a surface facing the second side z2 in the thickness direction z. On the back surface 212, a back conductive portion 23 is arranged.
  • the shapes of the main surface 211 and the back surface 212 are both rectangular. Note that the shape of the base material 21 is not limited.
  • the main surface conductive portion 22 is arranged on the main surface 211 of the base material 21.
  • the main surface conductive portion 22 is made of a conductive material.
  • the constituent material of the main surface conductive portion 22 is not particularly limited, and examples thereof include copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described.
  • the thickness dimension (dimension in the thickness direction z) T1 (see FIG. 6) of the main surface conductive portion 22 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness dimension T1 is approximately 0.25 mm. Note that the thickness dimension T1 is not limited.
  • the main surface conductive portion 22 includes a plurality of pads 221 and a plurality of wirings 222, as shown in FIG. 7, for example.
  • Each pad 221 has a rectangular shape, for example, and has the semiconductor chip 4, the passive element 6, the lead 1 (lead 11 described later), or the wire 7 (wires 71 and 72 described later) electrically connected.
  • the shape of the pad 221 is not limited.
  • Each pad 221 is spaced apart from each other.
  • Each of the plurality of wirings 222 is a conduction path that connects one of the pads 221 and one of the pads 221 to conduct them.
  • the shape of each wiring 222 is not limited.
  • the back conductive portion 23 is arranged on the back surface 212 of the base material 21.
  • the back conductive portion 23 is made of a conductive material.
  • the constituent material of the back conductive portion 23 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these.
  • the constituent material of the back surface conductive portion 23 is copper (Cu), as is the case with the main surface conductive portion 22.
  • the thickness dimension (dimension in the thickness direction z) of the back conductive portion 23 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more.
  • the thickness of the back conductive portion 23 is approximately 0.25 mm, similar to the thickness T1, but is not limited thereto.
  • the back surface conductive portion 23 covers the entire surface of the back surface 212. Note that the shape of the back conductive portion 23 is not limited. The back conductive portion 23 is exposed from the sealing resin 8, as shown in FIG.
  • the wiring board 2 is formed from a so-called DBC (Direct Bonded Copper) board.
  • the DBC board is a board in which copper foil is bonded to both sides of a ceramic plate.
  • the wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23.
  • the method for forming the wiring board 2 is not limited. Regardless of which method is used, it is necessary to form a copper layer of 0.2 mm or more.
  • the constituent material of the main surface conductive portion 22 and the back surface conductive portion 23 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
  • the wiring board 3 has a plurality of drive devices 5 and a plurality of passive elements 6 mounted thereon, and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the second side y2 in the first direction y.
  • the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y, and the wiring board 3 is located on the second side y2 of the first direction y with respect to the wiring board 2.
  • the wiring board 3 is a control unit board on which a control circuit for controlling the power circuit arranged on the wiring board 2 is arranged.
  • the wiring board 3 includes a base material 31, a main surface conductive portion 32, and a back surface conductive portion 33.
  • the base material 31 is plate-shaped and has a rectangular shape that is long in the second direction x when viewed in the thickness direction z.
  • the thickness dimension (dimension in the thickness direction z) of the base material 31 is, for example, about 0.1 mm to 1.0 mm, which is about the same as that of the base material 21. Note that the dimensions of the base material 31 are not limited.
  • the base material 31 is made of an insulating material.
  • the constituent material of the base material 31 is, for example, ceramics, and in this embodiment contains alumina (Al 2 O 3 ).
  • the base material 31 does not require as much thermal conductivity as the base material 21.
  • the base material 21 is made of ceramics made of aluminum nitride, and has higher thermal conductivity than the base material 31 made of ceramics made of alumina.
  • the constituent material of the base material 31 is not limited to this.
  • the constituent material of the base material 21 and the constituent material of the base material 31 may be the same.
  • the base material 31 has a main surface 311 and a back surface 312.
  • the main surface 311 and the back surface 312 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 311 is a surface facing the first side z1 in the thickness direction z.
  • a main surface conductive portion 32 is arranged on the main surface 311, and a plurality of drive devices 5, a plurality of passive elements 6, and a plurality of leads 1 are mounted thereon.
  • the back surface 312 is a surface facing the second side z2 in the thickness direction z.
  • On the back surface 312, a back conductive portion 33 is arranged.
  • the shapes of the main surface 311 and the back surface 312 are both rectangular. Note that the shape of the base material 31 is not limited.
  • the main surface conductive portion 32 is arranged on the main surface 311 of the base material 31.
  • the main surface conductive portion 32 is made of a conductive material.
  • the constituent material of the main surface conductive portion 32 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described.
  • the thickness dimension (dimension in the thickness direction z) T2 (see FIG. 6) of the main surface conductive part 32 is smaller than the thickness dimension T1, and has a thickness that allows finer processing than the main surface conductive part 22 by etching. be. In this embodiment, the thickness dimension T2 is, for example, about 0.1 mm. Note that the thickness dimension T2 is not limited.
  • the main surface conductive portion 32 includes a plurality of pads 321 and a plurality of wirings 322, as shown in FIG. 7, for example.
  • Each pad 321 has a rectangular shape, for example, and has a driving device 5, a passive element 6, a lead 1 (a lead 15 described later), or a wire 7 (wires 73 and 74 described later) electrically connected.
  • the shape of the pad 321 is not limited.
  • Each pad 321 is spaced apart from each other.
  • Each of the plurality of wirings 322 is a conduction path that connects one of the pads 321 and one of the pads 321 to conduct the two.
  • the shape of each wiring 322 is not limited. Note that a conductive plate-like member may be placed on the pad 321 to which the wire 7 is bonded in order to protect the pad 321 and the base material 31 from impact caused by wire bonding.
  • the back surface conductive part 33 is arranged on the back surface 312 of the base material 31.
  • the back conductive portion 33 is made of a conductive material.
  • the constituent material of the back conductive portion 33 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these.
  • the constituent material of the back conductive portion 33 is copper (Cu), as is the case with the main conductive portion 32 .
  • the thickness dimension (dimension in the thickness direction z) of the back conductive portion 33 is approximately the same as the thickness dimension T2, and is, for example, approximately 0.1 mm. Note that the thickness dimension of the back conductive portion 33 is not limited to this. In this embodiment, the back conductive portion 33 covers the entire back surface 312.
  • the shape of the back conductive portion 33 is not limited.
  • the back conductive portion 33 is exposed from the sealing resin 8, as shown in FIG.
  • the wiring board 3 does not need to include the back conductive portion 33.
  • the back surface 312 of the base material 31 may be exposed from the sealing resin 8, or the entire wiring board 3 may be covered with the sealing resin 8 (the wiring board 3 is not exposed from the sealing resin 8). good.
  • the wiring board 3 is formed from a so-called DBC board.
  • the DBC board is a board in which copper foil is bonded to both sides of a ceramic plate.
  • the copper foil of the DBC board is thinner than the copper foil of the DBC board for forming the wiring board 2.
  • the wiring board 3 is formed by patterning copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33.
  • the method of forming the wiring board 3 is not limited.
  • the wiring board 3 may be formed from a so-called DPC (Direct Plated Copper) board, which is a ceramic plate with copper plating on both sides.
  • DPC Direct Plated Copper
  • the wiring board 3 may be formed by disposing copper paste on both sides of a ceramic plate and firing the same.
  • the constituent material of the main surface conductive portion 32 and the back surface conductive portion 33 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
  • the plurality of leads 1 are configured to include metal.
  • the metal constituting the lead 1 is not particularly limited, and includes, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or alloys thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy). etc.).
  • the plurality of leads 1 may be plated with nickel (Ni).
  • the plurality of leads 1 may be formed, for example, by pressing a metal mold against a metal plate, or by patterning a metal plate by etching. Note that the method for forming the plurality of leads 1 is not limited.
  • the thickness of each lead 1 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. Each lead 1 is spaced apart from each other.
  • the plurality of leads 1 each include a plurality of leads 11, leads 12, leads 15, and leads 16.
  • the leads 11 and 12 constitute a conductive path to the semiconductor chip 4.
  • Leads 15 and 16 constitute a conduction path to drive device 5 or passive element 6.
  • the plurality of leads 11 are each arranged on the base material 21, and in this embodiment, are arranged on the main surface 211 closer to the first side y1 in the first direction y. Each lead 11 is bonded to a pad 221 of the main surface conductive portion 22 via a conductive bonding material 76 .
  • the conductive bonding material 76 may be any material that can conductively bond the leads 11 to the pads 221, such as silver paste, copper paste, solder, or the like. Note that the conductive bonding material 76 is not limited.
  • Each lead 11 is electrically connected to the semiconductor chip 4 via the main surface conductive portion 22 and the wire 71.
  • the plurality of leads 1 includes three leads 11. Note that the number and arrangement of leads 11 are not limited.
  • the structure of the lead 11 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 11 will be divided into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114.
  • the joint portion 111 has a main surface 111a and a back surface 111b.
  • the main surface 111a and the back surface 111b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 111a is a surface facing the first side z1 in the thickness direction z.
  • the back surface 111b is a surface facing the second side z2 in the thickness direction z.
  • the back surface 111b is bonded to the pad 221 of the main surface conductive portion 22 by a conductive bonding material 76.
  • the inclined connection portion 113 and the parallel connection portion 114 are covered with the sealing resin 8.
  • the inclined connection part 113 is connected to the joint part 111 and the parallel connection part 114 and is inclined with respect to the joint part 111 and the parallel connection part 114.
  • the parallel connecting portion 114 is connected to the inclined connecting portion 113 and the protruding portion 112 and is parallel to the joining portion 111 .
  • the protruding portion 112 is connected to the end of the parallel connection portion 114 and is a portion of the lead 11 that protrudes from the sealing resin 8 .
  • the protruding portion 112 protrudes to the side opposite to the joining portion 111 (y1 side) in the first direction y.
  • the protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent toward the side toward which the main surface 111a of the joint portion 111 faces in the thickness direction z.
  • the plurality of leads 12 are not arranged on the base material 21, but are arranged on the first side y1 of the base material 21 in the first direction y.
  • Each lead 12 does not include a portion corresponding to the joint portion 111 and the inclined connection portion 113 of the lead 11, but only includes a portion corresponding to the protrusion portion 112 and the parallel connection portion 114.
  • a wire 72 is electrically connected to a portion corresponding to the parallel connection portion 114.
  • Each lead 12 is electrically connected to the semiconductor chip 4 or the passive element 6 via the wire 72 and the main surface conductive portion 22.
  • the plurality of leads 1 includes six leads 12. Note that the configuration, number, and arrangement of the leads 12 are not limited to this.
  • the plurality of leads 15 are each arranged on the base material 31, and in this embodiment, are arranged on the main surface 311 closer to the second side y2 in the first direction y. Each lead 15 is bonded to a pad 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Each lead 15 is electrically connected to the drive device 5 or the passive element 6 via the main surface conductive portion 22 . In this embodiment, the plurality of leads 1 includes 18 leads 15. Note that the number and arrangement of leads 15 are not limited.
  • the structure of the lead 15 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 15 will be divided into a joining portion 151, a protruding portion 152, an inclined connecting portion 153, and a parallel connecting portion 154.
  • the joint portion 151 has a main surface 151a and a back surface 151b.
  • the main surface 151a and the back surface 151b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main surface 151a is a surface facing the first side z1 in the thickness direction z.
  • the back surface 151b is a surface facing the second side z2 in the thickness direction z.
  • the back surface 151b is bonded to the pad 321 of the main surface conductive portion 32 by a conductive bonding material 76.
  • the inclined connection portion 153 and the parallel connection portion 154 are covered with the sealing resin 8.
  • the inclined connection portion 153 is connected to the joint portion 151 and the parallel connection portion 154 and is inclined with respect to the joint portion 151 and the parallel connection portion 154.
  • the parallel connecting portion 154 is connected to the inclined connecting portion 153 and the protruding portion 152 and is parallel to the joining portion 151.
  • the protruding portion 152 is connected to the end of the parallel connection portion 154 and is a portion of the lead 15 that protrudes from the sealing resin 8 .
  • the protruding portion 152 protrudes to the side opposite to the joining portion 151 (y2 side) in the first direction y.
  • the protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent toward the side toward which the main surface 151a of the joint portion 151 faces in the thickness direction z.
  • the plurality of leads 16 are not arranged on the base material 31, but are arranged on the first side x1 or the second side x2 of the base material 31 in the second direction x.
  • Each lead 16 has a similar configuration to lead 15.
  • a wire 74 is conductively bonded to a portion corresponding to the bonding portion 151 instead of being bonded to the pad 321 of the main surface conductive portion 32 .
  • Each lead 16 is electrically connected to the drive device 5 and the passive element 6 via the wire 74 and the main surface conductive portion 32.
  • the plurality of leads 1 includes four leads 16. Note that the configuration, number, and arrangement of the leads 16 are not limited to this.
  • the plurality of semiconductor chips 4 are switching elements and power transistors that control power.
  • the semiconductor chip 4 is constructed using a semiconductor material mainly composed of SiC (silicon carbide).
  • the semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like.
  • the semiconductor chip 4 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Note that the semiconductor chip 4 is not limited to a MOSFET, and may be an IGBT (Insulated Gate Bipolar Transistor) or the like. Although this embodiment shows a case where the semiconductor device A1 includes four semiconductor chips 4, this is just an example, and the number of semiconductor chips 4 is not limited.
  • Each semiconductor chip 4 has a rectangular plate shape when viewed in the thickness direction z, and includes an element main surface 41, an element rear surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45.
  • the element main surface 41 and the element back surface 42 face opposite sides in the thickness direction z.
  • the element main surface 41 is a surface facing the first side z1 in the thickness direction z.
  • the back surface 42 of the element is a surface facing the second side z2 in the thickness direction z.
  • a source electrode 43 and a gate electrode 44 are arranged on the main surface 41 of the element.
  • a drain electrode 45 is arranged on the back surface 42 of the element. Note that the shapes and arrangement of the source electrode 43, gate electrode 44, and drain electrode 45 are not limited.
  • Each semiconductor chip 4 is mounted on the wiring board 2, as shown in FIGS. 3 and 5.
  • Each semiconductor chip 4 is arranged on the main surface 211 of the base material 21.
  • the four semiconductor chips 4 are arranged side by side in the second direction x on the main surface 211 closer to the second side y2 in the first direction y.
  • the arrangement position of each drive device 5 is not limited.
  • each semiconductor chip 4 is bonded to a pad 221 of the main surface conductive portion 22 by a conductive bonding material 76 with the element back surface 42 facing the main surface 211.
  • the drain electrode 45 of the semiconductor chip 4 is electrically connected to the pad 221 by the conductive bonding material 76 .
  • the source electrode 43 of the semiconductor chip 4 is electrically connected to the adjacent pad 221 by a wire 71.
  • the semiconductor device A1 includes two bridge circuits each made up of two semiconductor chips 4.
  • the source electrode 43 and gate electrode 44 of the semiconductor chip 4 are electrically connected to the driving device 5 via the wire 73 and the main surface conductive portion 32 of the wiring board 3, respectively.
  • Each of the plurality of drive devices 5 is a so-called gate driver that outputs a drive signal to drive the corresponding semiconductor chip 4.
  • the drive device 5 is an insulated gate driver in which a low voltage side into which a signal is input is insulated from a high voltage side through which a drive signal is output.
  • the driving device 5 is not limited to an insulated gate driver.
  • the semiconductor device A1 includes four drive devices 5 corresponding to the number of semiconductor chips 4.
  • Each drive device 5 is mounted on the wiring board 3, as shown in FIGS. 3 and 5.
  • Each drive device 5 is arranged on the main surface 311 of the base material 31.
  • the four drive devices 5 are arranged at the center (or approximately at the center) of the main surface 311 in the first direction y and in line in the second direction x. Note that the arrangement position of each drive device 5 is not limited.
  • the drive device 5 is an SOP (Small Outline Package) type package.
  • the drive device 5 includes a plurality of terminals that protrude and extend on both sides of the first direction y. These terminals are conductively bonded to the pads 321 of the main surface conductive portion 32 by a conductive bonding material 76 .
  • the package type of the drive device 5 is not limited to the SOP type, and may be other types such as a QFP (Quad Flat Package) type or an SOJ (Small Outline J-lead Package) type. Further, the size, shape, number of terminals, etc. of the drive device 5 are not limited. Further, instead of the drive device 5, a drive chip may be directly disposed on the wiring board 3. The drive device 5 outputs a drive signal to the gate electrode 44 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73. Further, the driving device 5 receives the potential of the source electrode 43 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73.
  • the plurality of passive elements 6 are mounted on the wiring board 2 or the wiring board 3, as shown in FIGS. 3 and 5. Each passive element 6 is disposed on the main surface 211 of the base material 21 or the main surface 311 of the base material 31, and is electrically connected to the pad 221 of the main surface conductive part 22 or the pad 321 of the main surface conductive part 32. ing.
  • the passive element 6 is, for example, a resistor, a capacitor, a coil, a diode, or the like. Passive element 6 includes two shunt resistors 6a and a thermistor 6b.
  • the two shunt resistors 6a are mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21. Each shunt resistor 6a straddles the two pads 221 of the main surface conductive portion 22 and is electrically connected to each pad 221. An output current of a bridge circuit composed of two semiconductor chips 4 flows through each shunt resistor 6a, and a potential difference between both terminals is output.
  • the thermistor 6b is mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31.
  • the thermistor 6b straddles the two pads 321 of the main surface conductive portion 32 and is electrically connected to each pad 321.
  • Each pad 321 to which the thermistor 6b is bonded is electrically connected to the lead 15 via the pad 321 electrically connected by a wiring 322.
  • a predetermined current is passed through the thermistor 6b, and the thermistor 6b outputs a voltage signal according to the temperature of the wiring board 3.
  • Each passive element 6 is mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31. Each passive element 6 is electrically connected to a pad 321 of the main surface conductive portion 32 and electrically connected to the drive device 5 via the wiring 322 and the pad 321. Note that the type, arrangement position, and number of each passive element 6 are not limited.
  • the plurality of wires 7 each include a plurality of wires 71, 72, 73, and 74.
  • the plurality of wires 71 are electrically connected to the source electrode 43 of the semiconductor chip 4 and the pad 221.
  • each semiconductor chip 4 and the pad 221 are connected by two wires 71, but the number of wires 71 connecting each semiconductor chip 4 and the pad 221 is not limited.
  • the wire 71 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 71 are not limited.
  • the plurality of wires 72 are electrically connected to the pads 221 of the main surface conductive portion 22 and the leads 12 .
  • the number of wires 72 connecting pads 221 and leads 12 is not limited.
  • the wire 72 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 72 are not limited.
  • the plurality of wires 73 are electrically connected to the source electrode 43 or gate electrode 44 of the semiconductor chip 4 and the pad 321 of the main surface conductive portion 32 of the wiring board 3.
  • each semiconductor chip 4 and the pad 321 are connected by one wire 73, but the number of wires 73 connecting each semiconductor chip 4 and the pad 321 is not limited.
  • the wire 73 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 73 are not limited.
  • the plurality of wires 74 are electrically connected to the pads 321 of the main surface conductive portion 32 of the wiring board 3 and the leads 16 .
  • each pad 321 and each lead 16 are connected by one wire 74, but the number of wires 74 connecting each pad 321 and each lead 16 is not limited.
  • the wire 74 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 74 are not limited.
  • the sealing resin 8 seals a plurality of semiconductor chips 4 , a plurality of drive devices 5 , a plurality of passive elements 6 , a plurality of wires 7 , a portion of each of the plurality of leads 1 , and a portion of the wiring board 2 and the wiring board 3 . covering at least part of each part.
  • the material of the sealing resin 8 is not particularly limited, and insulating materials such as epoxy resin and silicone gel may be used as appropriate.
  • the sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83.
  • the main resin surface 81 and the resin back surface 82 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z.
  • the main resin surface 81 is a surface facing the first side z1 in the thickness direction z.
  • the resin back surface 82 is a surface facing the second side z2 in the thickness direction z.
  • Each resin side surface 83 is connected to the resin main surface 81 and the resin back surface 82, and faces the second direction x or the first direction y. As shown in FIG.
  • each of the plurality of leads 11 and leads 12 protrudes from the resin side surface 83 facing the first side y1 in the first direction y of the sealing resin 8.
  • Each of the plurality of leads 15 and leads 16 protrudes from the resin side surface 83 facing the second side y2 in the first direction y of the sealing resin 8.
  • the manufacturing method of this example includes a substrate forming process (step S1), a lead frame bonding process (step S2), a semiconductor chip mounting process (step S3), a drive device mounting process (step S4), a wire
  • the process includes a connecting process (step S5), a resin forming process (step S6), and a frame cutting process (step S7).
  • step S1 two types of DBC substrates are first prepared.
  • One DBC substrate is a substrate in which copper foils having a thickness of T1 are bonded to both sides of an aluminum nitride ceramic plate.
  • the other DBC substrate is a substrate in which copper foil having a thickness of T2 is bonded to both sides of an alumina ceramic plate.
  • the copper foil on one side of each DBC board is patterned by etching.
  • the aluminum nitride DBC substrate becomes the wiring board 2.
  • the patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23.
  • the alumina DBC board becomes the wiring board 3.
  • the patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33.
  • step S2 first, the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y.
  • a conductive bonding paste is placed on a predetermined pad 221 of the main surface conductive portion 22 and a predetermined pad 321 of the main surface conductive portion 32.
  • the conductive bonding paste is, for example, silver paste, copper paste, or solder.
  • a lead frame is prepared.
  • the lead frame includes a plurality of leads 1 and further has a frame to which the plurality of leads 1 are connected. Note that the shape of the lead frame and the like are not limited at all.
  • each of the plurality of leads 11 is made to face a predetermined pad 221 via a conductive bonding paste.
  • each of the plurality of leads 15 is made to face a predetermined pad 321 via a conductive bonding paste.
  • the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. As a result, each lead 11 is bonded to a predetermined pad 221 via the conductive bonding material 76, and each lead 15 is bonded to the pad 321 via the conductive bonding material 76.
  • step S3 first, a conductive bonding paste is placed at a predetermined position of a predetermined pad 221 on the main surface conductive portion 22 of the wiring board 2. Each semiconductor chip 4 is then attached to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the semiconductor chip 4 is bonded to the pad 221 via the conductive bonding material 76. Further, in a similar process, the shunt resistor 6a is bonded to the pad 221 via the conductive bonding material 76.
  • step S4 first, a conductive bonding paste is placed on a predetermined pad 321 of the main surface conductive portion 32 of the wiring board 3. Each terminal of each drive device 5 is then adhered to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the drive device 5 is bonded to the pad 321 via the conductive bonding material 76. Further, the thermistor 6b and other passive elements 6 are bonded to the pad 321 via the conductive bonding material 76 by a similar process.
  • a plurality of wires 71 and 72 are connected.
  • wires made of aluminum (Al) are sequentially connected by, for example, a wedge bonding method.
  • a plurality of wires 71 are obtained.
  • the plurality of wires 73 and 74 are connected.
  • wire materials made of gold (Au) are sequentially connected by, for example, a capillary bonding method.
  • a plurality of wires 72 are obtained.
  • step S6 for example, a part of the lead frame, the wiring boards 2 and 3, each of the plurality of semiconductor chips 4, the driving device 5, the passive element 6, and the wire 7 are surrounded by a mold. Next, a liquid resin material is injected into the space defined by the mold. Next, the sealing resin 8 is obtained by curing this resin material.
  • step S7 the lead frame is cut at an appropriate location exposed from the sealing resin 8. As a result, the plurality of leads 1 are divided from each other. Thereafter, the above-described semiconductor device A1 is obtained by performing a process such as bending the plurality of leads 1 as necessary.
  • the wiring board 3 includes the main surface conductive portion 32 disposed on the main surface 311 of the base material 31.
  • the driving device 5 is electrically connected to the pad 321 of the main surface conductive portion 32 .
  • the conduction path to the drive device 5 can be configured by the main surface conductive portion 32 disposed on the main surface 311 of the base material 31. Therefore, compared to, for example, a case where the conduction path is formed of metal leads, it is possible to make the conduction path thinner and more dense.
  • the semiconductor device A1 includes a wiring board 2 in addition to the wiring board 3.
  • the wiring board 2 includes a main surface conductive portion 22 disposed on the main surface 211 of the base material 21 .
  • the semiconductor chip 4 is bonded to the pad 221.
  • the thickness T1 of the main surface conductive portion 22 is larger than the thickness T2 of the main surface conductive portion 32, and is thick enough to maintain the heat dissipation effect of the heat generated by the semiconductor chip 4.
  • the thickness dimension T2 is smaller than the thickness dimension T1, and is a thickness that allows finer processing by etching.
  • the semiconductor device A1 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense.
  • the wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. Therefore, compared to the case where the main surface conductive portion 22 and the back surface conductive portion 23 are respectively formed on the base material 21, the manufacturing process can be simplified. The same applies to the wiring board 3.
  • the base material 21 of the wiring board 2 is an aluminum nitride ceramic plate.
  • the base material 31 of the wiring board 3 is an alumina ceramic plate. Therefore, the base material 21 has higher thermal conductivity than the base material 31. Thereby, the wiring board 2 can appropriately dissipate the heat generated by the semiconductor chip 4. Further, the material cost of the wiring board 3, which does not require as much heat dissipation as the wiring board 2, can be reduced.
  • the back conductive portion 33 of the wiring board 2 is exposed from the resin back surface 82. Therefore, the heat transmitted from the semiconductor chip 4 to the wiring board 2 can be radiated to the outside more efficiently.
  • the semiconductor device A1 includes a thermistor 6b mounted on the wiring board 3. Therefore, the semiconductor device A1 can detect the temperature of the wiring board 3.
  • the plurality of leads 11 are bonded to the pads 221 of the main surface conductive portion 22 via the conductive bonding material 76. Thereby, the plurality of leads 11 are firmly fixed to the wiring board 2. Further, it is possible to reduce the resistance between the plurality of leads 11 and the main surface conductive portion 22. Further, the plurality of leads 15 are bonded to the pads 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Thereby, the plurality of leads 15 are firmly fixed to the wiring board 3. Furthermore, the resistance between the plurality of leads 15 and the main surface conductive portion 32 can be reduced.
  • the base material 31 does not require as much thermal conductivity as the base material 21, it may be a substrate containing synthetic resin such as glass epoxy resin. That is, the wiring board 3 may be a so-called PCB (Printed Circuit Board) board. Further, the base material 31 may be a multilayer substrate in which a plurality of base materials are laminated.
  • PCB printed Circuit Board
  • FIG. 9 is a diagram for explaining a semiconductor device A2 according to a second embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view showing the semiconductor device A2, and corresponds to FIG. 5.
  • the semiconductor device A2 according to the second embodiment differs from the first embodiment in that the entire wiring board 3 is covered with a sealing resin 8.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment.
  • the wiring board 3 does not include the back conductive portion 33.
  • the wiring board 3 according to this embodiment is formed by etching and patterning the copper foil of a DBC board in which copper foil is bonded to only one side of a ceramic plate. Further, the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8. Unlike the wiring board 2 on which the semiconductor chip 4 is mounted, the wiring board 3 is not required to have much heat dissipation. Therefore, even if the wiring board 3 is not exposed from the resin back surface 82 and its heat dissipation is suppressed, it does not pose much of a problem.
  • the semiconductor device A2 since the semiconductor device A2 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A2 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A2, since the wiring board 3 does not include the back conductive portion 33, material costs can be suppressed.
  • the wiring board 3 is not exposed from the resin back surface 82, but the present invention is not limited to this.
  • the back surface 312 of the base material 31 may be exposed from the resin back surface 82.
  • FIG. 10 is a diagram for explaining a semiconductor device A3 according to a third embodiment of the present disclosure.
  • FIG. 10 is a cross-sectional view showing the semiconductor device A3, and corresponds to FIG. 5.
  • the semiconductor device A3 according to the third embodiment differs from the first embodiment in that the passive element 6 is also arranged on the back surface 312 of the base material 31 of the wiring board 3.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first and second embodiments described above may be combined arbitrarily.
  • the wiring board 3 has passive elements 6 arranged not only on the main surface 311 but also on the back surface 312.
  • the back conductive portion 33 includes pads 331 and wiring 332.
  • the pad 331 and the wiring 332 are formed by patterning the copper foil on the other side of the DBC substrate by etching.
  • the shape of the back conductive portion 33 is not limited.
  • the passive element 6 is conductively bonded to the pad 331 via a conductive bonding material 76 .
  • the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8, as in the second embodiment.
  • the passive element 6 disposed on the back surface 312 is also covered with the sealing resin 8.
  • the electronic components arranged on the back surface 312 are not limited to the passive element 6; for example, the driving device 5 may be arranged on the back surface 312.
  • the semiconductor device A3 since the semiconductor device A3 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense. , can be compatible.
  • the semiconductor device A3 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A3, since the passive elements 6 can be arranged on both sides of the wiring board 3, more passive elements 6 can be mounted. Furthermore, when the passive elements 6 mounted on the wiring board 3 do not change, the shape of the wiring board 3 viewed in the thickness direction z can be made smaller by arranging the passive elements 6 on both sides. Thereby, the semiconductor device A3 can be downsized.
  • FIG. 11 is a diagram for explaining a semiconductor device A4 according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a cross-sectional view showing the semiconductor device A4, and corresponds to FIG. 5.
  • the semiconductor device A4 according to the fourth embodiment differs from the first embodiment in the arrangement method of the wiring board 2 and the wiring board 3.
  • the configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to third embodiments described above may be combined arbitrarily.
  • the wiring board 2 has a larger dimension in the first direction y than that of the semiconductor device A1.
  • the wiring board 3 is disposed on the first side z1 of the wiring board 2 in the thickness direction z and closer to the second side y2 of the wiring board 2 in the first direction y.
  • the entire wiring board 3 overlaps the wiring board 2 when viewed in the thickness direction z.
  • the wiring board 3 does not include the back conductive portion 33, and the back surface 312 of the base material 31 is joined to the main surface 211 of the base material 21 of the wiring board 2.
  • the semiconductor device A4 since the semiconductor device A4 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A4 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, in the semiconductor device A4, since the wiring board 2 has a large dimension in the first direction y, the area of the back conductive portion 23 exposed from the resin back surface 82 is also large. Thereby, the semiconductor device A4 can more efficiently radiate heat transferred from the semiconductor chip 4 to the wiring board 2 to the outside.
  • FIG. 12 is a diagram for explaining a semiconductor device A5 according to a fifth embodiment of the present disclosure.
  • FIG. 12 is a partially enlarged plan view showing the semiconductor device A5, and is a partially enlarged view of the diagram corresponding to FIG. Note that in FIG. 12, the sealing resin 8 is omitted.
  • the semiconductor device A5 according to the fifth embodiment differs from the first embodiment in that a thermistor is also mounted on the wiring board 2. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to fourth embodiments described above may be combined arbitrarily.
  • the semiconductor device A5 further includes a thermistor 6c.
  • the thermistor 6c is mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21.
  • the main surface conductive portion 22 of the wiring board 2 includes two pads 221a.
  • the two pads 221a are arranged in the x direction at the center of the main surface 211 of the base material 21 in the second direction x, at the end of the second side y2 in the first direction y, and spaced apart from each other in the x direction.
  • the thermistor 6c straddles the two pads 221a and is electrically connected to each pad 221a.
  • two wires 75 are further provided.
  • the wire 75 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 75 are not limited.
  • Each wire 75 is electrically connected to the pad 221a and the pad 321 of the main surface conductive portion 32, respectively.
  • the pads 321 to which each wire 75 is bonded are electrically connected to the leads 15 via the pads 321 electrically connected by wiring 322, respectively. Note that the layout of the main surface conductive portion 32 is not described.
  • a predetermined current is passed through the thermistor 6c, and the thermistor 6c outputs a voltage signal according to the temperature of the wiring board 2.
  • the semiconductor device A5 since the semiconductor device A5 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible.
  • the semiconductor device A5 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, since the semiconductor device A5 includes the thermistor 6c, the temperature of the wiring board 2 can be detected.
  • the semiconductor device A5 includes only one thermistor 6c for detecting the temperature of the wiring board 2, but the present invention is not limited to this.
  • the semiconductor device A5 may include, for example, four thermistors 6c, and each thermistor 6c may be arranged adjacent to the semiconductor chip 4. In this case, each thermistor 6c can detect the temperature of the adjacent semiconductor chip 4.
  • the semiconductor device according to the present disclosure is not limited to the embodiments described above.
  • the specific configuration of each part of the semiconductor device according to the present disclosure can be changed in design in various ways.
  • the present disclosure includes the embodiments described in the appendix below.
  • a first base material (21) having a first main surface (211) and a first back surface (212) facing oppositely to each other in the thickness direction (z); a first main surface conductive part (22) having electrical conductivity disposed on the first main surface; a second base material (31) having a second main surface (311) facing the same side as the first main surface in the thickness direction and a second back surface (312) facing the same side as the first back surface; a second main surface conductive part (32) having electrical conductivity disposed on the second main surface; a switching element (4) disposed on the first main surface and electrically connected to the first main surface conductive part; a drive device (5) disposed on the second main surface, electrically connected to the second main surface conductive part, and driving the switching element; a sealing resin (8) that covers at least a portion of the first base material and the second base material, and the entire switching element and the drive device; A semiconductor device (A1) comprising: Appendix 2.
  • the semiconductor device according to any one of appendices 1 to 6, wherein the second base material is disposed in a first direction (y) perpendicular to the thickness direction with respect to the first base material.
  • Appendix 8. further comprising a second back conductive portion (33) having conductivity disposed on the second back surface, The semiconductor device according to appendix 7, wherein the second back conductive portion is exposed from the sealing resin.
  • Appendix 9. (Third embodiment, FIG. 10) further comprising a backside electronic component (6) disposed on the second backside, The semiconductor device according to appendix 7, wherein the back side electronic component is covered with the sealing resin.
  • Appendix 10. (Fourth embodiment, FIG. 11) 7.
  • A1, A2, A3, A4, A5 Semiconductor device 1, 11, 12, 15, 16: Lead 111: Joint portion 111a: Main surface 111b: Back surface 112: Projecting portion 113: Inclined connection portion 114: Parallel connection portion 151: Joint portion 151a: Main surface 151b: Back surface 152: Protruding portion 153: Slanted connection portion 154: Parallel connection portion 2: Wiring board 21: Base material 211: Main surface 212: Back surface 22: Main surface conductive portion 221, 221a: Pad 222 : Wiring 23: Back conductive part 3: Wiring board 31: Base material 311: Main surface 312: Back surface 32: Main surface conductive part 321: Pad 322: Wiring 33: Back conductive part 331: Pad 332: Wiring 4: Semiconductor chip 41 : Element principal surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5: Drive device 6: Passive element 6a: Shunt resistor 6b, 6c: Thermistor 7,

Abstract

This semiconductor device comprises: a first substrate having a first main surface; a first main surface conductive part disposed on the first main surface; a second substrate having a second main surface; a second main surface conductive part disposed on the second main surface; a switching element disposed on the first main surface and conductively connected to the first main surface conductive part; a driving device that is disposed on the second main surface and conductively connected to the second main surface conductive part, and that drives the switching element; and a sealing resin that covers at least part of the first substrate and the second substrate, and the entirety of the switching element and the driving device.

Description

半導体装置semiconductor equipment
　本開示は、半導体装置に関する。 The present disclosure relates to a semiconductor device.
　種々の半導体装置の一つとして、ＩＰＭ（Intelligent Power Module）と称されるものがある。このような半導体装置は、複数の半導体チップと、複数の電極部と、放熱層と、封止樹脂部と、を備えている（特許文献１参照）。半導体チップは、いずれかの電極部のダイパッド部に配置される。複数の電極部が、半導体チップを外部と導通させる導通経路になっている。 One of the various semiconductor devices is one called IPM (Intelligent Power Module). Such a semiconductor device includes a plurality of semiconductor chips, a plurality of electrode sections, a heat dissipation layer, and a sealing resin section (see Patent Document 1). A semiconductor chip is placed on a die pad portion of one of the electrode portions. The plurality of electrode portions serve as conduction paths that connect the semiconductor chip to the outside.
特開２０２０－９８９３８号公報JP2020-98938A
　半導体チップには、コントロールＩＣなどのＬＳＩチップが含まれている。ＬＳＩチップには、複数種類の制御信号の入出力がある。制御信号の数が増えるほど、ＬＳＩチップへの導通経路の数を増やす必要があるが、これらの導通経路を従来のように複数の電極部によって構成しようとすると、半導体装置のさらなる高集積化が困難となるおそれがある。 Semiconductor chips include LSI chips such as control ICs. An LSI chip has input/output for multiple types of control signals. As the number of control signals increases, it is necessary to increase the number of conduction paths to the LSI chip, but if these conduction paths are constructed from multiple electrode sections as in the past, the integration of semiconductor devices will become even higher. It may become difficult.
　本開示は、従来よりも改良が施された半導体装置を提供することを一の課題とする。特に本開示は、上記した事情に鑑み、さらなる高集積化を可能とする半導体装置を提供することを一の課題とする。 An object of the present disclosure is to provide a semiconductor device that is improved over conventional ones. Particularly, in view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that enables even higher integration.
　本開示の第１の側面によって提供される半導体装置は、厚さ方向において互いに反対側を向く第１主面および第１裏面を有する第１基材と、前記第１主面上に配置された導電性を有する第１主面導電部と、前記厚さ方向において前記第１主面と同じ側を向く第２主面および前記第１裏面と同じ側を向く第２裏面を有する第２基材と、前記第２主面上に配置された導電性を有する第２主面導電部と、前記第１主面上に配置されて前記第１主面導電部に導通接続されたスイッチング素子と、前記第２主面上に配置されて前記第２主面導電部に導通接続され、かつ、前記スイッチング素子を駆動させる駆動装置と、前記第１基材および前記第２基材の少なくとも一部と、前記スイッチング素子および前記駆動装置の全体と、を覆う封止樹脂と、を備えている。 A semiconductor device provided by a first aspect of the present disclosure includes a first base material having a first main surface and a first back surface facing opposite to each other in the thickness direction, and a first base material disposed on the first main surface. A second base material having a first main surface conductive portion having conductivity, a second main surface facing the same side as the first main surface in the thickness direction, and a second back surface facing the same side as the first back surface. a second main surface conductive part having electrical conductivity disposed on the second main surface; a switching element disposed on the first main surface and electrically connected to the first main surface conductive part; a driving device disposed on the second main surface, electrically connected to the second main surface conductive portion, and driving the switching element; and at least a portion of the first base material and the second base material. and a sealing resin that covers the entire switching element and the drive device.
　上記構成によると、半導体装置においてさらなる高集積化が可能である。 According to the above configuration, even higher integration is possible in the semiconductor device.
　本開示のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.
図１は、本開示の第１実施形態に係る半導体装置を示す斜視図である。FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present disclosure. 図２は、図１の半導体装置を示す平面図である。FIG. 2 is a plan view showing the semiconductor device of FIG. 1. 図３は、図１の半導体装置を示す平面図であり、封止樹脂を透過した図である。FIG. 3 is a plan view showing the semiconductor device of FIG. 1, and is a view through the sealing resin. 図４は、図１の半導体装置を示す底面図である。FIG. 4 is a bottom view showing the semiconductor device of FIG. 1. 図５は、図３のＶ－Ｖ線に沿う断面図である。FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. 図６は、図５の部分拡大図である。FIG. 6 is a partially enlarged view of FIG. 5. 図７は、図１の半導体装置の各配線基板を示す平面図である。FIG. 7 is a plan view showing each wiring board of the semiconductor device of FIG. 1. 図８は、図１の半導体装置の製造方法の一例の一工程を示すフローチャートである。FIG. 8 is a flowchart showing one step of an example of the method for manufacturing the semiconductor device of FIG. 図９は、本開示の第２実施形態に係る半導体装置を示す断面図である。FIG. 9 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present disclosure. 図１０は、本開示の第３実施形態に係る半導体装置を示す断面図である。FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present disclosure. 図１１は、本開示の第４実施形態に係る半導体装置を示す断面図である。FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present disclosure. 図１２は、本開示の第５実施形態に係る半導体装置を示す部分拡大平面図であり、封止樹脂を透過した図である。FIG. 12 is a partially enlarged plan view showing a semiconductor device according to a fifth embodiment of the present disclosure, and is a view through a sealing resin.
　以下、本開示の好ましい実施の形態につき、図面を参照して具体的に説明する。 Hereinafter, preferred embodiments of the present disclosure will be specifically described with reference to the drawings.
　本開示において、「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接して、ある物Ａがある物Ｂ上に位置していること」、および、「ある物Ａとある物Ｂとの間に他の物が介在しつつ、ある物Ａがある物Ｂ上に位置していること」を含む。また、「ある物Ａがある物Ｂにある方向に見て重なる」とは、特段の断りのない限り、「ある物Ａがある物Ｂのすべてに重なること」、および、「ある物Ａがある物Ｂの一部に重なること」を含む。 In this disclosure, "a thing A is formed on a thing B" and "a thing A is formed on a thing B" mean "a thing A is formed on a thing B" unless otherwise specified. "It is formed directly on object B," and "It is formed on object B, with another object interposed between object A and object B." Similarly, "something A is placed on something B" and "something A is placed on something B" mean "something A is placed on something B" unless otherwise specified. This includes ``directly placed on object B'' and ``placed on object B with another object interposed between object A and object B.'' Similarly, "a certain object A is located on a certain object B" means, unless otherwise specified, "a certain object A is in contact with a certain object B, and a certain object A is located on a certain object B." ``The fact that a certain thing A is located on a certain thing B while another thing is interposed between the certain thing A and the certain thing B.'' In addition, "a certain object A overlaps a certain object B when viewed in a certain direction" means, unless otherwise specified, "a certain object A overlaps all of a certain object B" and "a certain object A overlaps with a certain object B". This includes "overlapping a part of something B."
　第１実施形態：
　図１～図７は、本開示に係る半導体装置の一例を示している。本実施形態の半導体装置Ａ１は、複数のリード１、配線基板２、配線基板３、複数の半導体チップ４、複数の駆動装置５、複数の受動素子６、複数のワイヤ７、および封止樹脂８を備えている。本実施形態において、半導体装置Ａ１は、ＩＰＭ（Intelligent Power Module）である。半導体装置Ａ１は、たとえば、エアーコンディショナやモータ制御機器などの用途に用いられる。 First embodiment:
1 to 7 show an example of a semiconductor device according to the present disclosure. The semiconductor device A1 of this embodiment includes a plurality of leads 1, a wiring board 2, a wiring board 3, a plurality of semiconductor chips 4, a plurality of drive devices 5, a plurality of passive elements 6, a plurality of wires 7, and a sealing resin 8. It is equipped with In this embodiment, the semiconductor device A1 is an IPM (Intelligent Power Module). The semiconductor device A1 is used for applications such as air conditioners and motor control equipment, for example.
　図１は、半導体装置Ａ１を示す斜視図である。図２は、半導体装置Ａ１を示す平面図である。図３は、半導体装置Ａ１を示す平面図であり、封止樹脂８を透過した図である。なお、図３においては、封止樹脂８の外形を想像線（二点鎖線）で示している。図４は、半導体装置Ａ１を示す底面図である。図５は、図３のＶ－Ｖ線に沿う断面図である。図６は、図５の部分拡大図である。図７は、配線基板２および配線基板３を示す平面図である。 FIG. 1 is a perspective view showing a semiconductor device A1. FIG. 2 is a plan view showing the semiconductor device A1. FIG. 3 is a plan view showing the semiconductor device A1, and is a view through the sealing resin 8. As shown in FIG. In addition, in FIG. 3, the outer shape of the sealing resin 8 is shown by an imaginary line (two-dot chain line). FIG. 4 is a bottom view showing the semiconductor device A1. FIG. 5 is a cross-sectional view taken along line VV in FIG. 3. FIG. 6 is a partially enlarged view of FIG. 5. FIG. 7 is a plan view showing the wiring board 2 and the wiring board 3.
　説明の便宜上、配線基板２の厚さ方向を厚さ方向ｚとし、厚さ方向ｚに直交する配線基板２の一方の辺に沿う方向（図２～図４における上下方向）を第１方向ｙ、厚さ方向ｚおよび第１方向ｙに直交する方向（図２～図４における左右方向）を第２方向ｘとする。なお、半導体装置Ａ１の形状および各寸法は限定されない。 For convenience of explanation, the thickness direction of the wiring board 2 is referred to as the thickness direction z, and the direction along one side of the wiring board 2 perpendicular to the thickness direction z (vertical direction in FIGS. 2 to 4) is referred to as the first direction y. , the direction perpendicular to the thickness direction z and the first direction y (the left-right direction in FIGS. 2 to 4) is the second direction x. Note that the shape and dimensions of the semiconductor device A1 are not limited.
　配線基板２は、複数の半導体チップ４および複数の受動素子６（後述するシャント抵抗６ａ）が搭載され、半導体装置Ａ１の第２方向ｘの中央で第１方向ｙの第１側ｙ１寄りに配置されている。後述するように複数の半導体チップ４はパワートランジスタであり、配線基板２は、パワー回路が配置されるパワー部用基板である。配線基板２は、基材２１、主面導電部２２、および裏面導電部２３を備えている。 The wiring board 2 is mounted with a plurality of semiconductor chips 4 and a plurality of passive elements 6 (shunt resistors 6a to be described later), and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the first side y1 in the first direction y. has been done. As described later, the plurality of semiconductor chips 4 are power transistors, and the wiring board 2 is a power section board on which a power circuit is arranged. The wiring board 2 includes a base material 21, a main surface conductive portion 22, and a back surface conductive portion 23.
　基材２１は、板状であり、厚さ方向ｚに視て（すなわち平面視で）、形状が第２方向ｘに長い矩形状である。基材２１の厚さ寸法（厚さ方向ｚの寸法）は、たとえば０．１ｍｍ～１．０ｍｍ程度である。なお、基材２１の各寸法は限定されない。基材２１は、絶縁性の材料からなる。基材２１の構成材料は、たとえば熱伝導性に優れたセラミックスであり、本実施形態では、窒化アルミニウム（ＡｌＮ）を含んでいる。なお、基材２１の構成材料は、これに限定されない。 The base material 21 is plate-shaped, and has a rectangular shape that is elongated in the second direction x when viewed in the thickness direction z (that is, in plan view). The thickness dimension (dimension in the thickness direction z) of the base material 21 is, for example, about 0.1 mm to 1.0 mm. Note that the dimensions of the base material 21 are not limited. The base material 21 is made of an insulating material. The constituent material of the base material 21 is, for example, ceramics with excellent thermal conductivity, and in this embodiment, includes aluminum nitride (AlN). Note that the constituent material of the base material 21 is not limited to this.
　基材２１は、主面２１１および裏面２１２を有する。主面２１１および裏面２１２は、厚さ方向ｚにおいて互いに反対側を向く面であり、ともに厚さ方向ｚに対して直交する平坦面である。主面２１１は、厚さ方向ｚの第１側ｚ１を向く面である。主面２１１には、主面導電部２２が配置されており、複数の半導体チップ４、複数の受動素子６、および、複数のリード１が搭載されている。裏面２１２は、厚さ方向ｚの第２側ｚ２を向く面である。裏面２１２には、裏面導電部２３が配置されている。主面２１１および裏面２１２の形状は、ともに矩形状である。なお、基材２１の形状は限定されない。 The base material 21 has a main surface 211 and a back surface 212. The main surface 211 and the back surface 212 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The main surface 211 is a surface facing the first side z1 in the thickness direction z. A main surface conductive portion 22 is arranged on the main surface 211, and a plurality of semiconductor chips 4, a plurality of passive elements 6, and a plurality of leads 1 are mounted on the main surface 211. The back surface 212 is a surface facing the second side z2 in the thickness direction z. On the back surface 212, a back conductive portion 23 is arranged. The shapes of the main surface 211 and the back surface 212 are both rectangular. Note that the shape of the base material 21 is not limited.
　主面導電部２２は、基材２１の主面２１１上に配置されている。主面導電部２２は、導電性材料からなる。主面導電部２２の構成材料は、特に限定されず、たとえば銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、およびこれらを含む合金などである。本実施形態では、銅（Ｃｕ）である場合について説明する。主面導電部２２の厚さ寸法（厚さ方向ｚの寸法）Ｔ１（図６参照）は、半導体チップ４が発する熱の放熱効果を維持できる厚さであり、たとえば０．２ｍｍ以上である。本実施形態では、厚さ寸法Ｔ１は、０．２５ｍｍ程度である。なお、厚さ寸法Ｔ１は限定されない。 The main surface conductive portion 22 is arranged on the main surface 211 of the base material 21. The main surface conductive portion 22 is made of a conductive material. The constituent material of the main surface conductive portion 22 is not particularly limited, and examples thereof include copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described. The thickness dimension (dimension in the thickness direction z) T1 (see FIG. 6) of the main surface conductive portion 22 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness dimension T1 is approximately 0.25 mm. Note that the thickness dimension T1 is not limited.
　主面導電部２２の形状等は特に限定されない。本実施形態では、主面導電部２２は、たとえば図７に示すように、複数のパッド２２１および複数の配線２２２を含んでいる。各パッド２２１は、たとえば矩形状であり、半導体チップ４、受動素子６、リード１（後述するリード１１）、またはワイヤ７（後述するワイヤ７１，７２）が導通接合されている。なお、パッド２２１の形状は限定されない。各パッド２２１は、互いに離間して配置されている。複数の配線２２２はそれぞれ、いずれかのパッド２２１といずれかのパッド２２１とに接続し、両者を導通する導通経路である。各配線２２２の形状は限定されない。 The shape etc. of the main surface conductive portion 22 are not particularly limited. In this embodiment, the main surface conductive portion 22 includes a plurality of pads 221 and a plurality of wirings 222, as shown in FIG. 7, for example. Each pad 221 has a rectangular shape, for example, and has the semiconductor chip 4, the passive element 6, the lead 1 (lead 11 described later), or the wire 7 ( wires 71 and 72 described later) electrically connected. Note that the shape of the pad 221 is not limited. Each pad 221 is spaced apart from each other. Each of the plurality of wirings 222 is a conduction path that connects one of the pads 221 and one of the pads 221 to conduct them. The shape of each wiring 222 is not limited.
　裏面導電部２３は、基材２１の裏面２１２上に配置されている。裏面導電部２３は、導電性材料からなる。裏面導電部２３の構成材料は、特に限定されず、たとえば銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、およびこれらを含む合金などである。本実施形態では、裏面導電部２３の構成材料は、主面導電部２２と同様、銅（Ｃｕ）である。裏面導電部２３の厚さ寸法（厚さ方向ｚの寸法）は、半導体チップ４が発する熱の放熱効果を維持できる厚さであり、たとえば０．２ｍｍ以上である。本実施形態では、裏面導電部２３の厚さ寸法は、厚さ寸法Ｔ１と同様、０．２５ｍｍ程度であるが、これに限定されない。本実施形態では、裏面導電部２３は、裏面２１２の全面を覆っている。なお、裏面導電部２３の形状は限定されない。裏面導電部２３は、図４に示すように、封止樹脂８から露出している。 The back conductive portion 23 is arranged on the back surface 212 of the base material 21. The back conductive portion 23 is made of a conductive material. The constituent material of the back conductive portion 23 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, the constituent material of the back surface conductive portion 23 is copper (Cu), as is the case with the main surface conductive portion 22. The thickness dimension (dimension in the thickness direction z) of the back conductive portion 23 is a thickness that can maintain the heat dissipation effect of the heat generated by the semiconductor chip 4, and is, for example, 0.2 mm or more. In this embodiment, the thickness of the back conductive portion 23 is approximately 0.25 mm, similar to the thickness T1, but is not limited thereto. In this embodiment, the back surface conductive portion 23 covers the entire surface of the back surface 212. Note that the shape of the back conductive portion 23 is not limited. The back conductive portion 23 is exposed from the sealing resin 8, as shown in FIG.
　本実施形態では、配線基板２は、いわゆるＤＢＣ（Direct Bonded Copper）基板から形成される。当該ＤＢＣ基板は、セラミックスの板の両面にそれぞれ、銅箔が接合された基板である。配線基板２は、当該ＤＢＣ基板の一方の面の銅箔をエッチングによりパターニングすることで形成される。一方の面のパターニングされた銅箔が主面導電部２２になり、他方の銅箔が裏面導電部２３になる。なお、配線基板２の形成方法は限定されない。いずれの方法で形成する場合でも、０．２ｍｍ以上の銅の層を形成する必要がある。また、上述したように、主面導電部２２および裏面導電部２３の構成材料は銅以外の金属であってもよく、当該金属の層がセラミックスの板の両面に形成される。 In this embodiment, the wiring board 2 is formed from a so-called DBC (Direct Bonded Copper) board. The DBC board is a board in which copper foil is bonded to both sides of a ceramic plate. The wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23. Note that the method for forming the wiring board 2 is not limited. Regardless of which method is used, it is necessary to form a copper layer of 0.2 mm or more. Further, as described above, the constituent material of the main surface conductive portion 22 and the back surface conductive portion 23 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
　配線基板３は、複数の駆動装置５および複数の受動素子６が搭載され、半導体装置Ａ１の第２方向ｘの中央で第１方向ｙの第２側ｙ２寄りに配置されている。配線基板２と配線基板３とは第１方向ｙに並んで配置され、配線基板３は、配線基板２に対して第１方向ｙの第２側ｙ２に位置している。配線基板３は、配線基板２に配置されたパワー回路を制御するための制御回路が配置された制御部用基板である。配線基板３は、基材３１、主面導電部３２、および裏面導電部３３を備えている。 The wiring board 3 has a plurality of drive devices 5 and a plurality of passive elements 6 mounted thereon, and is arranged at the center of the semiconductor device A1 in the second direction x and closer to the second side y2 in the first direction y. The wiring board 2 and the wiring board 3 are arranged side by side in the first direction y, and the wiring board 3 is located on the second side y2 of the first direction y with respect to the wiring board 2. The wiring board 3 is a control unit board on which a control circuit for controlling the power circuit arranged on the wiring board 2 is arranged. The wiring board 3 includes a base material 31, a main surface conductive portion 32, and a back surface conductive portion 33.
　基材３１は、板状であり、厚さ方向ｚに視た形状が第２方向ｘに長い矩形状である。基材３１の厚さ寸法（厚さ方向ｚの寸法）は、たとえば０．１ｍｍ～１．０ｍｍ程度であり、基材２１と同程度である。なお、基材３１の各寸法は限定されない。基材３１は、絶縁性の材料からなる。基材３１の構成材料は、たとえばセラミックスであり、本実施形態では、アルミナ（Ａｌ2Ｏ3）を含んでいる。基材３１は、基材２１ほど、熱伝導性を必要としない。本実施形態では、基材２１は、構成材料が窒化アルミニウムのセラミックスであり、構成材料がアルミナのセラミックスである基材３１より熱伝導性が高い。なお、基材３１の構成材料は、これに限定されない。たとえば、基材２１の構成材料と基材３１の構成材料とが同じであってもよい。 The base material 31 is plate-shaped and has a rectangular shape that is long in the second direction x when viewed in the thickness direction z. The thickness dimension (dimension in the thickness direction z) of the base material 31 is, for example, about 0.1 mm to 1.0 mm, which is about the same as that of the base material 21. Note that the dimensions of the base material 31 are not limited. The base material 31 is made of an insulating material. The constituent material of the base material 31 is, for example, ceramics, and in this embodiment contains alumina (Al 2 O 3 ). The base material 31 does not require as much thermal conductivity as the base material 21. In this embodiment, the base material 21 is made of ceramics made of aluminum nitride, and has higher thermal conductivity than the base material 31 made of ceramics made of alumina. Note that the constituent material of the base material 31 is not limited to this. For example, the constituent material of the base material 21 and the constituent material of the base material 31 may be the same.
　基材３１は、主面３１１および裏面３１２を有する。主面３１１および裏面３１２は、厚さ方向ｚにおいて互いに反対側を向く面であり、ともに厚さ方向ｚに対して直交する平坦面である。主面３１１は、厚さ方向ｚの第１側ｚ１を向く面である。主面３１１には、主面導電部３２が配置されており、複数の駆動装置５、複数の受動素子６、および、複数のリード１が搭載されている。裏面３１２は、厚さ方向ｚの第２側ｚ２を向く面である。裏面３１２には、裏面導電部３３が配置されている。主面３１１および裏面３１２の形状は、ともに矩形状である。なお、基材３１の形状は限定されない。 The base material 31 has a main surface 311 and a back surface 312. The main surface 311 and the back surface 312 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The main surface 311 is a surface facing the first side z1 in the thickness direction z. A main surface conductive portion 32 is arranged on the main surface 311, and a plurality of drive devices 5, a plurality of passive elements 6, and a plurality of leads 1 are mounted thereon. The back surface 312 is a surface facing the second side z2 in the thickness direction z. On the back surface 312, a back conductive portion 33 is arranged. The shapes of the main surface 311 and the back surface 312 are both rectangular. Note that the shape of the base material 31 is not limited.
　主面導電部３２は、基材３１の主面３１１上に配置されている。主面導電部３２は、導電性材料からなる。主面導電部３２の構成材料は、特に限定されず、たとえば銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、およびこれらを含む合金などである。本実施形態では、銅（Ｃｕ）である場合について説明する。主面導電部３２の厚さ寸法（厚さ方向ｚの寸法）Ｔ２（図６参照）は、厚さ寸法Ｔ１より小さく、エッチングによって、主面導電部２２より微細な加工が可能な厚さである。本実施形態では、厚さ寸法Ｔ２は、たとえば０．１ｍｍ程度である。なお、厚さ寸法Ｔ２は限定されない。 The main surface conductive portion 32 is arranged on the main surface 311 of the base material 31. The main surface conductive portion 32 is made of a conductive material. The constituent material of the main surface conductive portion 32 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, a case where copper (Cu) is used will be described. The thickness dimension (dimension in the thickness direction z) T2 (see FIG. 6) of the main surface conductive part 32 is smaller than the thickness dimension T1, and has a thickness that allows finer processing than the main surface conductive part 22 by etching. be. In this embodiment, the thickness dimension T2 is, for example, about 0.1 mm. Note that the thickness dimension T2 is not limited.
　主面導電部３２の形状等は特に限定されない。本実施形態では、主面導電部３２は、たとえば図７に示すように、複数のパッド３２１および複数の配線３２２を含んでいる。各パッド３２１は、たとえば矩形状であり、駆動装置５、受動素子６、リード１（後述するリード１５）、またはワイヤ７（後述するワイヤ７３，７４）が導通接合されている。なお、パッド３２１の形状は限定されない。各パッド３２１は、互いに離間して配置されている。複数の配線３２２はそれぞれ、いずれかのパッド３２１といずれかのパッド３２１とに接続し、両者を導通する導通経路である。各配線３２２の形状は限定されない。なお、ワイヤ７が接合されるパッド３２１には、ワイヤボンディングによる衝撃からパッド３２１および基材３１を保護するために、導電性の板状の部材を配置してもよい。 The shape etc. of the main surface conductive portion 32 are not particularly limited. In this embodiment, the main surface conductive portion 32 includes a plurality of pads 321 and a plurality of wirings 322, as shown in FIG. 7, for example. Each pad 321 has a rectangular shape, for example, and has a driving device 5, a passive element 6, a lead 1 (a lead 15 described later), or a wire 7 ( wires 73 and 74 described later) electrically connected. Note that the shape of the pad 321 is not limited. Each pad 321 is spaced apart from each other. Each of the plurality of wirings 322 is a conduction path that connects one of the pads 321 and one of the pads 321 to conduct the two. The shape of each wiring 322 is not limited. Note that a conductive plate-like member may be placed on the pad 321 to which the wire 7 is bonded in order to protect the pad 321 and the base material 31 from impact caused by wire bonding.
　裏面導電部３３は、基材３１の裏面３１２上に配置されている。裏面導電部３３は、導電性材料からなる。裏面導電部３３の構成材料は、特に限定されず、たとえば銅（Ｃｕ）、銀（Ａｇ）、金（Ａｕ）、およびこれらを含む合金などである。本実施形態では、裏面導電部３３の構成材料は、主面導電部３２と同様、銅（Ｃｕ）である。裏面導電部３３の厚さ寸法（厚さ方向ｚの寸法）は、厚さ寸法Ｔ２と同程度であり、たとえば０．１ｍｍ程度である。なお、裏面導電部３３の厚さ寸法は、これに限定されない。本実施形態では、裏面導電部３３は、裏面３１２の全面を覆っている。なお、裏面導電部３３の形状は限定されない。裏面導電部３３は、図４に示すように、封止樹脂８から露出している。なお、配線基板３は、裏面導電部３３を備えなくてもよい。この場合、基材３１の裏面３１２が封止樹脂８から露出してもよいし、配線基板３の全体が封止樹脂８に覆われ（配線基板３が封止樹脂８から露出しない）てもよい。 The back surface conductive part 33 is arranged on the back surface 312 of the base material 31. The back conductive portion 33 is made of a conductive material. The constituent material of the back conductive portion 33 is not particularly limited, and includes, for example, copper (Cu), silver (Ag), gold (Au), and alloys containing these. In this embodiment, the constituent material of the back conductive portion 33 is copper (Cu), as is the case with the main conductive portion 32 . The thickness dimension (dimension in the thickness direction z) of the back conductive portion 33 is approximately the same as the thickness dimension T2, and is, for example, approximately 0.1 mm. Note that the thickness dimension of the back conductive portion 33 is not limited to this. In this embodiment, the back conductive portion 33 covers the entire back surface 312. Note that the shape of the back conductive portion 33 is not limited. The back conductive portion 33 is exposed from the sealing resin 8, as shown in FIG. Note that the wiring board 3 does not need to include the back conductive portion 33. In this case, the back surface 312 of the base material 31 may be exposed from the sealing resin 8, or the entire wiring board 3 may be covered with the sealing resin 8 (the wiring board 3 is not exposed from the sealing resin 8). good.
　本実施形態では、配線基板３は、いわゆるＤＢＣ基板から形成される。当該ＤＢＣ基板は、セラミックスの板の両面にそれぞれ、銅箔が接合された基板である。当該ＤＢＣ基板の銅箔は、配線基板２を形成するためのＤＢＣ基板の銅箔より薄い。配線基板３は、配線基板２と同様、ＤＢＣ基板の一方の面の銅箔をエッチングによりパターニングすることで形成される。一方の面のパターニングされた銅箔が主面導電部３２になり、他方の銅箔が裏面導電部３３になる。なお、配線基板３の形成方法は限定されない。たとえば、配線基板３は、セラミックスの板の両面にそれぞれ銅めっきを形成したいわゆるＤＰＣ（Direct Plated Copper）基板から形成されてもよい。ＤＰＣ基板はＤＢＣ基板より銅の層が薄いので、主面導電部３２として、より微細な加工が可能である。また、配線基板３は、セラミックスの板の両面に銅ペーストを配置して焼成することで形成されてもよい。また、上述したように、主面導電部３２および裏面導電部３３の構成材料は銅以外の金属であってもよく、当該金属の層がセラミックスの板の両面に形成される。 In this embodiment, the wiring board 3 is formed from a so-called DBC board. The DBC board is a board in which copper foil is bonded to both sides of a ceramic plate. The copper foil of the DBC board is thinner than the copper foil of the DBC board for forming the wiring board 2. Like the wiring board 2, the wiring board 3 is formed by patterning copper foil on one side of the DBC board by etching. The patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33. Note that the method of forming the wiring board 3 is not limited. For example, the wiring board 3 may be formed from a so-called DPC (Direct Plated Copper) board, which is a ceramic plate with copper plating on both sides. Since the copper layer of the DPC substrate is thinner than that of the DBC substrate, finer processing as the main surface conductive portion 32 is possible. Further, the wiring board 3 may be formed by disposing copper paste on both sides of a ceramic plate and firing the same. Further, as described above, the constituent material of the main surface conductive portion 32 and the back surface conductive portion 33 may be a metal other than copper, and layers of the metal are formed on both surfaces of the ceramic plate.
　複数のリード１は、金属を含んで構成されている。リード１を構成する金属は特に限定されず、たとえば銅（Ｃｕ）、アルミニウム、鉄（Ｆｅ）、無酸素銅、またはこれらの合金（たとえば、Ｃｕ－Ｓｎ合金、Ｃｕ－Ｚｒ合金、Ｃｕ－Ｆｅ合金等）である。また、複数のリード１には、ニッケル（Ｎｉ）めっきが施されていてもよい。複数のリード１は、たとえば、金型を金属板に押し付けるプレス加工により形成されてもよいし、金属板をエッチングでパターニングすることにより形成されてもよい。なお、複数のリード１の形成方法は限定されない。各リード１の厚さは特に限定されず、たとえば０．４ｍｍ～０．８ｍｍ程度である。各リード１は、互いに離間している。 The plurality of leads 1 are configured to include metal. The metal constituting the lead 1 is not particularly limited, and includes, for example, copper (Cu), aluminum, iron (Fe), oxygen-free copper, or alloys thereof (for example, Cu-Sn alloy, Cu-Zr alloy, Cu-Fe alloy). etc.). Furthermore, the plurality of leads 1 may be plated with nickel (Ni). The plurality of leads 1 may be formed, for example, by pressing a metal mold against a metal plate, or by patterning a metal plate by etching. Note that the method for forming the plurality of leads 1 is not limited. The thickness of each lead 1 is not particularly limited, and is, for example, about 0.4 mm to 0.8 mm. Each lead 1 is spaced apart from each other.
　本実施形態においては、複数のリード１は、それぞれ複数のリード１１、リード１２、リード１５、およびリード１６を含んでいる。リード１１およびリード１２は、半導体チップ４への導通経路を構成している。リード１５およびリード１６は、駆動装置５または受動素子６への導通経路を構成している。 In this embodiment, the plurality of leads 1 each include a plurality of leads 11, leads 12, leads 15, and leads 16. The leads 11 and 12 constitute a conductive path to the semiconductor chip 4. Leads 15 and 16 constitute a conduction path to drive device 5 or passive element 6.
　複数のリード１１は、それぞれ、基材２１上に配置されており、本実施形態においては、主面２１１上の第１方向ｙの第１側ｙ１寄りに配置されている。各リード１１は、導電性接合材７６を介して、主面導電部２２のパッド２２１に接合されている。導電性接合材７６は、リード１１をパッド２２１に導通接合できるものであればよく、たとえば銀ペースト、銅ペーストやはんだ等が用いられる。なお、導電性接合材７６は限定されない。各リード１１は、主面導電部２２およびワイヤ７１を介して半導体チップ４に導通している。本実施形態では、複数のリード１は３個のリード１１を含んでいる。なお、リード１１の数および配置は限定されない。 The plurality of leads 11 are each arranged on the base material 21, and in this embodiment, are arranged on the main surface 211 closer to the first side y1 in the first direction y. Each lead 11 is bonded to a pad 221 of the main surface conductive portion 22 via a conductive bonding material 76 . The conductive bonding material 76 may be any material that can conductively bond the leads 11 to the pads 221, such as silver paste, copper paste, solder, or the like. Note that the conductive bonding material 76 is not limited. Each lead 11 is electrically connected to the semiconductor chip 4 via the main surface conductive portion 22 and the wire 71. In this embodiment, the plurality of leads 1 includes three leads 11. Note that the number and arrangement of leads 11 are not limited.
　リード１１の構成は特に限定されない。本実施形態においては、図５に示すように、リード１１を、接合部分１１１、突出部分１１２、傾斜接続部分１１３および平行接続部分１１４に区分けして説明する。 The structure of the lead 11 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 11 will be divided into a joint portion 111, a protruding portion 112, an inclined connection portion 113, and a parallel connection portion 114.
　接合部分１１１は、主面１１１ａおよび裏面１１１ｂを有する。主面１１１ａおよび裏面１１１ｂは、厚さ方向ｚにおいて互いに反対側を向く面であり、ともに厚さ方向ｚに対して直交する平坦面である。主面１１１ａは、厚さ方向ｚの第１側ｚ１を向く面である。裏面１１１ｂは、厚さ方向ｚの第２側ｚ２を向く面である。裏面１１１ｂは、導電性接合材７６によって主面導電部２２のパッド２２１に接合されている。傾斜接続部分１１３および平行接続部分１１４は、封止樹脂８によって覆われている。傾斜接続部分１１３は、接合部分１１１および平行接続部分１１４につながっており、接合部分１１１および平行接続部分１１４に対して傾斜している。平行接続部分１１４は、傾斜接続部分１１３および突出部分１１２につながっており、接合部分１１１に対して平行である。突出部分１１２は、平行接続部分１１４の端部につながり、リード１１のうち封止樹脂８から突出する部分である。突出部分１１２は、第１方向ｙにおいて接合部分１１１とは反対側（ｙ１側）に突出している。突出部分１１２は、たとえば半導体装置Ａ１を外部の回路に電気的に接続するために用いられる。図示された例においては、突出部分１１２は、厚さ方向ｚにおいて接合部分１１１の主面１１１ａが向く側に折り曲げられている。 The joint portion 111 has a main surface 111a and a back surface 111b. The main surface 111a and the back surface 111b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The main surface 111a is a surface facing the first side z1 in the thickness direction z. The back surface 111b is a surface facing the second side z2 in the thickness direction z. The back surface 111b is bonded to the pad 221 of the main surface conductive portion 22 by a conductive bonding material 76. The inclined connection portion 113 and the parallel connection portion 114 are covered with the sealing resin 8. The inclined connection part 113 is connected to the joint part 111 and the parallel connection part 114 and is inclined with respect to the joint part 111 and the parallel connection part 114. The parallel connecting portion 114 is connected to the inclined connecting portion 113 and the protruding portion 112 and is parallel to the joining portion 111 . The protruding portion 112 is connected to the end of the parallel connection portion 114 and is a portion of the lead 11 that protrudes from the sealing resin 8 . The protruding portion 112 protrudes to the side opposite to the joining portion 111 (y1 side) in the first direction y. The protruding portion 112 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 112 is bent toward the side toward which the main surface 111a of the joint portion 111 faces in the thickness direction z.
　複数のリード１２は、本実施形態では、基材２１上に配置されておらず、基材２１の第１方向ｙの第１側ｙ１に配置されている。各リード１２は、リード１１の接合部分１１１および傾斜接続部分１１３に相当する部位を含まず、突出部分１１２および平行接続部分１１４に相当する部位だけの構成である。平行接続部分１１４に相当する部位には、ワイヤ７２が導通接合されている。各リード１２は、ワイヤ７２および主面導電部２２を介して、半導体チップ４または受動素子６に導通している。本実施形態では、複数のリード１は６個のリード１２を含んでいる。なお、リード１２の構成、数、および配置はこれに限定されない。 In this embodiment, the plurality of leads 12 are not arranged on the base material 21, but are arranged on the first side y1 of the base material 21 in the first direction y. Each lead 12 does not include a portion corresponding to the joint portion 111 and the inclined connection portion 113 of the lead 11, but only includes a portion corresponding to the protrusion portion 112 and the parallel connection portion 114. A wire 72 is electrically connected to a portion corresponding to the parallel connection portion 114. Each lead 12 is electrically connected to the semiconductor chip 4 or the passive element 6 via the wire 72 and the main surface conductive portion 22. In this embodiment, the plurality of leads 1 includes six leads 12. Note that the configuration, number, and arrangement of the leads 12 are not limited to this.
　複数のリード１５は、それぞれ、基材３１上に配置されており、本実施形態においては、主面３１１上の第１方向ｙの第２側ｙ２寄りに配置されている。各リード１５は、導電性接合材７６を介して、主面導電部３２のパッド３２１に接合されている。各リード１５は、主面導電部２２を介して、駆動装置５または受動素子６に導通している。本実施形態では、複数のリード１は１８個のリード１５を含んでいる。なお、リード１５の数および配置は限定されない。 The plurality of leads 15 are each arranged on the base material 31, and in this embodiment, are arranged on the main surface 311 closer to the second side y2 in the first direction y. Each lead 15 is bonded to a pad 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Each lead 15 is electrically connected to the drive device 5 or the passive element 6 via the main surface conductive portion 22 . In this embodiment, the plurality of leads 1 includes 18 leads 15. Note that the number and arrangement of leads 15 are not limited.
　リード１５の構成は特に限定されない。本実施形態においては、図５に示すように、リード１５を、接合部分１５１、突出部分１５２、傾斜接続部分１５３および平行接続部分１５４に区分けして説明する。 The structure of the lead 15 is not particularly limited. In this embodiment, as shown in FIG. 5, the lead 15 will be divided into a joining portion 151, a protruding portion 152, an inclined connecting portion 153, and a parallel connecting portion 154.
　接合部分１５１は、主面１５１ａおよび裏面１５１ｂを有する。主面１５１ａおよび裏面１５１ｂは、厚さ方向ｚにおいて互いに反対側を向く面であり、ともに厚さ方向ｚに対して直交する平坦面である。主面１５１ａは、厚さ方向ｚの第１側ｚ１を向く面である。裏面１５１ｂは、厚さ方向ｚの第２側ｚ２を向く面である。裏面１５１ｂは、導電性接合材７６によって主面導電部３２のパッド３２１に接合されている。傾斜接続部分１５３および平行接続部分１５４は、封止樹脂８によって覆われている。傾斜接続部分１５３は、接合部分１５１および平行接続部分１５４につながっており、接合部分１５１および平行接続部分１５４に対して傾斜している。平行接続部分１５４は、傾斜接続部分１５３および突出部分１５２につながっており、接合部分１５１に対して平行である。突出部分１５２は、平行接続部分１５４の端部につながり、リード１５のうち封止樹脂８から突出する部分である。突出部分１５２は、第１方向ｙにおいて接合部分１５１とは反対側（ｙ２側）に突出している。突出部分１５２は、たとえば半導体装置Ａ１を外部の回路に電気的に接続するために用いられる。図示された例においては、突出部分１５２は、厚さ方向ｚにおいて接合部分１５１の主面１５１ａが向く側に折り曲げられている。 The joint portion 151 has a main surface 151a and a back surface 151b. The main surface 151a and the back surface 151b are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The main surface 151a is a surface facing the first side z1 in the thickness direction z. The back surface 151b is a surface facing the second side z2 in the thickness direction z. The back surface 151b is bonded to the pad 321 of the main surface conductive portion 32 by a conductive bonding material 76. The inclined connection portion 153 and the parallel connection portion 154 are covered with the sealing resin 8. The inclined connection portion 153 is connected to the joint portion 151 and the parallel connection portion 154 and is inclined with respect to the joint portion 151 and the parallel connection portion 154. The parallel connecting portion 154 is connected to the inclined connecting portion 153 and the protruding portion 152 and is parallel to the joining portion 151. The protruding portion 152 is connected to the end of the parallel connection portion 154 and is a portion of the lead 15 that protrudes from the sealing resin 8 . The protruding portion 152 protrudes to the side opposite to the joining portion 151 (y2 side) in the first direction y. The protruding portion 152 is used, for example, to electrically connect the semiconductor device A1 to an external circuit. In the illustrated example, the protruding portion 152 is bent toward the side toward which the main surface 151a of the joint portion 151 faces in the thickness direction z.
　複数のリード１６は、本実施形態では、基材３１上に配置されておらず、基材３１の第２方向ｘの第１側ｘ１または第２側ｘ２に配置されている。各リード１６は、リード１５と同様の構成である。接合部分１５１に相当する部位は、主面導電部３２のパッド３２１に接合する代わりに、ワイヤ７４が導通接合されている。各リード１６は、ワイヤ７４および主面導電部３２を介して、駆動装置５および受動素子６に導通している。本実施形態では、複数のリード１は４個のリード１６を含んでいる。なお、リード１６の構成、数、および配置はこれに限定されない。 In this embodiment, the plurality of leads 16 are not arranged on the base material 31, but are arranged on the first side x1 or the second side x2 of the base material 31 in the second direction x. Each lead 16 has a similar configuration to lead 15. A wire 74 is conductively bonded to a portion corresponding to the bonding portion 151 instead of being bonded to the pad 321 of the main surface conductive portion 32 . Each lead 16 is electrically connected to the drive device 5 and the passive element 6 via the wire 74 and the main surface conductive portion 32. In this embodiment, the plurality of leads 1 includes four leads 16. Note that the configuration, number, and arrangement of the leads 16 are not limited to this.
　複数の半導体チップ４は、スイッチング素子であり、電力を制御するパワートランジスタである。半導体チップ４は、ＳｉＣ（炭化ケイ素）を主とする半導体材料を用いて構成されている。当該半導体材料は、ＳｉＣに限定されず、Ｓｉ（シリコン）、ＧａＡｓ（ヒ化ガリウム）あるいはＧａＮ（窒化ガリウム）などであってもよい。半導体チップ４は、たとえば、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）である。なお、半導体チップ４は、ＭＯＳＦＥＴに限定されず、ＩＧＢＴ（Insulated Gate Bipolar Transistor）などであってもよい。本実施形態では、半導体装置Ａ１が４個の半導体チップ４を備えている場合を示しているが、これは一例であり、半導体チップ４の個数は、限定されない。 The plurality of semiconductor chips 4 are switching elements and power transistors that control power. The semiconductor chip 4 is constructed using a semiconductor material mainly composed of SiC (silicon carbide). The semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. The semiconductor chip 4 is, for example, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Note that the semiconductor chip 4 is not limited to a MOSFET, and may be an IGBT (Insulated Gate Bipolar Transistor) or the like. Although this embodiment shows a case where the semiconductor device A1 includes four semiconductor chips 4, this is just an example, and the number of semiconductor chips 4 is not limited.
　各半導体チップ４は、厚さ方向ｚに視て矩形状の板状であり、素子主面４１、素子裏面４２、ソース電極４３、ゲート電極４４、およびドレイン電極４５を備えている。素子主面４１および素子裏面４２は、厚さ方向ｚにおいて互いに反対側を向いている。素子主面４１は、厚さ方向ｚの第１側ｚ１を向く面である。素子裏面４２は、厚さ方向ｚの第２側ｚ２を向く面である。素子主面４１には、図３に示すように、ソース電極４３およびゲート電極４４が配置されている。また、素子裏面４２には、ドレイン電極４５が配置されている。なお、ソース電極４３、ゲート電極４４、およびドレイン電極４５の形状および配置は限定されない。 Each semiconductor chip 4 has a rectangular plate shape when viewed in the thickness direction z, and includes an element main surface 41, an element rear surface 42, a source electrode 43, a gate electrode 44, and a drain electrode 45. The element main surface 41 and the element back surface 42 face opposite sides in the thickness direction z. The element main surface 41 is a surface facing the first side z1 in the thickness direction z. The back surface 42 of the element is a surface facing the second side z2 in the thickness direction z. As shown in FIG. 3, a source electrode 43 and a gate electrode 44 are arranged on the main surface 41 of the element. Further, a drain electrode 45 is arranged on the back surface 42 of the element. Note that the shapes and arrangement of the source electrode 43, gate electrode 44, and drain electrode 45 are not limited.
　各半導体チップ４は、図３および図５に示すように、配線基板２に搭載されている。各半導体チップ４は、基材２１の主面２１１上に配置されている。本実施形態では、４個の半導体チップ４は、主面２１１の第１方向ｙの第２側ｙ２寄りで、第２方向ｘに並んで配置されている。なお、各駆動装置５の配置位置は限定されない。各半導体チップ４は、図５に示すように、素子裏面４２を主面２１１に向けて、導電性接合材７６によって、主面導電部２２のパッド２２１に接合されている。これにより、半導体チップ４のドレイン電極４５は、導電性接合材７６によって、パッド２２１に導通接続される。また、図３に示すように、半導体チップ４のソース電極４３は、ワイヤ７１によって、隣接するパッド２２１に導通接続される。半導体装置Ａ１は、２個の半導体チップ４により構成されたブリッジ回路を２個備えている。 Each semiconductor chip 4 is mounted on the wiring board 2, as shown in FIGS. 3 and 5. Each semiconductor chip 4 is arranged on the main surface 211 of the base material 21. In this embodiment, the four semiconductor chips 4 are arranged side by side in the second direction x on the main surface 211 closer to the second side y2 in the first direction y. Note that the arrangement position of each drive device 5 is not limited. As shown in FIG. 5, each semiconductor chip 4 is bonded to a pad 221 of the main surface conductive portion 22 by a conductive bonding material 76 with the element back surface 42 facing the main surface 211. Thereby, the drain electrode 45 of the semiconductor chip 4 is electrically connected to the pad 221 by the conductive bonding material 76 . Further, as shown in FIG. 3, the source electrode 43 of the semiconductor chip 4 is electrically connected to the adjacent pad 221 by a wire 71. The semiconductor device A1 includes two bridge circuits each made up of two semiconductor chips 4.
　図３に示すように、半導体チップ４のソース電極４３およびゲート電極４４は、それぞれ、ワイヤ７３および配線基板３の主面導電部３２を介して、駆動装置５に導通接続される。 As shown in FIG. 3, the source electrode 43 and gate electrode 44 of the semiconductor chip 4 are electrically connected to the driving device 5 via the wire 73 and the main surface conductive portion 32 of the wiring board 3, respectively.
　複数の駆動装置５は、それぞれ、駆動信号を出力して、対応する半導体チップ４を駆動させるいわゆるゲートドライバである。本実施形態では、駆動装置５は、信号が入力される低電圧側と駆動信号を出力する高電圧側とが絶縁されている絶縁ゲートドライバである。なお、駆動装置５は、絶縁ゲートドライバに限定されない。半導体装置Ａ１は、半導体チップ４の数に合わせて、４個の駆動装置５を備えている。 Each of the plurality of drive devices 5 is a so-called gate driver that outputs a drive signal to drive the corresponding semiconductor chip 4. In this embodiment, the drive device 5 is an insulated gate driver in which a low voltage side into which a signal is input is insulated from a high voltage side through which a drive signal is output. Note that the driving device 5 is not limited to an insulated gate driver. The semiconductor device A1 includes four drive devices 5 corresponding to the number of semiconductor chips 4.
　各駆動装置５は、図３および図５に示すように、配線基板３に搭載されている。各駆動装置５は、基材３１の主面３１１上に配置されている。本実施形態では、４個の駆動装置５は、主面３１１の第１方向ｙの中央（あるいは略中央）に、第２方向ｘに並んで配置されている。なお、各駆動装置５の配置位置は限定されない。駆動装置５は、本実施形態では、ＳＯＰ（Small Outline Package）タイプのパッケージである。駆動装置５は、第１方向ｙの両側に突出して延びる複数の端子を備えている。これらの端子は、導電性接合材７６によって、主面導電部３２のパッド３２１に導通接合されている。なお、駆動装置５のパッケージタイプは、ＳＯＰタイプに限定されず、例えばＱＦＰ（Quad Flat Package）タイプ、ＳＯＪ（Small Outline J-lead Package）タイプ等の他のタイプであってもよい。また、駆動装置５のサイズ、形状、端子の数などは限定されない。また、駆動装置５に代えて、駆動チップが配線基板３に直接配置されてもよい。駆動装置５は、主面導電部３２およびワイヤ７３を介して、対応する半導体チップ４のゲート電極４４に、駆動信号を出力する。また、駆動装置５は、主面導電部３２およびワイヤ７３を介して、対応する半導体チップ４のソース電極４３の電位を入力される。 Each drive device 5 is mounted on the wiring board 3, as shown in FIGS. 3 and 5. Each drive device 5 is arranged on the main surface 311 of the base material 31. In this embodiment, the four drive devices 5 are arranged at the center (or approximately at the center) of the main surface 311 in the first direction y and in line in the second direction x. Note that the arrangement position of each drive device 5 is not limited. In this embodiment, the drive device 5 is an SOP (Small Outline Package) type package. The drive device 5 includes a plurality of terminals that protrude and extend on both sides of the first direction y. These terminals are conductively bonded to the pads 321 of the main surface conductive portion 32 by a conductive bonding material 76 . Note that the package type of the drive device 5 is not limited to the SOP type, and may be other types such as a QFP (Quad Flat Package) type or an SOJ (Small Outline J-lead Package) type. Further, the size, shape, number of terminals, etc. of the drive device 5 are not limited. Further, instead of the drive device 5, a drive chip may be directly disposed on the wiring board 3. The drive device 5 outputs a drive signal to the gate electrode 44 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73. Further, the driving device 5 receives the potential of the source electrode 43 of the corresponding semiconductor chip 4 via the main surface conductive portion 32 and the wire 73.
　複数の受動素子６は、図３および図５に示すように、配線基板２または配線基板３に搭載されている。各受動素子６は、基材２１の主面２１１上または基材３１の主面３１１上に配置されており、主面導電部２２のパッド２２１または主面導電部３２のパッド３２１に導通接合されている。受動素子６は、たとえば、抵抗、コンデンサ、コイル、ダイオードなどである。受動素子６には、２個のシャント抵抗６ａおよびサーミスタ６ｂが含まれている。 The plurality of passive elements 6 are mounted on the wiring board 2 or the wiring board 3, as shown in FIGS. 3 and 5. Each passive element 6 is disposed on the main surface 211 of the base material 21 or the main surface 311 of the base material 31, and is electrically connected to the pad 221 of the main surface conductive part 22 or the pad 321 of the main surface conductive part 32. ing. The passive element 6 is, for example, a resistor, a capacitor, a coil, a diode, or the like. Passive element 6 includes two shunt resistors 6a and a thermistor 6b.
　２個のシャント抵抗６ａは、配線基板２に搭載され、基材２１の主面２１１上に配置されている。各シャント抵抗６ａは、主面導電部２２の２個のパッド２２１に跨って、各パッド２２１に導通接合されている。各シャント抵抗６ａには、２個の半導体チップ４で構成されるブリッジ回路の出力電流が流れ、両端子間の電位差が出力される。 The two shunt resistors 6a are mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21. Each shunt resistor 6a straddles the two pads 221 of the main surface conductive portion 22 and is electrically connected to each pad 221. An output current of a bridge circuit composed of two semiconductor chips 4 flows through each shunt resistor 6a, and a potential difference between both terminals is output.
　サーミスタ６ｂは、配線基板３に搭載され、基材３１の主面３１１上に配置されている。サーミスタ６ｂは、主面導電部３２の２個のパッド３２１に跨って、各パッド３２１に導通接合されている。サーミスタ６ｂが接合された各パッド３２１はそれぞれ、配線３２２によって導通接続されたパッド３２１を介して、リード１５に導通している。サーミスタ６ｂは、所定の電流が流されて、配線基板３の温度に応じた電圧信号を出力する。 The thermistor 6b is mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31. The thermistor 6b straddles the two pads 321 of the main surface conductive portion 32 and is electrically connected to each pad 321. Each pad 321 to which the thermistor 6b is bonded is electrically connected to the lead 15 via the pad 321 electrically connected by a wiring 322. A predetermined current is passed through the thermistor 6b, and the thermistor 6b outputs a voltage signal according to the temperature of the wiring board 3.
　その他の受動素子６は、配線基板３に搭載され、基材３１の主面３１１上に配置されている。各受動素子６は、主面導電部３２のパッド３２１に導通接合されており、配線３２２およびパッド３２１を介して、駆動装置５に導通している。なお、各受動素子６の種類、配置位置、数は限定されない。 Other passive elements 6 are mounted on the wiring board 3 and arranged on the main surface 311 of the base material 31. Each passive element 6 is electrically connected to a pad 321 of the main surface conductive portion 32 and electrically connected to the drive device 5 via the wiring 322 and the pad 321. Note that the type, arrangement position, and number of each passive element 6 are not limited.
　複数のワイヤ７は、それぞれ複数のワイヤ７１，７２，７３，７４を含んでいる。複数のワイヤ７１は、半導体チップ４のソース電極４３とパッド２２１とに導通接合されている。本実施形態では、各半導体チップ４とパッド２２１とは２本のワイヤ７１で接続されているが、各半導体チップ４とパッド２２１とを接続するワイヤ７１の本数は限定されない。ワイヤ７１は、たとえば、アルミニウム（Ａｌ）または銅（Ｃｕ）等からなる。なお、ワイヤ７１の材料および線径は限定されない。複数のワイヤ７２は、主面導電部２２のパッド２２１とリード１２とに導通接合されている。パッド２２１とリード１２とを接続するワイヤ７２の本数は限定されない。ワイヤ７２は、たとえば、アルミニウム（Ａｌ）または銅（Ｃｕ）等からなる。なお、ワイヤ７２の材料および線径は限定されない。 The plurality of wires 7 each include a plurality of wires 71, 72, 73, and 74. The plurality of wires 71 are electrically connected to the source electrode 43 of the semiconductor chip 4 and the pad 221. In this embodiment, each semiconductor chip 4 and the pad 221 are connected by two wires 71, but the number of wires 71 connecting each semiconductor chip 4 and the pad 221 is not limited. The wire 71 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 71 are not limited. The plurality of wires 72 are electrically connected to the pads 221 of the main surface conductive portion 22 and the leads 12 . The number of wires 72 connecting pads 221 and leads 12 is not limited. The wire 72 is made of, for example, aluminum (Al) or copper (Cu). Note that the material and wire diameter of the wire 72 are not limited.
　複数のワイヤ７３は、半導体チップ４のソース電極４３またはゲート電極４４と、配線基板３の主面導電部３２のパッド３２１とに導通接合されている。本実施形態では、各半導体チップ４とパッド３２１とはそれぞれ１本のワイヤ７３で接続されているが、各半導体チップ４とパッド３２１とを接続するワイヤ７３の本数は限定されない。ワイヤ７３は、たとえば、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、またはアルミニウム（Ａｌ）等からなる。なお、ワイヤ７３の材料および線径は限定されない。複数のワイヤ７４は、配線基板３の主面導電部３２のパッド３２１とリード１６とに導通接合されている。本実施形態では、各パッド３２１と各リード１６とはそれぞれ１本のワイヤ７４で接続されているが、各パッド３２１と各リード１６とを接続するワイヤ７４の本数は限定されない。ワイヤ７４は、たとえば、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、またはアルミニウム（Ａｌ）等からなる。なお、ワイヤ７４の材料および線径は限定されない。 The plurality of wires 73 are electrically connected to the source electrode 43 or gate electrode 44 of the semiconductor chip 4 and the pad 321 of the main surface conductive portion 32 of the wiring board 3. In this embodiment, each semiconductor chip 4 and the pad 321 are connected by one wire 73, but the number of wires 73 connecting each semiconductor chip 4 and the pad 321 is not limited. The wire 73 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 73 are not limited. The plurality of wires 74 are electrically connected to the pads 321 of the main surface conductive portion 32 of the wiring board 3 and the leads 16 . In this embodiment, each pad 321 and each lead 16 are connected by one wire 74, but the number of wires 74 connecting each pad 321 and each lead 16 is not limited. The wire 74 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 74 are not limited.
　封止樹脂８は、複数の半導体チップ４、複数の駆動装置５、複数の受動素子６、および複数のワイヤ７と、複数のリード１の一部ずつと、配線基板２および配線基板３の一部ずつとを少なくとも覆っている。封止樹脂８の材料は特に限定されず、たとえばエポキシ樹脂、シリコーンゲル等の絶縁材料が適宜用いられる。 The sealing resin 8 seals a plurality of semiconductor chips 4 , a plurality of drive devices 5 , a plurality of passive elements 6 , a plurality of wires 7 , a portion of each of the plurality of leads 1 , and a portion of the wiring board 2 and the wiring board 3 . covering at least part of each part. The material of the sealing resin 8 is not particularly limited, and insulating materials such as epoxy resin and silicone gel may be used as appropriate.
　封止樹脂８は、樹脂主面８１、樹脂裏面８２、および４個の樹脂側面８３を有する。樹脂主面８１および樹脂裏面８２は、厚さ方向ｚにおいて互いに反対側を向く面であり、ともに厚さ方向ｚに対して直交する平坦面である。樹脂主面８１は、厚さ方向ｚの第１側ｚ１を向く面である。樹脂裏面８２は、厚さ方向ｚの第２側ｚ２を向く面である。各樹脂側面８３は、それぞれ、樹脂主面８１および樹脂裏面８２につながり、第２方向ｘまたは第１方向ｙを向いている。図４に示すように、配線基板２の裏面導電部２３および配線基板３の裏面導電部３３は、封止樹脂８の樹脂裏面８２から露出している。また、それぞれ複数のリード１１およびリード１２は、封止樹脂８の第１方向ｙの第１側ｙ１を向く樹脂側面８３から突出している。それぞれ複数のリード１５およびリード１６は、封止樹脂８の第１方向ｙの第２側ｙ２を向く樹脂側面８３から突出している。 The sealing resin 8 has a resin main surface 81, a resin back surface 82, and four resin side surfaces 83. The main resin surface 81 and the resin back surface 82 are surfaces facing opposite to each other in the thickness direction z, and are both flat surfaces perpendicular to the thickness direction z. The main resin surface 81 is a surface facing the first side z1 in the thickness direction z. The resin back surface 82 is a surface facing the second side z2 in the thickness direction z. Each resin side surface 83 is connected to the resin main surface 81 and the resin back surface 82, and faces the second direction x or the first direction y. As shown in FIG. 4, the back conductive part 23 of the wiring board 2 and the back conductive part 33 of the wiring board 3 are exposed from the resin back surface 82 of the sealing resin 8. Further, each of the plurality of leads 11 and leads 12 protrudes from the resin side surface 83 facing the first side y1 in the first direction y of the sealing resin 8. Each of the plurality of leads 15 and leads 16 protrudes from the resin side surface 83 facing the second side y2 in the first direction y of the sealing resin 8.
　次に、半導体装置Ａ１の製造方法の一例について、図８を参照して以下に説明する。なお、以下に説明する製造方法は、半導体装置Ａ１を実現するための一手段であり、これに限定されない。 Next, an example of a method for manufacturing the semiconductor device A1 will be described below with reference to FIG. 8. Note that the manufacturing method described below is one means for realizing the semiconductor device A1, and is not limited thereto.
　図８に示すように、本例の製造方法は、基板形成工程（ステップＳ１）、リードフレーム接合工程（ステップＳ２）、半導体チップ実装工程（ステップＳ３）、駆動装置実装工程（ステップＳ４）、ワイヤ接続工程（ステップＳ５）、樹脂形成工程（ステップＳ６）、およびフレーム切断工程（ステップＳ７）を有する。 As shown in FIG. 8, the manufacturing method of this example includes a substrate forming process (step S1), a lead frame bonding process (step S2), a semiconductor chip mounting process (step S3), a drive device mounting process (step S4), a wire The process includes a connecting process (step S5), a resin forming process (step S6), and a frame cutting process (step S7).
　基板形成工程（ステップＳ１）では、まず、２種類のＤＢＣ基板が準備される。一方のＤＢＣ基板は、窒化アルミニウムのセラミックスの板の両面にそれぞれ厚さ寸法Ｔ１の銅箔が接合された基板である。他方のＤＢＣ基板は、アルミナのセラミックスの板の両面にそれぞれ厚さ寸法Ｔ２の銅箔が接合された基板である。次いで、各ＤＢＣ基板の一方の面の銅箔をエッチングによりパターニングする。これにより、窒化アルミニウムのＤＢＣ基板が配線基板２になる。一方の面のパターニングされた銅箔が主面導電部２２になり、他方の銅箔が裏面導電部２３になる。また、アルミナのＤＢＣ基板が配線基板３になる。一方の面のパターニングされた銅箔が主面導電部３２になり、他方の銅箔が裏面導電部３３になる。 In the substrate forming step (step S1), two types of DBC substrates are first prepared. One DBC substrate is a substrate in which copper foils having a thickness of T1 are bonded to both sides of an aluminum nitride ceramic plate. The other DBC substrate is a substrate in which copper foil having a thickness of T2 is bonded to both sides of an alumina ceramic plate. Next, the copper foil on one side of each DBC board is patterned by etching. As a result, the aluminum nitride DBC substrate becomes the wiring board 2. The patterned copper foil on one side becomes the main surface conductive part 22, and the other copper foil becomes the back surface conductive part 23. Further, the alumina DBC board becomes the wiring board 3. The patterned copper foil on one side becomes the main surface conductive part 32, and the other copper foil becomes the back surface conductive part 33.
　リードフレーム接合工程（ステップＳ２）では、まず、配線基板２および配線基板３が第１方向ｙに並べて配置される。次いで、主面導電部２２の所定のパッド２２１および主面導電部３２の所定のパッド３２１に導電性接合ペーストを配置する。導電性接合ペーストは、たとえば銀ペースト、銅ペーストやはんだ等である。次いで、リードフレームを準備する。リードフレームは、複数のリード１を含んでおり、さらに複数のリード１がつながるフレームを有する。なお、リードフレームの形状等は、何ら限定されない。次いで、複数のリード１１をそれぞれ導電性接合ペーストを介して所定のパッド２２１に対面させる。また、複数のリード１５をそれぞれ導電性接合ペーストを介して所定のパッド３２１に対面させる。次いで、導電性接合ペーストを加熱した後に冷却することにより、導電性接合材７６が形成される。これにより、各リード１１が導電性接合材７６を介して所定のパッド２２１に接合され、各リード１５が導電性接合材７６を介してパッド３２１に接合される。 In the lead frame bonding step (step S2), first, the wiring board 2 and the wiring board 3 are arranged side by side in the first direction y. Next, a conductive bonding paste is placed on a predetermined pad 221 of the main surface conductive portion 22 and a predetermined pad 321 of the main surface conductive portion 32. The conductive bonding paste is, for example, silver paste, copper paste, or solder. Next, a lead frame is prepared. The lead frame includes a plurality of leads 1 and further has a frame to which the plurality of leads 1 are connected. Note that the shape of the lead frame and the like are not limited at all. Next, each of the plurality of leads 11 is made to face a predetermined pad 221 via a conductive bonding paste. Further, each of the plurality of leads 15 is made to face a predetermined pad 321 via a conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. As a result, each lead 11 is bonded to a predetermined pad 221 via the conductive bonding material 76, and each lead 15 is bonded to the pad 321 via the conductive bonding material 76.
　半導体チップ実装工程（ステップＳ３）では、まず、配線基板２の主面導電部２２の所定のパッド２２１の所定の位置に、導電性接合ペーストを配置する。次いで、導電性接合ペーストに、各半導体チップ４を付着させる。次いで、導電性接合ペーストを加熱した後に冷却することにより、導電性接合材７６が形成される。これにより、半導体チップ４が導電性接合材７６を介してパッド２２１に接合される。また、同様の工程により、シャント抵抗６ａを、導電性接合材７６を介してパッド２２１に接合させる。 In the semiconductor chip mounting process (step S3), first, a conductive bonding paste is placed at a predetermined position of a predetermined pad 221 on the main surface conductive portion 22 of the wiring board 2. Each semiconductor chip 4 is then attached to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the semiconductor chip 4 is bonded to the pad 221 via the conductive bonding material 76. Further, in a similar process, the shunt resistor 6a is bonded to the pad 221 via the conductive bonding material 76.
　駆動装置実装工程（ステップＳ４）では、まず、配線基板３の主面導電部３２の所定のパッド３２１に、導電性接合ペーストを配置する。次いで、導電性接合ペーストに、各駆動装置５の各端子を付着させる。次いで、導電性接合ペーストを加熱した後に冷却することにより、導電性接合材７６が形成される。これにより、駆動装置５が導電性接合材７６を介してパッド３２１に接合される。また、同様の工程により、サーミスタ６ｂおよびその他の受動素子６を、導電性接合材７６を介してパッド３２１に接合させる。 In the drive device mounting step (step S4), first, a conductive bonding paste is placed on a predetermined pad 321 of the main surface conductive portion 32 of the wiring board 3. Each terminal of each drive device 5 is then adhered to the conductive bonding paste. Next, the conductive bonding material 76 is formed by heating and then cooling the conductive bonding paste. Thereby, the drive device 5 is bonded to the pad 321 via the conductive bonding material 76. Further, the thermistor 6b and other passive elements 6 are bonded to the pad 321 via the conductive bonding material 76 by a similar process.
　ワイヤ接続工程（ステップＳ５）では、まず、複数のワイヤ７１，７２を接続する。本例においては、たとえばウエッジボンディングの手法により、アルミニウム（Ａｌ）からなるワイヤ材を順次接続する。これにより、複数のワイヤ７１が得られる。次いで、複数のワイヤ７３，７４を接続する。本例においては、たとえばキャピラリボンディングの手法により、金（Ａｕ）からなるワイヤ材を順次接続する。これにより、複数のワイヤ７２が得られる。 In the wire connection step (step S5), first, a plurality of wires 71 and 72 are connected. In this example, wires made of aluminum (Al) are sequentially connected by, for example, a wedge bonding method. Thereby, a plurality of wires 71 are obtained. Next, the plurality of wires 73 and 74 are connected. In this example, wire materials made of gold (Au) are sequentially connected by, for example, a capillary bonding method. Thereby, a plurality of wires 72 are obtained.
　樹脂形成工程（ステップＳ６）では、たとえば、リードフレームの一部と、配線基板２，３と、それぞれ複数の半導体チップ４、駆動装置５、受動素子６、およびワイヤ７とを金型によって囲む。次いで、金型によって規定された空間に液状の樹脂材料を注入する。次いで、この樹脂材料を硬化させることにより、封止樹脂８が得られる。 In the resin forming step (step S6), for example, a part of the lead frame, the wiring boards 2 and 3, each of the plurality of semiconductor chips 4, the driving device 5, the passive element 6, and the wire 7 are surrounded by a mold. Next, a liquid resin material is injected into the space defined by the mold. Next, the sealing resin 8 is obtained by curing this resin material.
　フレーム切断工程（ステップＳ７）では、リードフレームのうち封止樹脂８から露出した部位の適所を切断する。これにより、複数のリード１が互いに分割される。この後は、必要に応じて、複数のリード１を折り曲げる等の処理を経ることにより、上述した半導体装置Ａ１が得られる。 In the frame cutting step (step S7), the lead frame is cut at an appropriate location exposed from the sealing resin 8. As a result, the plurality of leads 1 are divided from each other. Thereafter, the above-described semiconductor device A1 is obtained by performing a process such as bending the plurality of leads 1 as necessary.
　次に、半導体装置Ａ１の作用効果について説明する。 Next, the effects of the semiconductor device A1 will be explained.
　本実施形態によると、配線基板３は、基材３１の主面３１１上に配置された主面導電部３２を備えている。主面導電部３２は、パッド３２１に駆動装置５が導通接合されている。これにより、駆動装置５への導通経路を、基材３１の主面３１１上に配置された主面導電部３２によって構成できる。したがって、たとえば金属製のリードによって導通経路を構成する場合と比較して、導通経路の細線化および高密度化を図ることが可能である。 According to the present embodiment, the wiring board 3 includes the main surface conductive portion 32 disposed on the main surface 311 of the base material 31. The driving device 5 is electrically connected to the pad 321 of the main surface conductive portion 32 . Thereby, the conduction path to the drive device 5 can be configured by the main surface conductive portion 32 disposed on the main surface 311 of the base material 31. Therefore, compared to, for example, a case where the conduction path is formed of metal leads, it is possible to make the conduction path thinner and more dense.
　また、本実施形態によると、半導体装置Ａ１は、配線基板３とは別に、配線基板２を備えている。配線基板２は、基材２１の主面２１１上に配置された主面導電部２２を備えている。主面導電部２２は、パッド２２１に半導体チップ４が接合されている。主面導電部２２の厚さ寸法Ｔ１は、主面導電部３２の厚さ寸法Ｔ２と比較して大きく、半導体チップ４が発する熱の放熱効果を維持できる厚さである。一方、厚さ寸法Ｔ２は、厚さ寸法Ｔ１と比較して小さく、エッチングによってより微細な加工が可能な厚さである。共通の基材の主面に共通の主面導電部を配置した場合、主面導電部を厚くすると微細な加工が困難になり、主面導電部を薄くすると十分な放熱効果が得られない。半導体装置Ａ１は、配線基板２および配線基板３を備えているので、半導体チップ４が発する熱の放熱と、駆動装置５への導通経路の細線化および高密度化とを、両立できる。 Furthermore, according to the present embodiment, the semiconductor device A1 includes a wiring board 2 in addition to the wiring board 3. The wiring board 2 includes a main surface conductive portion 22 disposed on the main surface 211 of the base material 21 . In the main surface conductive portion 22, the semiconductor chip 4 is bonded to the pad 221. The thickness T1 of the main surface conductive portion 22 is larger than the thickness T2 of the main surface conductive portion 32, and is thick enough to maintain the heat dissipation effect of the heat generated by the semiconductor chip 4. On the other hand, the thickness dimension T2 is smaller than the thickness dimension T1, and is a thickness that allows finer processing by etching. When a common main surface conductive portion is arranged on the main surface of a common base material, if the main surface conductive portion is made thick, fine processing becomes difficult, and if the main surface conductive portion is made thin, a sufficient heat dissipation effect cannot be obtained. Since the semiconductor device A1 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense.
　また、本実施形態によると、配線基板２は、ＤＢＣ基板の一方の面の銅箔をエッチングによりパターニングすることで形成される。したがって、基材２１に主面導電部２２および裏面導電部２３をそれぞれ形成する場合と比較して、製造工程を簡易にできる。配線基板３も同様である。 Furthermore, according to the present embodiment, the wiring board 2 is formed by patterning the copper foil on one side of the DBC board by etching. Therefore, compared to the case where the main surface conductive portion 22 and the back surface conductive portion 23 are respectively formed on the base material 21, the manufacturing process can be simplified. The same applies to the wiring board 3.
　また、本実施形態によると、配線基板２の基材２１は、窒化アルミニウムのセラミックスの板である。また、配線基板３の基材３１は、アルミナのセラミックスの板である。したがって、基材２１は、基材３１より熱伝導性が高い。これにより、配線基板２は、半導体チップ４が発する熱を、適切に放熱できる。また、配線基板２ほど放熱性を要求されない配線基板３の材料コストを抑制できる。 Furthermore, according to the present embodiment, the base material 21 of the wiring board 2 is an aluminum nitride ceramic plate. Further, the base material 31 of the wiring board 3 is an alumina ceramic plate. Therefore, the base material 21 has higher thermal conductivity than the base material 31. Thereby, the wiring board 2 can appropriately dissipate the heat generated by the semiconductor chip 4. Further, the material cost of the wiring board 3, which does not require as much heat dissipation as the wiring board 2, can be reduced.
　また、本実施形態によると、配線基板２の裏面導電部３３は、樹脂裏面８２から露出している。これにより、半導体チップ４から配線基板２に伝わった熱を、より効率よく外部に放熱できる。 Furthermore, according to the present embodiment, the back conductive portion 33 of the wiring board 2 is exposed from the resin back surface 82. Thereby, the heat transmitted from the semiconductor chip 4 to the wiring board 2 can be radiated to the outside more efficiently.
　また、本実施形態によると、半導体装置Ａ１は、配線基板３に搭載されたサーミスタ６ｂを備えている。したがって、半導体装置Ａ１は、配線基板３の温度を検出することができる。 Furthermore, according to the present embodiment, the semiconductor device A1 includes a thermistor 6b mounted on the wiring board 3. Therefore, the semiconductor device A1 can detect the temperature of the wiring board 3.
　また、本実施形態によると、複数のリード１１は、導電性接合材７６を介して主面導電部２２のパッド２２１に接合されている。これにより、複数のリード１１は、配線基板２に対して強固に固定される。また、複数のリード１１と主面導電部２２との間の低抵抗化を図ることができる。また、複数のリード１５は、導電性接合材７６を介して主面導電部３２のパッド３２１に接合されている。これにより、複数のリード１５は、配線基板３に対して強固に固定される。また、複数のリード１５と主面導電部３２との間の低抵抗化を図ることができる。 Further, according to the present embodiment, the plurality of leads 11 are bonded to the pads 221 of the main surface conductive portion 22 via the conductive bonding material 76. Thereby, the plurality of leads 11 are firmly fixed to the wiring board 2. Further, it is possible to reduce the resistance between the plurality of leads 11 and the main surface conductive portion 22. Further, the plurality of leads 15 are bonded to the pads 321 of the main surface conductive portion 32 via a conductive bonding material 76 . Thereby, the plurality of leads 15 are firmly fixed to the wiring board 3. Furthermore, the resistance between the plurality of leads 15 and the main surface conductive portion 32 can be reduced.
　なお、本実施形態においては、基材３１の構成材料がセラミックスである場合について説明したが、これに限られない。基材３１は、基材２１ほど熱伝導性を必要としないので、ガラスエポキシ樹脂などの合成樹脂を含んだ基板であってもよい。つまり、配線基板３は、いわゆるＰＣＢ（Printed Circuit Board）基板であってもよい。また、基材３１は、複数の基材が積層された多層基板であってもよい。 In addition, in this embodiment, the case where the constituent material of the base material 31 was ceramics was described, but it is not limited to this. Since the base material 31 does not require as much thermal conductivity as the base material 21, it may be a substrate containing synthetic resin such as glass epoxy resin. That is, the wiring board 3 may be a so-called PCB (Printed Circuit Board) board. Further, the base material 31 may be a multilayer substrate in which a plurality of base materials are laminated.
　図９～図１２は、本開示の他の実施形態を示している。なお、これらの図において、上記実施形態と同一または類似の要素には、上記実施形態と同一の符号を付している。 9 to 12 show other embodiments of the present disclosure. Note that in these figures, elements that are the same or similar to those in the above embodiment are given the same reference numerals as in the above embodiment.
　第２実施形態：
　図９は、本開示の第２実施形態に係る半導体装置Ａ２を説明するための図である。図９は、半導体装置Ａ２を示す断面図であり、図５に対応する図である。第２実施形態に係る半導体装置Ａ２は、配線基板３の全体が封止樹脂８に覆われている点で、第１実施形態と異なっている。本実施形態の他の部分の構成および動作は、第１実施形態と同様である。 Second embodiment:
FIG. 9 is a diagram for explaining a semiconductor device A2 according to a second embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing the semiconductor device A2, and corresponds to FIG. 5. As shown in FIG. The semiconductor device A2 according to the second embodiment differs from the first embodiment in that the entire wiring board 3 is covered with a sealing resin 8. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment.
　本実施形態では、配線基板３は、裏面導電部３３を備えていない。本実施形態に係る配線基板３は、セラミックスの板の片面のみに銅箔が接合されたＤＢＣ基板の銅箔をエッチングによりパターニングすることで形成される。また、配線基板３は、樹脂裏面８２から露出しておらず、全体が封止樹脂８に覆われている。配線基板３は、半導体チップ４が搭載された配線基板２とは異なり、放熱性をあまり要求されない。したがって、配線基板３は、樹脂裏面８２から露出せず放熱性が抑制されても、あまり問題にならない。 In this embodiment, the wiring board 3 does not include the back conductive portion 33. The wiring board 3 according to this embodiment is formed by etching and patterning the copper foil of a DBC board in which copper foil is bonded to only one side of a ceramic plate. Further, the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8. Unlike the wiring board 2 on which the semiconductor chip 4 is mounted, the wiring board 3 is not required to have much heat dissipation. Therefore, even if the wiring board 3 is not exposed from the resin back surface 82 and its heat dissipation is suppressed, it does not pose much of a problem.
　本実施形態においても、半導体装置Ａ２は、配線基板２および配線基板３を備えているので、半導体チップ４が発する熱の放熱と、駆動装置５への導通経路の細線化および高密度化とを、両立できる。また、半導体装置Ａ２は、半導体装置Ａ１と共通する構成をとることにより、半導体装置Ａ１と同等の効果を奏する。さらに、半導体装置Ａ２は、配線基板３が裏面導電部３３を備えていないので、材料コストを抑制できる。 Also in this embodiment, since the semiconductor device A2 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible. In addition, the semiconductor device A2 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A2, since the wiring board 3 does not include the back conductive portion 33, material costs can be suppressed.
　なお、本実施形態では、配線基板３が樹脂裏面８２から露出していない場合について説明したが、これに限られない。配線基板３は、基材３１の裏面３１２が樹脂裏面８２から露出してもよい。 Note that, in this embodiment, a case has been described in which the wiring board 3 is not exposed from the resin back surface 82, but the present invention is not limited to this. In the wiring board 3, the back surface 312 of the base material 31 may be exposed from the resin back surface 82.
　第３実施形態：
　図１０は、本開示の第３実施形態に係る半導体装置Ａ３を説明するための図である。図１０は、半導体装置Ａ３を示す断面図であり、図５に対応する図である。第３実施形態に係る半導体装置Ａ３は、配線基板３の基材３１の裏面３１２上にも受動素子６が配置されている点で、第１実施形態と異なっている。本実施形態の他の部分の構成および動作は、第１実施形態と同様である。なお、上記の第１～２実施形態の各部が任意に組み合わせられてもよい。 Third embodiment:
FIG. 10 is a diagram for explaining a semiconductor device A3 according to a third embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing the semiconductor device A3, and corresponds to FIG. 5. As shown in FIG. The semiconductor device A3 according to the third embodiment differs from the first embodiment in that the passive element 6 is also arranged on the back surface 312 of the base material 31 of the wiring board 3. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first and second embodiments described above may be combined arbitrarily.
　本実施形態では、配線基板３は、主面３１１上だけではなく、裏面３１２上にも受動素子６が配置されている。なお、裏面３１２上に配置される受動素子６の種類、個数、および配置位置は限定されない。配線基板３は、裏面導電部３３がパッド３３１および配線３３２を含んでいる。パッド３３１および配線３３２は、ＤＢＣ基板の他方の面の銅箔をエッチングによりパターニングすることで形成される。なお、裏面導電部３３の形状は限定されない。パッド３３１には、導電性接合材７６を介して、受動素子６が導通接合されている。また、本実施形態でも第２実施形態と同様に、配線基板３は、樹脂裏面８２から露出しておらず、全体が封止樹脂８に覆われている。また、裏面３１２上に配置された受動素子６も封止樹脂８に覆われている。なお、裏面３１２上に配置される電子部品は受動素子６に限定されず、たとえば駆動装置５が裏面３１２上に配置されてもよい。 In this embodiment, the wiring board 3 has passive elements 6 arranged not only on the main surface 311 but also on the back surface 312. Note that the type, number, and arrangement position of the passive elements 6 arranged on the back surface 312 are not limited. In the wiring board 3, the back conductive portion 33 includes pads 331 and wiring 332. The pad 331 and the wiring 332 are formed by patterning the copper foil on the other side of the DBC substrate by etching. Note that the shape of the back conductive portion 33 is not limited. The passive element 6 is conductively bonded to the pad 331 via a conductive bonding material 76 . Further, in this embodiment as well, the wiring board 3 is not exposed from the resin back surface 82 and is entirely covered with the sealing resin 8, as in the second embodiment. Further, the passive element 6 disposed on the back surface 312 is also covered with the sealing resin 8. Note that the electronic components arranged on the back surface 312 are not limited to the passive element 6; for example, the driving device 5 may be arranged on the back surface 312.
　本実施形態においても、半導体装置Ａ３は、配線基板２および配線基板３を備えているので、半導体チップ４が発する熱の放熱と、駆動装置５への導通経路の細線化および高密度化とを、両立できる。また、半導体装置Ａ３は、半導体装置Ａ１と共通する構成をとることにより、半導体装置Ａ１と同等の効果を奏する。さらに、半導体装置Ａ３は、配線基板３の両面に受動素子６が配置できるので、より多くの受動素子６を搭載できる。また、配線基板３に搭載される受動素子６が変わらない場合、受動素子６を両面に配置することで、配線基板３の厚さ方向ｚに視た形状を小さくできる。これにより、半導体装置Ａ３は、小型化可能である。 Also in this embodiment, since the semiconductor device A3 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to make the conduction path to the drive device 5 thinner and more dense. , can be compatible. In addition, the semiconductor device A3 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Furthermore, in the semiconductor device A3, since the passive elements 6 can be arranged on both sides of the wiring board 3, more passive elements 6 can be mounted. Furthermore, when the passive elements 6 mounted on the wiring board 3 do not change, the shape of the wiring board 3 viewed in the thickness direction z can be made smaller by arranging the passive elements 6 on both sides. Thereby, the semiconductor device A3 can be downsized.
　第４実施形態：
　図１１は、本開示の第４実施形態に係る半導体装置Ａ４を説明するための図である。図１１は、半導体装置Ａ４を示す断面図であり、図５に対応する図である。第４実施形態に係る半導体装置Ａ４は、配線基板２および配線基板３の配置方法が、第１実施形態と異なっている。本実施形態の他の部分の構成および動作は、第１実施形態と同様である。なお、上記の第１～３実施形態の各部が任意に組み合わせられてもよい。 Fourth embodiment:
FIG. 11 is a diagram for explaining a semiconductor device A4 according to a fourth embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing the semiconductor device A4, and corresponds to FIG. 5. As shown in FIG. The semiconductor device A4 according to the fourth embodiment differs from the first embodiment in the arrangement method of the wiring board 2 and the wiring board 3. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to third embodiments described above may be combined arbitrarily.
　本実施形態では、配線基板２は、半導体装置Ａ１の場合と比較して、第１方向ｙの寸法が大きい。配線基板３は、配線基板２の厚さ方向ｚの第１側ｚ１で、配線基板２の第１方向ｙの第２側ｙ２寄りに配置されている。配線基板３は、厚さ方向ｚに視て全体が配線基板２に重なっている。配線基板３は、裏面導電部３３を備えておらず、基材３１の裏面３１２が、配線基板２の基材２１の主面２１１に接合されている。 In this embodiment, the wiring board 2 has a larger dimension in the first direction y than that of the semiconductor device A1. The wiring board 3 is disposed on the first side z1 of the wiring board 2 in the thickness direction z and closer to the second side y2 of the wiring board 2 in the first direction y. The entire wiring board 3 overlaps the wiring board 2 when viewed in the thickness direction z. The wiring board 3 does not include the back conductive portion 33, and the back surface 312 of the base material 31 is joined to the main surface 211 of the base material 21 of the wiring board 2.
　本実施形態においても、半導体装置Ａ４は、配線基板２および配線基板３を備えているので、半導体チップ４が発する熱の放熱と、駆動装置５への導通経路の細線化および高密度化とを、両立できる。また、半導体装置Ａ４は、半導体装置Ａ１と共通する構成をとることにより、半導体装置Ａ１と同等の効果を奏する。さらに、半導体装置Ａ４は、配線基板２の第１方向ｙの寸法が大きいので、樹脂裏面８２から露出する裏面導電部２３の面積も大きい。これにより、半導体装置Ａ４は、半導体チップ４から配線基板２に伝わった熱を、より効率よく外部に放熱できる。 Also in this embodiment, since the semiconductor device A4 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible. In addition, the semiconductor device A4 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, in the semiconductor device A4, since the wiring board 2 has a large dimension in the first direction y, the area of the back conductive portion 23 exposed from the resin back surface 82 is also large. Thereby, the semiconductor device A4 can more efficiently radiate heat transferred from the semiconductor chip 4 to the wiring board 2 to the outside.
　第５実施形態：
　図１２は、本開示の第５実施形態に係る半導体装置Ａ５を説明するための図である。図１２は、半導体装置Ａ５を示す部分拡大平面図であり、図３に対応する図の一部を拡大した図である。なお、図１２においては、封止樹脂８を省略している。第５実施形態に係る半導体装置Ａ５は、配線基板２にもサーミスタが搭載されている点で、第１実施形態と異なっている。本実施形態の他の部分の構成および動作は、第１実施形態と同様である。なお、上記の第１～４実施形態の各部が任意に組み合わせられてもよい。 Fifth embodiment:
FIG. 12 is a diagram for explaining a semiconductor device A5 according to a fifth embodiment of the present disclosure. FIG. 12 is a partially enlarged plan view showing the semiconductor device A5, and is a partially enlarged view of the diagram corresponding to FIG. Note that in FIG. 12, the sealing resin 8 is omitted. The semiconductor device A5 according to the fifth embodiment differs from the first embodiment in that a thermistor is also mounted on the wiring board 2. The configuration and operation of other parts of this embodiment are similar to those of the first embodiment. Note that each part of the first to fourth embodiments described above may be combined arbitrarily.
　本実施形態では、半導体装置Ａ５は、サーミスタ６ｃをさらに備えている。サーミスタ６ｃは、配線基板２に搭載され、基材２１の主面２１１上に配置されている。本実施形態では、配線基板２の主面導電部２２は、２個のパッド２２１ａを含んでいる。２個のパッド２２１ａは、基材２１の主面２１１の第２方向ｘの中央で第１方向ｙの第２側ｙ２の端部に、ｘ方向に並んで互いに離間して配置されている。サーミスタ６ｃは、２個のパッド２２１ａに跨って、各パッド２２１ａに導通接合されている。また、本実施形態では、２本のワイヤ７５をさらに備えている。ワイヤ７５は、たとえば、金（Ａｕ）、銀（Ａｇ）、銅（Ｃｕ）、またはアルミニウム（Ａｌ）等からなる。なお、ワイヤ７５の材料および線径は限定されない。各ワイヤ７５はそれぞれ、パッド２２１ａと主面導電部３２のパッド３２１とに導通接合されている。各ワイヤ７５が接合されたパッド３２１はそれぞれ、配線３２２によって導通接続されたパッド３２１を介して、リード１５に導通している。なお、主面導電部３２のレイアウトは記載を省略している。サーミスタ６ｃは、所定の電流が流されて、配線基板２の温度に応じた電圧信号を出力する。 In this embodiment, the semiconductor device A5 further includes a thermistor 6c. The thermistor 6c is mounted on the wiring board 2 and arranged on the main surface 211 of the base material 21. In this embodiment, the main surface conductive portion 22 of the wiring board 2 includes two pads 221a. The two pads 221a are arranged in the x direction at the center of the main surface 211 of the base material 21 in the second direction x, at the end of the second side y2 in the first direction y, and spaced apart from each other in the x direction. The thermistor 6c straddles the two pads 221a and is electrically connected to each pad 221a. Moreover, in this embodiment, two wires 75 are further provided. The wire 75 is made of, for example, gold (Au), silver (Ag), copper (Cu), or aluminum (Al). Note that the material and wire diameter of the wire 75 are not limited. Each wire 75 is electrically connected to the pad 221a and the pad 321 of the main surface conductive portion 32, respectively. The pads 321 to which each wire 75 is bonded are electrically connected to the leads 15 via the pads 321 electrically connected by wiring 322, respectively. Note that the layout of the main surface conductive portion 32 is not described. A predetermined current is passed through the thermistor 6c, and the thermistor 6c outputs a voltage signal according to the temperature of the wiring board 2.
　本実施形態においても、半導体装置Ａ５は、配線基板２および配線基板３を備えているので、半導体チップ４が発する熱の放熱と、駆動装置５への導通経路の細線化および高密度化とを、両立できる。また、半導体装置Ａ５は、半導体装置Ａ１と共通する構成をとることにより、半導体装置Ａ１と同等の効果を奏する。さらに、半導体装置Ａ５は、サーミスタ６ｃを備えているので、配線基板２の温度を検出することができる。 Also in this embodiment, since the semiconductor device A5 includes the wiring board 2 and the wiring board 3, it is possible to dissipate the heat generated by the semiconductor chip 4 and to thin and increase the density of the conduction path to the drive device 5. , can be compatible. In addition, the semiconductor device A5 has the same configuration as the semiconductor device A1, and thus achieves the same effects as the semiconductor device A1. Further, since the semiconductor device A5 includes the thermistor 6c, the temperature of the wiring board 2 can be detected.
　なお、本実施形態では、半導体装置Ａ５が、配線基板２の温度を検出するためのサーミスタ６ｃを１個だけ備えている場合について説明したが、これに限られない。半導体装置Ａ５は、たとえば４個のサーミスタ６ｃを備え、各サーミスタ６ｃがそれぞれ半導体チップ４に隣接して配置されてもよい。この場合、各サーミスタ６ｃはそれぞれ、隣接した半導体チップ４の温度を検出できる。 Note that in this embodiment, a case has been described in which the semiconductor device A5 includes only one thermistor 6c for detecting the temperature of the wiring board 2, but the present invention is not limited to this. The semiconductor device A5 may include, for example, four thermistors 6c, and each thermistor 6c may be arranged adjacent to the semiconductor chip 4. In this case, each thermistor 6c can detect the temperature of the adjacent semiconductor chip 4.
　本開示に係る半導体装置は、先述した実施形態に限定されるものではない。本開示に係る半導体装置の各部の具体的な構成は、種々に設計変更自在である。本開示は以下の付記に記載された実施形態を含む。 The semiconductor device according to the present disclosure is not limited to the embodiments described above. The specific configuration of each part of the semiconductor device according to the present disclosure can be changed in design in various ways. The present disclosure includes the embodiments described in the appendix below.
　付記１．
　厚さ方向（ｚ）において互いに反対側を向く第１主面（２１１）および第１裏面（２１２）を有する第１基材（２１）と、
　前記第１主面上に配置された導電性を有する第１主面導電部（２２）と、
　前記厚さ方向において前記第１主面と同じ側を向く第２主面（３１１）および前記第１裏面と同じ側を向く第２裏面（３１２）を有する第２基材（３１）と、
　前記第２主面上に配置された導電性を有する第２主面導電部（３２）と、
　前記第１主面上に配置されて前記第１主面導電部に導通接続されたスイッチング素子（４）と、
　前記第２主面上に配置されて前記第２主面導電部に導通接続され、かつ、前記スイッチング素子を駆動させる駆動装置（５）と、
　前記第１基材および前記第２基材の少なくとも一部と、前記スイッチング素子および前記駆動装置の全体と、を覆う封止樹脂（８）と、
を備えている、半導体装置（Ａ１）。
　付記２．（図６）
　前記第１主面導電部の前記厚さ方向の第１寸法（Ｔ１）は、前記第２主面導電部の前記厚さ方向の第２寸法（Ｔ２）より大きい、付記１に記載の半導体装置。
　付記３．
　前記第１基材は、前記第２基材より熱伝導性が高い、付記１または２に記載の半導体装置。
　付記４．
　前記第１基材は、窒化アルミニウムを含んでいる、付記１ないし３のいずれかに記載の半導体装置。
　付記５．
　前記第２基材は、アルミナを含んでいる、付記１ないし４のいずれかに記載の半導体装置。
　付記６．
　前記第２基材は、合成樹脂を含んでいる、付記１ないし４のいずれかに記載の半導体装置。
　付記７．
　前記第２基材は、前記第１基材に対して、前記厚さ方向に直交する第１方向（ｙ）に配置されている、付記１ないし６のいずれかに記載の半導体装置。
　付記８．
　前記第２裏面上に配置された導電性を有する第２裏面導電部（３３）をさらに備え、
　前記第２裏面導電部は、前記封止樹脂から露出している、付記７に記載の半導体装置。
　付記９．（第３実施形態、図１０）
　前記第２裏面上に配置された裏面電子部品（６）をさらに備え、
　前記裏面電子部品は、前記封止樹脂に覆われている、付記７に記載の半導体装置。
　付記１０．（第４実施形態、図１１）
　前記第２基材は、前記第１基材に対して、前記厚さ方向に配置されている、付記１ないし６のいずれかに記載の半導体装置。
　付記１１．
　前記第１裏面上に配置された導電性を有する第１裏面導電部（２３）をさらに備え、
　前記第１裏面導電部は、前記封止樹脂から露出している、付記１ないし１０のいずれかに記載の半導体装置。
　付記１２．
　前記駆動装置は、絶縁ゲートドライバである、付記１ないし１１のいずれかに記載の半導体装置。
　付記１３．（第５実施形態、図１２）
　前記第１主面上に配置された第１温度検出部（６ｃ）をさらに備えている、付記１ないし１２のいずれかに記載の半導体装置。
　付記１４．
　前記第２主面上に配置された第２温度検出部（６ｂ）をさらに備えている、付記１ないし１３のいずれかに記載の半導体装置。 Additional note 1.
a first base material (21) having a first main surface (211) and a first back surface (212) facing oppositely to each other in the thickness direction (z);
a first main surface conductive part (22) having electrical conductivity disposed on the first main surface;
a second base material (31) having a second main surface (311) facing the same side as the first main surface in the thickness direction and a second back surface (312) facing the same side as the first back surface;
a second main surface conductive part (32) having electrical conductivity disposed on the second main surface;
a switching element (4) disposed on the first main surface and electrically connected to the first main surface conductive part;
a drive device (5) disposed on the second main surface, electrically connected to the second main surface conductive part, and driving the switching element;
a sealing resin (8) that covers at least a portion of the first base material and the second base material, and the entire switching element and the drive device;
A semiconductor device (A1) comprising:
Appendix 2. (Figure 6)
The semiconductor device according to Supplementary Note 1, wherein the first dimension (T1) of the first main surface conductive part in the thickness direction is larger than the second dimension (T2) of the second main surface conductive part in the thickness direction. .
Appendix 3.
The semiconductor device according to appendix 1 or 2, wherein the first base material has higher thermal conductivity than the second base material.
Appendix 4.
The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein the first base material contains aluminum nitride.
Appendix 5.
5. The semiconductor device according to any one of appendices 1 to 4, wherein the second base material contains alumina.
Appendix 6.
5. The semiconductor device according to any one of appendices 1 to 4, wherein the second base material contains a synthetic resin.
Appendix 7.
7. The semiconductor device according to any one of appendices 1 to 6, wherein the second base material is disposed in a first direction (y) perpendicular to the thickness direction with respect to the first base material.
Appendix 8.
further comprising a second back conductive portion (33) having conductivity disposed on the second back surface,
The semiconductor device according to appendix 7, wherein the second back conductive portion is exposed from the sealing resin.
Appendix 9. (Third embodiment, FIG. 10)
further comprising a backside electronic component (6) disposed on the second backside,
The semiconductor device according to appendix 7, wherein the back side electronic component is covered with the sealing resin.
Appendix 10. (Fourth embodiment, FIG. 11)
7. The semiconductor device according to any one of appendices 1 to 6, wherein the second base material is disposed in the thickness direction with respect to the first base material.
Appendix 11.
further comprising a first back conductive portion (23) having conductivity disposed on the first back surface,
11. The semiconductor device according to any one of appendices 1 to 10, wherein the first back conductive portion is exposed from the sealing resin.
Appendix 12.
12. The semiconductor device according to any one of Supplementary Notes 1 to 11, wherein the driving device is an insulated gate driver.
Appendix 13. (Fifth embodiment, FIG. 12)
The semiconductor device according to any one of appendices 1 to 12, further comprising a first temperature detection section (6c) arranged on the first main surface.
Appendix 14.
14. The semiconductor device according to any one of appendices 1 to 13, further comprising a second temperature detection section (6b) disposed on the second main surface.
Ａ１，Ａ２，Ａ３，Ａ４，Ａ５：半導体装置
１，１１，１２，１５，１６：リード
１１１：接合部分　　　　１１１ａ：主面
１１１ｂ：裏面　　　　１１２：突出部分
１１３：傾斜接続部分　　　　１１４：平行接続部分
１５１：接合部分　　　　１５１ａ：主面
１５１ｂ：裏面　　　　１５２：突出部分
１５３：傾斜接続部分　　　　１５４：平行接続部分
２：配線基板　　　　２１：基材
２１１：主面　　　　２１２：裏面
２２：主面導電部　　　　２２１，２２１ａ：パッド
２２２：配線　　　　２３：裏面導電部
３：配線基板　　　　３１：基材
３１１：主面　　　　３１２：裏面
３２：主面導電部　　　　３２１：パッド
３２２：配線　　　　３３：裏面導電部
３３１：パッド　　　　３３２：配線
４：半導体チップ　　　　４１：素子主面
４２：素子裏面　　　　４３：ソース電極
４４：ゲート電極　　　　４５：ドレイン電極
５：駆動装置　　　　６：受動素子
６ａ：シャント抵抗　　　　６ｂ，６ｃ：サーミスタ
７，７１～７５：ワイヤ　　　　７６：導電性接合材
８：封止樹脂　　　　８１：樹脂主面
８２：樹脂裏面　　　　８３：樹脂側面 A1, A2, A3, A4, A5: Semiconductor device 1, 11, 12, 15, 16: Lead 111: Joint portion 111a: Main surface 111b: Back surface 112: Projecting portion 113: Inclined connection portion 114: Parallel connection portion 151: Joint portion 151a: Main surface 151b: Back surface 152: Protruding portion 153: Slanted connection portion 154: Parallel connection portion 2: Wiring board 21: Base material 211: Main surface 212: Back surface 22: Main surface conductive portion 221, 221a: Pad 222 : Wiring 23: Back conductive part 3: Wiring board 31: Base material 311: Main surface 312: Back surface 32: Main surface conductive part 321: Pad 322: Wiring 33: Back conductive part 331: Pad 332: Wiring 4: Semiconductor chip 41 : Element principal surface 42: Element back surface 43: Source electrode 44: Gate electrode 45: Drain electrode 5: Drive device 6: Passive element 6a: Shunt resistor 6b, 6c: Thermistor 7, 71 to 75: Wire 76: Conductive bonding material 8: Sealing resin 81: Resin main surface 82: Resin back surface 83: Resin side surface

Claims (14)

  1. 　厚さ方向において互いに反対側を向く第１主面および第１裏面を有する第１基材と、
    　前記第１主面上に配置された導電性を有する第１主面導電部と、
    　前記厚さ方向において前記第１主面と同じ側を向く第２主面および前記第１裏面と同じ側を向く第２裏面を有する第２基材と、
    　前記第２主面上に配置された導電性を有する第２主面導電部と、
    　前記第１主面上に配置されて前記第１主面導電部に導通接続されたスイッチング素子と、
    　前記第２主面上に配置されて前記第２主面導電部に導通接続され、かつ、前記スイッチング素子を駆動させる駆動装置と、
    　前記第１基材および前記第２基材の少なくとも一部と、前記スイッチング素子および前記駆動装置の全体と、を覆う封止樹脂と、
    を備えている、半導体装置。     a first base material having a first main surface and a first back surface facing opposite to each other in the thickness direction;
    a first main surface conductive portion having electrical conductivity disposed on the first main surface;
    a second base material having a second main surface facing the same side as the first main surface in the thickness direction and a second back surface facing the same side as the first back surface;
    a second main surface conductive portion having electrical conductivity disposed on the second main surface;
    a switching element disposed on the first main surface and electrically connected to the first main surface conductive part;
    a driving device disposed on the second main surface, electrically connected to the second main surface conductive portion, and driving the switching element;
    a sealing resin that covers at least a portion of the first base material and the second base material, and the entire switching element and the drive device;
    A semiconductor device equipped with
  2. 　前記第１主面導電部の前記厚さ方向の第１寸法は、前記第２主面導電部の前記厚さ方向の第２寸法より大きい、請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the first dimension in the thickness direction of the first main surface conductive portion is larger than the second dimension in the thickness direction of the second main surface conductive portion.
  3. 　前記第１基材は、前記第２基材より熱伝導性が高い、請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the first base material has higher thermal conductivity than the second base material.
  4. 　前記第１基材は、窒化アルミニウムを含んでいる、請求項１ないし３のいずれかに記載の半導体装置。 4. The semiconductor device according to claim 1, wherein the first base material contains aluminum nitride.
  5. 　前記第２基材は、アルミナを含んでいる、請求項１ないし４のいずれかに記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the second base material contains alumina.
  6. 　前記第２基材は、合成樹脂を含んでいる、請求項１ないし４のいずれかに記載の半導体装置。 5. The semiconductor device according to claim 1, wherein the second base material contains a synthetic resin.
  7. 　前記第２基材は、前記第１基材に対して、前記厚さ方向に直交する第１方向に配置されている、請求項１ないし６のいずれかに記載の半導体装置。 7. The semiconductor device according to claim 1, wherein the second base material is arranged in a first direction perpendicular to the thickness direction with respect to the first base material.
  8. 　前記第２裏面上に配置された導電性を有する第２裏面導電部をさらに備え、
    　前記第２裏面導電部は、前記封止樹脂から露出している、請求項７に記載の半導体装置。     further comprising a second back conductive portion having conductivity disposed on the second back surface,
    8. The semiconductor device according to claim 7, wherein the second back conductive portion is exposed from the sealing resin.
  9. 　前記第２裏面上に配置された裏面電子部品をさらに備え、
    　前記裏面電子部品は、前記封止樹脂に覆われている、請求項７に記載の半導体装置。     further comprising a backside electronic component disposed on the second backside,
    8. The semiconductor device according to claim 7, wherein the backside electronic component is covered with the sealing resin.
  10. 　前記第２基材は、前記第１基材に対して、前記厚さ方向に配置されている、請求項１ないし６のいずれかに記載の半導体装置。 7. The semiconductor device according to claim 1, wherein the second base material is arranged in the thickness direction with respect to the first base material.
  11. 　前記第１裏面上に配置された導電性を有する第１裏面導電部をさらに備え、
    　前記第１裏面導電部は、前記封止樹脂から露出している、請求項１ないし１０のいずれかに記載の半導体装置。     further comprising a first back conductive portion having conductivity disposed on the first back surface,
    11. The semiconductor device according to claim 1, wherein the first back conductive portion is exposed from the sealing resin.
  12. 　前記駆動装置は、絶縁ゲートドライバである、請求項１ないし１１のいずれかに記載の半導体装置。 12. The semiconductor device according to claim 1, wherein the driving device is an insulated gate driver.
  13. 　前記第１主面上に配置された第１温度検出部をさらに備えている、請求項１ないし１２のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 12, further comprising a first temperature detection section disposed on the first main surface.
  14. 　前記第２主面上に配置された第２温度検出部をさらに備えている、請求項１ないし１３のいずれかに記載の半導体装置。 The semiconductor device according to any one of claims 1 to 13, further comprising a second temperature detection section disposed on the second main surface.
PCT/JP2023/018745 2022-06-13 2023-05-19 Semiconductor device WO2023243306A1 (en)

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JPH098223A (en) * 1995-06-16 1997-01-10 Mitsubishi Electric Corp Semiconductor power module and its manufacture
JP2011054625A (en) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd Circuit device
JP2013058726A (en) * 2011-08-12 2013-03-28 Sanyo Electric Co Ltd Mounting substrate and circuit device using the same
JP2013074254A (en) * 2011-09-29 2013-04-22 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
WO2014064822A1 (en) * 2012-10-26 2014-05-01 株式会社日立産機システム Power semiconductor module, and power conversion device provided with same
WO2015174198A1 (en) * 2014-05-13 2015-11-19 三菱電機株式会社 Semiconductor device and manufacturing method therefor
JP2022053848A (en) * 2020-09-25 2022-04-06 富士電機株式会社 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH098223A (en) * 1995-06-16 1997-01-10 Mitsubishi Electric Corp Semiconductor power module and its manufacture
JP2011054625A (en) * 2009-08-31 2011-03-17 Sanyo Electric Co Ltd Circuit device
JP2013058726A (en) * 2011-08-12 2013-03-28 Sanyo Electric Co Ltd Mounting substrate and circuit device using the same
JP2013074254A (en) * 2011-09-29 2013-04-22 Mitsubishi Electric Corp Semiconductor device and manufacturing method of the same
WO2014064822A1 (en) * 2012-10-26 2014-05-01 株式会社日立産機システム Power semiconductor module, and power conversion device provided with same
WO2015174198A1 (en) * 2014-05-13 2015-11-19 三菱電機株式会社 Semiconductor device and manufacturing method therefor
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