WO2023240796A1 - Panneau d'affichage et dispositif d'affichage - Google Patents

Panneau d'affichage et dispositif d'affichage Download PDF

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Publication number
WO2023240796A1
WO2023240796A1 PCT/CN2022/114847 CN2022114847W WO2023240796A1 WO 2023240796 A1 WO2023240796 A1 WO 2023240796A1 CN 2022114847 W CN2022114847 W CN 2022114847W WO 2023240796 A1 WO2023240796 A1 WO 2023240796A1
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WIPO (PCT)
Prior art keywords
signal
wiring
display panel
groups
trace
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Application number
PCT/CN2022/114847
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English (en)
Chinese (zh)
Inventor
张兵
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昆山国显光电有限公司
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Publication of WO2023240796A1 publication Critical patent/WO2023240796A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Definitions

  • the present application belongs to the technical field of electronic products, and particularly relates to a display panel and a display device.
  • Embodiments of the present application provide a display panel and a display device that reduce capacitance interference between adjacent signal wiring groups and reduce capacitance differences between signal wiring groups, thereby ensuring the display effect of the display panel.
  • embodiments of the present application provide a plurality of signal traces. At least in part of the plurality of signal traces, two of the signal traces extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance is greater than the maximum distance between two signal traces in the same signal trace group; and/or, at least one of the signal trace groups includes a bent section.
  • the distance between two signal traces in the same signal trace group is equal everywhere.
  • At least one of the signal trace groups includes connected bent segments and straight segments, and the sum of the lengths of the bent segments and straight segments of each of the signal traces is equal.
  • At least one of the bent sections of the signal wiring group is arranged in a serpentine wiring arrangement.
  • the minimum distance between the straight sections of two adjacent groups of signal wiring groups is greater than the minimum distance between the bent sections of two adjacent groups of signal wiring groups.
  • the minimum distance between the linear segments of two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment; preferably, the minimum distance between the two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment.
  • the minimum distance between the linear segments of the signal trace group is equal to three times the trace width of a single linear segment; preferably, the trace width of a single linear segment is 2 ⁇ m to 3 ⁇ m; preferably, The minimum distance between the straight segments of the two adjacent groups of signal wiring groups is 6 ⁇ m to 9 ⁇ m.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area and an edge wiring area.
  • the edge wiring area is located in the middle wiring area perpendicular to the wiring area. Both sides in the extension direction; in the middle wiring area, the wiring length of the bent section of each signal wiring group is greater than the wiring length of the straight section; in the edge wiring area, The wiring length of the bending section of each signal wiring group is smaller than the wiring length of the straight section.
  • the present application also includes a substrate, a first metal layer and a second metal layer stacked along the thickness direction of the display panel.
  • the second metal layer includes a plurality of conductive blocks, the signal traces and
  • the first metal layer is arranged on the same layer; along the thickness direction of the display panel, the orthographic projection of the conductive block on the substrate and the orthographic projection of the signal trace on the substrate at least partially overlap, In the overlapping area of the single conductive block and the orthographic projection of the signal trace on the substrate, the trace lengths of each of the signal trace groups are equal.
  • an external circuit and a pixel driving circuit are further included.
  • the external circuit is electrically connected to the pixel driving circuit; and each of the signal lines is electrically connected to a different external circuit.
  • Another aspect of the embodiment of the present application provides a display device, including: the display panel in any of the above embodiments.
  • the display panel provided by the embodiment of the present application includes multiple signal traces. At least part of the multiple signal traces, two signal traces extend side by side to form a signal trace group. Since each signal trace The materials used are the same, that is, the impedance is the same. According to the calculation rules of capacitance, the greater the distance, the smaller the capacitance. The minimum distance between adjacent signal trace groups is set to be greater than the two signal traces in the same signal trace group.
  • the capacitance between adjacent signal trace groups can be smaller than the capacitance between two signal traces in the same signal trace group, thereby reducing capacitive interference between adjacent signal trace groups and reducing
  • the capacitance difference between small signal traces ensures the display effect of the display panel.
  • at least one set of signal trace groups includes a bending section, the overlapping area between the two signal traces of the signal trace group can be increased, and the capacitance generated by the bending section is relatively increased, which can be achieved by adjusting the bending section.
  • the wiring length of the bent section adjusts the capacitance difference between each signal wiring group, and the use of bent sections can also shorten the extension length of the signal wiring group and save wiring space.
  • Figure 1 is a circuit diagram of an external circuit
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Figure 3 is a partial enlarged view of an embodiment at B in Figure 2;
  • Figure 4 is a schematic structural diagram of a bending section provided by an embodiment of the present application.
  • Figure 5 is a partial enlarged view of an embodiment at C in Figure 2;
  • Figure 6 is a partial enlarged view of another embodiment at C in Figure 2;
  • Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6.
  • 1-control chip 2-signal wiring; 21-bent section; 22-straight line section; 3-conductive block; M1-first metal layer; M2-second metal layer; A1-middle wiring area; A2- Edge routing area; Y-first direction; X-second direction.
  • transistors made of low-temperature polysilicon or oxides will have threshold voltage Vth drift during use. For example, factors such as illumination in the oxide semiconductor, source-drain electrode voltage stress, etc. may cause the threshold voltage Vth to drift. Voltage drift causes the current through the light-emitting element to be inconsistent with the required current, and the display uniformity of the display panel cannot be satisfied.
  • an external circuit can be used to compensate the threshold voltage of the driving transistor of the pixel driving circuit, as shown in Figure 1.
  • Figure 1 is a circuit diagram of an external circuit. Each external circuit is connected to a different signal line Date/Sense respectively. During compensation, the capacitor Cdata needs to be charged through the signal line Date/Sense first so that the capacitor Cdata reaches the VDD+Vth voltage. Since VDD is a constant, it can be measured Vth, and finally perform voltage compensation on the driving transistor of the pixel driving circuit based on the measured Vth.
  • the embodiments of the present application provide a display panel and a display device. Each embodiment of the display panel and the display device will be described below with reference to FIGS. 2 to 7 .
  • Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application
  • Figure 3 is a partial enlarged view of an embodiment at B in Figure 2
  • Figure 4 is an implementation of the present application.
  • the example provides a schematic structural diagram of the bending section
  • Figure 5 is a partial enlarged view of an embodiment at C in Figure 2.
  • a display panel provided by an embodiment of the present application includes a plurality of signal traces 2. At least part of the plurality of signal traces 2, two signal traces 2 extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance b between two signal traces 2 is greater than the maximum distance a between two signal traces 2 in the same signal trace group; and/or, at least one signal trace group includes a bending section 21 .
  • the display panel provided by the embodiment of the present application includes signal traces 2.
  • Two signal traces 2 extend side by side to form a signal trace group. Since the materials used in each signal trace 2 are the same, that is, the impedances are the same, according to the calculation rules of capacitance , the larger the distance, the smaller the capacitance.
  • the minimum distance b between adjacent signal trace groups is set to be greater than the maximum distance a between two signal traces 2 in the same signal trace group, the adjacent signal traces 2 can be The capacitance between signal trace groups is smaller than the capacitance between two signal traces 2 in the same signal trace group, which reduces the capacitive interference between adjacent signal trace groups and reduces the capacitance difference between signal traces 2. This ensures the display effect of the display panel.
  • the bending section 21 can increase the overlapping area between the two signal traces 2 of the signal trace group, and the capacitance generated by the bending section 21 is relatively small. Increase, the capacitance difference between the signal wiring groups can be adjusted by adjusting the wiring length of the bending section 21, and the use of the bending section 21 can also shorten the extension length of the signal wiring group and save wiring space.
  • two signal traces 2 extend side by side to form a signal trace group, that is, part of the signal traces 2 may not form a signal trace group, and part may form a signal trace group.
  • the signal wiring group can be set with a bending section or without a bending section.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area A1 and an edge wiring area A2.
  • the edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction.
  • the signal traces 2 located in the edge trace area A2 can all form a signal trace group, or can partially form a signal trace group, and the minimum distance b between adjacent signal trace groups should be greater than the same signal trace group.
  • the maximum distance a between two signal traces 2 in the trace group to reduce the capacitance interference between adjacent signal trace groups can be determined based on the capacitance difference of the signal trace 2 located in the edge trace area A2 choose.
  • the ones located in the middle wiring area A1 can be extended side by side to form a signal wiring group, and at least one set of signal wiring groups includes a bending section 21.
  • the bending section 21 can increase the capacitance between the signal wirings and can be adjusted by bending.
  • the wiring length of segment 21 adjusts the capacitance difference between each signal wiring group, and can also shorten the extension length of the signal wiring group in the middle wiring area A1, saving wiring space.
  • the minimum distance b between adjacent signal trace groups is greater than the maximum distance a between two signal traces 2 in the same signal trace group, and at least one signal trace group includes a bending section.
  • the setting method of 21 can be applied to signal trace 2 at the same time, or can be applied to signal trace 2 alone, such as signal trace 2 located in different locations, as long as the capacitance difference between signal traces 2 can be reduced to ensure The display effect of the display panel is sufficient, and there are no special restrictions.
  • the display panel also includes a control chip 1.
  • Each signal trace 2 is electrically connected to the control chip 1.
  • the control chip 1 can provide signals for external circuits through the signal traces 2, and the signal traces 2 can correspond to the external circuit.
  • the control chip 1 is a fan-out line.
  • the control chip 1 can also provide signal control for the internal compensation circuit or pixel drive circuit of the display panel. That is, the signal line 2 can also be the fan-out line or other lines for the internal compensation circuit or pixel drive circuit.
  • the embodiment of the present application is aimed at improving the wiring method of the signal trace 2, and there is no special limitation on the application scenarios of the signal trace 2.
  • the distance between two signal traces 2 in the same signal trace group is equal everywhere. Since the materials used in each signal trace 2 are the same, that is, the impedance is the same, by making the distance equal everywhere, This can realize that the capacitance between the two signal traces 2 in the same signal trace group is equal everywhere, and improve the capacitance consistency of the two signal traces 2 in the same signal trace group.
  • the signal wiring group includes connected bent sections 21 and straight sections 22.
  • the curved sections 21 and straight sections 22 of each signal wiring group are The sum of the line lengths are all equal.
  • the sum of the wiring lengths of the bending section 21 and the straight section 22 of each signal wiring group is equal to ensure that each signal wiring 2 of each signal wiring group has the same impedance, without Because the proportions of the wiring lengths of the curved sections 21 and the straight sections 22 of each signal wiring group are different, the impedances are different, which makes it easy to adjust the capacitance of each signal wiring group under the condition that the impedance is the same.
  • Capacitance C k ⁇ S/d; where k is the dielectric constant of the medium between the traces, S is the facing area of the two traces, and d is the distance between the two traces.
  • the facing area S between the two signal traces 2 can be effectively increased, thereby increasing the capacitance C.
  • the bending sections 21 of each signal wiring group can be arranged in a serpentine shape, and the different bending sections 21 formed by the bending in the serpentine shape are arranged relative to each other, that is, two more bending sections are added.
  • the facing area S between the signal traces 2 can generate additional capacitance and increase the capacitance generated by the bending section 21 .
  • the bent section 21 extends along the first direction Y, as shown in FIG. 3 , which can better utilize the wiring space.
  • the bending section 21 extends along the second direction X, and the second direction X intersects the first direction Y.
  • the second direction X can be perpendicular to the first direction Y, and is not particularly limited.
  • the serpentine trace can be formed by straight lines, and the bending angle of each straight line at the bend is a right angle, as shown in Figure 2.
  • the serpentine trace can also be a curve segment, that is, the bend section 21 can be a curve that is bent multiple times. Formation is not particularly limited.
  • the bending section 21 of each signal wiring group can also be a polyline segment formed by bending multiple straight lines, similar to a "Z" type wiring or other irregular polyline segments, according to The required wiring length of the bending segment 21 can be determined by selecting the number of bends and the bending angle of the bending line segment.
  • the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than the minimum distance between the bent segments 21 of two adjacent signal trace groups, that is, by increasing The distance d between the two traces is used to reduce the capacitance of the signal trace group in the straight section 22 and facilitate adjustment of the capacitance difference between the signal trace groups.
  • the angle between the extending direction of the straight segments 22 and the first direction Y is an acute angle, that is, each straight segment 22 is distributed in an inclined line, so that each straight segment 22 is directed toward the location of the control chip 1 The position is closed and electrically connected to the control chip 1.
  • the display panel includes a fan-out area.
  • the fan-out area includes a middle wiring area A1 and an edge wiring area A2.
  • the edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction. On both sides of The trace length of segment 21 is smaller than the trace length of straight segment 22 .
  • the signal wiring group in the edge wiring area A2 needs to extend from both sides to the middle in order to facilitate connection with the control chip 1, while the signal wiring group in the middle wiring area A1
  • the inclination angle of the wiring group is relatively small or extends directly vertically along the first direction Y in order to make the wiring length of the signal wiring group in the middle wiring area A1 equal to the length of the signal wiring group in the edge wiring area A2.
  • the wiring length of the bending section 21 of each signal wiring group is greater than or equal to the wiring length of the straight section 22; to reduce the risk caused by the middle wiring area A1 , the impedance difference caused by the wiring length of the edge wiring area A2, thereby reducing the capacitance difference between the middle wiring area A1 and the edge wiring area A2.
  • the signal wiring group in the edge wiring area A2 includes a bending section 21. The wiring length of the bending section 21 of each signal wiring group is shorter than the wiring length of the straight section 22, so as to reduce the wiring length in the middle wiring area A1. , the capacitance difference of A2 in the edge wiring area.
  • the wiring length of the bent section 21 of each signal wiring group is greater than the wiring length of the straight section 22; in the edge wiring area A2, the curved section of each signal wiring group is longer than the wiring length of the straight section 22.
  • the trace length of 21 is smaller than the trace length of straight segment 22, that is, in the middle trace area A1, the capacitance of the bent segment 21 plays a major role, and in the edge trace area A2, the capacitance of the straight segment 22 plays a major role.
  • the middle wiring area A1 uses a single wiring to form a serpentine wiring to reduce the length of the wiring in its extension direction, this structure will not generate additional capacitance in the bending section 21, resulting in the intermediate wiring
  • the capacitance of the traces in the line area A1 is smaller than the capacitance of the traces in the edge trace area A2, resulting in a capacitance difference.
  • the embodiment of the present application forms a signal wiring group by extending two signal wirings 2 side by side.
  • the signal wiring group includes a bending section 21 to generate additional capacitance. , that is, increasing the capacitance of the middle wiring area A1.
  • the stacking area is increased, thereby increasing the capacitance of the bending section 21 and saving wiring space.
  • the capacitance of the signal wiring group in the straight line segment 22 can also be reduced by increasing the minimum distance between the straight segments 22 of two adjacent signal wiring groups, that is, increasing the distance d between the two wiring groups.
  • the method of increasing the capacitance of the bent section 21 and the method of reducing the capacitance of the straight section 22 are combined to reduce the capacitance difference between the signal wiring groups in the middle wiring area A1 and the edge wiring area A2.
  • the display panel also includes an external circuit and a pixel driving circuit, and the external circuit and the pixel driving circuit are electrically connected; each signal line 2 is electrically connected to a different external circuit respectively.
  • the capacitance range between each signal trace 2 is 25pf ⁇ 35pf, and when the charging time is 1ms, the voltage range of Cdata is 1.709V ⁇ 1.870 V, the measured difference range of Vth is -100mV ⁇ 100mV. When the charging time is 18ms, the voltage range of Cdata is 2.764V ⁇ 2.846V, and the measured difference range of Vth is -50mV ⁇ 50mV.
  • the capacitance range between the signal traces 2 is 28.5pf ⁇ 31.5pf.
  • the voltage range of Cdata is 1.762V ⁇ 1.810V, and the measured difference in Vth The range is -25mV ⁇ 25mV.
  • the voltage range of Cdata is 2.788V ⁇ 2.813V, and the measured Vth difference range is -15mV ⁇ 15mV.
  • the use of the signal traces 2 in the embodiment of the present application can effectively reduce the capacitance range between the signal traces 2, and whether it is when the charging time is 1ms or when the charging time is 18ms, the capacitance range is relatively good.
  • the voltage range of Cdata and the measured difference range of Vth in the embodiment of the present application are significantly reduced, which improves the accuracy of the voltage compensation value of the driving transistor of each pixel driving circuit by each external circuit. , thereby improving the display effect of the display panel.
  • the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than or equal to twice the trace width of a single straight segment 22 to ensure that the straight segments 22 of two adjacent signal trace groups are The capacitance value between them is significantly reduced, which meets the need to balance the capacitance difference between the signal wiring group located in the middle wiring area A1 and the edge wiring area A2; in this embodiment, specifically, when the same signal wiring When the minimum distance between two signal traces 2 in the group is equal to the width of a single signal trace 2, the minimum distance between the straight line segments 22 of two adjacent signal trace groups can be equal to the width of a single straight line segment 22. Three times the line width, that is, a space for one signal line 2 is reserved between the straight segments 22 of two adjacent signal line groups to facilitate installation.
  • the trace width of a single straight line segment 22 is 2 ⁇ m to 3 ⁇ m, and the minimum distance between the straight segments 22 of two adjacent signal line groups is 6 ⁇ m to 9 ⁇ m.
  • the size of the capacitance is adjusted by adjusting the minimum distance between the straight segments 22 of two adjacent groups of signal traces.
  • the trace width of a single straight line segment 22 and the minimum distance between the straight line segments 22 of two adjacent signal trace groups are not limited to the above numerical range, and can be selected according to the need to reduce the capacitance difference of the signal traces 2 .
  • capacitance may also occur between the signal traces 2 and other conductive layers of the adjacent display panel.
  • Figure 6 is a partial enlarged view of another embodiment at C in Figure 2;
  • Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6.
  • the display panel also includes a substrate, a first metal layer M1 and a second metal layer M2 that are stacked along the thickness direction of the display panel.
  • the second metal layer M2 includes a plurality of conductive blocks 3.
  • the signal traces 2 are the same as the first metal layer M1.
  • each signal trace 2 and the first metal layer M1 are arranged on the same layer; that is, the vertical distance between each signal trace 2 and the second metal layer M2 is equal, and the distance between each signal trace 2 is The trace width and unit impedance are equal. Therefore, the parameter that affects the capacitance between each signal trace 2 and the conductive block 3 of the second metal layer M2 is only the length of the overlapping portion of the signal trace 2 and the single conductive block 3. In this embodiment, by limiting the overlapping area of the orthographic projection of the single conductive block 3 and the signal trace 2 on the substrate along the thickness direction of the display panel, the trace lengths of each signal trace group are equal to ensure that the trace lengths of each signal trace group are equal.
  • each conductive block 3 may be a polygon such as a triangle or a trapezoid, or a shape including a curved edge such as an ellipse or a circle.
  • the second metal layer M2 may specifically be a wiring layer for VDD positive voltage wiring and VSS negative voltage wiring.
  • An embodiment of the present application also provides a display device, including: the display panel in any of the above embodiments.
  • the display device provided by the embodiment of the present application can be applied to mobile phones or any electronic product with a display function, including but not limited to the following categories: televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart phones Rings, smart glasses, vehicle-mounted displays, medical equipment, industrial control equipment, touch interactive terminals, etc.
  • the embodiments of this application do not specifically limit this.

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Abstract

La présente demande divulgue un panneau d'affichage et un dispositif d'affichage. Le panneau d'affichage comprend : une pluralité de fils de signal. Dans au moins certains de la pluralité de fils de signal, deux fils de signal s'étendent côte à côte pour former un groupe de fils de signal ; la distance minimale entre des groupes de fils de signal adjacents est supérieure à la distance maximale entre deux fils de signal dans un même groupe de fils de signal, et/ou au moins un groupe de fils de signal comprend un segment courbé. L'interférence de capacité entre les groupes de fils de signal adjacents est réduite, et la différence de capacité entre des fils de signal est réduite, de telle sorte que l'effet d'affichage du panneau d'affichage est en outre assuré ; et la longueur d'extension d'un groupe de fils de signal peut être raccourcie au moyen du segment courbé, ce qui permet d'économiser de l'espace de câblage.
PCT/CN2022/114847 2022-06-15 2022-08-25 Panneau d'affichage et dispositif d'affichage WO2023240796A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210674469.8A CN114937673A (zh) 2022-06-15 2022-06-15 显示面板及显示装置
CN202210674469.8 2022-06-15

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WO2023240796A1 true WO2023240796A1 (fr) 2023-12-21

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CN114937673A (zh) * 2022-06-15 2022-08-23 昆山国显光电有限公司 显示面板及显示装置

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CN114446997A (zh) * 2022-01-17 2022-05-06 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
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Publication number Priority date Publication date Assignee Title
JP2009122318A (ja) * 2007-11-14 2009-06-04 Hitachi Displays Ltd 表示装置
CN101893962A (zh) * 2010-07-08 2010-11-24 友达光电股份有限公司 触控显示器及其触控显示基板
CN104969283A (zh) * 2013-02-26 2015-10-07 夏普株式会社 显示装置
CN109643525A (zh) * 2017-05-23 2019-04-16 京东方科技集团股份有限公司 具有多条第一接线和多条第二接线的显示面板和显示装置
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CN111696461A (zh) * 2020-06-30 2020-09-22 武汉天马微电子有限公司 一种显示面板和显示装置
CN114446997A (zh) * 2022-01-17 2022-05-06 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN114937673A (zh) * 2022-06-15 2022-08-23 昆山国显光电有限公司 显示面板及显示装置

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