WO2023240796A1

WO2023240796A1 - Display panel and display device

Info

Publication number: WO2023240796A1
Application number: PCT/CN2022/114847
Authority: WO
Inventors: 张兵
Original assignee: 昆山国显光电有限公司
Priority date: 2022-06-15
Filing date: 2022-08-25
Publication date: 2023-12-21
Also published as: CN114937673A

Abstract

The present application discloses a display panel and a display device. The display panel comprises: a plurality of signal wires. In at least some of the plurality of signal wires, two signal wires extend side by side to form a signal wire group; the minimum distance between adjacent signal wire groups is greater than the maximum distance between two signal wires in a same signal wire group, and/or at least one signal wire group comprises a bent segment. The capacitance interference between the adjacent signal wire groups is reduced, and the capacitance difference between signal wires is reduced, so that the display effect of the display panel is further ensured; and the extension length of a signal wire group can be shortened by means of the bent segment, thereby saving wiring space.

Description

Display panels and display devices

This application claims priority to the Chinese patent application filed with the China Patent Office on June 15, 2022, with application number 202210674469.8 and the application name "Display Panel and Display Device", the entire content of which is incorporated into this application by reference.

Technical field

The present application belongs to the technical field of electronic products, and particularly relates to a display panel and a display device.

Background technique

At present, small and medium-sized panels in the LTPS (Low Temperature Poly-Silicon) field generally use 7T1C pixel circuits for internal compensation of threshold voltages. A large number of thin film transistors are used, which is not conducive to the development of higher PPI. In addition, for under-screen applications, a camera with higher light transmittance is required. The traditional 7T1C circuit has poor light transmittance and cannot achieve homogeneous display of the main and secondary screens. The use of external compensation can reduce the number of thin film transistors in the panel. quantity, enabling high PPI and off-screen applications.

However, due to the wiring limitations of the existing external compensation circuit, the detected threshold voltage is inaccurate, resulting in display problems.

Therefore, a new display panel and display device are urgently needed.

Contents of the invention

Embodiments of the present application provide a display panel and a display device that reduce capacitance interference between adjacent signal wiring groups and reduce capacitance differences between signal wiring groups, thereby ensuring the display effect of the display panel.

On the one hand, embodiments of the present application provide a plurality of signal traces. At least in part of the plurality of signal traces, two of the signal traces extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance is greater than the maximum distance between two signal traces in the same signal trace group; and/or, at least one of the signal trace groups includes a bent section.

According to one aspect of the present application, the distance between two signal traces in the same signal trace group is equal everywhere.

According to one aspect of the present application, at least one of the signal trace groups includes connected bent segments and straight segments, and the sum of the lengths of the bent segments and straight segments of each of the signal traces is equal.

According to one aspect of the present application, at least one of the bent sections of the signal wiring group is arranged in a serpentine wiring arrangement.

According to one aspect of the present application, the minimum distance between the straight sections of two adjacent groups of signal wiring groups is greater than the minimum distance between the bent sections of two adjacent groups of signal wiring groups.

According to one aspect of the present application, the minimum distance between the linear segments of two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment; preferably, the minimum distance between the two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment. The minimum distance between the linear segments of the signal trace group is equal to three times the trace width of a single linear segment; preferably, the trace width of a single linear segment is 2 μm to 3 μm; preferably, The minimum distance between the straight segments of the two adjacent groups of signal wiring groups is 6 μm to 9 μm.

According to one aspect of the present application, the display panel includes a fan-out area. The fan-out area includes a middle wiring area and an edge wiring area. The edge wiring area is located in the middle wiring area perpendicular to the wiring area. Both sides in the extension direction; in the middle wiring area, the wiring length of the bent section of each signal wiring group is greater than the wiring length of the straight section; in the edge wiring area, The wiring length of the bending section of each signal wiring group is smaller than the wiring length of the straight section.

According to one aspect of the present application, it also includes a substrate, a first metal layer and a second metal layer stacked along the thickness direction of the display panel. The second metal layer includes a plurality of conductive blocks, the signal traces and The first metal layer is arranged on the same layer; along the thickness direction of the display panel, the orthographic projection of the conductive block on the substrate and the orthographic projection of the signal trace on the substrate at least partially overlap, In the overlapping area of the single conductive block and the orthographic projection of the signal trace on the substrate, the trace lengths of each of the signal trace groups are equal.

According to one aspect of the present application, an external circuit and a pixel driving circuit are further included. The external circuit is electrically connected to the pixel driving circuit; and each of the signal lines is electrically connected to a different external circuit.

Another aspect of the embodiment of the present application provides a display device, including: the display panel in any of the above embodiments.

Compared with the existing technology, the display panel provided by the embodiment of the present application includes multiple signal traces. At least part of the multiple signal traces, two signal traces extend side by side to form a signal trace group. Since each signal trace The materials used are the same, that is, the impedance is the same. According to the calculation rules of capacitance, the greater the distance, the smaller the capacitance. The minimum distance between adjacent signal trace groups is set to be greater than the two signal traces in the same signal trace group. When the maximum distance between lines is reached, the capacitance between adjacent signal trace groups can be smaller than the capacitance between two signal traces in the same signal trace group, thereby reducing capacitive interference between adjacent signal trace groups and reducing The capacitance difference between small signal traces ensures the display effect of the display panel. When at least one set of signal trace groups includes a bending section, the overlapping area between the two signal traces of the signal trace group can be increased, and the capacitance generated by the bending section is relatively increased, which can be achieved by adjusting the bending section. The wiring length of the bent section adjusts the capacitance difference between each signal wiring group, and the use of bent sections can also shorten the extension length of the signal wiring group and save wiring space.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the drawings required to be used in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. Those of ordinary skill in the art can also obtain other drawings based on these drawings without exerting creative efforts.

Figure 1 is a circuit diagram of an external circuit;

Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application;

Figure 3 is a partial enlarged view of an embodiment at B in Figure 2;

Figure 4 is a schematic structural diagram of a bending section provided by an embodiment of the present application;

Figure 5 is a partial enlarged view of an embodiment at C in Figure 2;

Figure 6 is a partial enlarged view of another embodiment at C in Figure 2;

Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6.

In the attached picture:

1-control chip; 2-signal wiring; 21-bent section; 22-straight line section; 3-conductive block; M1-first metal layer; M2-second metal layer; A1-middle wiring area; A2- Edge routing area; Y-first direction; X-second direction.

Detailed ways

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described in further detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations are mutually exclusive. any such actual relationship or sequence exists between them. Furthermore, the terms "comprises," "comprises," or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element.

It will be understood that when describing the structure of components, when one layer or region is referred to as being "on" or "over" another layer or region, it can mean being directly on the other layer or region, or There are other layers or areas between it and another layer, another area. And if the part is turned over, that layer, one area, will be "under" or "under" another layer, area.

It will be apparent to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of the application. Thus, this application is intended to cover the modifications and variations of this application provided they come within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the implementation modes provided in the embodiments of this application can be combined with each other if there is no contradiction.

In related technologies, transistors made of low-temperature polysilicon or oxides will have threshold voltage Vth drift during use. For example, factors such as illumination in the oxide semiconductor, source-drain electrode voltage stress, etc. may cause the threshold voltage Vth to drift. Voltage drift causes the current through the light-emitting element to be inconsistent with the required current, and the display uniformity of the display panel cannot be satisfied.

In order to solve the above problem, an external circuit can be used to compensate the threshold voltage of the driving transistor of the pixel driving circuit, as shown in Figure 1. Figure 1 is a circuit diagram of an external circuit. Each external circuit is connected to a different signal line Date/Sense respectively. During compensation, the capacitor Cdata needs to be charged through the signal line Date/Sense first so that the capacitor Cdata reaches the VDD+Vth voltage. Since VDD is a constant, it can be measured Vth, and finally perform voltage compensation on the driving transistor of the pixel driving circuit based on the measured Vth. The applicant's research found that due to the limitations of the wiring form when connecting the existing signal line Date/Sense and the control chip, the capacitance difference between each signal line Date/Sense in the prior art is large, which in turn leads to the large difference in capacitance between each signal line Date/Sense. When /Sense charges the capacitor Cdata, within the same charging time, there are differences in the VDD+Vth voltage values reached by the capacitor Cdata in different external circuits, resulting in inaccurate Vth values measured. There are also large differences in the voltage compensation values of the drive transistors of the pixel drive circuit, causing problems with the display.

The embodiments of the present application provide a display panel and a display device. Each embodiment of the display panel and the display device will be described below with reference to FIGS. 2 to 7 .

Please refer to Figures 2 to 5. Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present application; Figure 3 is a partial enlarged view of an embodiment at B in Figure 2; Figure 4 is an implementation of the present application. The example provides a schematic structural diagram of the bending section; Figure 5 is a partial enlarged view of an embodiment at C in Figure 2.

A display panel provided by an embodiment of the present application includes a plurality of signal traces 2. At least part of the plurality of signal traces 2, two signal traces 2 extend side by side to form a signal trace group; between adjacent signal trace groups The minimum distance b between two signal traces 2 is greater than the maximum distance a between two signal traces 2 in the same signal trace group; and/or, at least one signal trace group includes a bending section 21 .

The display panel provided by the embodiment of the present application includes signal traces 2. Two signal traces 2 extend side by side to form a signal trace group. Since the materials used in each signal trace 2 are the same, that is, the impedances are the same, according to the calculation rules of capacitance , the larger the distance, the smaller the capacitance. When the minimum distance b between adjacent signal trace groups is set to be greater than the maximum distance a between two signal traces 2 in the same signal trace group, the adjacent signal traces 2 can be The capacitance between signal trace groups is smaller than the capacitance between two signal traces 2 in the same signal trace group, which reduces the capacitive interference between adjacent signal trace groups and reduces the capacitance difference between signal traces 2. This ensures the display effect of the display panel. When at least one set of signal trace groups includes the bending section 21, the bending section 21 can increase the overlapping area between the two signal traces 2 of the signal trace group, and the capacitance generated by the bending section 21 is relatively small. Increase, the capacitance difference between the signal wiring groups can be adjusted by adjusting the wiring length of the bending section 21, and the use of the bending section 21 can also shorten the extension length of the signal wiring group and save wiring space.

It should be noted that, among at least some of the plurality of signal traces 2 , two signal traces 2 extend side by side to form a signal trace group, that is, part of the signal traces 2 may not form a signal trace group, and part may form a signal trace group. The signal wiring group can be set with a bending section or without a bending section.

In some embodiments of the present application, the display panel includes a fan-out area. The fan-out area includes a middle wiring area A1 and an edge wiring area A2. The edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction. On both sides of the top, the signal traces 2 located in the edge trace area A2 can all form a signal trace group, or can partially form a signal trace group, and the minimum distance b between adjacent signal trace groups should be greater than the same signal trace group. The maximum distance a between two signal traces 2 in the trace group to reduce the capacitance interference between adjacent signal trace groups can be determined based on the capacitance difference of the signal trace 2 located in the edge trace area A2 choose.

The ones located in the middle wiring area A1 can be extended side by side to form a signal wiring group, and at least one set of signal wiring groups includes a bending section 21. The bending section 21 can increase the capacitance between the signal wirings and can be adjusted by bending. The wiring length of segment 21 adjusts the capacitance difference between each signal wiring group, and can also shorten the extension length of the signal wiring group in the middle wiring area A1, saving wiring space.

In this embodiment, the minimum distance b between adjacent signal trace groups is greater than the maximum distance a between two signal traces 2 in the same signal trace group, and at least one signal trace group includes a bending section. The setting method of 21 can be applied to signal trace 2 at the same time, or can be applied to signal trace 2 alone, such as signal trace 2 located in different locations, as long as the capacitance difference between signal traces 2 can be reduced to ensure The display effect of the display panel is sufficient, and there are no special restrictions.

Optionally, the display panel also includes a control chip 1. Each signal trace 2 is electrically connected to the control chip 1. The control chip 1 can provide signals for external circuits through the signal traces 2, and the signal traces 2 can correspond to the external circuit. The control chip 1 is a fan-out line. The control chip 1 can also provide signal control for the internal compensation circuit or pixel drive circuit of the display panel. That is, the signal line 2 can also be the fan-out line or other lines for the internal compensation circuit or pixel drive circuit. , the embodiment of the present application is aimed at improving the wiring method of the signal trace 2, and there is no special limitation on the application scenarios of the signal trace 2.

In some optional embodiments, the distance between two signal traces 2 in the same signal trace group is equal everywhere. Since the materials used in each signal trace 2 are the same, that is, the impedance is the same, by making the distance equal everywhere, This can realize that the capacitance between the two signal traces 2 in the same signal trace group is equal everywhere, and improve the capacitance consistency of the two signal traces 2 in the same signal trace group.

Please refer to Figures 3 and 5. In some optional embodiments, the signal wiring group includes connected bent sections 21 and straight sections 22. The curved sections 21 and straight sections 22 of each signal wiring group are The sum of the line lengths are all equal.

It can be understood that the sum of the wiring lengths of the bending section 21 and the straight section 22 of each signal wiring group is equal to ensure that each signal wiring 2 of each signal wiring group has the same impedance, without Because the proportions of the wiring lengths of the curved sections 21 and the straight sections 22 of each signal wiring group are different, the impedances are different, which makes it easy to adjust the capacitance of each signal wiring group under the condition that the impedance is the same.

Specifically, the calculation rules for capacitance are as follows:

Capacitance C=k×S/d; where k is the dielectric constant of the medium between the traces, S is the facing area of the two traces, and d is the distance between the two traces.

By bending the bending sections 21 of the two signal traces 2 in the same signal trace group at least twice, the facing area S between the two signal traces 2 can be effectively increased, thereby increasing the capacitance C.

Optionally, the bending sections 21 of each signal wiring group can be arranged in a serpentine shape, and the different bending sections 21 formed by the bending in the serpentine shape are arranged relative to each other, that is, two more bending sections are added. The facing area S between the signal traces 2 can generate additional capacitance and increase the capacitance generated by the bending section 21 .

In some optional embodiments, the bent section 21 extends along the first direction Y, as shown in FIG. 3 , which can better utilize the wiring space. Optionally, the bending section 21 extends along the second direction X, and the second direction X intersects the first direction Y. As shown in FIG. 4 , the second direction X can be perpendicular to the first direction Y, and is not particularly limited.

The serpentine trace can be formed by straight lines, and the bending angle of each straight line at the bend is a right angle, as shown in Figure 2. The serpentine trace can also be a curve segment, that is, the bend section 21 can be a curve that is bent multiple times. Formation is not particularly limited.

In addition to the above-mentioned serpentine wiring form, the bending section 21 of each signal wiring group can also be a polyline segment formed by bending multiple straight lines, similar to a "Z" type wiring or other irregular polyline segments, according to The required wiring length of the bending segment 21 can be determined by selecting the number of bends and the bending angle of the bending line segment.

In some optional embodiments, the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than the minimum distance between the bent segments 21 of two adjacent signal trace groups, that is, by increasing The distance d between the two traces is used to reduce the capacitance of the signal trace group in the straight section 22 and facilitate adjustment of the capacitance difference between the signal trace groups. In this embodiment, optionally, the angle between the extending direction of the straight segments 22 and the first direction Y is an acute angle, that is, each straight segment 22 is distributed in an inclined line, so that each straight segment 22 is directed toward the location of the control chip 1 The position is closed and electrically connected to the control chip 1.

In some optional embodiments, the display panel includes a fan-out area. The fan-out area includes a middle wiring area A1 and an edge wiring area A2. The edge wiring area A2 is located in the middle wiring area A1 in a direction perpendicular to the wiring extension direction. On both sides of The trace length of segment 21 is smaller than the trace length of straight segment 22 .

It should be noted that due to the limitation of the installation position of the control chip 1, the signal wiring group in the edge wiring area A2 needs to extend from both sides to the middle in order to facilitate connection with the control chip 1, while the signal wiring group in the middle wiring area A1 The inclination angle of the wiring group is relatively small or extends directly vertically along the first direction Y in order to make the wiring length of the signal wiring group in the middle wiring area A1 equal to the length of the signal wiring group in the edge wiring area A2. Line length, in this embodiment, in the middle wiring area A1, the wiring length of the bending section 21 of each signal wiring group is greater than or equal to the wiring length of the straight section 22; to reduce the risk caused by the middle wiring area A1 , the impedance difference caused by the wiring length of the edge wiring area A2, thereby reducing the capacitance difference between the middle wiring area A1 and the edge wiring area A2. Furthermore, the signal wiring group in the edge wiring area A2 includes a bending section 21. The wiring length of the bending section 21 of each signal wiring group is shorter than the wiring length of the straight section 22, so as to reduce the wiring length in the middle wiring area A1. , the capacitance difference of A2 in the edge wiring area.

Furthermore, usually in the middle wiring area A1, the wiring length of the bent section 21 of each signal wiring group is greater than the wiring length of the straight section 22; in the edge wiring area A2, the curved section of each signal wiring group is longer than the wiring length of the straight section 22. The trace length of 21 is smaller than the trace length of straight segment 22, that is, in the middle trace area A1, the capacitance of the bent segment 21 plays a major role, and in the edge trace area A2, the capacitance of the straight segment 22 plays a major role. In the prior art, since the middle wiring area A1 uses a single wiring to form a serpentine wiring to reduce the length of the wiring in its extension direction, this structure will not generate additional capacitance in the bending section 21, resulting in the intermediate wiring The capacitance of the traces in the line area A1 is smaller than the capacitance of the traces in the edge trace area A2, resulting in a capacitance difference.

In order to reduce the capacitance difference between the middle wiring area A1 and the edge wiring area A2, the embodiment of the present application forms a signal wiring group by extending two signal wirings 2 side by side. The signal wiring group includes a bending section 21 to generate additional capacitance. , that is, increasing the capacitance of the middle wiring area A1. Specifically, since the materials used for each signal trace 2 are the same, that is, the unit impedance of each signal trace 2 is the same, and the sum of the trace lengths of the bent section 21 and the straight section 22 of each signal trace 2 is equal, according to The above calculation rule for capacitance is: capacitance C=k×S/d. By setting the bending section 21 in a serpentine wiring form, the intersection between the two signal traces 2 of the bending section 21 can be increased. The stacking area is increased, thereby increasing the capacitance of the bending section 21 and saving wiring space.

At the same time, the capacitance of the signal wiring group in the straight line segment 22 can also be reduced by increasing the minimum distance between the straight segments 22 of two adjacent signal wiring groups, that is, increasing the distance d between the two wiring groups. The method of increasing the capacitance of the bent section 21 and the method of reducing the capacitance of the straight section 22 are combined to reduce the capacitance difference between the signal wiring groups in the middle wiring area A1 and the edge wiring area A2.

Optionally, the display panel also includes an external circuit and a pixel driving circuit, and the external circuit and the pixel driving circuit are electrically connected; each signal line 2 is electrically connected to a different external circuit respectively.

That is to say, after the above wiring form is applied to the external circuit, due to the reduced capacitance difference between the signal traces 2, when the capacitor Cdata is charged through each signal trace 2, in the same charging time, in different external circuits The difference in the VDD+Vth voltage value reached by the capacitor Cdata is reduced, which improves the accuracy of the measured Vth value. The difference in the voltage compensation value of the drive transistor of each pixel drive circuit by each external circuit is also reduced. This further improves the display effect of the display panel.

It has been experimentally measured by the applicant that when using the existing signal trace 2 layout, the capacitance range between each signal trace 2 is 25pf ~ 35pf, and when the charging time is 1ms, the voltage range of Cdata is 1.709V ~ 1.870 V, the measured difference range of Vth is -100mV~100mV. When the charging time is 18ms, the voltage range of Cdata is 2.764V~2.846V, and the measured difference range of Vth is -50mV~50mV.

In the embodiment of the present application, the capacitance range between the signal traces 2 is 28.5pf ~ 31.5pf. When the charging time is 1ms, the voltage range of Cdata is 1.762V ~ 1.810V, and the measured difference in Vth The range is -25mV~25mV. When the charging time is 18ms, the voltage range of Cdata is 2.788V~2.813V, and the measured Vth difference range is -15mV~15mV.

By comparing the above data, it can be found that the use of the signal traces 2 in the embodiment of the present application can effectively reduce the capacitance range between the signal traces 2, and whether it is when the charging time is 1ms or when the charging time is 18ms, the capacitance range is relatively good. Compared with the prior art, the voltage range of Cdata and the measured difference range of Vth in the embodiment of the present application are significantly reduced, which improves the accuracy of the voltage compensation value of the driving transistor of each pixel driving circuit by each external circuit. , thereby improving the display effect of the display panel.

Optionally, the minimum distance between the straight segments 22 of two adjacent signal trace groups is greater than or equal to twice the trace width of a single straight segment 22 to ensure that the straight segments 22 of two adjacent signal trace groups are The capacitance value between them is significantly reduced, which meets the need to balance the capacitance difference between the signal wiring group located in the middle wiring area A1 and the edge wiring area A2; in this embodiment, specifically, when the same signal wiring When the minimum distance between two signal traces 2 in the group is equal to the width of a single signal trace 2, the minimum distance between the straight line segments 22 of two adjacent signal trace groups can be equal to the width of a single straight line segment 22. Three times the line width, that is, a space for one signal line 2 is reserved between the straight segments 22 of two adjacent signal line groups to facilitate installation.

Optionally, the trace width of a single straight line segment 22 is 2 μm to 3 μm, and the minimum distance between the straight segments 22 of two adjacent signal line groups is 6 μm to 9 μm. The size of the capacitance is adjusted by adjusting the minimum distance between the straight segments 22 of two adjacent groups of signal traces. Of course, the trace width of a single straight line segment 22 and the minimum distance between the straight line segments 22 of two adjacent signal trace groups are not limited to the above numerical range, and can be selected according to the need to reduce the capacitance difference of the signal traces 2 .

It should be noted that in addition to the capacitance that may occur between the signal traces 2 , capacitance may also occur between the signal traces 2 and other conductive layers of the adjacent display panel.

Please refer to Figures 6 and 7. Figure 6 is a partial enlarged view of another embodiment at C in Figure 2; Figure 7 is a film structure diagram of an embodiment at D-D in Figure 6. The display panel also includes a substrate, a first metal layer M1 and a second metal layer M2 that are stacked along the thickness direction of the display panel. The second metal layer M2 includes a plurality of conductive blocks 3. The signal traces 2 are the same as the first metal layer M1. Layer setting; along the thickness direction of the display panel, the orthographic projection of the conductive block 3 on the substrate and the orthographic projection of the signal trace 2 on the substrate at least partially overlap, and the orthographic projection of the single conductive block 3 and the signal trace 2 on the substrate Within the overlapping area, the trace lengths of each signal trace group are equal.

It should be noted that since each signal trace 2 and the first metal layer M1 are arranged on the same layer; that is, the vertical distance between each signal trace 2 and the second metal layer M2 is equal, and the distance between each signal trace 2 is The trace width and unit impedance are equal. Therefore, the parameter that affects the capacitance between each signal trace 2 and the conductive block 3 of the second metal layer M2 is only the length of the overlapping portion of the signal trace 2 and the single conductive block 3. In this embodiment, by limiting the overlapping area of the orthographic projection of the single conductive block 3 and the signal trace 2 on the substrate along the thickness direction of the display panel, the trace lengths of each signal trace group are equal to ensure that the trace lengths of each signal trace group are equal. The facing capacitances of the signal wiring groups and the conductive block 3 are equal, thereby reducing the capacitance difference between each signal wiring group and the conductive block 3 along the thickness direction of the display panel. Optionally, the shape of each conductive block 3 may be a polygon such as a triangle or a trapezoid, or a shape including a curved edge such as an ellipse or a circle. The second metal layer M2 may specifically be a wiring layer for VDD positive voltage wiring and VSS negative voltage wiring.

An embodiment of the present application also provides a display device, including: the display panel in any of the above embodiments.

The display device provided by the embodiment of the present application can be applied to mobile phones or any electronic product with a display function, including but not limited to the following categories: televisions, notebook computers, desktop monitors, tablet computers, digital cameras, smart phones Rings, smart glasses, vehicle-mounted displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

The above are only specific implementations of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the above-described systems, modules and units can be referred to the foregoing method embodiments. The corresponding process will not be described again here. It should be understood that the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and these modifications or substitutions should be covered. within the protection scope of this application.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps. That is to say, the steps may be performed in the order mentioned in the embodiment, or may be different from the order in the embodiment, or several steps may be performed simultaneously.

Claims

A display panel, including: a plurality of signal wiring lines, at least in part of the plurality of signal wiring lines, two of the signal wiring lines extend side by side to form a signal wiring group;

The minimum distance between adjacent signal wiring groups is greater than the maximum distance between two signal wiring groups in the same signal wiring group; and/or,

At least one of the signal trace groups includes a bent section.
The display panel according to claim 1, wherein the distance between two signal traces in the same signal trace group is equal everywhere.
The display panel according to claim 1, wherein at least one group of the signal wiring groups includes the connected bent sections and straight sections, and the curved sections and straight sections of each of the signal wiring groups are The sum of the line lengths are all equal.
The display panel according to claim 3, wherein at least one of the bent sections of the signal wiring group is arranged in a serpentine wiring arrangement.
The display panel according to claim 3, wherein a minimum distance between the straight segments of two adjacent groups of signal wiring groups is greater than a minimum distance between the bending segments of two adjacent groups of signal wiring groups. the minimum distance between them.
The display panel according to claim 3, wherein the minimum distance between the linear segments of two adjacent groups of signal traces is greater than or equal to twice the trace width of a single linear segment;

Preferably, the minimum distance between the linear segments of two adjacent groups of signal traces is equal to three times the trace width of a single linear segment;

Preferably, the width of a single linear segment is 2 μm to 3 μm;

Preferably, the minimum distance between the linear segments of the two adjacent groups of signal wiring groups is 6 μm to 9 μm.
The display panel of claim 4, wherein the display panel includes a fan-out area, the fan-out area includes a middle wiring area and an edge wiring area, the edge wiring area is located in the middle wiring area On both sides perpendicular to the direction of trace extension;

In the middle wiring area, the wiring length of the bent section of each signal wiring group is greater than or equal to the wiring length of the straight section;

In the edge wiring area, the wiring length of the bending section of each signal wiring group is smaller than the wiring length of the straight section.
The display panel according to claim 1, further comprising a substrate, a first metal layer and a second metal layer stacked along a thickness direction of the display panel, the second metal layer including a plurality of conductive blocks, The signal wiring and the first metal layer are arranged on the same layer;

Along the thickness direction of the display panel, the orthographic projection of the conductive block on the substrate and the orthographic projection of the signal trace on the substrate at least partially overlap. When a single conductive block and the signal The traces are in the overlapping area of the orthographic projection on the substrate, and the trace lengths of each of the signal trace groups are equal.
The display panel according to claim 1, further comprising an external circuit and a pixel driving circuit, the external circuit and the pixel driving circuit being electrically connected;

Each of the signal traces is electrically connected to a different external circuit.
A display device, comprising: the display panel according to any one of claims 1 to 9.