WO2023240416A1 - 存储阵列及其制备方法、存储器、电子设备 - Google Patents

存储阵列及其制备方法、存储器、电子设备 Download PDF

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WO2023240416A1
WO2023240416A1 PCT/CN2022/098471 CN2022098471W WO2023240416A1 WO 2023240416 A1 WO2023240416 A1 WO 2023240416A1 CN 2022098471 W CN2022098471 W CN 2022098471W WO 2023240416 A1 WO2023240416 A1 WO 2023240416A1
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electrode
ferroelectric
layer
memory
resistance layer
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PCT/CN2022/098471
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English (en)
French (fr)
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谭万良
许俊豪
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华为技术有限公司
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Priority to PCT/CN2022/098471 priority Critical patent/WO2023240416A1/zh
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  • the present application relates to the field of semiconductor storage technology, and in particular, to a storage array and its preparation method, memory, and electronic equipment.
  • FRAM Ferroelectric random access memory
  • DRAM dynamic random access memory
  • flash memory flash memory
  • crossbar array structure In order to increase the storage capacity of FRAM, existing FRAM can adopt a cross bar array structure.
  • the crossbar array structure is shown in Figure 1. It has multiple word lines (WL) and multiple bit lines (BL), which are connected through the word lines WL and bit lines BL to form an array.
  • a memory cell is provided at the intersection of a word line WL and a bit line BL. The memory cell can be read or written through voltage regulation between WL and BL.
  • each word line WL and each bit line BL in the crossbar array structure are connected to multiple memory cells, the process of reading and writing a specific memory cell will cause interference to other memory cells, causing other The information in the storage unit is difficult to read or even lost.
  • Embodiments of the present application provide a memory array and its preparation method, memory, and electronic equipment, which are used to improve the anti-interference ability of the memory unit during the memory reading and writing process.
  • a first aspect of the embodiment of the present application provides a memory array, which can be applied to a memory.
  • the memory can be, for example, a ferroelectric random access memory (FRAM).
  • the memory array includes a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor.
  • the ferroelectric capacitor includes a first electrode and a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode.
  • the ferroelectric layer serves as a storage medium.
  • the material of the ferroelectric layer may include a hafnium oxide-based material.
  • the ferroelectric capacitor further includes at least one nonlinear resistance layer disposed between the first electrode and the second electrode and parallel to the ferroelectric layer.
  • the ferroelectric capacitor includes a nonlinear resistor layer that divides voltage in series with the ferroelectric layer.
  • a nonlinear resistor layer that divides voltage in series with the ferroelectric layer.
  • the material resistance of the nonlinear resistor layer decreases nonlinearly.
  • the resistance of the nonlinear resistor layer decreases nonlinearly, and the corresponding divided voltage obtained by the ferroelectric layer increases nonlinearly. That is, as the voltage applied to the ferroelectric capacitor increases, the divided voltage obtained by the ferroelectric layer first increases slowly and then increases rapidly.
  • the memory array provided by the embodiment of the present application inserts a non-linear resistance layer parallel to the ferroelectric layer in the ferroelectric capacitor, so that the non-linear resistance layer and the ferroelectric layer divide the voltage applied to the ferroelectric capacitor.
  • the material of the nonlinear resistor layer has the characteristic that the resistance of the nonlinear resistor layer decreases nonlinearly as the applied voltage increases, so that the resistance of the nonlinear resistor layer decreases nonlinearly as the applied voltage increases. Then, after the above nonlinear resistor layer is placed in a ferroelectric capacitor, as the voltage applied to the ferroelectric capacitor increases, the resistance of the nonlinear resistor layer decreases nonlinearly, and the voltage division obtained by the nonlinear resistor layer is nonlinear. decrease.
  • the ferroelectric polarization flip of the ferroelectric capacitor also has the characteristic of changing non-linearly with voltage changes.
  • the proportion of the divided voltage obtained by the ferroelectric layer is small, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is small, which has almost no effect on the storage state of the memory cell. No effect.
  • the voltage applied to the ferroelectric capacitor is large (read and write voltage)
  • the proportion of the divided voltage obtained by the ferroelectric layer is large, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is large, and the read and write operations can be completed normally.
  • the existence of the nonlinear resistance layer can regulate the voltage response characteristics of the memory cell, enhance the nonlinear response characteristics of the memory cell as the voltage increases, and suppress the ferroelectric polarization flip of the ferroelectric capacitor at small voltages. This effectively enhances the anti-interference performance of the memory unit.
  • the material of the nonlinear resistance layer is a conductive material with resistive switching characteristics. That is to say, the material of the nonlinear resistor layer is a conductive material, and the resistance of the nonlinear resistor layer material can change as the voltage changes. This is a low-cost implementation.
  • the material of the nonlinear resistor layer has metal-insulator transition properties.
  • the material of the nonlinear resistor layer can change from a metallic material to an insulating material as the voltage changes. This is a low-cost implementation.
  • the material of the nonlinear resistor layer includes transition metal oxides, lanthanide oxides, perovskite composite oxides, solid electrolytes or organic polymers. This is one possible way to do it.
  • the material of the nonlinear resistance layer includes at least one of Ta 2 O 5 , Nb 2 O 5 , TiO 2 , HfO 2 , GeSbTe or AgInSbTe. This is one possible way to do it.
  • At least one side of the ferroelectric layer is provided with a nonlinear resistance layer. This is one possible way to do it.
  • the ferroelectric capacitor further includes at least one third electrode, the third electrode is disposed between the first electrode and the second electrode; the third electrode is disposed between the ferroelectric layer and the nonlinear resistance layer. .
  • the first electrode and the second electrode are arranged in a direction perpendicular to the substrate. This is one possible way to do it.
  • the first electrode and the second electrode are arranged in a direction parallel to the substrate. This is one possible way to do it.
  • the material of the ferroelectric layer includes a hafnium oxide-based material.
  • the thickness of hafnium oxide-based ferroelectric capacitors can be reduced to ten nanometers or even sub-ten nanometers. In this case, high-density integration or even three-dimensional integration can be achieved, which has great advantages in building ultra-high-density memory chips.
  • the preparation process of hafnium oxide-based ferroelectric capacitors can have good compatibility with silicon-based semiconductor processes, so that mature manufacturing processes can be used to manufacture the ferroelectric capacitors without increasing manufacturing costs.
  • a second aspect of the embodiment of the present application provides a storage array.
  • the memory array includes a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor.
  • the ferroelectric capacitor includes a first electrode and a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode.
  • the ferroelectric layer serves as a storage medium.
  • the material of the ferroelectric layer may include a hafnium oxide-based material.
  • the ferroelectric capacitor further includes at least one nonlinear resistance layer disposed between the first electrode and the second electrode and parallel to the ferroelectric layer. That is, the ferroelectric capacitor includes a nonlinear resistor layer that divides voltage in series with the ferroelectric layer.
  • a plurality of memory cells are disposed on the substrate, each memory cell including a ferroelectric capacitor.
  • the material of the nonlinear resistance layer is a conductive material with resistive switching characteristics.
  • the memory array provided by the embodiment of the present application inserts a non-linear resistance layer parallel to the ferroelectric layer in the ferroelectric capacitor, so that the non-linear resistance layer and the ferroelectric layer divide the voltage applied to the ferroelectric capacitor.
  • the material of the nonlinear resistor layer is a conductive material with resistive switching characteristics. Therefore, the resistance of the nonlinear resistor layer can be reduced nonlinearly as the applied voltage increases. Then, after the above nonlinear resistor layer is placed in a ferroelectric capacitor, as the voltage applied to the ferroelectric capacitor increases, the resistance of the nonlinear resistor layer decreases nonlinearly, and the voltage division obtained by the nonlinear resistor layer is nonlinear. decrease.
  • the ferroelectric polarization flip of the ferroelectric capacitor also has the characteristic of changing non-linearly with voltage changes.
  • the proportion of the divided voltage obtained by the ferroelectric layer is small, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is small, which has almost no effect on the storage state of the memory cell. No effect.
  • the voltage applied to the ferroelectric capacitor is large (read and write voltage)
  • the proportion of the divided voltage obtained by the ferroelectric layer is large, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is large, and the read and write operations can be completed normally.
  • the existence of the nonlinear resistance layer can regulate the voltage response characteristics of the memory cell, enhance the nonlinear response characteristics of the memory cell as the voltage increases, and suppress the ferroelectric polarization flip of the ferroelectric capacitor at small voltages. This effectively enhances the anti-interference performance of the memory unit.
  • the material of the nonlinear resistance layer includes transition metal oxides, lanthanide oxides, perovskite composite oxides, or organic polymers. This is a low-cost implementation.
  • the material of the nonlinear resistance layer includes at least one of Ta 2 O 5 , Nb 2 O 5 , TiO 2 , and HfO 2 . This is a low-cost implementation.
  • the ferroelectric capacitor further includes at least one third electrode, the third electrode is disposed between the first electrode and the second electrode; the third electrode is disposed between the ferroelectric layer and the nonlinear resistance layer. .
  • the first electrode and the second electrode are arranged in a direction perpendicular to the substrate. This is one possible way to do it.
  • the first electrode and the second electrode are arranged in a direction parallel to the substrate. This is one possible way to do it.
  • the material of the ferroelectric layer includes a hafnium oxide-based material.
  • the thickness of hafnium oxide-based ferroelectric capacitors can be reduced to ten nanometers or even sub-ten nanometers. In this case, high-density integration or even three-dimensional integration can be achieved, which has great advantages in building ultra-high-density memory chips.
  • the preparation process of hafnium oxide-based ferroelectric capacitors can have good compatibility with silicon-based semiconductor processes, so that mature manufacturing processes can be used to manufacture the ferroelectric capacitors without increasing manufacturing costs.
  • a third aspect of the embodiment of the present application provides a storage array.
  • the memory array includes a substrate and a plurality of memory cells formed on the substrate, each memory cell including a ferroelectric capacitor.
  • the ferroelectric capacitor includes a first electrode and a second electrode, and a ferroelectric layer disposed between the first electrode and the second electrode.
  • the ferroelectric layer serves as a storage medium, and the material of the ferroelectric layer may include a hafnium oxide-based material.
  • the ferroelectric capacitor further includes at least one nonlinear resistance layer disposed between the first electrode and the second electrode and parallel to the ferroelectric layer. That is, the ferroelectric capacitor includes a nonlinear resistor layer that divides voltage in series with the ferroelectric layer.
  • a plurality of memory cells are disposed on the substrate, each memory cell including a ferroelectric capacitor. Among them, the material of the nonlinear resistor layer has metal-insulator transition characteristics.
  • the memory array provided by the embodiment of the present application inserts a non-linear resistance layer parallel to the ferroelectric layer in the ferroelectric capacitor, so that the non-linear resistance layer and the ferroelectric layer divide the voltage applied to the ferroelectric capacitor.
  • the resistance of the nonlinear resistor layer can be realized to decrease nonlinearly as the applied voltage increases. Then, after the above nonlinear resistor layer is placed in a ferroelectric capacitor, as the voltage applied to the ferroelectric capacitor increases, the resistance of the nonlinear resistor layer decreases nonlinearly, and the voltage division obtained by the nonlinear resistor layer is nonlinear. decrease.
  • the ferroelectric polarization flip of the ferroelectric capacitor also has the characteristic of changing non-linearly with voltage changes.
  • the proportion of the divided voltage obtained by the ferroelectric layer is small, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is small, which has almost no effect on the storage state of the memory cell. No effect.
  • the voltage applied to the ferroelectric capacitor is large (read and write voltage)
  • the proportion of the divided voltage obtained by the ferroelectric layer is large, and the amount of ferroelectric polarization flip of the ferroelectric capacitor is large, and the read and write operations can be completed normally.
  • the existence of the nonlinear resistance layer can regulate the voltage response characteristics of the memory cell, enhance the nonlinear response characteristics of the memory cell as the voltage increases, and suppress the ferroelectric polarization flip of the ferroelectric capacitor at small voltages. This effectively enhances the anti-interference performance of the memory unit.
  • the material of the nonlinear resistance layer includes a solid electrolyte. This is a low-cost implementation.
  • the material of the nonlinear resistance layer includes at least one of GeSbTe or AgInSbTe. This is a low-cost implementation.
  • the ferroelectric capacitor further includes at least one third electrode, the third electrode is disposed between the first electrode and the second electrode; the third electrode is disposed between the ferroelectric layer and the nonlinear resistance layer. .
  • the first electrode and the second electrode are arranged in a direction perpendicular to the substrate. This is one possible way to do it.
  • the first electrode and the second electrode are arranged in a direction parallel to the substrate. This is one possible way to do it.
  • the material of the ferroelectric layer includes a hafnium oxide-based material.
  • the thickness of hafnium oxide-based ferroelectric capacitors can be reduced to ten nanometers or even sub-ten nanometers. In this case, high-density integration or even three-dimensional integration can be achieved, which has great advantages in building ultra-high-density memory chips.
  • the preparation process of hafnium oxide-based ferroelectric capacitors can have good compatibility with silicon-based semiconductor processes, so that mature manufacturing processes can be used to manufacture the ferroelectric capacitors without increasing manufacturing costs.
  • a fourth aspect of the embodiment of the present application provides a memory, including: a controller; and the storage array of any one of the first aspect, the second aspect, and the third aspect; the controller is electrically connected to the storage array.
  • the memory provided by the embodiment of the present application includes the memory array of the first aspect, the second aspect, or the third aspect, and its beneficial effects are the same as those of the memory array, which will not be described again here.
  • a fifth aspect of the embodiment of the present application provides an electronic device, including: a circuit board; and a memory as in the fourth aspect; the circuit board and the memory are electrically connected.
  • a sixth aspect of the embodiment of the present application provides a method for preparing a memory array, including: forming a plurality of memory cells on a substrate, each memory cell including a ferroelectric capacitor; wherein the ferroelectric capacitor includes a first electrode and a third electrode. Two electrodes, as well as a ferroelectric layer and at least one nonlinear resistor layer disposed between the first electrode and the second electrode; the resistance of the material of the nonlinear resistor layer decreases nonlinearly as the applied voltage increases.
  • the memory array preparation method provided by the embodiment of the present application is used to prepare the memory array of the first aspect, and its beneficial effects are the same as those of the memory array, and will not be described again here.
  • the material of the nonlinear resistance layer is a conductive material with resistive switching characteristics.
  • the material of the nonlinear resistor layer has metal-insulator transition properties.
  • the material of the nonlinear resistor layer includes transition metal oxides, lanthanide oxides, perovskite composite oxides, solid electrolytes or organic polymers.
  • the material of the nonlinear resistance layer includes at least one of Ta 2 O 5 , Nb 2 O 5 , TiO 2 , HfO 2 , GeSbTe or AgInSbTe.
  • the ferroelectric capacitor further includes at least one third electrode, the third electrode is disposed between the first electrode and the second electrode; the third electrode is disposed between the ferroelectric layer and the nonlinear resistance layer. .
  • a seventh aspect of the embodiments of the present application provides a method for preparing a memory array, which is used to prepare the memory array of the second aspect or the third aspect.
  • Figure 1 shows a cross-bar array structural arrangement of a memory provided by related technologies
  • Figure 2 is a circuit diagram of an electronic device provided by an embodiment of the present application.
  • Figure 3 is a circuit diagram of a memory provided by an embodiment of the present application.
  • Figure 4 is a circuit diagram of a memory unit in a memory array provided by an embodiment of the present application.
  • Figure 5 is a circuit diagram of a memory array provided by an embodiment of the present application.
  • Figure 6 is a circuit diagram of a memory unit in another memory array provided by an embodiment of the present application.
  • Figure 7 is a circuit diagram of another memory array provided by an embodiment of the present application.
  • Figure 8A is a positional relationship diagram between a ferroelectric capacitor and a substrate provided by an embodiment of the present application.
  • Figure 8B is a positional relationship diagram between another ferroelectric capacitor and a substrate provided by an embodiment of the present application.
  • Figure 8C is a schematic top view of a ferroelectric capacitor provided by an embodiment of the present application.
  • FIGS. 9A-9E are schematic structural diagrams of a ferroelectric capacitor provided by embodiments of the present application.
  • Figure 10A is an electrical characteristic curve of a memory cell illustrating an embodiment of the present application.
  • Figure 10B is an electrical characteristic curve of a memory cell provided by an embodiment of the present application when a positive electric field is applied;
  • Figure 11A is a curve of voltage changing with time provided by an embodiment of the present application.
  • Figure 11B is a curve of the voltage division obtained on the ferroelectric layer as the voltage changes according to an embodiment of the present application.
  • Figure 11C is a residual polarization intensity curve of a memory cell as the voltage changes according to an embodiment of the present application.
  • Figure 11D is a curve of polarization charge changing with voltage of a memory cell provided by an embodiment of the present application.
  • Figure 12A is another curve of the voltage division obtained on the ferroelectric layer as the voltage changes according to an embodiment of the present application.
  • Figure 12B is another residual polarization intensity curve of a memory cell as the voltage changes according to an embodiment of the present application.
  • Figure 12C is a curve of polarization charge changing with voltage of another memory cell provided by an embodiment of the present application.
  • FIGS 13A-14D are schematic structural diagrams of another ferroelectric capacitor provided by embodiments of the present application.
  • 200-Electronic equipment 210-System on a chip; 211-Application processor; 212-Image processing unit; 213-Random access memory; 220-Read-only memory; 230-Communication chip; 240-Power management chip; 250-Bus; 300-memory; 310-storage array; 320-decoder; 330-driver; 340-timing controller; 350-cache; 360-input and output driver; 400-storage unit; 401-storage unit; 402-storage unit ; 403-storage unit; 404-storage unit; 11-first electrode; 12-second electrode; 13-ferroelectric layer; 14-nonlinear resistance layer; 15-third electrode; 100-substrate.
  • orientation terms such as “upper”, “lower”, “left”, and “right” may include but are not limited to being defined relative to the orientation of the components in the drawings. It should be understood that, These directional terms may be relative concepts and are used for relative description and clarification, which may change accordingly according to changes in the orientation in which components are placed in the drawings.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral body; it can be a direct connection. , can also be connected indirectly through intermediaries.
  • phase coupling may refer to a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • contact can mean direct contact or indirect contact through an intermediary.
  • Ferroelectric materials They can maintain spontaneous polarization by aligning their internal electric dipole moments with an applied electric field, even when the externally applied electric field is removed.
  • a ferroelectric is a material in which the polarization value (or electric field) remains semi-permanently, even after a constant voltage is applied and the voltage returns to zero volts.
  • Unit cell It is a structure composed of a large number of microscopic material units (atoms, ions, molecules, etc.) arranged in an orderly manner according to certain rules.
  • Ferroelectric phase crystal The structure of the unit cell causes the positive and negative charge centers to not overlap and an electric dipole moment appears, resulting in an electric polarization intensity that is not equal to zero, making the crystal spontaneously polarized, and the direction of the electric dipole moment can be changed by an external electric field. , showing characteristics similar to ferromagnets.
  • Volatile memory refers to memory that stores information that disappears when the current is interrupted, such as common dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM) )wait.
  • DRAM Dynamic Random Access Memory
  • SRAM static random access memory
  • Non-volatile memory refers to memory in which the stored information does not disappear when the current is interrupted, such as various types of read-only memory (Read-Only Memory, ROM), new types of memory such as Magnetic Random Access Memory (Magnetic Random Access) Memory, MRAM) or ferroelectric random access memory (Ferroelectric Random Access Memory, FRAM), etc.
  • ROM Read-Only Memory
  • MRAM Magnetic Random Access Memory
  • FRAM Feroelectric Random Access Memory
  • Ferroelectric random access memory is based on the ferroelectric effect of ferroelectric materials to store data.
  • Ferroelectric memory has the advantages of ultra-high storage density, low power consumption, small size, low read and write voltage, high read and write speed, good cycle performance, radiation resistance and non-volatility. , is expected to become the main competitor to replace dynamic random access memory (DRAM).
  • the memory cells in ferroelectric memory include transistors and ferroelectric capacitors, which store information based on the ferroelectric effect.
  • a ferroelectric capacitor includes two electrodes and a ferroelectric material, such as a ferroelectric layer, disposed between the two electrodes.
  • the dielectric constant of ferroelectric materials can not only be adjusted, but also the difference before and after the polarization state of the ferroelectric film layer is flipped is very large, which makes ferroelectric capacitors smaller compared to other capacitors. , for example, is much smaller than the capacitor used to store charge in DRAM.
  • the ferroelectric layer can be formed using common ferroelectric materials. After crystallization treatment, a ferroelectric phase crystal structure can be formed in the ferroelectric layer.
  • the central atom stays in a low-energy state along the electric field.
  • the electric field reversal is applied to the ferroelectric layer, the central atom moves along the direction of the electric field in the crystal. Move and stop in another low energy state. A large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains, which form polarized charges under the action of an electric field.
  • the polarization charge formed by the reversal of the ferroelectric domain under the electric field is high, and the polarization charge formed by the non-reversal of the ferroelectric domain under the electric field is low.
  • the binary stable state of this ferroelectric material allows ferroelectricity to be used as memory.
  • Embodiments of the present application provide an electronic device including a memory.
  • the memory may be, for example, a ferroelectric memory.
  • Figure 2 shows an electronic device 200 provided by an embodiment of the present application.
  • the electronic device 200 can be a terminal device, such as a mobile phone, a tablet, a smart bracelet, or a personal computer (PC), server, workstation, etc. .
  • the electronic device 200 includes a bus 250, a system on chip (SOC) 210 and a read-only memory (read-only memory, ROM) 220 connected to the bus 250.
  • SOC210 can be used to process data, such as processing application data, processing image data, and caching temporary data.
  • ROM 220 can be used to save non-volatile data, such as audio files, video files, etc.
  • ROM 220 can be PROM (programmable read-only memory, programmable read-only memory), EPROM (erasable programmable read-only memory, erasable programmable read-only memory), flash
  • the electronic device 200 may also include a communication chip 230 and a power management chip 240.
  • the communication chip 230 can be used to process the protocol stack, or to amplify and filter analog radio frequency signals, or to implement the above functions at the same time.
  • the power management chip 240 can be used to power other chips.
  • the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a cache data Random access memory (RAM) 213.
  • AP application processor
  • GPU graphics processing unit
  • RAM cache data Random access memory
  • the above-mentioned AP211, GPU212 and RAM213 may be integrated into one die, or respectively integrated into multiple die, and packaged in a package structure. For example, using 2.5D (dimension), 3D packaging, or other advanced packaging technologies.
  • the above-mentioned AP211 and GPU212 are integrated in one die, and the RAM 213 is integrated in another die.
  • the two dies are packaged in a package structure to obtain faster inter-die data transmission speed. and higher data transmission bandwidth.
  • FIG. 3 is a schematic structural diagram of a memory 300 provided by an embodiment of the present application.
  • the memory 300 may be, for example, a ferroelectric memory.
  • the memory 300 may be RAM 213 as shown in Figure 2, which belongs to FRAM.
  • the memory 300 may also be a RAM provided outside the SOC 210 . This application does not limit the location of the memory 300 in the device and its positional relationship with the SOC 210 .
  • the memory 300 provided in the embodiment of the present application may not be assembled in an electronic device, and the memory 300 may directly exist as a single product.
  • the memory is a solid state disk (SSD) or a magnetic random access memory (MRAM).
  • the memory 300 includes a storage array 310 and a controller.
  • the controller is electrically connected to the storage array and is used to control the reading and writing of the storage cells in the storage array.
  • the controller may include logic to control the read and write timing, and the controller may also include an analog circuit part (such as a sense amplifier).
  • the controller may include at least one of a decoder 320, a driver 330, a timing controller 340, a buffer 350, and an input-output driver 360.
  • the storage array 310 can be independently integrated in a chip (or bare chip), and the controller can be independently integrated in a chip.
  • the storage array chip and the controller chip can be integrated and interconnected to form the above-mentioned memory.
  • the memory array 310 can also be integrated into the same chip as the controller.
  • the storage array 310 includes a plurality of storage units 400 arranged in an array, where each storage unit 400 can be used to store 1 bit or multiple bits of data.
  • the memory array 310 also includes signal lines such as word lines (WL) and bit lines (BL). Each memory cell 400 is electrically connected to the corresponding word line WL and bit line BL.
  • One or more of the above-mentioned word lines WL and bit lines BL are used to select the memory cells 400 to be read and written in the memory array by receiving the control level output by the control circuit, so as to change the polarity of the ferroelectric capacitor in the memory cells 400. direction to realize data reading and writing operations.
  • the decoder 320 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed.
  • the driver 330 is used to control the level of the signal line according to the decoding result generated by the decoder 320, thereby achieving access to the designated storage unit 400.
  • the buffer 350 is used to cache the read data. For example, first-in first-out (FIFO) may be used for caching.
  • the timing controller 340 is used to control the timing of the buffer 350 and control the driver 330 to drive the signal lines in the memory array 310.
  • the input and output driver 360 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.
  • the above-mentioned memory array 310, decoder 320, driver 330, timing controller 340, buffer 350 and input/output driver 360 can be integrated into one chip, or can be integrated into multiple chips respectively.
  • the memory 300 involved in this application may be a ferroelectric random access memory (FRAM) or a ferroelectric field effect transistor (ferroelectric field-effect-transistor, FeFET) memory.
  • FRAM ferroelectric random access memory
  • FeFET ferroelectric field effect transistor
  • Figure 4 shows a circuit structure diagram of one of the memory cells 400 of the FRAM.
  • the memory cell 400 includes at least one ferroelectric capacitor (the example in Figure 4 shows a ferroelectric capacitor C1, a ferroelectric capacitor C2 and a ferroelectric capacitor C3) and a transistor Tr, such a memory cell 400 may be called a 1TnC memory cell.
  • the memory cell 400 may be called a 1T1C memory cell.
  • the transistor Tr here may be a metal-oxide-semiconductor field-effect transistor (MOSFET).
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • the memory unit 400 also includes a word line (WL), a bit line (BL) and a plate line (PL), and in the memory unit 400, the first terminal of the transistor Tr is connected to The bit line BL is electrically connected, the control end of the transistor Tr is electrically connected to the word line WL, the second end of the transistor Tr is electrically connected to one end of the capacitor C, and the other end of the capacitor C is electrically connected to the plate line PL.
  • WL word line
  • BL bit line
  • PL plate line
  • one of the drain or source of the transistor Tr is called the first terminal, the corresponding other terminal is called the second terminal, and the control terminal of the transistor Tr is the gate.
  • the drain and source of the transistor Tr can be determined according to the flow direction of the current. For example, in Figure 4, when the current flows from left to right, the left end is the drain and the right end is the source. On the contrary, when the current flows from right to left When , the right end is the drain and the left end is the source.
  • the transistor Tr here is a transistor device with three terminals. Then, the transistor Tr can choose an NMOS (N-channel metal oxide semiconductor, N-channel metal oxide semiconductor) tube, or it can choose a PMOS (P -channel metal oxide semiconductor, P-channel metal oxide semiconductor) tube.
  • NMOS N-channel metal oxide semiconductor, N-channel metal oxide semiconductor
  • PMOS P -channel metal oxide semiconductor, P-channel metal oxide semiconductor
  • a storage unit 400 shown in FIG. 4 can be used to store multi-bit data to increase the storage capacity of each storage unit.
  • the ferroelectric capacitor C1, the ferroelectric capacitor C2 and the ferroelectric capacitor C3 share a transistor Tr.
  • the number of transistors in each memory cell 400 can also be reduced to increase the storage density.
  • the memory array 310 can be obtained by arranging the memory cells 400 shown in FIG. 4 in an array, in which each memory cell 400 has the same circuit structure.
  • the memory array 310 shown in FIG. 5 exemplifies a memory array including four memory units: a memory unit 401, a memory unit 402, a memory unit 403, and a memory unit 404.
  • Those skilled in the art can design the arrangement of the storage units 400 and the number of the storage units 400 in the storage array 310 according to the storage capacity requirements of the memory 300 .
  • the storage array 310 may further include more storage units 400, and the storage units 400 may be arranged in the X, Y, and Z directions that are perpendicular to each other to form a three-dimensional storage array.
  • the word line WL extends along the X direction, and further, the control end of the transistor Tr of the multiple memory cells arranged along the WL electrical connection. Furthermore, the bit line BL extends in the Y direction perpendicular to the X direction. In this case, the first ends of the transistors Tr of the plurality of memory cells arranged in the Y direction are electrically connected to the same bit line BL.
  • FIG. 6 shows a circuit structure diagram of another memory unit 400 of FRAM.
  • the memory unit 400 includes a first transistor Tr1 and a second transistor Tr2, and a plurality of ferroelectric capacitors (the example in FIG. 6 illustrates a ferroelectric capacitor C1 and a ferroelectric capacitor C2).
  • Such a memory unit may be called 2TnC memory cell.
  • Ferroelectric capacitor C2 and ferroelectric capacitor C1 have the same structure, including two electrodes and a ferroelectric layer between the two electrodes. In order to facilitate the following connection between ferroelectric capacitor C2 and ferroelectric capacitor C1 and other structures. The electrical connection relationship is clearly described.
  • One electrode of the ferroelectric capacitor C1 can be called the first electrode, and the other electrode can be called the second electrode.
  • One electrode of the ferroelectric capacitor C2 can be called the third electrode, and the other electrode can be called the fourth electrode.
  • the memory unit 400 also includes a word line (word line, WL), a write bit line (write bit line, WBL), a read bit line (read bit line, RBL), and a source line (source line, SL). and control line (CL).
  • word line, WL word line
  • WBL write bit line
  • RBL read bit line
  • source line source line
  • CL control line
  • the control terminal of the first transistor Tr1 is electrically connected to the control line CL
  • the first terminal of the first transistor Tr1 is electrically connected to the first electrode of the ferroelectric capacitor C1 and the third electrode of the ferroelectric capacitor C2 respectively.
  • the first transistor Tr1 The second end of the ferroelectric capacitor C1 is electrically connected to the write bit line WBL, and the second electrode of the ferroelectric capacitor C1 and the fourth electrode of the ferroelectric capacitor C2 are electrically connected to the corresponding word line WL.
  • the first end of the second transistor Tr2 is electrically connected to the source line SL, the second end is electrically connected to the read bit line RBL, and the control end of the second transistor T2 is respectively connected to the first pole and the ferroelectric capacitor C1.
  • the third pole of capacitor C2 is electrically connected.
  • the memory cells 400 shown in FIG. 6 are arranged in an array to obtain the memory array 310 shown in FIG. 7 .
  • the memory array 310 shown in FIG. 7 exemplifies a memory array including four memory units: a memory unit 401, a memory unit 402, a memory unit 403, and a memory unit 404.
  • control line CL0 the control line
  • control line CL1 the control line
  • control line CL2 the control line
  • control line CL3 the control line
  • the memory array 310 includes two write bit lines, namely write bit line WBL0 and write bit line WBL1, and each write bit line extends along the X direction.
  • write bit line WBL0 When it also includes more write bit lines WBL , these write bit lines WBL are arranged in parallel along the Y direction perpendicular to the WBL1, memory cell 403 and memory cell 404 share write bit line WBL0.
  • the read bit line RBL and the write bit line WBL are set up in the same manner, which will not be described again here.
  • the source line SL in the memory array is not only shared by the source lines SL of multiple memory cells arranged along the X direction, but also shared by the multiple memory cells arranged along the Y direction.
  • the source line SL of the memory unit 401 here is shared with the source line SL of the memory unit 404.
  • the source line SL of the memory unit 401 and the source line SL of the memory unit 402 are also shared. That is, the memory unit 401, the memory unit 402, and the memory unit here are 403 and the source line SL of the memory unit 404 are connected to each other.
  • a source line SL layer structure parallel to the substrate can be formed to electrically connect the source lines parallel to the substrate.
  • the word line WL in this memory array is not only shared by the plurality of memory cells arranged in the X direction, but also shared by the plurality of memory cells arranged in the Y direction. , for example, here the word line WL0 connected to the ferroelectric capacitor C0 of the memory unit 401 and the word line WL0 connected to the ferroelectric capacitor C0 of the memory unit 402 are shared, and the word line WL0 connected to the ferroelectric capacitor C0 of the memory unit 401 is shared with the memory unit.
  • the word line WL0 connected to the ferroelectric capacitor C0 of 404 is also shared, that is, the word lines WL0 of the four ferroelectric capacitors C0 of the memory unit 401, memory unit 402, memory unit 403 and memory unit 404 are connected to each other. WL1 of the four ferroelectric capacitors C1 of the memory unit 402, the memory unit 403, and the memory unit 404 are connected to each other. Similarly, in an achievable process structure, a word line layer structure parallel to the substrate can be provided to connect word lines located on the same layer to each other.
  • the ferroelectric capacitor structure may include a first electrode and a second electrode, and may be formed between the first electrode and the second electrode. ferroelectric layer. Or it can be understood that the ferroelectric capacitor has a metal-ferroelectric-metal (metal-ferroelectric-metal, MFM) structure.
  • MFM metal-ferroelectric-metal
  • hafnium oxide-based ferroelectric memory arrays composed of ferroelectric layers of hafnium oxide-based materials can be reduced to ten nanometers or even sub-ten nanometers, enabling high-density integration and even three-dimensional integration. Ultra-high-density memory chips have unique advantages.
  • the manufacturing process of hafnium oxide-based ferroelectric memory arrays is also well compatible with mature silicon-based semiconductor processes. Therefore, hafnium oxide-based ferroelectric memory arrays are expected to become the core units of new ferroelectric memory arrays in the future.
  • hafnium oxide-based ferroelectric memory arrays In a hafnium oxide-based ferroelectric memory chip, if a cross bar structure (cross bar) is used, multiple hafnium oxide-based memory cells are connected through word lines WL and bit lines BL to form an array. When the memory chip needs to read or write data, it is necessary to apply voltage to a certain word line WL and bit line BL to select, read and write a specific hafnium oxide-based memory cell.
  • the word line WL and the bit line BL in the memory chip are not completely independent, the voltage applied to a certain word line WL or bit line BL will cause interference to the hafnium oxide-based memory cells on nearby lines, resulting in related hafnium oxide-based ferroelectric
  • the rough-out unit undergoes ferroelectric polarization flip under the disturbance voltage, making the stored information difficult to read or even lost. Therefore, how to enhance the anti-interference ability of hafnium oxide-based memory cells during the reading and writing process is one of the current problems that needs to be solved urgently.
  • the solution to the interference problem faced by hafnium oxide-based memory cells in the read and write operations of memory chips is to reduce the interference of read and write pulses on non-target devices by optimizing the pulse parameters and timing logic of read and write operations. .
  • Vcc when the operating voltage Vcc is applied to select, read and write the target memory cell, a voltage of 1/3Vcc is applied to the non-target memory cell, thereby suppressing the interference of the voltage of the line where the target memory cell is located on the non-target memory cell.
  • the above solution mainly enhances the anti-interference ability of the memory unit from the circuit level, and has certain requirements for the anti-interference performance of the memory unit itself. If the memory unit itself has poor anti-interference performance, it cannot be used. In addition, due to the application of voltage to non-target memory cells during read and write operations, the non-target memory cells may be subject to unnecessary electric field stress, resulting in reduced durability.
  • embodiments of the present application also provide a memory array that changes the structure of the ferroelectric capacitor in the memory array to suppress the ferroelectric polarization flip of the memory cell under low electric fields, thereby enhancing the anti-interference performance of the memory cell itself.
  • the memory array includes a substrate 100 and memory cells 400 provided on the substrate 100 .
  • the storage array includes multiple storage units 400, and FIG. 8A only takes one storage unit 400 as an example for illustration.
  • the memory unit 400 includes a transistor and a ferroelectric capacitor C. For convenience of explanation, only the structure of the ferroelectric capacitor C is shown in FIG. 8A .
  • the ferroelectric capacitor C includes a first electrode 11 and a second electrode 12 , and a ferroelectric layer 13 formed between the first electrode 11 and the second electrode 12 .
  • the ferroelectric capacitor C also includes at least one layer of nonlinear resistance layer 14 (a layer of nonlinear resistance layer 14 is used as an example in FIG. 8A for illustration). Furthermore, at least one nonlinear resistance layer 14 and a ferroelectric layer 13 are provided between the first electrode 11 and the second electrode 12 .
  • first electrode 11 and the second electrode 12 are arranged in a direction perpendicular to the thickness of the second electrode 12.
  • the surface of the first electrode 11 perpendicular to the thickness and the surface of the second electrode 12 perpendicular to the thickness are arranged oppositely.
  • the first electrode 11 A gap space is defined with the second electrode 12 , and the nonlinear resistance layer 14 and the ferroelectric layer 13 are disposed in the gap space between the first electrode 11 and the second electrode 12 .
  • the first electrode 11 and the second electrode 12 are stacked, and the ferroelectric layer 13 and the varistor layer 14 are stacked between the first electrode 11 and the second electrode 12 .
  • the thickness direction of the first electrode 11 and the second electrode 12 is perpendicular to the substrate 100 , and the first electrode 11 and the second electrode 12 in the ferroelectric capacitor C are along the same direction as the substrate 100 .
  • Vertical orientation setting is
  • each layer structure of the first electrode 11, the second electrode 12, the ferroelectric layer 13, at least one nonlinear resistance layer 14 and at least one third electrode 15 is arranged parallel to the substrate 100, so that The ferroelectric capacitor C can be called a planar ferroelectric capacitor structure.
  • the thickness direction of the first electrode 11 and the second electrode 12 is parallel to the substrate 100 , and the first electrode 11 and the second electrode 12 are arranged in a direction parallel to the substrate 100 .
  • Such ferroelectric capacitor C can be called a vertical ferroelectric capacitor structure.
  • a vertical capacitor structure When using a vertical capacitor structure, three-dimensional stacking can be achieved to increase storage density and storage capacity.
  • Figure 8B shows one of the possible structures in the vertical ferroelectric capacitor structure
  • Figure 8C is a top view of Figure 8B.
  • the first electrode 11 extends along a direction perpendicular to the substrate 100 , and the ferroelectric layer 13 , at least one nonlinear resistor layer 14 , at least one third electrode 15 and the second electrode 12 extend parallel to the substrate 100 The direction is around the periphery of the first electrode 11 in turn. In this way, a ferroelectric capacitor C with a columnar structure is formed.
  • the cross-section of the ferroelectric capacitor C with a cylindrical structure may be circular as shown in FIG. 8C , or may be rectangular, or may be in other shapes.
  • the first electrode 11 and the second electrode 12 can be made of metal-containing materials.
  • the materials of the first electrode 11 and the second electrode 12 include metal, metal nitride, metal carbide, conductive metal nitride, conductive metal oxide or combinations thereof.
  • the material of the first electrode 11 may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir) ), ruthenium oxide (RuO 2 ), iridium oxide (IrO 2 ), niobium nitride (NbN), molybdenum nitride (MoN) or combinations thereof.
  • the material of the second electrode 12 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), nitrogen Tungsten (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO 2 ), niobium nitride (NbN), molybdenum nitride (MoN), iridium oxide (IrO 2 ), silicon (Si), germanium (Ge), silicon germanium (SiGe) or combinations thereof.
  • the materials of the first electrode 11 and the second electrode 12 may be the same or different.
  • the thickness of the first electrode 11 and the second electrode 12 along the stacking direction may be, but is not limited to, 1 nm to 100 nm. Also, the thickness of the first electrode 11 and the thickness of the second electrode 12 may be equal or unequal.
  • the above-mentioned ferroelectric layer 13 has ferroelectricity, so that it has spontaneous polarization within a certain temperature range, and its spontaneous polarization direction can be reversed due to the reverse direction of the external electric field. In this case, when its polarization orientation is reversed, the ferroelectric capacitor C will be charged and discharged, which can then be recognized by the external circuit and achieve a "0" or "1" storage state.
  • the ferroelectric layer 13 is made of hafnium oxide-based material.
  • the thickness of hafnium oxide-based ferroelectric capacitor C can be reduced to ten nanometers or even sub-ten nanometers. In this case, high-density integration and even three-dimensional integration can be achieved, which has greater advantages in building ultra-high-density memory chips. Big advantage.
  • the preparation process of the hafnium oxide-based ferroelectric capacitor C can have good compatibility with the silicon-based semiconductor process.
  • the ferroelectric capacitor C can be manufactured using a mature manufacturing process without increasing the manufacturing cost.
  • the above-mentioned hafnium oxide-based material may be a material with ferroelectricity based on a hafnium oxide (HfO) material system.
  • the material of the ferroelectric layer 13 may be zirconium (Zr)-doped hafnium dioxide (HfO 2 ), silicon (Si)-doped HfO 2 , aluminum (Al)-doped HfO 2 , or lanthanum (La)-doped HfO 2 .
  • the above-mentioned hafnium oxide-based material may also be a material with ferroelectricity in the hafnium zirconium oxide (HZO) material system.
  • the material of the ferroelectric layer 13 may be lanthanum (La) doped HZO, yttrium (Y) doped HZO, strontium (Sr) doped HZO, gadolinium (Gd) doped HZO, gadolinium lanthanum (Gd) /La) co-doped HZO, etc.
  • the doping element may also be one or more of nitrogen, iron, lutetium, praseodymium, germanium, scandium, cerium, neodymium, magnesium, barium, indium, gallium, calcium, and carbon.
  • the above-mentioned hafnium oxide-based material can also be a material system such as hafnium silicon oxide, hafnium aluminum oxide, hafnium lanthanum oxide, hafnium zirconium lanthanum oxide, hafnium zirconium cerium oxide, hafnium zirconium yttrium oxide, hafnium zirconium gadolinium oxide, etc., with ferroelectricity s material.
  • titanium nitride TiN can be selected to make the first electrode 11 and the second electrode 12, and zirconium (Zr)-doped hafnium dioxide (HZO) can be used to make the ferroelectric layer 13, thereby making full use of the HZO layer to provide Tensile stress is conducive to the formation of ferroelectric phases, and the TiN material is compatible with the semiconductor CMOS process.
  • Zr zirconium
  • HZO hafnium dioxide
  • titanium nitride can be used to make the first electrode 11 and the second electrode 12
  • zirconium (Zr)-doped hafnium dioxide can be used to make the ferroelectric layer 13, thereby making full use of
  • the HZO layer provides the characteristics of tensile stress that is beneficial to the formation of the ferroelectric phase, and the characteristics of the TiN material that can be compatible with the semiconductor CMOS process.
  • the thickness of the ferroelectric layer 13 along the stacking direction may be, but is not limited to, 1 nm to 100 nm.
  • a crystal in a ferroelectric phase is formed in the ferroelectric layer 13.
  • the central atoms of the crystal stop in a low energy state along the electric field.
  • the electric field is reversed and applied to the ferroelectric layer, In the electric layer, the central atom moves in the crystal along the direction of the electric field and stops in another low-energy state.
  • a large number of central atoms move and couple in the crystal unit cell to form ferroelectric domains.
  • the ferroelectric domains form polarization charges under the action of the electric field.
  • the polarization charges formed before and after the ferroelectric domains are reversed under the electric field have different energy levels. This is This binary stable state will cause the ferroelectric capacitor C to charge and discharge, which can then be recognized by the external circuit and achieve a "0" or "1" storage state.
  • the non-linear resistance layer 14 is provided on at least one side of the ferroelectric layer 13.
  • the ferroelectric capacitor C includes a nonlinear resistance layer 14 , and the nonlinear resistance layer 14 is provided on one side of the ferroelectric layer 13 .
  • the nonlinear resistance layer 14 is provided between the ferroelectric layer 13 and the first electrode 11 .
  • the nonlinear resistance layer 14 is provided between the ferroelectric layer 13 and the second electrode 12 .
  • the ferroelectric capacitor C includes a multi-layer nonlinear resistance layer 14 , and at least one side of the ferroelectric layer 13 is provided with the nonlinear resistance layer 14 .
  • At least one layer of nonlinear resistance layer 14 is provided between the ferroelectric layer 13 and the first electrode 11 , and at least one layer of nonlinear resistance layer 14 is also provided between the ferroelectric layer 13 and the second electrode 12 .
  • the multilayer nonlinear resistance layer 14 is disposed between the ferroelectric layer 13 and the first electrode 11 .
  • the multilayer nonlinear resistance layer 14 is disposed between the ferroelectric layer 13 and the second electrode 12 .
  • the material of the nonlinear resistance layer 14 has the characteristic that as the applied voltage increases, the resistance of the material of the nonlinear resistance layer 14 decreases nonlinearly.
  • first electrode 11 and the second electrode 12 of the ferroelectric capacitor C serve as voltage receiving ends to receive signal lines (such as bit lines BL and plate lines PL, or word lines WL and write bits).
  • signal lines such as bit lines BL and plate lines PL, or word lines WL and write bits.
  • the material properties of the nonlinear resistance layer 14 are such that as the voltage applied to the ferroelectric capacitor C increases, the resistance of the nonlinear resistance layer 14 decreases nonlinearly. Or it can be understood that as the voltage applied to the ferroelectric capacitor C increases, the slope nonlinearity of the resistance curve of the nonlinear resistance layer 14 increases.
  • nonlinearity decreases, which can be understood as the voltage applied to the ferroelectric capacitor C increases linearly, but the resistance of the nonlinear resistance layer 14 first decreases slowly and then decreases rapidly. That is, the resistance of the nonlinear resistance layer 14 exhibits nonlinear changes as the applied voltage increases. When the applied voltage is small, the resistance of the nonlinear resistance layer 14 is large. When the applied voltage is large, the resistance of the nonlinear resistance layer 14 decreases rapidly.
  • Vcc is the voltage applied for read and write operations.
  • the ferroelectric layer 13 and the nonlinear resistor layer 14 are stacked in parallel. Then, the ferroelectric layer 13 and the nonlinear resistor layer 14 are in a series relationship.
  • the ferroelectric layer 13 and the nonlinear resistor layer 14 can be equivalent to a series connection. of two resistors.
  • the ferroelectric capacitor C in the unselected memory cells will be applied with a voltage less than Vcc (for example, less than 1/3Vcc ).
  • Vcc voltage less than 1/3Vcc
  • the resistance of the nonlinear resistor layer 14 is relatively large.
  • the voltage applied on the ferroelectric layer 13 is significantly reduced.
  • the polarization charge output by the ferroelectric capacitor C is almost zero. Therefore, this "voltage less than Vcc" disturbance has almost no impact on the storage state of the memory cell, and the anti-interference performance of the memory cell is enhanced.
  • the ferroelectric capacitor C in the memory cell will be applied with Vcc voltage.
  • the nonlinear resistance layer 14 decreases rapidly and is almost negligible.
  • the voltage applied on the ferroelectric layer 13 is almost equal to Vcc.
  • ferroelectric capacitor C outputs polarized charge.
  • FIG. 10A shows the electrical characteristic curve of a hafnium oxide-based memory cell that does not include the nonlinear resistance layer 14 (typical).
  • the abscissa is the voltage V
  • the ordinate is the remnant polarization intensity Pr.
  • FIG. 10B shows the relationship between the electrical characteristics of a hafnium oxide-based memory cell including a nonlinear resistance layer 14 and its anti-interference performance when a positive electric field is applied.
  • the negative electric field is similar to the positive electric field.
  • the solid line in FIG. 10B is the electrical output characteristic of the hafnium oxide-based memory cell that does not include the nonlinear resistance layer 14 (typical)
  • the dotted line in FIG. 10B is the electrical output characteristic of the hafnium oxide based memory cell that includes the nonlinear resistance layer 14.
  • the ferroelectric polarization of hafnium oxide-based memory cells has begun to flip. As the voltage rises to 1/2Vcc, a certain amount of ferroelectric polarization in the memory cell has flipped, that is, the perturbation voltage of 1/2Vcc will have a significant impact on the storage state of the device.
  • the ferroelectric polarization of the hafnium oxide-based memory cell including the nonlinear resistance layer 14 also begins to flip.
  • the voltage rises to 1/2Vcc the residual polarization intensity Pr slowly increases, or barely increases.
  • the voltage rises to greater than 1/2Vcc the residual polarization intensity Pr increases rapidly. In this way, at low voltage (less than 1/2Vcc), the polarization charge output by the memory unit is almost zero. Therefore, the small voltage disturbance voltage has almost no impact on the storage state of the memory unit, and the anti-interference performance of the memory unit is obtained. Enhance.
  • the nonlinear resistance layer 14 arranged parallel to the ferroelectric layer 13 is inserted into the ferroelectric capacitor C, so that the pair of the nonlinear resistance layer 14 and the ferroelectric layer 13 is applied to the ferroelectric capacitor C.
  • the voltage on C is divided.
  • the material of the nonlinear resistor layer 14 has the characteristic of nonlinear reduction in resistance as the applied voltage increases, so that the resistance of the nonlinear resistor layer 14 decreases nonlinearly as the applied voltage increases.
  • the nonlinear resistor layer 14 is placed in the ferroelectric capacitor C, as the voltage applied to the ferroelectric capacitor C increases, the resistance of the nonlinear resistor layer 14 decreases nonlinearly, and the resistance of the nonlinear resistor layer 14 The partial pressure decreases nonlinearly.
  • the divided voltage obtained by the ferroelectric layer 13 increases nonlinearly. That is, when the voltage applied to the ferroelectric capacitor C is small, the ratio of the divided voltage obtained by the ferroelectric layer 13 is small. When the voltage applied to the ferroelectric capacitor C is larger, the ratio of the divided voltage obtained by the ferroelectric layer 13 is larger.
  • the ferroelectric polarization flip of the ferroelectric capacitor C also has the characteristic of changing non-linearly with the voltage change. That is, when the voltage (interference voltage) applied to the ferroelectric capacitor C is small, the ratio of the divided voltage obtained by the ferroelectric layer 13 is small, and the ferroelectric polarization inversion amount of the ferroelectric capacitor C is small, which affects the memory cell. Storage state has little impact. When the voltage applied to the ferroelectric capacitor C is large (read and write voltage), the ratio of the divided voltage obtained by the ferroelectric layer 13 is large, and the amount of ferroelectric polarization flip of the ferroelectric capacitor C is large, and reading and writing can be completed normally. operate.
  • the existence of the nonlinear resistance layer 14 can regulate the voltage response characteristics of the memory cell, enhance the nonlinear response characteristics of the memory cell as the voltage increases, and suppress the ferroelectric polarization of the ferroelectric capacitor C under small voltages. flip, thereby effectively enhancing the anti-interference performance of the memory cell.
  • the material of the nonlinear resistor layer 14 is a conductive material, and the material of the nonlinear resistor layer 14 has resistive switching characteristics.
  • the resistive switching characteristic can be understood as: the resistance of the material of the nonlinear resistor layer 14 is not fixed and changes with the change of voltage.
  • the material of varistor layer 14 includes transition metal oxides.
  • transition metal oxides include oxides containing transition metals.
  • the material of the varistor layer 14 includes at least one of tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), titanium dioxide (TiO 2 ), or hafnium dioxide (HfO 2 ).
  • the material of the ferroelectric layer 13 is a material of the HfO material system, the ferroelectric layer 13 will be doped with HfO 2 . Therefore, when the material of the nonlinear resistor layer 14 includes HfO 2 , the film boundary between the ferroelectric layer 13 and the nonlinear resistor layer 14 can be divided by analyzing the doping components in the film layer.
  • the material of the varistor layer 14 includes lanthanide oxide.
  • lanthanide oxides include oxides containing lanthanide elements.
  • the materials of the nonlinear resistor layer 14 include lanthanum oxide (La 2 O 3 ) and praseodymium oxide (Pr 6 O 11 ).
  • the material of the nonlinear resistor layer 14 includes a perovskite composite oxide.
  • perovskite composite oxide is a new inorganic non-metallic material with unique physical and chemical properties.
  • the A position is generally a rare earth or alkaline earth element ion.
  • the B site is a transition element ion, and both the A site and the B site can be partially replaced by other metal ions with similar radii to keep their crystal structure basically unchanged.
  • the material of the nonlinear resistor layer 14 includes doped strontium titanate (SrTiO 3 ), barium titanate (BaTiO 3 ), and lanthanum manganate (LaMnO 3 ).
  • the material of the varistor layer 14 includes organic polymers.
  • organic polymers refer to macromolecules with multiple repeating monomer units that are covalently bonded by one or several organic molecules or molecular groups.
  • the material of the varistor layer 14 includes polyethyl methacrylate (PEMA), polyazomethine (PAM), polytriphenylamine (PTPA) or poly2,7-( 9,9-dihexylfluorene block suspension copolymer (poly[2,7-(9,9-dihexylfluorene)]-block-polypendentisoindigo, PF 14 -b- Pison ).
  • PEMA polyethyl methacrylate
  • PAM polyazomethine
  • PTPA polytriphenylamine
  • poly2,7-( 9,9-dihexylfluorene block suspension copolymer poly[2,7-(9,9-dihexylfluorene)]-block-polypendentisoindigo, PF 14 -b- Pison ).
  • oxygen vacancy channels or metal ion channels will be formed or cut off when the external voltage changes.
  • oxygen vacancy channels or metal ion channels when the voltage is low, oxygen vacancy channels or metal ion channels will be formed relatively slowly, and the resistance of the nonlinear resistance layer 14 will be relatively large.
  • oxygen vacancy channels or metal ion channels When the voltage is relatively high, oxygen vacancy channels or metal ion channels will form comparison blocks, and the resistance of the nonlinear resistance layer 14 will decrease rapidly.
  • the material of the nonlinear resistor layer 14 has resistive switching characteristics, and the resistance of the nonlinear resistor layer 14 changes as the voltage changes. Furthermore, by selecting a material whose resistive switching characteristic is that the resistance decreases non-linearly as the voltage increases, it can be realized that as the voltage applied to the ferroelectric capacitor C increases, the resistance of the material of the nonlinear resistance layer 14 becomes non-linear. Decrease linearly.
  • the voltage Vcc applied to the ferroelectric capacitor C changes linearly with time.
  • FIG. 11B shows a curve of the voltage on the ferroelectric layer 13 changing with time as the applied voltage Vcc increases.
  • the solid line is the variation curve of the voltage on the ferroelectric layer 13 when the nonlinear resistor layer 14 is not provided.
  • the dotted line is the variation curve of the voltage on the ferroelectric layer 13 after the nonlinear resistor layer 14 is provided. Since at low voltage, the resistance of the nonlinear resistor layer 14 is relatively large and the voltage division ratio is large, therefore the voltage divided by the ferroelectric layer 13 is small. As the voltage increases, the resistance of the nonlinear resistor layer 14 decreases rapidly, and the voltage distributed by the ferroelectric layer 13 suddenly increases. Therefore, the voltage of the ferroelectric layer 13 exhibits nonlinear change characteristics with time.
  • FIG. 11C is a curve of the residual polarization intensity Pr of the ferroelectric layer 13 as a function of time.
  • the solid line is the change curve of the residual polarization intensity Pr when the nonlinear resistor layer 14 is not inserted, and the dotted line is the change curve of the residual polarization intensity Pr after the nonlinear resistor layer 14 is inserted. After the nonlinear resistor layer 14 is inserted, the voltage of the ferroelectric layer 13 changes nonlinearly with time.
  • the polarization charge output of the ferroelectric capacitor C changes nonlinearly with the voltage change.
  • the total voltage is small, the voltage divided by the ferroelectric layer 13 is small, the amount of ferroelectric polarization flip is small, and the output current of the ferroelectric capacitor C is small, which can effectively enhance the anti-interference ability of the memory cell.
  • the resistance of the nonlinear resistor layer 14 suddenly decreases, the voltage divided by the ferroelectric layer 13 suddenly increases, and the output current of the ferroelectric capacitor C suddenly increases, causing the ferroelectric layer 13 to generate sufficient Ferroelectric polarization flip.
  • the nonlinear characteristics of the nonlinear resistor layer 14 can be adjusted by adjusting factors such as the thickness, quantity, and location of the nonlinear resistor layer 14 .
  • Figure 11D is the output characteristic curve of the ferroelectric capacitor C.
  • the solid line indicates that the polarization charge output of the ferroelectric capacitor C changes linearly with the voltage change, and is used as a reference.
  • the double-dotted long-dash line, dotted line, and dotted line indicate that the polarization charge output of the ferroelectric capacitor C changes nonlinearly with the voltage change, and the nonlinear characteristics of the double-dotted long-dash line, dotted line, and dotted line gradually increase to enhance storage The anti-interference ability of the unit.
  • the material of the varistor layer 14 has metal-insulator transition properties.
  • metal-insulator transition refers to the physical transformation from a metal conductor to a non-conductive insulator (or semiconductor). Or the physical transformation from an insulator to a conductor.
  • the material combined with the varistor layer 14 has the characteristic that the resistance decreases nonlinearly as the voltage increases. Therefore, the material of the varistor layer 14 in the embodiment of the present application has the characteristics of being an insulator under low voltage and a metal under high voltage.
  • the material of varistor layer 14 includes a solid electrolyte.
  • solid electrolytes are objects that exhibit ionic conductivity in the solid state (that is, below the melting point).
  • the materials of the varistor layer 14 include sulfides such as germanium sulfide ( Gex S y ), silver sulfide (Ag 2 S), copper sulfide (Cu 2 S), silver iodide (AgI), and rubidium silver iodide (RbAg). 4 I 5 ) and other iodides, selenides such as germanium selenide (Ge x Se y ), germanium telluride (Ge x Te y ), antimony telluride (Sb x Te y ), germanium antimony tellurium alloy (GeSbTe), silver Indium antimony tellurium alloy (AgInSbTe) and other tellurides.
  • sulfides such as germanium sulfide ( Gex S y ), silver sulfide (Ag 2 S), copper sulfide (Cu 2 S), silver iodide (AgI), and rubidium silver iodide (R
  • the Joule heat will also change when the external voltage changes, causing the material of the nonlinear resistor layer 14 to undergo a phase change, realizing the interchangeable transformation of the insulator phase and the metal phase.
  • the material of the nonlinear resistance layer 14 is mainly an insulator phase, and the resistance of the nonlinear resistance layer 14 is large.
  • the voltage is relatively high, Joule heat increases, and the material of the nonlinear resistor layer 14 undergoes a phase change.
  • the nonlinear resistor layer 14 is mainly a metal phase, and the material of the nonlinear resistor layer 14 changes from an insulator phase to a metallic phase. The resistance of the material of the linear resistance layer 14 suddenly decreases.
  • the material of the nonlinear resistor layer 14 has metal-insulator transition characteristics, and the resistance of the material of the nonlinear resistor layer 14 changes as the voltage changes. Furthermore, by selecting a material whose metal-insulator transition characteristics change from an insulator to a metal as the voltage increases, it is possible to achieve a change in the material of the nonlinear resistance layer 14 as the voltage applied to the ferroelectric capacitor C increases. The resistance decreases nonlinearly, and the resistance of the nonlinear resistance layer 14 decreases nonlinearly.
  • the voltage Vcc applied to the ferroelectric capacitor C changes linearly with time.
  • FIG. 12A shows the change curve of the voltage on the ferroelectric layer 13 with time as the applied voltage Vcc increases.
  • the solid line is the variation curve of the voltage on the ferroelectric layer 13 when the nonlinear resistor layer 14 is not provided
  • the dotted line is the variation curve of the voltage on the ferroelectric layer 13 after the nonlinear resistor layer 14 is provided. Since at low voltage, the resistance of the nonlinear resistor layer 14 is relatively large and the voltage division ratio is large, therefore the voltage divided by the ferroelectric layer 13 is small. As the voltage increases, the nonlinear resistor layer 14 undergoes a phase change from an insulator to a metallic phase. The resistance of the nonlinear resistor layer 14 decreases rapidly, and the voltage distributed by the ferroelectric layer 13 suddenly increases. Therefore, the voltage of the ferroelectric layer 13 exhibits nonlinear change characteristics with time.
  • FIG. 12B shows the change curve of the residual polarization intensity Pr of the ferroelectric layer 13 with time.
  • the solid line is the change curve of the residual polarization intensity Pr when the nonlinear resistor layer 14 is not inserted
  • the dotted line is the change curve of the residual polarization intensity Pr after the nonlinear resistor layer 14 is inserted.
  • the voltage of the ferroelectric layer 13 changes nonlinearly with time.
  • the polarization charge output of the ferroelectric capacitor C changes nonlinearly with the voltage change.
  • the total voltage is small, the voltage divided by the ferroelectric layer 13 is small, the amount of ferroelectric polarization flip is small, and the output current of the ferroelectric capacitor C is small, which can effectively enhance the anti-interference ability of the memory cell.
  • the ferroelectric capacitor C further includes at least one third electrode, and the at least one third electrode is disposed between the first electrode 11 and the second electrode 12 .
  • the ferroelectric capacitor C further includes a third electrode 15 .
  • the ferroelectric capacitor C includes two capacitors connected in series.
  • the two poles of one capacitor are the first electrode 11 and the third electrode 15 .
  • the two poles are the capacitors of the first electrode 11 and the third electrode 15 .
  • the two capacitors of another capacitor are the second electrode 12 and the third electrode 15 .
  • the capacitor whose two poles are the second electrode 12 and the third electrode 15 is called an upper capacitor. At least one of the upper capacitor and the lower capacitor is a ferroelectric capacitor.
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are stacked in contact.
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are disposed between the first electrode 11 and the third electrode 15 .
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are both located in the lower capacitor, and the nonlinear resistance layer 14 and the ferroelectric layer 13 are in contact with each other in series.
  • the ferroelectric layer 13 may be disposed close to the first electrode 11 as shown in FIG. 13A , or the nonlinear resistance layer 14 may be disposed close to the first electrode 11 .
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are disposed between the second electrode 12 and the third electrode 15 .
  • a third electrode 15 is provided between the nonlinear resistance layer 14 and the ferroelectric layer 13 .
  • the nonlinear resistance layer 14 is provided between the second electrode 12 and the third electrode 15
  • the ferroelectric layer 13 is provided between the first electrode 11 and the third electrode 15 .
  • the nonlinear resistor layer 14 is disposed in the upper capacitor
  • the ferroelectric layer 13 is disposed in the lower capacitor
  • the nonlinear resistor layer 14 and the ferroelectric layer 13 are connected in series through the third electrode 15 .
  • the nonlinear resistance layer 14 is disposed between the first electrode 11 and the third electrode 15
  • the ferroelectric layer 13 is disposed between the second electrode 12 and the third electrode 15 .
  • the influence of the nonlinear resistance layer 14 on the ferroelectric polarization of the ferroelectric layer 13 can be reduced.
  • FIG. 13A and FIG. 13B only take the ferroelectric capacitor C including a layer of nonlinear resistance layer 14 as an example for illustration.
  • the ferroelectric capacitor C may also include a multi-layer non-linear resistance layer 14.
  • the multi-layer non-linear resistance layer 14 is reasonably arranged according to needs.
  • the multi-layer non-linear resistance layer 14 is located at the first electrode 11 and the second electrode 12. between.
  • the ferroelectric capacitor C further includes a plurality of third electrodes 15 .
  • the ferroelectric capacitor C includes two or more capacitors connected in series.
  • the two poles of one capacitor are the first electrode 11 and the third electrode 15 .
  • the two poles are the first electrode 11 and the third electrode 15 .
  • the capacitance is called lower capacitance.
  • the two poles of a capacitor are the second electrode 12 and the third electrode 15.
  • the capacitor whose two poles are the second electrode 12 and the third electrode 15 is called an upper capacitor.
  • Two third electrodes 15. In the embodiment of the present application, the capacitor whose two poles are both third electrodes 15 is called an intermediate capacitor. At least one of the upper capacitor, at least one intermediate capacitor and the lower capacitor is a ferroelectric capacitor.
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are stacked in contact.
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are located between two third electrodes 15 .
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are located between the first electrode 11 and the third electrode 15 .
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are located between the second electrode 12 and the third electrode 15 .
  • the nonlinear resistance layer 14 can be located on the side of the ferroelectric layer 13 close to the first electrode 11 , or the nonlinear resistance layer 14 can be located on the side of the ferroelectric layer close to the second electrode 12 .
  • the nonlinear resistance layer 14 and the ferroelectric layer 13 are stacked in contact, and the nonlinear resistance layer 14 is provided on both sides of the ferroelectric layer 13 .
  • part of the nonlinear resistance layer 14 and the ferroelectric layer 13 are stacked in contact, and a third electrode 15 is provided between part of the nonlinear resistance layer 14 and the ferroelectric layer 13 .
  • a third electrode 15 is provided between the nonlinear resistance layer 14 and the ferroelectric layer 13 .
  • nonlinear resistance layer 14 and the ferroelectric layer 13 are located in different capacitors.
  • the ferroelectric layer 13 is located between two third electrodes 15 .
  • the ferroelectric layer 13 is located between the first electrode 11 and the third electrode 15 .
  • the ferroelectric layer 13 is located between the second electrode 12 and the third electrode 15 .
  • the positional relationship between the nonlinear resistance layer 14 and the ferroelectric layer 13 illustrated in FIGS. 14A to 14D is only an illustration and does not make any limitation.
  • the three electrodes 15 only need to be disposed between the first electrode 11 and the second electrode 12 .
  • Embodiments of the present application also provide a method for manufacturing a memory array.
  • the method for manufacturing a memory array forms multiple memory cells on a substrate, and each memory cell includes any of the above ferroelectric capacitors C.
  • the ferroelectric capacitor C includes a first electrode 11 and a second electrode 12 , a ferroelectric layer 13 and at least one nonlinear resistance layer 14 disposed between the first electrode 11 and the second electrode 12 .
  • the material of the varistor layer 14 has the characteristic that the resistance decreases nonlinearly as the applied voltage increases.
  • the material of the nonlinear resistance layer 14 is a conductive material with resistive switching characteristics.
  • the material of the varistor layer 14 includes transition metal oxide.
  • the material of the varistor layer 14 includes at least one of Ta 2 O 5 , Nb 2 O 5 , TiO 2 or HfO 2 .
  • the material of the varistor layer 14 includes lanthanide oxide.
  • the materials of the nonlinear resistance layer 14 include La 2 O 3 and Pr 6 O 11 .
  • the material of the nonlinear resistance layer 14 includes a perovskite type composite oxide.
  • the material of the nonlinear resistance layer 14 includes doped SrTiO 3 , BaTiO 3 , and LaMnO 3 .
  • the material of the varistor layer 14 includes an organic polymer.
  • the material of the nonlinear resistance layer 14 includes PEMA, PAM, PTPA or PF 14 -b- Pison .
  • the material of the varistor layer 14 has metal-insulator transition properties.
  • the material of the varistor layer 14 includes a solid electrolyte.
  • the materials of the nonlinear resistance layer 14 include sulfides such as Gex Sy , Ag 2 S, and Cu 2 S, iodides such as AgI, RbAg 4 I 5 , etc., selenides such as Gex Se y , Gex Te y , Sb x Te y , GeSbTe, AgInSbTe and other tellurides.
  • the ferroelectric capacitor C further includes at least one third electrode 15 disposed between the first electrode 11 and the second electrode 12 , and the ferroelectric layer 13 A third electrode 15 is provided between the nonlinear resistor layer 14 and the nonlinear resistor layer 14 .

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Abstract

本申请实施例提供一种存储阵列及其制备方法、存储器、电子设备，涉及半导体存储技术领域，用于提高存储器读写过程中存储单元的抗干扰能力。存储阵列包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电电容器。铁电电容器包括的第一电极和第二电极，以及串联在第一电极和第二电极之间的作为存储介质的氧化铪基铁电层和用于改变铁电层电压的非线性电阻层。其中，非线性电阻层的材料具有随被施加的电压的增大，电阻非线性减小的特性。那么，铁电层相应的就会具有随着铁电电容器被施加的电压的增大，铁电层所得的分压非线性增大的特性，以提高存储单元对小电压的抗干扰能力。

Description

存储阵列及其制备方法、存储器、电子设备 技术领域
本申请涉及半导体存储技术领域，尤其涉及一种存储阵列及其制备方法、存储器、电子设备。
背景技术
存储器是用于储存信息的装置。通常是将信息数字化后再以利用电、磁或光学等方式的媒体加以存储。铁电随机存取存储器(ferroelectric random access memory，FRAM)作为一种新型存储器，较传统的动态随机存取存储器(dynamic random access memory，DRAM)或者闪存等存储器，因同时具有较低的读写电压、低功耗、小的器件尺寸、高的读写速度、良好的循环性能、抗辐照和非易失性等优势，越来越广泛的被利用。
为了增加FRAM的存储容量，现有的FRAM可以采用交叉棒(cross bar)阵列结构。该交叉棒阵列结构如图1所示，具有多条字线(word line，WL)和多条位线(bit line，BL)，通过字线WL和位线BL进行连接从而构成阵列。一条字线WL和一条位线BL交叉位置处设置有一个存储单元，通过WL与BL间的电压调控可以存储单元进行读或写操作。
但是，由于交叉棒阵列结构中每条字线WL和每条位线BL分别连接多个存储单元，这就导致对特定存储单元进行读写的过程中，会对其他存储单元产生干扰，导致其他存储单元的信息难以被读出、甚至丢失。
发明内容
本申请实施例提供一种存储阵列及其制备方法、存储器、电子设备，用于提高存储器读写过程中存储单元的抗干扰能力。
为达到上述目的，本申请采用如下技术方案：
本申请实施例的第一方面，提供一种存储阵列，该存储阵列可以应用于存储器中，存储器例如可以是铁电随机存取存储器(ferroelectric random access memory，FRAM)。存储阵列包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电电容器。铁电电容器包括第一电极和第二电极，以及设置在第一电极和第二电极之间的铁电层，铁电层作为存储介质，铁电层的材料可以包括氧化铪基材料。另外，该铁电电容器还包括设置在第一电极和第二电极之间，且与铁电层平行的至少一层非线性电阻层。也就是说，铁电电容器包括与铁电层串联分压的非线性电阻层。其中，随被施加电压的增大，非线性电阻层的材料电阻非线性减小。那么，随着铁电电容器被施加的电压的增大，非线性电阻层的电阻非线性减小，相应的铁电层所得的分压非线性增大。即，随着铁电电容器被施加的电压的增大，铁电层所得分压先缓慢增大，再快速增大。
本申请实施例提供的存储阵列，通过在铁电电容器中插入与铁电层平行的非线性 电阻层，使得非线性电阻层与铁电层对施加到铁电电容器上的电压进行分压。非线性电阻层的材料具有随被施加电压的增大，电阻非线性减小的特性，使得非线性电阻层的电阻随被施加电压的增大非线性减小。那么将上述非线性电阻层放入铁电电容器中后，随着施加到铁电电容器上的电压的增大，非线性电阻层的电阻非线性减小，非线性电阻层所得的分压非线性减小。对应的，随着施加到铁电电容器上的电压的增大铁电层所得的分压会非线性增大。也就是说，在施加到铁电电容器上的电压较小时，铁电层所得的分压的比例较小。在施加到铁电电容器上的电压较大时，铁电层所得的分压的比例较大。使得铁电电容器的铁电极化翻转也具有随电压变化而非线性变化的特性。即，在铁电电容器上被施加的电压较小(干扰电压)时，铁电层所得的分压的比例较小，铁电电容器的铁电极化翻转量较小，对存储单元的存储状态几乎没有影响。在铁电电容器上被施加的电压较大(读写电压)时，铁电层所得的分压的比例较大，铁电电容器的铁电极化翻转量较大，可正常完成读写操作。这样一来，相当于非线性电阻层的存在可以调控存储单元的电压响应特性，增强存储单元随电压增大时的非线性响应特性，实现抑制铁电电容器在小电压下的铁电极化翻转，从而有效增强存储单元的抗干扰性能。
在一种可能的实现方式中，非线性电阻层的材料为具有阻变特性的导电材料。也就是说，非线性电阻层的材料为导电材料，且非线性电阻层材料的电阻随着电压的变化是可以变化的。这是一种低成本的实现方式。
在一种可能的实现方式中，非线性电阻层的材料具有金属-绝缘体转变特性。也就是说，非线性电阻层的材料能够随着电压的变化由金属材料转变为绝缘材料。这是一种低成本的实现方式。
在一种可能的实现方式中，非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物、固体电解质或者有机聚合物。这是一种可能的实现方式。
在一种可能的实现方式中，非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2、GeSbTe或者AgInSbTe中的至少一种。这是一种可能的实现方式。
在一种可能的实现方式中，铁电层的至少一侧设置有非线性电阻层。这是一种可能的实现方式。
在一种可能的实现方式中，铁电电容器还包括至少一个第三电极，第三电极设置在第一电极和第二电极之间；铁电层和非线性电阻层之间设置有第三电极。通过将铁电层和非线性电阻层间隔设置，可降低非线性电阻层对铁电层铁电极化的影响。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相垂直的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相平行的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，铁电层的材料包括氧化铪基材料。氧化铪基铁电电容器的厚度尺寸可以微缩到十纳米乃至亚十纳米，这样的话，可以实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有较大的优势。另外，氧化铪基铁电电容器的制备工艺可以与硅基半导体工艺具有良好的兼容性，这样可以利用成熟的制造工艺制得该铁电电容器，不会增加制造成本。
本申请实施例的第二方面，提供一种存储阵列。存储阵列包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电电容器。铁电电容器包括第一电极和第二电极，以及设置在第一电极和第二电极之间的铁电层，铁电层作为存储介质，铁电层的材料可以包括氧化铪基材料。另外，该铁电电容器还包括设置在第一电极和第二电极之间，且与铁电层平行的至少一层非线性电阻层。也就是说，铁电电容器包括与铁电层串联分压的非线性电阻层。多个存储单元，设置在衬底上，每个存储单元包括铁电电容器。其中，非线性电阻层的材料为具有阻变特性的导电材料。
本申请实施例提供的存储阵列，通过在铁电电容器中插入与铁电层平行的非线性电阻层，使得非线性电阻层与铁电层对施加到铁电电容器上的电压进行分压。非线性电阻层的材料为具有阻变特性的导电材料，那么，可实现非线性电阻层的电阻随被施加电压的增大非线性减小。那么将上述非线性电阻层放入铁电电容器中后，随着施加到铁电电容器上的电压的增大，非线性电阻层的电阻非线性减小，非线性电阻层所得的分压非线性减小。对应的，随着施加到铁电电容器上的电压的增大铁电层所得的分压会非线性增大。也就是说，在施加到铁电电容器上的电压较小时，铁电层所得的分压的比例较小。在施加到铁电电容器上的电压较大时，铁电层所得的分压的比例较大。使得铁电电容器的铁电极化翻转也具有随电压变化而非线性变化的特性。即，在铁电电容器上被施加的电压较小(干扰电压)时，铁电层所得的分压的比例较小，铁电电容器的铁电极化翻转量较小，对存储单元的存储状态几乎没有影响。在铁电电容器上被施加的电压较大(读写电压)时，铁电层所得的分压的比例较大，铁电电容器的铁电极化翻转量较大，可正常完成读写操作。这样一来，相当于非线性电阻层的存在可以调控存储单元的电压响应特性，增强存储单元随电压增大时的非线性响应特性，实现抑制铁电电容器在小电压下的铁电极化翻转，从而有效增强存储单元的抗干扰性能。
在一种可能的实现方式中，非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物或者有机聚合物。这是一种低成本的实现方式。
在一种可能的实现方式中，非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2中的至少一种。这是一种低成本的实现方式。
在一种可能的实现方式中，铁电电容器还包括至少一个第三电极，第三电极设置在第一电极和第二电极之间；铁电层和非线性电阻层之间设置有第三电极。通过将铁电层和非线性电阻层间隔设置，可降低非线性电阻层对铁电层铁电极化的影响。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相垂直的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相平行的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，铁电层的材料包括氧化铪基材料。氧化铪基铁电电容器的厚度尺寸可以微缩到十纳米乃至亚十纳米，这样的话，可以实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有较大的优势。另外，氧化铪基铁电电容器的制备工艺可以与硅基半导体工艺具有良好的兼容性，这样可以利用成熟的制造工艺制得该铁电电容器，不会增加制造成本。
本申请实施例的第三方面，提供一种存储阵列。存储阵列包括：衬底和形成在衬底上的多个存储单元，每个存储单元包括铁电电容器。铁电电容器包括设置的第一电极和第二电极，以及设置在第一电极和第二电极之间的铁电层，铁电层作为存储介质，铁电层的材料可以包括氧化铪基材料。另外，该铁电电容器还包括设置在第一电极和第二电极之间，且与铁电层平行的至少一层非线性电阻层。也就是说，铁电电容器包括与铁电层串联分压的非线性电阻层。多个存储单元，设置在衬底上，每个存储单元包括铁电电容器。其中，非线性电阻层的材料具有金属-绝缘体转变特性。
本申请实施例提供的存储阵列，通过在铁电电容器中插入与铁电层平行的非线性电阻层，使得非线性电阻层与铁电层对施加到铁电电容器上的电压进行分压。非线性电阻层的材料金属-绝缘体转变特性，那么，可实现非线性电阻层的电阻随被施加电压的增大非线性减小。那么将上述非线性电阻层放入铁电电容器中后，随着施加到铁电电容器上的电压的增大，非线性电阻层的电阻非线性减小，非线性电阻层所得的分压非线性减小。对应的，随着施加到铁电电容器上的电压的增大铁电层所得的分压会非线性增大。也就是说，在施加到铁电电容器上的电压较小时，铁电层所得的分压的比例较小。在施加到铁电电容器上的电压较大时，铁电层所得的分压的比例较大。使得铁电电容器的铁电极化翻转也具有随电压变化而非线性变化的特性。即，在铁电电容器上被施加的电压较小(干扰电压)时，铁电层所得的分压的比例较小，铁电电容器的铁电极化翻转量较小，对存储单元的存储状态几乎没有影响。在铁电电容器上被施加的电压较大(读写电压)时，铁电层所得的分压的比例较大，铁电电容器的铁电极化翻转量较大，可正常完成读写操作。这样一来，相当于非线性电阻层的存在可以调控存储单元的电压响应特性，增强存储单元随电压增大时的非线性响应特性，实现抑制铁电电容器在小电压下的铁电极化翻转，从而有效增强存储单元的抗干扰性能。
在一种可能的实现方式中，非线性电阻层的材料包括固体电解质。这是一种低成本的实现方式。
在一种可能的实现方式中，非线性电阻层的材料包括GeSbTe或者AgInSbTe中的至少一种。这是一种低成本的实现方式。
在一种可能的实现方式中，铁电电容器还包括至少一个第三电极，第三电极设置在第一电极和第二电极之间；铁电层和非线性电阻层之间设置有第三电极。通过将铁电层和非线性电阻层间隔设置，可降低非线性电阻层对铁电层铁电极化的影响。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相垂直的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，第一电极和第二电极沿与衬底相平行的方向设置。这是一种可能的实现方式。
在一种可能的实现方式中，铁电层的材料包括氧化铪基材料。氧化铪基铁电电容器的厚度尺寸可以微缩到十纳米乃至亚十纳米，这样的话，可以实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有较大的优势。另外，氧化铪基铁电电容器的制备工艺可以与硅基半导体工艺具有良好的兼容性，这样可以利用成熟的制造工艺制得该铁电电容器，不会增加制造成本。
本申请实施例的第四方面，提供一种存储器，包括：控制器；和第一方面、第二 方面、第三方面任一项的存储阵列；控制器与存储阵列电连接。本申请实施例提供的存储器包括第一方面、第二方面或第三方面的存储阵列，其有益效果与存储阵列的有益效果相同，此处不再赘述。
本申请实施例的第五方面，提供一种电子设备，包括：电路板；和如第四方面的存储器；电路板和存储器电连接。
本申请实施例的第六方面，提供一种存储阵列的制备方法，包括：在衬底上形成多个存储单元，每个存储单元包括铁电电容器；其中，铁电电容器包括第一电极和第二电极，以及设置在第一电极和第二电极之间的铁电层和至少一层非线性电阻层；非线性电阻层的材料随被施加电压的增大，电阻非线性减小。
本申请实施例提供的存储阵列的制备方法用于制备第一方面的存储阵列，其有益效果与存储阵列的有益效果相同，此处不再赘述。
在一种可能的实现方式中，非线性电阻层的材料为具有阻变特性的导电材料。
在一种可能的实现方式中，非线性电阻层的材料具有金属-绝缘体转变特性。
在一种可能的实现方式中，非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物、固体电解质或者有机聚合物。
在一种可能的实现方式中，非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2、GeSbTe或者AgInSbTe中的至少一种。
在一种可能的实现方式中，铁电电容器还包括至少一个第三电极，第三电极设置在第一电极和第二电极之间；铁电层和非线性电阻层之间设置有第三电极。
本申请实施例的第七方面，提供一种存储阵列的制备方法，用于制备第二方面或者第三方面的存储阵列。
附图说明
图1为相关技术提供的一种存储器的交叉棒阵列结构排布方式；
图2为本申请实施例提供的一种电子设备中的电路图；
图3为本申请实施例提供的一种存储器的电路图；
图4为本申请实施例提供的一种存储阵列中一个存储单元的电路图；
图5为本申请实施例提供的一种存储阵列的电路图；
图6为本申请实施例提供的另一种存储阵列中一个存储单元的电路图；
图7为本申请实施例提供的另一种存储阵列的电路图；
图8A为本申请实施例提供的一种铁电电容器与衬底的位置关系图；
图8B为本申请实施例提供的另一种铁电电容器与衬底的位置关系图；
图8C为本申请实施例提供的一种铁电电容器的俯视示意图；
图9A-图9E为本申请实施例提供的一种铁电电容器的结构示意图；
图10A为本申请实施例示意的一种存储单元的电学特性曲线；
图10B为本申请实施例提供的一种存储单元在施加正电场时的电学特性曲线；
图11A为本申请实施例提供的一种电压随时间变化的曲线；
图11B为本申请实施例提供的一种随着电压的变化铁电层上所得分压的曲线；
图11C为本申请实施例提供的一种随着电压的变化存储单元的剩余极化强度曲线；
图11D为本申请实施例提供的一种存储单元的极化电荷随电压变化的曲线；
图12A为本申请实施例提供的另一种随着电压的变化铁电层上所得分压的曲线；
图12B为本申请实施例提供的另一种随着电压的变化存储单元的剩余极化强度曲线；
图12C为本申请实施例提供的另一种存储单元的极化电荷随电压变化的曲线；
图13A-图14D为本申请实施例提供的另一种铁电电容器的结构示意图。
附图标记：
200-电子设备；210-片上系统；211-应用处理器；212-图像处理单元；213-随机存取存储器；220-只读存储器；230-通信芯片；240-电源管理芯片；250-总线；300-存储器；310-存储阵列；320-译码器；330-驱动器；340-时序控制器；350-缓存器；360-输入输出驱动；400-存储单元；401-存储单元；402-存储单元；403-存储单元；404-存储单元；11-第一电极；12-第二电极；13-铁电层；14-非线性电阻层；15-第三电极；100-衬底。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第二”、“第一”等仅用于描述方便，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第二”、“第一”等的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
此外，本申请实施例中，“上”、“下”、“左”、“右”等方位术语可以包括但不限于相对附图中的部件示意置放的方位来定义的，应当理解到，这些方向性术语可以是相对的概念，它们用于相对于的描述和澄清，其可以根据附图中部件附图所放置的方位的变化而相应地发生变化。
在本申请实施例中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“相耦接”可以是直接的电性连接，也可以通过中间媒介间接的电性连接。术语“接触”可以是直接接触，也可以是通过中间媒介间接的接触。
本申请实施例中，“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。
在介绍本申请所涉及的实施例之前，先介绍本申请涉及的技术术语，具体如下：
铁电材料：其可通过施加电场排列内部电偶极矩而保持自发极化，即使撤去外部施加电场时亦然。换句话说，铁电体是如下的材料：其中极化强度(极化)值(或电场)半永久地保留在其中，即使在施加恒定的电压并且使电压恢复到零伏之后亦然。
晶胞：是由大量微观物质单位(原子、离子、分子等)按一定规则有序排列的结 构。
铁电相晶体：晶胞的结构使正负电荷中心不重合而出现电偶极矩，产生不等于零的电极化强度，使晶体具有自发极化，且电偶极矩方向可以因外电场而改变，呈现出类似于铁磁体的特点。
存储器按照易失性来分类，可分为易失性(volatile)存储器(又称内存)和非易失性(non-volatile)存储器(又称外存)。易失性存储器是指当电流中断后，所存储的信息便会消失的存储器，例如常见的动态随机存取存储器(Dynamic Random Access Memory，DRAM)，静态随机存取存储器(Static Random Access Memory，SRAM)等。上述DRAM和SRAM的区别在于，DRAM需要周期性充电，而SRAM只需要保持通电，无需周期性更新。非易失性存储器指当电流中断后，所存储的信息不会消失的存储器，例如各种类型的只读存储器(Read-Only Memory，ROM)，新型存储器例如磁性随机存取内存(Magnetic Random Access Memory，MRAM)或铁电随机存取内存(Ferroelectric Random Access Memory，FRAM)等。
铁电随机存取存储器(ferroelectric random access memory，FRAM)是基于铁电材料的铁电效应来存储数据。铁电存储器因其具有超高的存储密度、低功耗、小尺寸、较低的读写电压、较高的读写速度和良好的循环性能，且有抗辐照和非易失性等优势，有望成为替代动态随机存取存储器(dynamic random access memory，DRAM)的主要竞争者。铁电存储器中的存储单元包含晶体管和铁电电容器，铁电电容器基于铁电效应存储信息。铁电电容器包括两个电极，以及设置于两个电极之间的铁电材料，例如铁电层。由于铁电材料的非线性特性，铁电材料的介电常数不仅可以调节，而且在铁电膜层极化状态翻转前后的差值非常大，这使得铁电电容器与其他电容相比体积较小，比如，比DRAM中的用于存储电荷的电容体积小很多。
在铁电存储器中，铁电层可以采用常见的铁电材料形成。经过结晶处理，在铁电层中可形成铁电相晶体结构。当一个电场被施加到存储单元的铁电层时，中心原子顺着电场停在低能量状态，反之，当电场反转被施加到该铁电层时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态。大量中心原子在晶体单胞中移动耦合形成铁电畴(ferroelectric domains)，铁电畴在电场作用下形成极化电荷。铁电畴在电场下反转所形成的极化电荷较高，铁电畴在电场下无反转所形成的极化电荷较低，这种铁电材料的二元稳定状态使得铁电可以作为存储器。
本申请实施例提供一种包含存储器的电子设备，存储器例如可以是铁电存储器。图2为本申请实施例提供的一种电子设备200，该电子设备200可以是终端设备，例如手机，平板电脑，智能手环，也可以是个人电脑(personal computer，PC)、服务器、工作站等。电子设备200包括总线250，以及与总线250连接的片上系统(system on chip，SOC)210和只读存储器(read-only memory，ROM)220。SOC210可以用于处理数据，例如处理应用程序的数据，处理图像数据，以及缓存临时数据。ROM220可以用于保存非易失性数据，例如音频文件、视频文件等。ROM220可以为PROM(programmable read-only memory，可编程序只读存储器)，EPROM(erasable programmable read-only memory，可擦除可编程只读存储器)，闪存(flash memory)等。
此外，电子设备200还可以包括通信芯片230和电源管理芯片240。通信芯片230可以用于协议栈的处理，或对模拟射频信号进行放大、滤波等处理，或同时实现上述功能。电源管理芯片240可以用于对其他芯片进行供电。
在一种实施方式中，SOC210可以包括用于处理应用程序的应用处理器(application processor，AP)211，用于处理图像数据的图像处理单元(graphics processing unit，GPU)212，以及用于缓存数据的随机存取存储器(random access memory，RAM)213。
上述AP211、GPU212和RAM213可以被集成于一个裸片(die)中，或者分别集成于多个裸片(die)中，并被封装在一个封装结构中。例如采用2.5D(dimension)、3D封装、或其他的先进封装技术。
在一种实施方式中，上述AP211和GPU212被集成于一个die中，RAM213被集成于另一个die中，这两个die被封装在一个封装结构中，以此获得更快的die间数据传输速和更高的数据传输带宽。
图3为本申请实施例提供的一种存储器300的结构示意图。存储器300例如可以是铁电存储器。该存储器300可以是如图2所示的RAM213，属于FRAM。在一种实施方式中，存储器300也可以是设置于SOC210外部的RAM。本申请不对存储器300在设备中的位置以及与SOC210的位置关系进行限定。
当然，本申请实施例提供的存储器300也可以不组装在电子设备中，存储器300直接作为一个单品存在。示例的，存储器为固态硬盘(solid state disk，SSD)或者磁性随机存储器(magnetoresistive random access memory，MRAM)。
继续如图3，存储器300包括存储阵列310和控制器，控制器与存储阵列电连接，用于控制存储阵列中存储单元的读写。控制器可以包括控制读写时序的逻辑，控制器也可以包括模拟电路部分(例如灵敏放大器)。示例的，控制器例如可以包括译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360中的至少一种。
需要指出的是，存储阵列310可以独立的集成在一个芯片(或者裸芯片)中，控制器独立的集成在一个芯片中，将存储阵列芯片和控制器芯片进行整合互联，形成上述存储器。存储阵列310也可以和控制器集成在同一个芯片中。
继续参考图3，存储阵列310包括多个呈阵列排列的存储单元400，其中每个存储单元400可以用于存储1bit或者多bit的数据。存储阵列310还包括字线(word line，WL)、位线(bit line，BL)等信号线。每一个存储单元400都与对应的字线WL、位线BL电连接。上述字线WL、位线BL中的一个或多个用于通过接收控制电路输出的控制电平，选择存储阵列中待读写的存储单元400，以改变存储单元400中的铁电电容器的极化方向，从而实现数据的读写操作。
在图3所示存储器300结构中，译码器320用于根据接收到的地址进行译码，以确定需要访问的存储单元400。驱动器330用于根据译码器320产生的译码结果来控制信号线的电平，从而实现对指定存储单元400的访问。缓存器350用于将读取的数据进行缓存，例如可以采用先入先出(first-in first-out，FIFO)来进行缓存。时序控制器340用于控制缓存器350的时序，以及控制驱动器330驱动存储阵列310中的信 号线。输入输出驱动360用于驱动传输信号，例如驱动接收的数据信号和驱动需要发送的数据信号，使得数据信号可以被远距离传输。
上述存储阵列310、译码器320、驱动器330、时序控制器340、缓存器350和输入输出驱动360可以集成于一个芯片中，也可以分别集成于多个芯片中。
本申请涉及的存储器300可以是铁电随机存取存储器(ferroelectric random access memory，FRAM)，也可以是铁电场效应晶体管(ferroelectric filed-effect-transistor，FeFET)存储器。
比如，图4给出了FRAM的其中一个存储单元400的电路结构图，如图4所示，该存储单元400包括至少一个铁电电容器(图4示例的示意出铁电电容器C1、铁电电容器C2和铁电电容器C3)和一个晶体管Tr，这样的存储单元400可以被称为1TnC存储单元。在存储单元400包括一个铁电电容器和一个晶体管Tr的情况下，存储单元400可以被称为1T1C存储单元。
这里的晶体管Tr可以是金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor，MOSFET)。
另外，该存储单元400还包括字线(word line，WL)、位线(bit line，BL)和板线(plate line，PL)，并且在该存储单元400中，晶体管Tr的第一端与位线BL电连接，晶体管Tr的控制端与字线WL电连接，晶体管Tr的第二端与电容器C的一端电连接，电容器C的另一端与板线PL电连接。
在本申请中，晶体管Tr的漏极(drain)或源极(source)中的一极称为第一端，相应的另一极称为第二端，晶体管Tr的控制端为栅极。晶体管Tr的漏极和源极可以根据电流的流向而确定，比如，在图4中，电流从左至右时，则左端为漏极，右端为源极，相反的，当电流从右向左时，右端为漏极，左端为源极。
可以这样理解，这里的晶体管Tr是一种具有三端子的晶体管器件，那么，该晶体管Tr可以选择NMOS(N-channel metal oxide semiconductor，N沟道金属氧化物半导体)管，或者可以选择PMOS(P-channel metal oxide semiconductor，P沟道金属氧化物半导体)管。
图4示出的一个存储单元400可以用于存储多bit的数据，以提升每一个存储单元的存储容量。尤其是，铁电电容器C1、铁电电容器C2和铁电电容器C3共用一个晶体管Tr，进而，还可以减少每个存储单元400的晶体管的数量，以提升存储密度。
将上述图4所示的存储单元400按照阵列排布就可以得到存储阵列310，其中每个存储单元400的电路结构相同。比如，图5示出的存储阵列310中，示例性的给出了包括存储单元401、存储单元402、存储单元403和存储单元404的四个存储单元的存储阵列。本领域技术人员可以根据存储器300的存储容量需求设计存储阵列310中存储单元400的排列方式和存储单元400的个数。
在一种实施方式中，存储阵列310还可以包括更多的存储单元400，且这些存储单元400可以在彼此相互垂直的X方向、Y方向和Z方向上排列，以形成三维存储阵列。
在一种可选择的实施方式中，图5所示的存储阵列310中，字线WL沿X方向 延伸，进而，沿X方向排布的多个存储单元的晶体管Tr的控制端与同一字线WL电连接。还有，位线BL沿与X方向相垂直的Y方向延伸。如此的话，沿Y方向排布的多个存储单元的晶体管Tr的第一端与同一位线BL电连接。
图6给出了FRAM的另一种存储单元400的电路结构图。在该存储单元400中，包含第一晶体管Tr1和第二晶体管Tr2，以及多个铁电电容器(图6示例的示意出铁电电容器C1和铁电电容器C2)，这样的存储单元可以被称为2TnC存储单元。铁电电容器C2和铁电电容器C1的结构相同，均包括两个电极和位于两个电极之间的铁电层，为了便于下述将铁电电容器C2和铁电电容器C1与其他结构之间的电连接关系描述清楚，可以将铁电电容器C1的一个电极叫第一电极，另一个电极叫第二电极，铁电电容器C2的一个电极叫第三电极，另一个电极叫第四电极。
再结合图6，该存储单元400还包括字线(word line，WL)、写位线(write bit line，WBL)、读位线(read bit line，RBL)、源线(source line，SL)和控制线(control line，CL)。其中，第一晶体管Tr1的控制端与控制线CL电连接，第一晶体管Tr1的第一端分别与铁电电容器C1的第一电极和铁电电容器C2的第三电极电连接，第一晶体管Tr1的第二端与写位线WBL电连接，铁电电容器C1的第二电极和铁电电容器C2的第四电极与相对应的字线WL电连接。
再如图6，第二晶体管Tr2的第一端与源线SL电连接，第二端与读位线RBL电连接，第二晶体管T2的控制端分别与铁电电容器C1的第一极和铁电电容器C2的第三极电连接。
在一种可选择的实施方式中，将上述图6所示的存储单元400按照阵列排布就可以得到图7所示的存储阵列310。
比如，图7示出的存储阵列310中，示例性的给出了包括存储单元401、存储单元402、存储单元403和存储单元404的四个存储单元的存储阵列。
在图7给出的存储阵列310中，包括了两条控制线，分别为控制线CL0和控制线CL1，并且每一条控制线沿Y方向延伸，当存储阵列310还包括更多的存储单元时，那么，会相对应的还包括更多的控制线CL，这些控制线沿与Y方向垂直的X方向并行布设，还有，沿Y方向布设的多个存储单元可以共用一条控制线，比如，存储单元401和存储单元404共用选中控制线CL0，存储单元402和存储单元403共用控制线CL1。
继续结合图7，该存储阵列310包括了两条写位线，分别为写位线WBL0和写位线WBL1，并且每一条写位线沿X方向延伸，当还包括更多的写位线WBL，这些写位线WBL沿与X方向垂直的Y方向并行布设，还有，沿X方向布设的多个存储单元可以共用一条写位线WBL，比如，存储单元401和存储单元402共用写位线WBL1，存储单元403和存储单元404共用写位线WBL0。
同样的，读位线RBL和写位线WBL的设置方式相同，在此不再赘述。
需要注意的是，关于该存储阵列中的源线SL，不仅沿X方向布设的多个存储单元的源线SL共用，而且沿Y方向布设的多个存储单元的源线SL也共用，比如，这里的存储单元401的源线SL和存储单元404的源线SL共用，存储单元401的源线SL和存储单元402的源线SL也共用，即这里的存储单元401、存储单元402、存储 单元403和存储单元404的源线SL相互连接。在可实现的工艺结构中，可以形成与衬底相平行的源线SL层结构，以将与衬底相平行的源线相互电连接。
还有，需要注意的是，关于该存储阵列中的字线WL，不仅沿X方向布设的多个存储单元的字线WL共用，而且沿Y方向布设的多个存储单元的字线WL也共用，比如，这里的存储单元401的铁电电容器C0连接的字线WL0和存储单元402的铁电电容器C0连接的字线WL0共用，存储单元401的铁电电容器C0连接的字线WL0和存储单元404的铁电电容器C0连接的字线WL0也共用，即这里的存储单元401、存储单元402、存储单元403和存储单元404的四个铁电电容器C0的字线WL0相互连接，存储单元401、存储单元402、存储单元403和存储单元404的四个铁电电容器C1的WL1相互连接。同理的，在可实现的工艺结构中，可以设置与衬底相平行的字线层结构，以将位于同一层的字线相互连接。
在上述图4、图5、图6和图7示出的存储阵列的存储单元400中，铁电电容器结构可以包括第一电极和第二电极，以及形成在第一电极和第二电极之间的铁电层。或者理解为，铁电电容器为金属-铁电-金属(metal-ferroelectric-metal，MFM)结构。
由于与传统铁电材料相比，包括氧化铪基材料的铁电层构成的氧化铪基铁电存储阵列的厚度可缩小至十纳米乃至亚十纳米，可实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有其独特的优势。此外，氧化铪基铁电存储阵列制备工艺还与成熟的硅基半导体工艺具有良好的兼容性。因此，氧化铪基铁电存储阵列有望成为未来新型铁电存储阵列的核心单元。
目前，约束氧化铪基铁电存储阵列应用于商业存储阵列的最大问题之一是氧化铪基铁电存储阵列的抗干扰性能(disturbance)。在氧化铪基铁电存储芯片中，如果采用交叉阵列结构(cross bar)，多个氧化铪基存储单元通过字线WL和位线BL进行连接从而构成阵列。当存储芯片需要读取或写入数据时，需要通过对某一字线WL和位线BL施加电压，从而实现对特定氧化铪基存储单元的选择与读写。由于存储芯片中字线WL和位线BL不是完全独立的，在某一字线WL或位线BL所加的电压会对附近线路上的氧化铪基存储单元形成干扰，导致相关氧化铪基铁电粗出单元在扰动电压下发生铁电极化翻转，使其存储的信息难以被读出、甚至丢失。因此，如何增强氧化铪基存储单元在读写过程中的抗干扰能力是当前亟需解决的问题之一。
相关技术中，解决氧化铪基存储单元在存储芯片的读写操作中所面临的干扰问题的方案是：通过优化读写操作的脉冲参数和时序逻辑来减小读写脉冲对非目标器件的干扰。
例如，在施加操作电压Vcc对目标存储单元进行选择与读写时，对非目标存储单元施加1/3Vcc电压，从而抑制目标存储单元所在线路的电压对非目标存储单元的干扰。
示例的，在每个时钟周期内当目标存储单元的字线WL施加电压Vcc时，对非目标存储单元所在的字线WL和位线BL分别施加1/3Vcc和2/3Vcc电压。当目标存储单元的位线BL施加Vcc时，对非目标存储单元所在的字线WL和位线BL分别施加2/3Vcc和1/3Vcc电压。由于字线WL和位线BL的相对电位交替变化，其扰动电压将引起不同方向的铁电极化翻转，由此驱动非目标存储单元的铁电极化强度在不同 时钟周期内或增强或减小，经过多个时钟周期后保持不变，从而减小非目标存储单元存储信息的损失。
上述方案主要从电路层面增强存储单元的抗干扰能力，对存储单元本身的抗干扰性能有一定的要求。如果存储单元本身抗干扰性能很差则无法使用。此外由于在读写操作过程中对非目标存储单元施加电压，可能导致非目标存储单元受到不必要的电场压力，使其耐久性能下降。
基于此，本申请实施例还提供一种存储阵列，通过改变存储阵列中铁电电容器的结构，抑制存储单元在低电场下的铁电极化翻转，从而增强存储单元本身的抗干扰性能。
如图8A所示，存储阵列包括衬底100和设置在衬底100上的存储单元400。存储阵列中包括多个存储单元400，图8A中仅是以一个存储单元400为例进行示意。
其中，存储单元400包括晶体管和铁电电容器C，为了便于说明，图8A中仅示意出铁电电容器C的结构。
铁电电容器C包括第一电极11和第二电极12，和形成在第一电极11和第二电极12之间的铁电层13。铁电电容器C还包括至少一层非线性电阻层14(图8A中以一层非线性电阻层14为例进行示意)。并且，至少一层非线性电阻层14和铁电层13设置在第一电极11和第二电极12之间。
其中，第一电极11和第二电极12沿垂直于第二电极12厚度的方向排布，第一电极11垂直于厚度的表面和第二电极12垂直于厚度的表面相对设置，第一电极11和第二电极12限定出一个间隙空间，非线性电阻层14和铁电层13设置在第一电极11和第二电极12之间的间隙空间内。或者理解为，第一电极11和第二电极12层叠设置，铁电层13和非线性电阻层14层叠设置在第一电极11和第二电极12之间。
在一些实施例中，如图8A所示，第一电极11和第二电极12的厚度方向垂直于衬底100，铁电电容器C中第一电极11和第二电极12沿与衬底100相垂直的方向设置。
也就是说，第一电极11、第二电极12、铁电层13、至少一层非线性电阻层14以及至少一个第三电极15中的每一层结构均与衬底100相平行布设，这样的铁电电容器C可以被称为平面铁电电容结构。
在另一些实施例中，如图8B所示，第一电极11和第二电极12的厚度方向平行于衬底100，第一电极11和第二电极12沿与衬底100相平行的方向设置。
这样的铁电电容器C可以被称为垂直铁电电容结构。采用垂直电容结构时，可以实现三维层叠，以提升存储密度，提升存储容量。
图8B给出了垂直铁电电容结构中的其中一种可实现结构，且图8C是图8B中的俯视图。
具体的，第一电极11沿与衬底100相垂直的方向延伸，铁电层13、至少一层非线性电阻层14、至少一个第三电极15和第二电12沿与衬底100相平行的方向依次环绕在第一电极11的外围。这样形成了呈柱形结构的铁电电容器C。
其中，呈柱形结构的铁电电容器C的横断面可以是图8C所示圆形，或者可以是矩形，又或者可以是其他形状。
在一些实施方式中，上述第一电极11和第二电极12可以采用含金属的材料制得。
例如，第一电极11和第二电极12的材料包括金属、金属氮化物、金属碳化物、导电金属氮化物、导电金属氧化物或它们的组合。
示例的，第一电极11的材料可以包括钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、钨(W)、氮化钨(WN)、钌(Ru)、铱(Ir)、氧化钌(RuO 2)、氧化铱(IrO 2)、氮化铌(NbN)、氮化钼(MoN)或它们的组合。
第二电极12的材料可以包括例如钛(Ti)、氮化钛(TiN)、氮化钽(TaN)、碳氮化钛(TiCN)、碳氮化钽(TaCN)、钨(W)、氮化钨(WN)、钌(Ru)、铱(Ir)、氧化钌(RuO 2)、氮化铌(NbN)、氮化钼(MoN)、氧化铱(IrO 2)、硅(Si)、锗(Ge)、锗硅(SiGe)或它们的组合。
其中，第一电极11和第二电极12的材料可以是相同的，也可以是不同的。
在一些实施例中，第一电极11和第二电极12的沿层叠方向的厚度可为但不限于1nm至100nm。以及，第一电极11的厚度和第二电极12的厚度可以相等，也可以不相等。
上述铁电层13具有铁电性，从而，其在一定的温度范围内具有自发极化，而且其自发极化方向可以因外电场方向的反向而反向。这样的话，当其极化取向发生翻转时，会使得铁电电容器C发生充放电，进而能够被外电路所识别，实现“0”或“1”存储状态。
在一些实施例中，铁电层13采用氧化铪基材料制得。相比采用其他铁电材料，氧化铪基铁电电容器C的厚度尺寸可以微缩到十纳米乃至亚十纳米，这样的话，可以实现高密度集成乃至三维集成，在构建超高密度存储芯片方面具有较大的优势。另外，氧化铪基铁电电容器C的制备工艺可以与硅基半导体工艺具有良好的兼容性，
这样可以利用成熟的制造工艺制得该铁电电容器C，不会增加制造成本。
示例的，上述氧化铪基材料可以是基于氧化铪(hafnium oxide，HfO)材料体系的、具有铁电性的材料。比如，铁电层13的材料可以是锆(Zr)掺杂的二氧化铪(HfO 2)、硅(Si)掺杂的HfO 2、铝(Al)掺杂的HfO 2、镧(La)掺杂的HfO 2、钇(Y)掺杂的HfO 2、钆(Gd)掺杂的HfO 2、锶(Sr)掺杂的HfO 2等。
或者，上述氧化铪基材料也可以是铪锆氧(hafnium zirconium oxide，HZO)材料体系的、具有铁电性的材料。比如，铁电层13的材料可以是镧(La)掺杂的HZO、钇(Y)掺杂的HZO、锶(Sr)掺杂的HZO、钆(Gd)掺杂的HZO、钆镧(Gd/La)共掺杂的HZO等。掺杂元素还可以是氮、铁、镥、镨、锗、钪、铈、钕、镁、钡、铟、镓、钙、碳中的一种或多种。
或者，上述氧化铪基材料也可以是铪硅氧、铪铝氧、铪镧氧、铪锆镧氧、铪锆铈氧、铪锆钇氧、铪锆钆氧等材料体系的，具有铁电性的材料。
在一些场景中，可以选择氮化钛TiN制得第一电极11和第二电12，采用锆(Zr)掺杂的二氧化铪(HZO)制得铁电层13，从而充分利用HZO层提供拉应力有利于形成铁电相的特性，以及TiN材料可以与半导体CMOS工艺相兼容的特性。
在一些实施例中，可以选择氮化钛(TiN)制得第一电极11和第二电极12，采 用锆(Zr)掺杂的二氧化铪(HZO)制得铁电层13，从而充分利用HZO层提供拉应力有利于形成铁电相的特性，以及TiN材料可以与半导体CMOS工艺相兼容的特性。
另外，铁电层13沿层叠方向的厚度可以为但不限于为1nm至100nm。
其中，铁电层13中形成有处于铁电相的晶体，当一个电场被施加到铁电层13时，晶体的中心原子顺着电场停在低能量状态，当电场反转被施加到该铁电层时，中心原子顺着电场的方向在晶体里移动并停在另一低能量状态。大量中心原子在晶体单胞中移动耦合形成铁电畴(ferroelectric domains)，铁电畴在电场作用下形成极化电荷，铁电畴在电场下反转前后所形成的极化电荷能量高低不同，这种二元稳定状态，会使得铁电电容器C发生充放电，进而能够被外电路所识别，实现“0”或“1”存储状态。
关于非线性电阻层14，在一种可能的实现方式中，如图9A所示，铁电层13的至少一侧设置有非线性电阻层14。
在一些实施例中，如图9A所示，铁电电容器C包括一层非线性电阻层14，铁电层13的一侧设置有非线性电阻层14。
那么，示例的，如图9A所示，非线性电阻层14设置在铁电层13和第一电极11之间。
或者，示例的，如图9B所示，非线性电阻层14设置在铁电层13和第二电极12之间。
在另一些实施例中，如图9C所示，铁电电容器C包括多层非线性电阻层14，铁电层13的至少一侧设置有非线性电阻层14。
那么，示例的，如图9C所示，铁电层13与第一电极11之间设置有至少一层非线性电阻层14，铁电层13和第二电极12之间也设置有至少一层非线性电阻层14。
或者，示例的，如图9D所示，多层非线性电阻层14设置在铁电层13和第一电极11之间。
或者，示例的，如图9E所示，多层非线性电阻层14设置在铁电层13和第二电极12之间。
其中，非线性电阻层14的材料具有随着被施加的电压的增大，非线性电阻层14的材料的电阻非线性减小的特性。
也就是说，在向由上述具有随着被施加的电压的增大，电阻非线性减小特性的材料构成的非线性电阻层14的两端施加电压时，非线性电阻层14中材料的电阻非线性减小，非线性电阻层14的电阻非线性减小。
通过图4和图6的描述可知，铁电电容器C的第一电极11和第二电极12作为电压接收端，接收信号线(例如位线BL和板线PL，或者，字线WL和写位线
WBL)施加的电压。那么，非线性电阻层14的材料特性使得非线性电阻层14具有随着铁电电容器C被施加的电压的增大，非线性电阻层14的电阻非线性减小的特性。或者理解为，随着铁电电容器C被施加的电压的增大，非线性电阻层14的电阻曲线的斜非线性增大。
此处，非线性减小，可以理解为，铁电电容器C被施加的电压呈线性增大，但 是非线性电阻层14的电阻先缓慢减小，再快速减小。也就是说，非线性电阻层14的电阻随被施加电压的增大表现出非线性变化。当被施加电压较小时，非线性电阻层14的电阻较大，当被施加的电压较大时，非线性电阻层14的电阻迅速减小。
示例的，在铁电电容器C被施加的电压在1/2Vcc以内的情况下，非线性电阻层14的电阻几乎不减小。在铁电电容器C被施加的电压大于1/2Vcc以后，非线性电阻层14的电阻快速减小。其中，Vcc为读写操作所施加的电压。
请参考图9E，铁电层13和非线性电阻层14平行层叠设置，那么，铁电层13和非线性电阻层14属于串联关系，铁电层13和非线性电阻层14可以等效为串联的两个电阻。
基于此，对于未被选中的存储单元而言，由于受到被选中的存储单元的干扰，该未被选中的存储单元中的铁电电容器C会被施加一个小于Vcc的电压(例如小于1/3Vcc)。在这种情况下，非线性电阻层14的电阻较大，铁电层13和非线性电阻层14对1/3Vcc分压后，铁电层13上施加的电压明显减小。而在低电压下，铁电电容器C输出的极化电荷几乎为零。因此，这个“小于Vcc的电压”的扰动，对存储单元的存储状态几乎没有影响，存储单元的抗干扰性能得到增强。而在下一时刻，上述未被选中的存储单元被选中后，该存储单元中的铁电电容器C会被施加Vcc电压。在这种情况下，非线性电阻层14的迅速减小，几乎可以忽略。铁电层13和非线性电阻层14对Vcc分压后，铁电层13上施加的电压几乎等于Vcc。在高电压下，铁电电容器C输出极化电荷。
其中，图10A为不包括非线性电阻层14(典型的)的氧化铪基存储单元的电学特性曲线。其中，横坐标为电压V，纵坐标为剩余极化强度Pr。当施加正电场时，存储单元沿正电场方向的极化强度随着正电场的增强先缓慢增加，然后迅速上升，最后缓慢饱和。当施加负电场时，存储单元沿负电场方向的极化强度随着负电场的增强先缓慢增加，然后迅速上升，最后缓慢饱和。
图10B为包括非线性电阻层14的氧化铪基存储单元，在施加正电场时的电学特性与其抗干扰性能的关系，负电场下与正电场类似。图10B中实线为不包括非线性电阻层14(典型的)的氧化铪基存储单元的电学输出特性，图10B中虚线为包括非线性电阻层14的氧化铪基存储单元的电学输出特性。
可以看出，当施加电场时，即使电场很小，不包括非线性电阻层14(典型的)
的氧化铪基存储单元的铁电极化已经开始翻转。随着电压上升至1/2Vcc时，存储单元已经有一定量的铁电极化发生翻转，即1/2Vcc的扰动电压将对器件的存储状态有显著影响。
而当施加电场时，包括非线性电阻层14的氧化铪基存储单元的铁电极化也开始翻转，但是随着电压上升至1/2Vcc时，剩余极化强度Pr缓慢增加，或者几乎不增加。随着电压上升至大于1/2Vcc，剩余极化强度Pr快速增加。这样一来，在低电压下(小于1/2Vcc)，存储单元输出的极化电荷几乎为零，因此，小电压的扰动电压对存储单元的存储状态几乎没有影响，存储单元的抗干扰性能得到增强。
因此，本申请实施例提供的存储阵列，通过在铁电电容器C中插入与铁电层13平行设置的非线性电阻层14，使得非线性电阻层14与铁电层13对施加到铁电电容 器C上的电压进行分压。非线性电阻层14的材料具有随被施加电压的增大，电阻非线性减小的特性，使得非线性电阻层14的电阻随被施加电压的增大非线性减小。那么将上述非线性电阻层14放入铁电电容器C中后，随着施加到铁电电容器C上的电压的增大，非线性电阻层14的电阻非线性减小，非线性电阻层14所得的分压非线性减小。对应的，随着施加到铁电电容器C上的电压的增大，铁电层13所得的分压非线性增大。也就是说，在施加到铁电电容器C上的电压较小时，铁电层13所得的分压的比例较小。在施加到铁电电容器C上的电压较大时，铁电层13所得的分压的比例较大。使得铁电电容器C的铁电极化翻转也具有随电压变化而非线性变化的特性。即，在铁电电容器C上被施加的电压较小(干扰电压)时，铁电层13所得的分压的比例较小，铁电电容器C的铁电极化翻转量较小，对存储单元的存储状态几乎没有影响。在铁电电容器C上被施加的电压较大(读写电压)时，铁电层13所得的分压的比例较大，铁电电容器C的铁电极化翻转量较大，可正常完成读写操作。这样一来，相当于非线性电阻层14的存在可以调控存储单元的电压响应特性，增强存储单元随电压增大时的非线性响应特性，实现抑制铁电电容器C在小电压下的铁电极化翻转，从而有效增强存储单元的抗干扰性能。
关于非线性电阻层14的材料，在第一种可能的实现方式中，非线性电阻层14的材料为导电材料，非线性电阻层14的材料具有阻变特性。
其中，阻变特性可以理解为：非线性电阻层14的材料的电阻非固定值，会随着电压的变化而变化。
在一些实施例中，非线性电阻层14的材料包括过渡金属氧化物。
其中，过渡金属氧化物(transition metal oxides)，是包括含有过渡金属的氧化物。
例如，非线性电阻层14的材料包括氧化钽(Ta 2O 5)、氧化铌(Nb 2O 5)、二氧化钛(TiO 2)或者二氧化铪(HfO 2)中的至少一种。
此处需要强调的是，通过上述对铁电层13的材料的描述可知，在铁电层13的材料为HfO材料体系的材料时，铁电层13会对HfO 2进行掺杂。因此，在非线性电阻层14的材料包括HfO 2的情况下，可通过对膜层中掺杂成分进行分析，以划分铁电层13和非线性电阻层14的膜层边界。
在另一些实施例中，非线性电阻层14的材料包括镧系氧化物。
其中，镧系氧化物，是包括含有镧系元素的氧化物。
例如，非线性电阻层14的材料包括氧化镧(La 2O 3)、氧化镨(Pr 6O 11)。
在又一些实施例中，非线性电阻层14的材料包括钙钛矿型复合氧化物。
其中，钙钛矿型复合氧化物的通式为ABO 3，钙钛矿型复合氧化物是一种具有独特物理性质和化学性质的新型无机非金属材料，A位一般是稀土或碱土元素离子，B位为过渡元素离子，A位和B位皆可被半径相近的其他金属离子部分取代而保持其晶体结构基本不变。
示例的，非线性电阻层14的材料包括掺杂的钛酸锶(SrTiO 3)、钛酸钡(BaTiO 3)、锰酸镧(LaMnO 3)。
在又一些实施例中，非线性电阻层14的材料包括有机聚合物。
其中，有机聚合物是指由一种或几种有机分子或分子团以共价键结合成具有多个重复单体单元的大分子。
示例的，非线性电阻层14的材料包括聚甲基丙烯酸乙酯(poly ethyl methacrylate，PEMA)、聚甲亚胺(Polyazomethine，PAM)、聚合三苯胺(polytriphenylamine，PTPA)或者聚2,7-(9,9-二己基芴嵌段悬挂共聚物(poly[2,7-(9,9-dihexylfluorene)]-block-polypendentisoindigo，PF 14-b-Piso n)。
由于具有阻变特性的材料在外加电压变化的情况下，氧空位通道或者金属离子通道会形成或者截断。
例如，在电压较小的情况下，氧空位通道或者金属离子通道会形成的比较慢，非线性电阻层14的电阻较大。在电压较大的情况下，氧空位通道或者金属离子通道会形成的比较块，非线性电阻层14的电阻会快速减小。
因此，非线性电阻层14的材料具有阻变特性，非线性电阻层14的电阻会随着电压的变化而变化。进一步的，通过选取阻变特性为随着电压的增大，电阻非线性减小的材料，可实现随着铁电电容器C被施加的电压的增大，非线性电阻层14的材料的电阻非线性减小。
如图11A所示，向铁电电容器C施加的电压Vcc随时间的变化线性变化。
图11B为随着施加电压Vcc的增大，铁电层13上的电压随时间的变化曲线。其中，实线为未设置非线性电阻层14时，铁电层13上电压的变化曲线。虚线为设置非线性电阻层14后，铁电层13上电压的变化曲线。由于在低电压下，非线性电阻层14的电阻较大，分压的比例较大，因此铁电层13所分得的电压较小。随着电压增大，非线性电阻层14的电阻迅速减小，铁电层13所分得的电压骤然增大。因此，铁电层13的电压随时间表现出非线性的变化特性。
图11C为铁电层13的剩余极化强度Pr随时间的变化曲线。其中，实线为未插入非线性电阻层14时的剩余极化强度Pr变化曲线，虚线为插入非线性电阻层14后的剩余极化强度Pr变化曲线。插入非线性电阻层14后，铁电层13的电压随时间变化非线性变化。
因此，如图11D所示，在铁电电容器C中插入具有阻变特性的非线性电阻层14后，铁电电容器C的极化电荷输出随电压变化非线性变化。在总电压较小时，铁电层13所分得的电压较小，其铁电极化翻转量较小，铁电电容器C的输出电流较小，从而可以有效增强存储单元的抗干扰能力。而当总电压较大，非线性电阻层14的电阻骤然减小，铁电层13所分得的电压骤然增大，铁电电容器C的输出电流骤然增大，使铁电层13产生足够的铁电极化翻转。
在一些实施例中，通过调整非线性电阻层14的厚度、数量、位置等因素，可以调节非线性电阻层14的非线性特性。图11D为铁电电容器C的输出特性曲线。图11D中，实线表示铁电电容器C的极化电荷输出随电压变化线性变化，用来作为参照。双点长划线、点化线、虚线表示铁电电容器C的极化电荷输出随电压变化非线性变化，且双点长划线、点化线、虚线的非线性特性逐步增强，以增强存储单元的抗干扰能力。
在第二种可能的实现方式中，非线性电阻层14的材料具有金属-绝缘体转变特 性。
其中，金属-绝缘体转变(metal-insulator transition)是指从金属导体变成不导电的绝缘体(或半导体)的物理转变。或者从绝缘体变成导电体的物理转变。结合非线性电阻层14的材料具有随着电压增大，电阻非线性减小的特性。因此，本申请实施例中的非线性电阻层14的材料具有在低电压下为绝缘体，在高电压下为金属的特性。
在一些实施例中，非线性电阻层14的材料包括固体电解质。
其中，固体电解质是一类在固态时(即熔点以下)呈现离子导电性的物体。
示例的，非线性电阻层14的材料包括硫化锗(Ge xS y)、硫化银(Ag 2S)、硫化铜(Cu 2S)等硫化物，碘化银(AgI)、碘化铷银(RbAg 4I 5)等碘化物，硒化锗(Ge xSe y)等硒化物，碲化锗(Ge xTe y)、碲化锑(Sb xTe y)、锗锑碲合金(GeSbTe)、银铟锑碲合金(AgInSbTe)等碲化物。
由于具有金属-绝缘体转变特性的材料，在外加电压变化的情况下，焦耳热也会变化，使得非线性电阻层14的材料发生相变，实现绝缘体相和金属相的互换转变。
例如，在电压较小的情况下，焦耳热较小，非线性电阻层14的材料以绝缘体相为主，非线性电阻层14的电阻较大。在电压较大的情况下，焦耳热增加，非线性电阻层14的材料发生相变，非线性电阻层14以金属相为主，非线性电阻层14的材料从绝缘体相变为金属相，非线性电阻层14的材料的电阻骤然降低。
因此，非线性电阻层14的材料具有金属-绝缘体转变特性，非线性电阻层14的材料的电阻会随着电压的变化而变化。进一步的，通过选取金属-绝缘体转变特性为随着电压的增大，从绝缘体转变为金属的材料，可实现随着铁电电容器C被施加的电压的增大，非线性电阻层14的材料的电阻非线性减小，非线性电阻层14的电阻非线性减小。
如图11A所示，向铁电电容器C施加的电压Vcc随时间的变化线性变化。
图12A为随着施加电压Vcc的增大，铁电层13上的电压随时间的变化曲线。其中，实线为未设置非线性电阻层14时，铁电层13上电压的变化曲线，虚线为设置非线性电阻层14后，铁电层13上电压的变化曲线。由于在低电压下，非线性电阻层14的电阻较大，分压的比例较大，因此铁电层13所分得的电压较小。随着电压增大，非线性电阻层14发生相变，由绝缘体转变为金属相，非线性电阻层14的电阻迅速减小，铁电层13所分得的电压骤然增大。因此，铁电层13的电压随时间表现出非线性的变化特性。
图12B为铁电层13的剩余极化强度Pr随时间的变化曲线。其中，实线为未插入非线性电阻层14时的剩余极化强度Pr变化曲线，虚线为插入非线性电阻层14后的剩余极化强度Pr变化曲线。插入非线性电阻层14后，铁电层13的电压随时间变化非线性变化。
因此，如图12C所示，在铁电电容器C中插入具有金属-绝缘体转变特性的非线性电阻层14后，铁电电容器C的极化电荷输出随电压变化非线性变化。在总电压较小时，铁电层13所分得的电压较小，其铁电极化翻转量较小，铁电电容器C的输出电流较小，从而可以有效增强存储单元的抗干扰能力。而当总电压较大，超过非线性 电阻层14发生相变的临界电压时，非线性电阻层14的电阻骤然减小，铁电层13所分得的电压骤然增大，铁电电容器C的输出电流骤然增大，使铁电层13产生足够的铁电极化翻转。
在一些实施例中，铁电电容器C还包括至少一个第三电极，至少一个第三电极设置于第一电极11和第二电极12之间。
在一种可能的实现方式中，如图13A所示，铁电电容器C还包括一个第三电极15。
在这种情况下，铁电电容器C包括两个串联的电容，一个电容的两极为第一电极11和第三电极15，本申请实施例将两极为第一电极11和第三电极15的电容称为下电容。另一个电容的两极为第二电极12和第三电极15，本申请实施例将两极为第二电极12和第三电极15的电容称为上电容。上电容和下电容中至少一个为铁电电容。
在一些实施例中，如图13A所示，非线性电阻层14和铁电层13接触层叠。
示例的，非线性电阻层14和铁电层13设置于第一电极11和第三电极15之间。
也就是说，非线性电阻层14和铁电层13均位于下电容中，非线性电阻层14和铁电层13接触串联。
其中，可以是如图13A所示的铁电层13靠近第一电极11设置，也可以是非线性电阻层14靠近第一电极11设置。
或者，示例的，非线性电阻层14和铁电层13设置于第二电极12和第三电极15之间。
在另一些实施例中，如图13B所示，非线性电阻层14和铁电层13之间设置有第三电极15。
示例的，如图13B所示，非线性电阻层14设置于第二电极12和第三电极15，铁电层13设置于第一电极11和第三电极15之间。
也就是说，非线性电阻层14设置于上电容中，铁电层13设置于下电容中，非线性电阻层14和铁电层13通过第三电极15串联。
或者，示例的，非线性电阻层14设置于第一电极11和第三电极15，铁电层13设置于第二电极12和第三电极15之间。
通过将非线性电阻层14和铁电层13间隔设置，可减小非线性电阻层14对铁电层13铁电极化的影响。
其中，图13A和图13B仅是以铁电电容器C包括一层非线性电阻层14为例进行示意。如图13C所示，铁电电容器C也可以包括多层非线性电阻层14，多层非线性电阻层14根据需要合理设置，多层非线性电阻层14位于第一电极11和第二电极12之间即可。
在另一种可能的实现方式中，如图14A所示，铁电电容器C还包括多个第三电极15。
在这种情况下，铁电电容器C包括两个以上串联的电容，一个电容的两极为第一电极11和第三电极15，本申请实施例将两极为第一电极11和第三电极15的电容称为下电容。一个电容的两极为第二电极12和第三电极15，本申请实施例将两极为 第二电极12和第三电极15的电容称为上电容，还有至少一个电容的两极为相邻设置的两个第三电极15，本申请实施例将两极均为第三电极15的电容称为中间电容。上电容、至少一个中间电容以及下电容中至少一个为铁电电容。
在一些实施例中，如图14A所示，非线性电阻层14和铁电层13接触层叠。
示例的，非线性电阻层14和铁电层13位于两个第三电极15之间。
或者，示例的，非线性电阻层14和铁电层13位于第一电极11和第三电极15之间。
或者，示例的，非线性电阻层14和铁电层13位于第二电极12和第三电极15之间。
当然，无论哪种结构，可以是非线性电阻层14位于铁电层13靠近第一电极11一侧，也可以是非线性电阻层14位于铁电层靠近第二电极12一侧。
或者，示例的，如图14B所示，非线性电阻层14和铁电层13接触层叠，且铁电层13的两侧均设置有非线性电阻层14。
或者，示例的，如图14C所示，部分非线性电阻层14和铁电层13接触层叠，部分非线性电阻层14和铁电层13之间设置有第三电极15。
在另一些实施例中，如图14D所示，非线性电阻层14和铁电层13之间设置有第三电极15。
或者理解为，非线性电阻层14和铁电层13位于不同的电容中。
示例的，如图14D所示，铁电层13位于两个第三电极15之间。
或者，示例的，铁电层13位于第一电极11和第三电极15之间。
或者，示例的，铁电层13位于第二电极12和第三电极15之间。
图14A-图14D中示意的非线性电阻层14和铁电层13的位置关系，仅为一种示意，不做任何限定，铁电层13、至少一层非线性电阻层14以及至少一个第三电极15设置于第一电极11和第二电极12之间即可。
本申请实施例还提供一种存储阵列的制备方法，存储阵列的制备方法在衬底上形成多个存储单元，每个存储单元包括上述任一种铁电电容器C。
其中，铁电电容器C的结构，可以参考上述关于铁电电容器C的相关描述。
示例的，铁电电容器C包括第一电极11和第二电极12，以及设置在第一电极11和第二电极12之间的铁电层13和至少一层非线性电阻层14。非线性电阻层14的材料具有随被施加电压的增大，电阻非线性减小的特性。
在一些实施例中，非线性电阻层14的材料为具有阻变特性的导电材料。
示例的，非线性电阻层14的材料包括过渡金属氧化物。
例如，非线性电阻层14的材料包括Ta 2O 5、Nb 2O 5、TiO 2或者HfO 2中的至少一种。
或者，示例的，非线性电阻层14的材料包括镧系氧化物。
例如，非线性电阻层14的材料包括La 2O 3、Pr 6O 11。
或者，示例的，非线性电阻层14的材料包括钙钛矿型复合氧化物。
例如，非线性电阻层14的材料包括掺杂的SrTiO 3、BaTiO 3、LaMnO 3。
或者，示例的，非线性电阻层14的材料包括有机聚合物。
例如，非线性电阻层14的材料包括PEMA、PAM、PTPA或者PF 14-b-Piso n。
在另一些实施例中，非线性电阻层14的材料具有金属-绝缘体转变特性。
示例的，非线性电阻层14的材料包括固体电解质。
例如，非线性电阻层14的材料包括Ge xS y、Ag 2S、Cu 2S等硫化物，AgI、RbAg 4I 5等碘化物，Ge xSe y等硒化物，Ge xTe y、Sb xTe y、GeSbTe、AgInSbTe等碲化物。
在一些实施例中，如图13A-图14D所示，铁电电容器C还包括至少一个第三电极15，第三电极15设置在第一电极11和第二电极12之间，铁电层13和非线性电阻层14之间设置有第三电极15。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (25)

  1. 一种存储阵列，其特征在于，包括：
    衬底；
    多个存储单元，设置在所述衬底上，每个所述存储单元包括铁电电容器；
    所述铁电电容器包括：
    第一电极和第二电极；
    铁电层和至少一层非线性电阻层，设置在所述第一电极和所述第二电极之间；
    其中，所述非线性电阻层的材料具有随被施加电压的增大，电阻非线性减小的特性。
  2. 根据权利要求1所述的存储阵列，其特征在于，所述非线性电阻层的材料为具有阻变特性的导电材料。
  3. 根据权利要求1所述的存储阵列，其特征在于，所述非线性电阻层的材料具有金属-绝缘体转变特性。
  4. 根据权利要求1所述的存储阵列，其特征在于，所述非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物、固体电解质或者有机聚合物。
  5. 根据权利要求1所述的存储阵列，其特征在于，所述非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2、GeSbTe或者AgInSbTe中的至少一种。
  6. 根据权利要求1-4任一项所述的存储阵列，其特征在于，所述铁电电容器还包括至少一个第三电极，所述第三电极设置在所述第一电极和所述第二电极之间；
    所述铁电层和所述非线性电阻层之间设置有所述第三电极。
  7. 根据权利要求1-6任一项所述的存储阵列，其特征在于，所述第一电极和所述第二电极沿与所述衬底相垂直的方向设置。
  8. 根据权利要求1-6任一项所述的存储阵列，其特征在于，所述第一电极和所述第二电极沿与所述衬底相平行的方向设置。
  9. 根据权利要求1-8任一项所述的存储阵列，其特征在于，所述铁电层的材料包括氧化铪基材料。
  10. 一种存储阵列，其特征在于，包括：
    衬底；
    多个存储单元，设置在所述衬底上，每个所述存储单元包括铁电电容器；
    所述铁电电容器包括：
    第一电极和第二电极；
    铁电层和至少一层非线性电阻层，设置在所述第一电极和所述第二电极之间；
    其中，所述非线性电阻层的材料为具有阻变特性的导电材料；或者，所述非线性电阻层的材料具有金属-绝缘体转变特性。
  11. 根据权利要求10所述的存储阵列，其特征在于，所述非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物、固体电解质或者有机聚合物。
  12. 根据权利要求10所述的存储阵列，其特征在于，所述非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2、GeSbTe或者AgInSbTe中的至少一种。
  13. 根据权利要求10-12任一项所述的存储阵列，其特征在于，所述铁电电容器还包括至少一个第三电极，所述第三电极设置在所述第一电极和所述第二电极之间；
    所述铁电层和所述非线性电阻层之间设置有所述第三电极。
  14. 根据权利要求10-13任一项所述的存储阵列，其特征在于，所述第一电极和所述第二电极沿与所述衬底相垂直的方向设置。
  15. 根据权利要求10-14任一项所述的存储阵列，其特征在于，所述第一电极和所述第二电极沿与所述衬底相平行的方向设置。
  16. 根据权利要求10-15任一项所述的存储阵列，其特征在于，所述铁电层的材料包括氧化铪基材料。
  17. 一种存储器，其特征在于，包括：控制器；和如权利要求1-16任一项所述的存储阵列；所述控制器与所述存储阵列电连接。
  18. 一种电子设备，其特征在于，包括：电路板；和如权利要求17所述的存储器；所述电路板和所述存储器电连接。
  19. 一种存储阵列的制备方法，其特征在于，包括：
    在衬底上形成多个存储单元，每个所述存储单元包括铁电电容器；
    其中，所述铁电电容器包括的第一电极和第二电极，以及设置在所述第一电极和所述第二电极之间的铁电层和至少一层非线性电阻层；所述非线性电阻层的材料具有随被施加电压的增大，电阻非线性减小的特性。
  20. 根据权利要求19所述的存储阵列的制备方法，其特征在于，所述非线性电阻层的材料为具有阻变特性的导电材料。
  21. 根据权利要求19所述的存储阵列的制备方法，其特征在于，所述非线性电阻层的材料具有金属-绝缘体转变特性。
  22. 根据权利要求19所述的存储阵列的制备方法，其特征在于，所述非线性电阻层的材料包括过渡金属氧化物、镧系氧化物、钙钛矿型复合氧化物、固体电解质或者有机聚合物。
  23. 根据权利要求19所述的存储阵列的制备方法，其特征在于，所述非线性电阻层的材料包括Ta 2O 5、Nb 2O 5、TiO 2、HfO 2、GeSbTe或者AgInSbTe中的至少一种。
  24. 根据权利要求19-23任一项所述的存储阵列的制备方法，其特征在于，所述铁电电容器还包括至少一个第三电极，所述第三电极设置在所述第一电极和所述第二电极之间；所述铁电层和所述非线性电阻层之间设置有所述第三电极。
  25. 一种存储阵列的制备方法，其特征在于，用于制备权利要求10-16任一项所述的存储阵列。
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