WO2023231187A1 - 半导体结构的制造方法 - Google Patents

半导体结构的制造方法 Download PDF

Info

Publication number
WO2023231187A1
WO2023231187A1 PCT/CN2022/113731 CN2022113731W WO2023231187A1 WO 2023231187 A1 WO2023231187 A1 WO 2023231187A1 CN 2022113731 W CN2022113731 W CN 2022113731W WO 2023231187 A1 WO2023231187 A1 WO 2023231187A1
Authority
WO
WIPO (PCT)
Prior art keywords
temperature
substrate
deposition
region
area
Prior art date
Application number
PCT/CN2022/113731
Other languages
English (en)
French (fr)
Inventor
丁孟雅
王晓玲
郭军
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Publication of WO2023231187A1 publication Critical patent/WO2023231187A1/zh

Links

Images

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • Embodiments of the present disclosure belong to the field of semiconductors, and specifically relate to a method of manufacturing a semiconductor structure.
  • Film deposition is an essential link in the manufacturing process of semiconductor structures. Its principle is that one or several gas phase compounds or elements containing film elements react chemically on the surface of the substrate to form a film layer. Subsequently, a photoresist layer can be formed on the film layer, and the photoresist layer can be photolithographically processed to obtain a patterned photoresist layer. Using the photoresist layer as a mask to etch the film layer, the pattern of the photoresist layer can be transferred to the film layer.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure, which is at least beneficial to improving the pattern accuracy of the photoresist layer and the film layer.
  • embodiments of the present disclosure provide a method of manufacturing a semiconductor structure, wherein the method of manufacturing a semiconductor structure includes: providing a substrate, the front side of the substrate includes a first region and a second region, the The height of the first area is greater than the height of the second area; a deposition process is performed to form a film layer on the front side of the substrate; during the deposition process, the temperature of the first area is lower than that of the second area temperature; forming a photoresist layer on the film layer, and performing photolithography treatment on the photoresist layer; after the photolithography treatment, using the photoresist layer as a mask, etching the film layer.
  • the first zone with a higher control height has a lower temperature
  • the second zone with a lower control height has a higher temperature, so that the thickness of the film layer in the second zone is greater than that in the first zone. Therefore, the flatness of the top surface of the film layer is relatively high, which can avoid affecting the pattern of the photoresist layer. Using this photoresist layer as a mask to etch the film layer, a more precise film pattern can be obtained.
  • Figures 1-2 respectively show structural schematic diagrams corresponding to each step in a method for manufacturing a semiconductor structure
  • Figures 3-4 respectively show structural schematic diagrams corresponding to each step in another method of manufacturing a semiconductor structure
  • Figure 13 shows a schematic diagram of a deposition processing chamber
  • Figure 14 shows a schematic diagram of the chamber during the cooling stage in the deposition process according to an embodiment of the present disclosure
  • Figures 15 to 19 respectively show schematic diagrams of the temperature changes of the heating coils corresponding to different deposition areas when forming a convex film layer according to an embodiment of the present disclosure
  • Figure 20 shows a schematic diagram of the chamber during the heating stage in the deposition process provided by an embodiment of the present disclosure
  • 21 to 25 respectively show schematic diagrams of the temperature changes of the heating coils corresponding to different deposition areas when forming a concave film layer according to an embodiment of the present disclosure.
  • a substrate 10 with a flat surface is provided; a film layer 20 with a uniform thickness is formed on the substrate 10 ; and a patterned photoresist layer 30 is formed on the film layer 20 .
  • the pattern of the photoresist layer 30 has higher precision. For example, the size of each pattern is equal and the spacing between the patterns is equal.
  • the film layer 20 is etched to transfer the pattern of the photoresist layer to the film layer 20 . Since the pattern precision of the photoresist layer 30 is relatively high, a film layer pattern with relatively high precision can be formed.
  • warpage may occur when the substrate 10 undergoes various temperature-changing processes such as high-temperature treatment and cooling treatment.
  • areas on the surface of the substrate 10 have different heights, thereby reducing the flatness of the top surface of the film layer 20 .
  • a photoresist layer 30 is formed on the top surface of the film layer 20 , and after the photoresist layer 30 is patterned, the pattern of the photoresist layer 30 will be deformed.
  • the film layer 20 is etched to transfer the pattern of the photoresist layer 30 to the film layer. Since the pattern accuracy of the photoresist layer 30 is low, the pattern accuracy of the film layer 20 will be affected.
  • the size of each film layer pattern is different, and the spacing between the film layer patterns is also different, where the first spacing S1 > the second spacing S2 > the third spacing S3 , thus affecting the performance of the semiconductor structure.
  • Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.
  • the manufacturing method adjusts the temperature of a first region and a second region of a substrate during a deposition process to form film layers of different thicknesses in the first region and the second region, thereby It can compensate for the warpage caused by the substrate, thereby helping to improve the pattern accuracy of the photoresist layer and film layer.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure.
  • the manufacturing method includes: providing a substrate 1, the front surface of the substrate 1 includes a first region A and a second region B.
  • the first region A The height of the first area A is greater than the height of the second area B; a deposition process is performed to form a film layer 2 on the front side of the substrate 1; during the deposition process, the temperature of the first area A is less than the temperature of the second area B; a film layer 2 is formed on the Photoresist layer 3, and perform photolithography processing on photoresist layer 3; after photolithography processing, use photoresist layer 3 as a mask to etch film layer 2.
  • the film layer 2 can be a single film layer or a multi-layer film layer.
  • the material of film layer 2 may be insulating material or metal material.
  • the reaction formula is: Among them, Si(OC 2 H 5 ) 4 is Tetra Ethyl Ortho Silicate. It can be seen from this reaction equation that the formation process of film layer 2 requires heating, and the amount of heat will affect the formation speed of film layer 2.
  • the first area A and the second area A on the surface of the substrate 1 can be controlled by adjusting the temperature change mode of the temperature control device 6 and adjusting the placement position of the temperature control device 6 .
  • Zone B has different temperatures.
  • the temperature control device 6 may be a heating device, and the heat transferred to the substrate 1 is controlled by adjusting the temperature of the temperature control device 6 itself.
  • the distance relationship between the temperature control device 6 and the first zone A and the second zone B will affect the temperature changes of the first zone A and the second zone B.
  • Example 1 Referring to Figure 5, a substrate 1 is provided.
  • the first region A is the edge of the substrate 1, the second region B is the center of the substrate 1, and the first region A is arranged around the second region B, that is, the substrate 1 is concave.
  • the substrate 1 can be a wafer, and the sizes of the wafers are mainly 8 inches and 12 inches.
  • the temperature control device 6 (refer to FIG. 13 ) is disposed opposite to the edge of the substrate 1 , that is, the temperature control device 6 is closer to the edge of the substrate 1 than to the center of the substrate 1 . Therefore, when the heat transferred by the temperature control device 6 to the substrate 1 changes, the temperature change speed of the edge of the substrate 1 is greater than that of the center of the substrate 1 .
  • the deposition process includes a cooling stage, and the temperature of the substrate 1 decreases during the cooling stage. That is to say, during the cooling stage, the edge of the substrate 1 cools down faster than the center of the substrate 1 . Therefore, at the same time, the temperature of the edge of the substrate 1 is lower than the temperature of the center of the substrate 1 .
  • the film layer 2 at the edge of the substrate 1 is thinner, and the film layer 2 at the center of the substrate 1 is thicker. Therefore, for the concave substrate 1, a convex film layer 2 can be prepared, so that the film layer 2 can compensate for the warpage caused by the substrate 1.
  • a photoresist layer 3 is formed on the film layer 2, and the photoresist layer 3 is exposed and developed to form a desired pattern. Since the top surface of the film layer 2 has a relatively high flatness, the influence on the pattern of the photoresist layer 3 can be avoided.
  • an anti-reflective layer 4 may be formed on the film layer 2 before forming the photoresist layer 3 .
  • the main components of the anti-reflective layer 4 are cross-linkable resin, thermal acid generator, surfactant and solvent.
  • the anti-reflection layer 4 can reduce reflection and improve standing wave problems.
  • the anti-reflective layer 4 and the film layer 2 are sequentially etched by etching gas. Since the pattern of the photoresist layer 3 is not deformed, the pattern accuracy of the film layer 2 can be improved. For example, the size of each pattern is the same, and the first spacing d1, the second spacing d2 and the third spacing d3 of the patterns are equal.
  • Example 2 Referring to Figure 9, a substrate 1 is provided.
  • the first area A is the center of the substrate 1
  • the second area B is the edge of the substrate 1
  • the second area B is arranged around the first area; that is, the substrate 1 is convex.
  • the temperature control device 6 is arranged opposite to the edge of the substrate 1 so that the edge of the substrate 1 has a greater temperature change speed.
  • the deposition process includes a heating stage, and the temperature of the substrate 1 increases during the heating stage. That is to say, during the heating stage, the edge of the substrate 1 heats up faster than the center of the substrate 1 . Therefore, at the same time, the temperature of the edge of the substrate 1 is greater than the temperature of the center of the substrate 1 .
  • the film layer at the edge of the substrate 1 is thicker and the film layer at the center of the substrate 1 is thinner. Therefore, for the convex substrate 1, a concave film layer 2 can be prepared so that the film layer 2 makes up for the substrate 1 The resulting warpage.
  • an anti-reflective layer 4 and a photoresist layer 3 are formed on the film layer, and the photoresist layer 3 is subjected to photolithography processing. Since the top surface of the film layer 2 has a relatively high flatness, the influence on the pattern of the photoresist layer 3 can be avoided.
  • the photolithography process also includes: using the photoresist layer 3 as a mask, etching the film layer 2 and the anti-reflection layer 4, so that a film layer pattern with uniform size and spacing can be obtained.
  • Example 2 For the relevant principles of Example 2, please refer to the detailed description in Example 1 and will not be repeated here.
  • the temperature difference between the first area A and the second area B is proportional to the height difference between the first area A and the second area B.
  • the degree of convexity of the substrate 1 is large, the temperature at the center of the substrate 1 can be made much lower than the temperature at the edge of the substrate 1, thereby increasing the degree of depression of the film layer 2; if the degree of convexity of the substrate 1 is small, Then the temperature at the center of the substrate 1 can be made slightly smaller than the temperature at the edge of the substrate 1 , thereby reducing the degree of depression of the film layer 2 .
  • the degree of depression of the substrate 1 is large, the temperature at the center of the substrate 1 can be much greater than the temperature at the edge of the substrate 1, thereby increasing the degree of convexity of the film layer 2; if the degree of depression of the substrate 1 is small, it can be made The temperature at the center of the substrate 1 is slightly greater than the temperature at the edge of the substrate 1, thereby reducing the convexity of the film layer 2.
  • the degree of convexity of the substrate 1 can be matched with the degree of depression of the film layer 2 , or the degree of depression of the substrate 1 can be matched with the degree of convexity of the film layer 2 , thereby helping to improve the ability of the film layer 2 to compensate for the warpage of the substrate 1
  • the effect is to increase the flatness of the top surface of the film layer 2.
  • the degree of warping is usually greater for large-sized semiconductor structures. Therefore, the temperature difference between the first region A and the second region B can also be adjusted according to the size of the semiconductor structure, so that the shape of the film layer 2 can match the shape of the substrate 1 .
  • the deposition process may be a low pressure chemical vapor deposition process, an atmospheric pressure chemical vapor deposition process or an atomic layer deposition process.
  • atmospheric pressure chemical vapor deposition is a chemical vapor deposition method under normal pressure conditions. Its deposition process parameters are easy to control, have good repeatability, and are suitable for mass production.
  • the chamber pressure of the low-pressure chemical vapor deposition process is approximately below 133 Pa, which can speed up the transmission rate of reaction gases and by-products, thereby increasing the formation rate of the film layer 2 .
  • the atomic layer deposition process can improve the adhesion and density of the film layer 2. In the above deposition process, the temperatures of the first area A and the second area B can be adjusted to improve the flatness of the top surface of the film layer 2 .
  • the deposition processing chamber 7 includes a plurality of deposition areas arranged in the height direction, and each deposition area can accommodate a plurality of substrates 1 arranged in the height direction. It should be noted that only the film layer 2 in the semiconductor structure is shown in FIG. 13 , but the substrate 1 is not shown. Since multiple substrates 1 can be deposited at the same time, it is beneficial to improve production efficiency and reduce production costs.
  • the deposition processing chamber 7 may be a furnace tube.
  • the temperature changes of the substrate 1 in different deposition areas are different.
  • the reaction gas of the deposition process enters the chamber 7 from the bottom of the chamber 7 , and the bold arrow in FIG. 13 indicates the flow direction of the reaction gas.
  • the inlet and outlet of the reactive gas are provided on the side wall of the bottom of the chamber 7 , and the inlet and outlet can be located on opposite sides of the chamber 7 , that is, the reactive gas usually approaches the edge of the substrate 1 first.
  • the reaction gas When the reaction gas first enters the bottom of the chamber 7, its temperature is low; as the reaction gas continues to rise, it absorbs more and more heat, so the temperature becomes higher and higher; the reaction gas will eventually be heated to the temperature of the chamber 7 Same temperature within 7 days. If the temperature control device 6 transfers the same amount of heat to each deposition area, then under the influence of the temperature of the reaction gas itself, the substrate 1 in different deposition areas will have different degrees of temperature change. Specifically, at the bottom of the chamber 7 , the temperature at the center of the substrate 1 will be higher than the temperature at the edge of the substrate 1 ; and at the top of the chamber 7 , the temperature at the center of the substrate 1 will be approximately the same as the temperature at the edge of the substrate 1 .
  • the film layer 2 located in the bottom area 51 will have a thick center and thin edges.
  • the film layer 2 located in the top area 52 will have a more uniform thickness, that is, the thick center and thin edges will gradually disappear.
  • the temperature of different deposition areas can be adjusted individually so that the degree of convexity or depression of the film layer 2 on different substrates 1 remains consistent, thereby reducing the size of different semiconductor structures. difference between.
  • Example 1 Refer to FIG. 14 .
  • FIG. 14 only shows the film layer 2 in the semiconductor structure, but not the substrate 1 .
  • the first area A is the edge of the substrate 1 and the second area B is the center of the substrate 1, that is, when the substrate 1 is concave, a convex film layer 2 needs to be formed.
  • the temperature control device 6 includes a plurality of temperature control units 61, and the temperature control units 61 are arranged in one-to-one correspondence with the deposition areas.
  • the temperature control unit 61 may be provided at the periphery of the chamber 7 . In the cooling stage, and in the direction from the bottom of the chamber 7 to the top, the cooling rate of the temperature control unit 61 increases sequentially. That is to say, the temperature control units 61 corresponding to different deposition areas can be operated independently to compensate for the temperature deviation caused by the reaction gases with different hot and cold degrees.
  • the deposition region includes a bottom region 51 and a top region 52 .
  • the temperature of the reaction gas is lower, and accordingly, the cooling rate of the temperature control unit 61 can be slowed down; for the top area 52, the temperature of the reaction gas is higher, and accordingly, the cooling rate of the temperature control unit 61 can be increased. rate. Therefore, in fact, the temperature changes of the substrate 1 in the top region 52 and the substrate 1 in the bottom region 51 are similar, and the degree of convexity of the film layer 2 in different deposition regions is relatively consistent.
  • the cooling rate of the temperature control unit 61 corresponding to the bottom area 51 is less than 0.5°C/min, such as 0.1°C/min, 0.2°C/min or 0.4°C/min.
  • the temperature cooling rate of the temperature control unit 61 corresponding to the top area 52 is 0.5°C/min-2.2°C/min. For example, 0.7°C/min, 1°C/min or 2°C/min.
  • the cooling rate is within the above range, it is beneficial to improve the flatness of the top surface of the film layer 2 and reduce the difference between the film layer 2 in the bottom region 51 and the top region 52 .
  • the temperature control unit 61 corresponding to the bottom area 51 can also be in a constant temperature or temperature rising state.
  • the temperature control unit 61 corresponding to the bottom area 51 is in a heating or constant temperature state, this does not mean that the substrate 1 is also in a heating or constant temperature state; on the contrary, under the influence of the lower temperature reaction gas, the bottom area 51 The substrate 1 is still in the cooling stage, and a film layer 2 with a thick center and thin edges can be formed.
  • the temperature control unit 61 includes multi-layer heating coils 62, and each heating coil 62 can be controlled individually, or the multi-layer heating coils 62 can also be controlled as a whole.
  • the cooling rates of the multi-layer heating coils 62 corresponding to the same deposition area are the same.
  • the multi-layer heating coils 62 in the same temperature control unit 61 are connected to the same control signal, that is, the multi-layer heating coils 62 are controlled as a whole, which is beneficial to simplifying the temperature control process.
  • the cooling rate of the multi-layer heating coils 62 corresponding to the same deposition area increases sequentially. That is to say, the multi-layer heating coils 62 in the same temperature control unit 61 are respectively controlled so that the cooling rates of each heating coil 62 are different, thereby achieving more refined control within the deposition area, thereby reducing the temperature of each film in the same deposition area.
  • Layer 2 differences That is, a deposition region is also composed of multiple sub-regions, and each sub-region can be controlled independently.
  • the top area 52 may include a first sub-area 521, a second sub-area 522, a third sub-area 523, and a fourth sub-area 524.
  • FIG. 15 shows the temperature change curve of the heating coil 62 corresponding to the bottom region 51 when the convex film layer 2 is formed.
  • FIG. 16 shows the temperature change curve of the heating coil 62 corresponding to the first sub-region 521 when the convex film layer 2 is formed.
  • Figure 17 shows the temperature change curve of the heating coil 62 corresponding to the second sub-region 522 when the convex film layer 2 is formed.
  • Figure 18 shows the third sub-region 523 when the convex film layer 2 is formed. The corresponding temperature change curve of the heating coil 62 , FIG.
  • the third time period T3 corresponds to the cooling stage of the deposition process.
  • the heating coil 62 corresponding to the bottom area 51 may be in a constant temperature state.
  • the cooling rates of the heating coils 62 corresponding to the first to fourth sub-regions 524 may increase sequentially. Therefore, the film layer 2 in the bottom region 51 and the first to fourth sub-regions 524 has a relatively consistent degree of protrusion.
  • the bottom region 51 can also be configured as multiple sub-regions, and the multiple sub-regions have different cooling rates, thereby achieving refined control of the bottom region 51 .
  • the deposition process further includes: a constant temperature stage, in which the temperature of the substrate 1 remains constant. That is to say, in both the constant temperature stage and the cooling stage, the reaction gas is introduced into the chamber 7, so the thickness of the film layer 2 continues to increase in these two stages.
  • the constant temperature stage the temperatures at the center of the substrate 1 and at the edge of the substrate 1 remain consistent, so the deposition rate is the same. Setting a constant temperature stage is beneficial to improving the quality of film layer 2.
  • the constant temperature phase may be performed after the cooling phase, or the constant temperature phase may be performed before the cooling phase.
  • the second time period T2 corresponds to the constant temperature stage.
  • the deposition process Before the deposition process, it also includes: preheating process to make the temperature of the substrate 1 reach the deposition initial temperature.
  • the initial deposition temperature can be set according to different film layer 2 materials to increase the rate of deposition processing.
  • the initial deposition temperature can also be set according to changes in the deposition process. For example, when the deposition process includes a cooling stage, the initial deposition temperature can be increased accordingly to avoid excessively low temperature affecting the quality of the film layer 2 .
  • the first time period T1 corresponds to the preheating process.
  • the preheating treatment may include a heating stage and a temperature stabilization stage.
  • the temperature of the temperature control device 6 can rise rapidly to shorten the time of the preheating process.
  • the temperature stabilization stage the temperature of the temperature control device 6 does not change, so that the temperature in the chamber 7 can remain stable, thereby facilitating the subsequent deposition process to form a high-quality film layer 2 .
  • a cooling process is also included to reduce the temperature of the substrate 1 . That is, the temperature of the substrate 1 is restored, which facilitates subsequent processes.
  • the fourth time period T4 corresponds to the cooling process.
  • Example 2 Refer to FIG. 20 .
  • FIG. 20 only shows the film layer 2 in the semiconductor structure, but not the substrate 1 .
  • the first area A is the center of the substrate 1 and the second area B is the edge of the substrate 1, that is, the substrate 1 is convex, and a concave film layer 2 needs to be formed.
  • the temperature control device 6 includes a plurality of temperature control units 61, and the temperature control units 61 are arranged in one-to-one correspondence with the deposition area; during the heating stage, and in the direction from the bottom of the chamber 7 to the top, the temperature control units 61 The heating rate decreases successively.
  • the substrate 1 in each deposition area can have a relatively consistent heating rate, so that the film layer 2 in each deposition area can have a relatively consistent degree of depression.
  • the deposition region includes a bottom region 51 and a top region 52 .
  • the temperature rise rate of the temperature control unit 61 corresponding to the bottom area 51 is 1.5-2.2°C/min, for example, 1.6°C/min, 2°C/min or 2.1°C/min.
  • the temperature rise rate of the temperature control unit 61 corresponding to the top area 52 is less than 1.5°C/min, such as 1°C/min, 0.8°C/min or 0.5°C/min.
  • the heating rates of the multi-layer heating coils 62 corresponding to the same deposition area are the same, which is beneficial to simplifying the temperature control process.
  • the heating rate of the multi-layer heating coils 62 corresponding to the same deposition area is sequentially reduced. That is, the multi-layer heating coils 62 are controlled separately, thereby achieving more refined control within the deposition area, thereby reducing the difference between the film layers 2 in the same deposition area.
  • the top area 52 may include a first sub-area, a second sub-area 522, a third sub-area 523, and a fourth sub-area 524.
  • Figure 21 shows the temperature change curve of the heating coil 62 corresponding to the bottom area 51.
  • Figure 22 shows the temperature change curve of the heating coil 62 corresponding to the first sub-region when the concave film layer 2 is formed.
  • Figure 23 shows The temperature change curve of the heating coil 62 corresponding to the second sub-region 522 when the concave film layer 2 is formed.
  • FIG. 24 shows the temperature change curve of the heating coil 62 corresponding to the third sub-region 523 when the concave film layer 2 is formed.
  • Figure 25 shows the temperature change curve of the heating coil 62 corresponding to the fourth sub-region 524 when the concave film layer 2 is formed.
  • the second time period T2 in the temperature change curve corresponds to the heating stage.
  • the heating rates of the heating coils 62 corresponding to the bottom region 51 and the first to fourth sub-regions 524 decrease sequentially. Therefore, the film layer 2 in the bottom region 51 and the first to fourth sub-regions 524 has a relatively consistent degree of depression.
  • the bottom region 51 can also be configured as multiple sub-regions, and the multiple sub-regions have different heating rates, thereby achieving refined control of the bottom region 51 .
  • the deposition process further includes: a constant temperature stage, in which the temperature of the substrate 1 remains constant.
  • the constant temperature stage In the constant temperature stage, the temperatures at the center of the substrate 1 and at the edge of the substrate 1 remain consistent, so the deposition rate is the same.
  • the constant temperature stage may be performed after the temperature rising stage, or the constant temperature stage may be performed before the temperature rising stage.
  • the third time period T3 corresponds to the constant temperature stage.
  • the deposition process Before the deposition process, it also includes: preheating process to make the temperature of the substrate 1 reach the deposition initial temperature.
  • the deposition process includes a heating stage, the initial deposition temperature can be reduced accordingly to avoid excessive temperature affecting the quality of the film layer 2 .
  • the first period T1 corresponds to the preheating process.
  • the preheating treatment may include a heating stage, a rapid temperature rise stage and a temperature stabilization stage.
  • a cooling process is also included to reduce the temperature of the substrate 1 . That is, the temperature of the substrate 1 is restored, which facilitates subsequent processes.
  • the fourth period T4 corresponds to the cooling process.
  • the embodiment of the present disclosure performs temperature adjustment on areas with different heights on the surface of the substrate 1, thereby forming a thicker film layer 2 in the lower height area and a thinner film layer 2 in the higher height area; That is, by adjusting the distribution of the film thickness to compensate for the warpage problem of the substrate 1, the problem of uneven size and spacing of the etched pattern is avoided, which is conducive to obtaining an ideal pattern.
  • the temperature change rate of the temperature control unit 61 corresponding to each deposition area can be adjusted, so that the substrate 1 in each deposition area has a relatively consistent temperature change rate, so as to improve the deposition rate of each deposition area. Area of film layer 2 consistency.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mechanical Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

本公开实施例涉及半导体领域，提供一种半导体结构的制造方法，半导体结构的制造方法包括：提供基底，所述基底的正面包括第一区和第二区，所述第一区的高度大于所述第二区的高度；进行沉积处理，以在所述基底的正面形成膜层；在所述沉积处理中，所述第一区的温度小于所述第二区的温度；在所述膜层上形成光刻胶层，并对所述光刻胶层进行光刻处理；所述光刻处理后，以所述光刻胶层为掩膜，刻蚀所述膜层。本公开实施例至少有利于提高光刻胶层和膜层的图案的精准度。

Description

半导体结构的制造方法
交叉引用
本申请引用于2022年6月02日递交的名称为“半导体结构的制造方法”的第202210625185.X号中国专利申请，其通过引用被全部并入本申请。
技术领域
本公开实施例属于半导体领域，具体涉及一种半导体结构的制造方法。
背景技术
膜层沉积是半导体结构制造过程中必不可少的环节，其原理为：含有膜层元素的一种或几种气相化合物或单质在基底表面上进行化学反应，从而生成膜层。后续可在膜层上形成光刻胶层，并对光刻胶层进行光刻处理，从而可以获得图案化的光刻胶层。以光刻胶层为掩膜刻蚀膜层，可以将光刻胶层的图案转移至膜层。
然而，光刻胶层和膜层的图案精度有待提升。
发明内容
本公开实施例提供一种半导体结构的制造方法，至少有利于提高光刻胶层和膜层的图案精度。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构的制造方法，其中，半导体结构的制造方法包括：提供基底，所述基底的正面包括第一区和第二区，所述第一区的高度大于所述第二区的高度；进行沉积处理，以在所述基底的正面形成膜层；在所述沉积处理中，所述第一区的温度小于所述第二区的温度；在所述膜层上形成光刻胶层，并对所述光刻胶层进行光刻处理；所述光刻处理后，以所述光刻胶层为掩膜，刻蚀所述膜层。
本公开实施例提供的技术方案至少具有以下优点：
在基底出现翘曲时，基底表面的不同区域具有不同的高度。在沉积处理的过程中，温度越高则膜层的形成速率越快。因此，控制高度较高的第一区具有更低的温度，控制高度较低的第二区具有更高的温度，从而使得第二 区的膜层比第一区的膜层的厚度更大。因此，膜层顶面的平整度较高，能够避免影响光刻胶层的图案。以此光刻胶层为掩膜刻蚀膜层，可以获得精度更高的膜层图案。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1-图2分别示出了一种半导体结构的制造方法中各步骤对应的结构示意图；
图3-图4分别示出了另一种半导体结构的制造方法中各步骤对应的结构示意图；
图5-图8分别示出了本公开一实施例所述的一种半导体结构的制造方法中各步骤对应的结构示意图；
图9-图12分别示出了本公开一实施例所述的另一种半导体结构的制造方法中各步骤对应的结构示意图；
图13示出了一种沉积处理的腔室示意图；
图14示出了本公开一实施例所述的沉积处理中降温阶段下的腔室示意图；
图15-图19分别示出了本公开一实施例所述的在形成凸形膜层时不同沉积区域对应的加热线圈的温度变化示意图；
图20示出了本公开一实施例提供的沉积处理中升温阶段下的腔室示意图；
图21-图25分别示出了本公开一实施例所述的在形成凹形膜层时不同沉积区域对应的加热线圈的温度变化示意图。
具体实施方式
参考图1，提供一种表面平整的基底10；在基底10上形成厚度均匀的膜层20；在膜层20上形成图案化的光刻胶层30。不难发现，由于膜层20的顶面较为平整，因而光刻胶层30的图案具有较高的精度，举例而言，各图案的尺寸相等，各图案间的间距相等。参考图2，对膜层20进行刻蚀， 以将光刻胶层的图案转移至膜层20。由于光刻胶层30的图案精度较高，因而可以形成较高精度的膜层图案。
然而，基底10经过高温处理和降温处理等多种温度变化的制程，会出现翘曲的现象。具体地，参考图3，基底10表面的区域具有不同的高度，进而降低膜层20顶面的平整度。在膜层20顶面形成光刻胶层30，并对光刻胶层30进行图形化处理后，光刻胶层30的图案会发生变形。参考图4，对膜层20进行刻蚀，以将光刻胶层30的图案转移至膜层。由于光刻胶层30的图案精度较低，因而会影响膜层20图案的精度。举例而言，各膜层图案的尺寸不同，膜层图案间的间距也不同，其中，第一间距S1>第二间距S2>第三间距S3，从而影响半导体结构的性能。
本公开实施例提供一种半导体结构的制造方法，该制造方法在沉积处理中调整基底的第一区和第二区的温度，以在第一区和第二区形成不同厚度的膜层，从而能够弥补基底带来的翘曲，从而有利于提高光刻胶层和膜层的图案精度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
如图5-图25所示，本公开一实施例提供一种半导体结构的制造方法，制造方法包括：提供基底1，基底1的正面包括第一区A和第二区B，第一区A的高度大于第二区B的高度；进行沉积处理，以在基底1的正面形成膜层2；在沉积处理中，第一区A的温度小于第二区B的温度；在膜层2上形成光刻胶层3，并对光刻胶层3进行光刻处理；光刻处理后，以光刻胶层3为掩膜，刻蚀膜层2。
换言之，在基底1出现翘曲时，基底1表面不同的区域具有不同的高度。在沉积处理过程中，温度越高则膜层2的沉积的速率越快。对于高度更高的第一区A，控制其具有更低的温度，从而在第一区A可以形成更薄的膜层2；对于高度更低的第二区B，控制其具有更高的温度，从而在第二区B可以形成更厚的膜层2。如此，能够提高膜层2顶面的平整度，避免光刻胶 层3和膜层2的图案发生变形，以提高图案精度。如此，有利于提高半导体结构的性能。
示例地，此膜层2可以为单层膜层或多层膜层。膜层2的材料可以为绝缘材料或金属材料。以膜层2的材料为二氧化硅为例，其反应式为:
Figure PCTCN2022113731-appb-000001
其中，Si(OC 2H 5) 4为正硅酸四乙酯(Tetra Ethyl Ortho Silicate)。由该反应式可知，膜层2的生成过程需要加热，而热量的大小会影响膜层2的形成速度。
在一些实施例中，在沉积处理的过程中，可以通过调节温控装置6的温度变化模式以及调整温控装置6的摆放位置等方式，从而控制基底1表面的第一区A和第二区B具有不同的温度。具体地，温控装置6可以为发热装置，通过调节温控装置6自身的温度，以控制向基底1传递的热量。此外，温控装置6与第一区A和第二区B的距离关系会影响第一区A和第二区B的温度变化情况。
为便于理解，以下对制造方法的原理进行举例说明。
示例一，参考图5，提供基底1，第一区A为基底1的边缘，第二区B为基底1的中心，第一区A环绕第二区B设置，即基底1为凹形。示例地，基底1可以为晶圆，晶圆的尺寸以8英寸和12英寸为主。
温控装置6(参考图13)与基底1的边缘相对设置，即，相比于基底1的中心，温控装置6更靠近基底1的边缘。因此，在温控装置6向基底1传递的热量发生改变时，基底1边缘比基底1中心的温度变化速度大。
在基底1为凹形时，沉积处理包括降温阶段，基底1在降温阶段的温度降低。也就是说，在降温阶段，基底1边缘比基底1中心更快降温，因此，在同一时刻下，基底1边缘的温度小于基底1中心的温度。参考图6，沉积处理完成后，基底1边缘的膜层2更薄，基底1中心的膜层2更厚。因此，针对凹形基底1，可制备凸形膜层2，使得膜层2弥补基底1带来的翘曲度。
参考图7，在膜层2上形成光刻胶层3，并对光刻胶层3曝光显影以形成所需的图案。由于膜层2顶面的平整度较高，因而可以避免对光刻胶层3的图案的影响。在一些实施例中，在形成光刻胶层3前还可以在膜层2上形成抗反射层4。抗反射层4主要成分是能交联的树脂、热致酸发生剂、表面活性剂以及溶剂。抗反射层4能够减少反射并且改善驻波问题。
参考图8，以光刻胶层3为掩膜，通过刻蚀气体依次刻蚀抗反射层4和膜层2。由于光刻胶层3的图案未发生变形，因而可以提高膜层2的图案精度。示例地，各图案的尺寸大小相同，且图案的第一间距d1、第二间距d2和第三间距d3相等。
示例二，参考图9，提供基底1，第一区A为基底1的中心，第二区B为基底1的边缘，第二区B环绕第一区设置；即基底1为凸形。
同理，温控装置6与基底1的边缘相对设置，以使得基底1的边缘具有更大的温度变化速度。在基底1为凸形时，沉积处理包括升温阶段，基底1在升温阶段的温度升高。也就是说，在升温阶段，基底1边缘比基底1中心更快升温，因此，在同一时刻下，基底1边缘的温度大于基底1中心的温度。参考图10，沉积处理完成后，基底1边缘的膜层更厚，基底1中心的膜层更薄，因此，针对凸形基底1，可制备凹形膜层2，使得膜层2弥补基底1带来的翘曲度。
参考图11，在膜层上形成抗反射层4和光刻胶层3，并对光刻胶层3进行光刻处理。由于膜层2顶面的平整度较高，因而可以避免对光刻胶层3的图案的影响。
参考图12，在光刻处理后还包括：以光刻胶层3为掩膜，刻蚀膜层2和抗反射层4，从而可以获得具有均一尺寸和间距的膜层图案。
示例二的相关原理可参考示例一中的详细说明，在此不再赘述。
在沉积处理中，第一区A与第二区B的温度差与第一区A与第二区B的高度差呈正比关系。举例而言，若基底1的凸起程度较大，则可以使得基底1中心的温度远小于基底1边缘的温度，从而增大膜层2的凹陷程度；若基底1的凸起程度较小，则可以使得基底1中心的温度略小于基底1边缘的温度，从而减小膜层2的凹陷程度。反之，若基底1的凹陷程度较大，则可以使得基底1中心的温度远大于基底1边缘的温度，从而增大膜层2的凸起程度；若基底1的凹陷程度较小，则可以使得基底1中心的温度略大于基底1边缘的温度，从而减小膜层2的凸起程度。如此，能够使得基底1的凸起程度与膜层2的凹陷程度相匹配，或者使得基底1的凹陷程度与膜层2的凸起程度相匹配，从而有利于提高膜层2弥补基底1翘曲度的效果，以增大膜层2顶面的平整程度。
此外，对于大尺寸的半导体结构，其发生翘曲的程度通常更大。因此，还可以根据半导体结构的尺寸大小对第一区A和第二区B的温度差进行调整，以使得膜层2的形状能够与基底1的形状相匹配。
沉积处理可以为低压化学气相沉积工艺、常压化学气相沉积工艺或原子层沉积工艺。具体地，常压化学气相沉积是在常压条件下的化学气相沉积方法，其沉积工艺参数易控制，重复性好、宜于批量生产。低压化学气相沉积工艺的腔室压力大约在133Pa以下，可以使得反应气体和副产物的传输速率加快，从而提高膜层2的形成速率。原子层沉积工艺能够提高膜层2的附着力以及密实程度。在上述沉积工艺中，均可以对第一区A和第二区B的温度进行调整，以提高膜层2顶面的平整度。
在一些实施例中，参考图13，沉积处理的腔室7包括在高度方向排列的多个沉积区域，每一沉积区域可容纳在高度方向排列的多个基底1。需要说明的是，图13中仅示意出半导体结构中的膜层2，而未示出基底1。由于可同时对多个基底1进行沉积处理，从而有利于提高生产效率，降低生产成本。示例地，沉积处理的腔室7可以为炉管。
值得注意的是，不同沉积区域的基底1的温度变化情况不同。具体地，参考图13，沉积处理的反应气体从腔室7的底部进入腔室7，图13中的粗体箭头示意了反应气体的流动方向。在一些实施例中，腔室7底部的侧壁上设有反应气体的入口和出口，且入口和出口可位于腔室7的相对两侧，即反应气体通常先接近基底1的边缘。反应气体刚进入腔室7的底部时，其温度较低；随着反应气体的不断上升，其吸收的热量越来越多，因而温度越来越高；反应气体最终会被加热到和腔室7内一样的温度。若温控装置6对各沉积区域传递的热量相同，则在反应气体自身温度的影响下，不同沉积区域的基底1会具有不同的温度变化程度。具体地，在腔室7的底部，基底1中心的温度会高于基底1边缘的温度；而在腔室7的顶部，基底1中心的温度与基底1边缘的温度大致相同。由于在反应气体在不同沉积区域存在温差，因而不同沉积区域的膜层2的厚度存在偏差。具体地，位于底部区域51的膜层2会出现中心厚边缘薄的现象，位于顶部区域52的膜层2具有更为均一的厚度，即中心厚边缘薄的现象会逐渐消失。
因此，基于气体流向在不同沉积区域造成的温度差异，可以对不同的 沉积区域单独进行温度调整，以使得不同基底1上的膜层2的凸起或凹陷程度保持一致，从而减小不同半导体结构之间的差异。
以下将对不同沉积区域的温度调节方式进行举例说明。
示例一，参考图14，图14中仅示意出半导体结构中的膜层2，而未示出基底1。在第一区A为基底1的边缘，第二区B为基底1的中心时，即基底1为凹形时，需形成凸形的膜层2。
温控装置6包括多个温控单元61，温控单元61与沉积区域一一对应设置。示例地，温控单元61可设置在腔室7的外围。在降温阶段，且在腔室7的底部指向顶部的方向上，温控单元61的降温速率依次增大。也就是说，不同沉积区域对应的的温控单元61可单独操作，以弥补冷热程度不同的反应气体所带来的温度偏差。
在一些实施例中，沉积区域包括底部区域51和顶部区域52。对于底部区域51，反应气体的温度较低，相应地，可减慢温控单元61的降温速率；对于顶部区域52，反应气体的温度较高，相应地，可增大温控单元61的降温速率。因此，实际上顶部区域52的基底1与底部区域51的基底1的温度变化程度相当，不同沉积区域的膜层2的凸起程度较为一致。
示例地，底部区域51对应的温控单元61的降温速率小于0.5℃/min，比如0.1℃/min、0.2℃/min或0.4℃/min。示例地，顶部区域52对应的温控单元61的降温速率为0.5℃/min-2.2℃/min。比如0.7℃/min、1℃/min或2℃/min。在降温速率处于上述范围时，有利于提高膜层2顶面的平整度，且降低底部区域51与顶部区域52的膜层2之间的差异。
需要说明的是，由于反应气体自身的温度对底部区域51的影响较大，因此，底部区域51对应的温控单元61还可以处于恒温或升温状态。换言之，虽然底部区域51对应的温控单元61处于升温或恒温状态，但这并不意味着基底1也处于升温或恒温状态；相反的，底部区域51在较低温度的反应气体的影响下，基底1仍然处于降温阶段，可以形成中心厚边缘薄的膜层2。
温控单元61包括多层加热线圈62，每一加热线圈62可以被单独控制，或者，多层加热线圈62也可以作为一个整体被控制。
在一些实施例中，在降温阶段，同一沉积区域对应的多层加热线圈62的降温速率相同。示例地，同一温控单元61内的多层加热线圈62与同一控 制信号连接，即多层加热线圈62作为一个整体被控制，从而有利于简化温度控制过程。
在另一些实施例中，在降温阶段，且在腔室7的底部指向顶部的方向上，同一沉积区域对应的多层加热线圈62的降温速率依次增大。也就是说，分别控制同一温控单元61内的多层加热线圈62，以使得各加热线圈62的降温速率不同，从而在沉积区域内部实现更加精细化的控制，进而降低同一沉积区域内各膜层2的差异。即，一个沉积区域也由多个子区域构成，各子区域可以被单独控制。
举例而言，顶部区域52可以包括第一子区域521、第二子区域522、第三子区域523和第四子区域524。图15示出了在形成凸形膜层2时底部区域51对应的加热线圈62的温度变化曲线，图16示出了在形成凸形膜层2时第一子区域521对应的加热线圈62的温度变化曲线，图17示出了在形成凸形膜层2时第二子区域522对应的加热线圈62的温度变化曲线，图18在形成凸形膜层2时示出了第三子区域523对应的加热线圈62的温度变化曲线，图19示出了在形成凸形膜层2时第四子区域524对应的加热线圈62的温度变化曲线。参考图15-图19，在温度变化曲线中，第三时间段T3对应沉积处理的降温阶段。在降温阶段，底部区域51对应的加热线圈62可以处于恒温状态。第一至第四子区域524对应的加热线圈62的降温速率可以依次增大。因此，底部区域51以及第一至第四子区域524中的膜层2具有相对一致的凸起程度。此外，底部区域51也可以设置为多个子区域，且多个子区域的降温速率不同，从而实现对底部区域51的精细化控制。
在一些实施例中，沉积处理还包括：恒温阶段，基底1在恒温阶段的温度保持不变。也就是说，在恒温阶段和降温阶段，均向腔室7通入反应气体，因而膜层2的厚度在这两个阶段不断增加。在恒温阶段，基底1中心和基底1边缘的温度保持一致，因而沉积速率相同。设置恒温阶段有利于提升膜层2的质量。此外，恒温阶段可以后于降温阶段进行，或者恒温阶段可以先于降温阶段进行。继续参考图15-图19，第二时间段T2对应于恒温阶段。
在沉积处理前，还包括：预加热处理，以使基底1的温度达到沉积初始温度。沉积初始温度可以根据不同的膜层2材料进行设置，以提高沉积处理的速率。此外，沉积初始温度还可以根据沉积处理的变化情况进行设置， 比如，在沉积处理包括降温阶段时，则可以相应提高沉积初始温度，以避免温度过低而影响膜层2质量。继续参考图15-图19，第一时间段T1对应预加热处理。
示例地，预加热处理可以包括加热阶段和温度稳定阶段。在加热阶段，温控装置6的温度可以快速上升，以缩短预加热处理的时间。在温度稳定阶段，温控装置6的温度不变，以使得腔室7内的温度能保持稳定，从而有利于后续沉积处理形成高质量的膜层2。
在沉积处理后，还包括：冷却处理，以降低基底1的温度。即基底1的温度得以恢复，便于进行后续的制程。继续参考图15-图19，第四时间段T4对应冷却处理。
示例二，参考图20，图20中仅示意出半导体结构中的膜层2，而未示出基底1。在第一区A为基底1的中心，第二区B为基底1的边缘时，即基底1为凸形，需形成凹形的膜层2。
同理可知，温控装置6包括多个温控单元61，温控单元61与沉积区域一一对应设置；在升温阶段，且在腔室7的底部指向顶部的方向上，温控单元61的升温速率依次降低。如此，能够使得各沉积区域的基底1具有较为一致的升温速率，从而使得各沉积区域的膜层2具有相对一致的凹陷程度。
在一些实施例中，沉积区域包括底部区域51和顶部区域52。底部区域51对应的温控单元61的升温速率为1.5-2.2℃/min，比如，1.6℃/min、2℃/min或2.1℃/min。顶部区域52对应的温控单元61的升温速率小于1.5℃/min，比如1℃/min、0.8℃/min或0.5℃/min。在升温速率处于上述范围时，有利于提高膜层2顶面的平整度，且降低底部区域51的膜层2与顶部区域52的膜层2差异。
在一些实施例中，在升温阶段，同一沉积区域对应的多层加热线圈62的升温速率相同，从而有利于简化温度控制过程。
在另一些实施例中，在升温阶段，且在腔室7的底部指向顶部的方向上，同一沉积区域对应的多层加热线圈62的升温速率依次降低。即分别控制多层加热线圈62，从而在沉积区域内部实现更加精细化的控制，进而降低同一沉积区域内的膜层2的差异。
举例而言，顶部区域52可以包括第一子区域、第二子区域522、第三 子区域523和第四子区域524。图21示出了底部区域51对应的加热线圈62的温度变化曲线，图22示出了在形成凹形膜层2时第一子区域对应的加热线圈62的温度变化曲线，图23示出了在形成凹形膜层2时第二子区域522对应的加热线圈62的温度变化曲线，图24示出了在形成凹形膜层2时第三子区域523对应的加热线圈62的温度变化曲线，图25示出了在形成凹形膜层2时第四子区域524对应的加热线圈62的温度变化曲线。参考图21-图25，温度变化曲线中的第二时间段T2对应升温阶段。在升温阶段，底部区域51以及第一至第四子区域524对应的加热线圈62的升温速率依次降低。因此，底部区域51、第一至第四子区域524中的膜层2具有相对一致的凹陷程度。此外，底部区域51也可以设置为多个子区域，且多个子区域的升温速率不同，从而实现对底部区域51的精细化控制。
在一些实施例中，沉积处理还包括：恒温阶段，基底1在恒温阶段的温度保持不变。在恒温阶段，基底1中心和基底1边缘的温度保持一致，因而沉积速率相同。此外，恒温阶段可以后于升温阶段进行，或者恒温阶段也可以先于升温阶段进行。继续参考图21-图25，第三时间段T3对应于恒温阶段。
在沉积处理前，还包括：预加热处理，以使基底1的温度达到沉积初始温度。在沉积处理包括升温阶段时，则可以相应降低沉积初始温度，以避免温度过高而影响膜层2质量。继续参考图21-图25，第一时间段T1对应于预加热处理。预加热处理可以包括加热阶段快速升温阶段和温度稳定阶段，相关说明可以参考前述示例的详细说明。
在沉积处理后，还包括：冷却处理，以降低基底1的温度。即基底1的温度得以恢复，便于进行后续的制程。继续参考图21-图25，第四时间段T4对应于冷却处理。
综上所述，本公开实施例针对基底1表面不同高度的区域进行温度调节，从而在高度较低的区域形成更厚的膜层2，在高度较高的区域形成更薄的膜层2；即通过调节膜厚的分布以弥补基底1的翘曲问题，避免刻蚀后的图案出现尺寸以及间距不一的问题，有利于得到理想的图案。此外，在反应气体冷热分布不均的情况下，可以调整各沉积区域对应的温控单元61的温度变化速率，从而使得各沉积区域的基底1具有较为一致的温度变化速率， 以提高各沉积区域的膜层2的一致性。
在本说明书的描述中，参考术语“一些实施例”、“示例地”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
尽管上面已经示出和描述了本公开的实施例，可以理解的是，上述实施例是示例性的，不能理解为对本公开的限制，本领域的普通技术人员在本公开的范围内可以对上述实施例进行变化、修改、替换和变型，故但凡依本公开的权利要求和说明书所做的变化或修饰，皆应属于本公开专利涵盖的范围之内。

Claims (17)

  1. 一种半导体结构的制造方法，包括：
    提供基底，所述基底的正面包括第一区和第二区，所述第一区的高度大于所述第二区的高度；
    进行沉积处理，以在所述基底的正面形成膜层；在所述沉积处理中，所述第一区的温度小于所述第二区的温度；
    在所述膜层上形成光刻胶层，并对所述光刻胶层进行光刻处理；
    所述光刻处理后，以所述光刻胶层为掩膜，刻蚀所述膜层。
  2. 根据权利要求1所述的半导体结构的制造方法，其中，所述第一区为所述基底的边缘，所述第二区为所述基底的中心，所述第一区环绕所述第二区设置；
    在所述沉积处理中，通过调节温控装置自身的温度，以控制向所述基底传递的热量；所述温控装置与所述基底的边缘相对设置；
    所述沉积处理包括降温阶段，所述基底在所述降温阶段的温度降低。
  3. 根据权利要求2所述的半导体结构的制造方法，其中，
    所述沉积处理的腔室包括在高度方向排列的多个沉积区域，每一所述沉积区域可容纳在高度方向排列的多个所述基底；
    所述沉积处理的反应气体从腔室的底部进入所述腔室；
    所述温控装置包括多个温控单元，所述温控单元与所述沉积区域一一对应设置；在所述降温阶段，且在所述腔室的底部指向顶部的方向上，所述温控单元的降温速率依次增大。
  4. 根据权利要求3所述的半导体结构的制造方法，其中，所述沉积区域包括底部区域和顶部区域，所述底部区域对应的所述温控单元的降温速率小于0.5℃/min；所述顶部区域对应的温控单元的降温速率为0.5℃/min-2.2℃/min。
  5. 根据权利要求3所述的半导体结构的制造方法，其中，
    所述温控单元包括多层加热线圈；在所述降温阶段，同一所述沉积区域对应的多层所述加热线圈的降温速率相同。
  6. 根据权利要求3所述的半导体结构的制造方法，其中，
    所述温控单元包括多层加热线圈；在所述降温阶段，且在所述腔室 的底部指向顶部的方向上，同一所述沉积区域对应的多层加热线圈的降温速率依次增大。
  7. 根据权利要求2所述的半导体结构的制造方法，其中，所述沉积处理还包括：恒温阶段，所述基底在所述恒温阶段的温度保持不变。
  8. 根据权利要求1所述的半导体结构的制造方法，其中，所述第一区为所述基底的中心，所述第二区为所述基底的边缘，所述第二区环绕所述第一区设置；
    在所述沉积处理中，通过调节温控装置自身的温度，以控制向所述基底传递的热量；所述温控装置与所述基底的边缘相对设置；
    所述沉积处理包括升温阶段，所述基底在所述升温阶段的温度升高。
  9. 根据权利要求8所述的半导体结构的制造方法，其中，
    所述沉积处理的腔室包括在高度方向排列的多个沉积区域，每一所述沉积区域可容纳在高度方向排列的多个所述基底；
    所述沉积处理的反应气体从所述腔室的底部进入所述腔室；
    所述温控装置包括多个温控单元，所述温控单元与所述沉积区域一一对应设置；在所述升温阶段，且在所述腔室的底部指向顶部的方向上，所述温控单元的升温速率依次降低。
  10. 根据权利要求9所述的半导体结构的制造方法，其中，所述沉积区域包括底部区域和顶部区域，所述底部区域对应的温控单元的升温速率为1.5℃/min-2.2℃/min，所述顶部区域对应的温控单元的升温速率小于1.5℃/min。
  11. 根据权利要求9所述的半导体结构的制造方法，其中，
    所述温控单元包括多层加热线圈；在所述升温阶段，同一所述沉积区域对应的多层所述加热线圈的升温速率相同。
  12. 根据权利要求9所述的半导体结构的制造方法，其中，
    所述温控单元包括多层加热线圈；在所述升温阶段，且在所述腔室的底部指向顶部的方向上，同一所述沉积区域对应的多层加热线圈的升温速率依次降低。
  13. 根据权利要求8所述的半导体结构的制造方法，其中，所述沉积处理还包括：恒温阶段，所述基底在所述恒温阶段的温度保持不变。
  14. 根据权利要求1所述的半导体结构的制造方法，其中，在所述沉积处理中，所述第一区与所述第二区的温度差与所述第一区与所述第二区的高度差呈正比关系。
  15. 根据权利要求1所述的半导体结构的制造方法，其中，
    在所述沉积处理前，还包括：预加热处理，以使所述基底的温度达到沉积初始温度；
    在所述沉积处理后，还包括：冷却处理，以降低所述基底的温度。
  16. 根据权利要求15所述的半导体结构的制造方法，其中，
    所述预加热处理包括依次进行的加热阶段和温度稳定阶段。
  17. 根据权利要求1所述的半导体结构的制造方法，其中，所述沉积处理包括：低压化学气相沉积工艺、常压化学气相沉积工艺或原子层沉积工艺。
PCT/CN2022/113731 2022-06-02 2022-08-19 半导体结构的制造方法 WO2023231187A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210625185.X 2022-06-02
CN202210625185.XA CN117219492A (zh) 2022-06-02 2022-06-02 半导体结构的制造方法

Publications (1)

Publication Number Publication Date
WO2023231187A1 true WO2023231187A1 (zh) 2023-12-07

Family

ID=89026758

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/113731 WO2023231187A1 (zh) 2022-06-02 2022-08-19 半导体结构的制造方法

Country Status (2)

Country Link
CN (1) CN117219492A (zh)
WO (1) WO2023231187A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102121099A (zh) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 使用lpcvd工艺沉积薄膜的方法
CN102443786A (zh) * 2011-11-08 2012-05-09 上海华力微电子有限公司 一种改进等离子体增强化学汽相沉积薄膜均匀度的方法
CN102487037A (zh) * 2010-12-02 2012-06-06 上海华虹Nec电子有限公司 缓冲高温工艺中薄膜局部应力释放的方法
KR20170024211A (ko) * 2015-08-24 2017-03-07 세메스 주식회사 기판 지지 유닛, 기판 처리 장치, 그리고 기판 처리 방법
CN109273378A (zh) * 2018-09-20 2019-01-25 长江存储科技有限责任公司 平衡晶圆弯曲度分布的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102121099A (zh) * 2010-01-08 2011-07-13 中芯国际集成电路制造(上海)有限公司 使用lpcvd工艺沉积薄膜的方法
CN102487037A (zh) * 2010-12-02 2012-06-06 上海华虹Nec电子有限公司 缓冲高温工艺中薄膜局部应力释放的方法
CN102443786A (zh) * 2011-11-08 2012-05-09 上海华力微电子有限公司 一种改进等离子体增强化学汽相沉积薄膜均匀度的方法
KR20170024211A (ko) * 2015-08-24 2017-03-07 세메스 주식회사 기판 지지 유닛, 기판 처리 장치, 그리고 기판 처리 방법
CN109273378A (zh) * 2018-09-20 2019-01-25 长江存储科技有限责任公司 平衡晶圆弯曲度分布的方法

Also Published As

Publication number Publication date
CN117219492A (zh) 2023-12-12

Similar Documents

Publication Publication Date Title
US10113233B2 (en) Multi-zone temperature control for semiconductor wafer
US20130171746A1 (en) Multi-zone temperature control for semiconductor wafer
JP2023514497A (ja) 局所応力調整のためのｕｖ硬化
JPH09260470A (ja) サセプタおよび熱処理装置および熱処理方法
US9890455B2 (en) Pre-heat ring designs to increase deposition uniformity and substrate throughput
TWI841589B (zh) 用於減弱cvd和圖案化hvm系統的晶圓彎曲的方法和設備
CN109385623B (zh) 一种薄膜沉积方法和沉积薄膜
TW200924105A (en) A device for layered deposition of various materials on a semiconductor substrate, as well as a lift pin for use in such a device
US3314393A (en) Vapor deposition device
WO2023231187A1 (zh) 半导体结构的制造方法
WO2024077865A1 (zh) 一种改善翘曲的成膜方法
JP2023525710A (ja) Ｃｄ制御をパターン化するための自動化フィードフォワードおよびフィードバックシーケンス
US5439850A (en) Method for forming a layer of uniform thickness on a semiconductor wafer during rapid thermal processing
JP2002110654A (ja) 半導体装置の製造方法
JP3596312B2 (ja) 熱処理装置
JP5104192B2 (ja) レジスト塗布基板の熱処理装置及びその熱処理方法
JPS6053751B2 (ja) プラズマ処理装置
WO2022116481A1 (zh) 薄膜的炉管沉积方法及半导体器件
JP2000164588A (ja) 基板加熱方法及び装置
JP2014003164A (ja) 半導体装置の製造方法及び半導体装置並びに半導体装置の製造システム
CN114695088A (zh) 半导体结构及其形成方法
CN104752170B (zh) 双重图形化的形成方法
JP5042456B2 (ja) ステンシルマスクの製造方法
CN110331387A (zh) 一种化学气相沉积工艺
CN114300354B (zh) 一种非对称半导体结构的制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22944498

Country of ref document: EP

Kind code of ref document: A1