WO2022116481A1 - 薄膜的炉管沉积方法及半导体器件 - Google Patents

薄膜的炉管沉积方法及半导体器件 Download PDF

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WO2022116481A1
WO2022116481A1 PCT/CN2021/095463 CN2021095463W WO2022116481A1 WO 2022116481 A1 WO2022116481 A1 WO 2022116481A1 CN 2021095463 W CN2021095463 W CN 2021095463W WO 2022116481 A1 WO2022116481 A1 WO 2022116481A1
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temperature
thin film
deposition
furnace tube
annealing
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PCT/CN2021/095463
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English (en)
French (fr)
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黄其赞
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长鑫存储技术有限公司
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Priority to US17/438,831 priority Critical patent/US20230053417A1/en
Publication of WO2022116481A1 publication Critical patent/WO2022116481A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67248—Temperature monitoring
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/34—Nitrides
    • C23C16/345—Silicon nitride
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45523—Pulsed gas flow or change of composition over time
    • C23C16/45525—Atomic layer deposition [ALD]
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52—Controlling or regulating the coating process
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD

Definitions

  • the present disclosure relates to, but is not limited to, a thin film furnace tube deposition method and a semiconductor device.
  • the nitride layer in DRAM is mainly used for sidewall isolation, masking impurity ions, support and stop layer for chemical mechanical polishing. Due to the special structure of the furnace tube, the same thickness of film is deposited, and the temperature from the top to the bottom of the furnace tube is different. As a result, the density of the film is different. The film of the semiconductor device formed from the top to the bottom of the furnace tube has a large difference in the etching rate in the subsequent etching process. This difference affects the performance of the film and is not conducive to the stability of the etching process. Production yield.
  • the present disclosure provides a method for depositing a thin film in a furnace tube.
  • the deposition method makes the performance of the thin film formed by deposition in the furnace tube more consistent and stable, which is beneficial to improve the yield of products deposited on the furnace tube.
  • the method for depositing a thin film in a furnace tube includes: providing a deposition furnace tube, a process chamber in the furnace tube is divided into a plurality of process regions along an up-down direction, and a plurality of temperature controllers respectively correspond to the plurality of process regions one-to-one to separately control the temperature of a plurality of process regions; a substrate is provided, a thin film deposition process is performed on the substrate, and the temperature controller is controlled so that the set deposition temperature of the process region in the top-to-bottom direction is gradually gradient Decrease; perform the annealing process, and control the temperature controller, so that the set annealing temperature of the process area in the top-to-bottom direction increases gradually in a gradient.
  • the set deposition temperature of any two adjacent process regions gradually decreases in an equal gradient.
  • the temperature difference between the set deposition temperatures of any two adjacent process regions ranges from 2°C to 5°C.
  • the set deposition temperature of any two adjacent process regions gradually decreases in an equal gradient.
  • the temperature difference between the set annealing temperatures of any two adjacent process regions ranges from 2°C to 5°C.
  • the set annealing temperature of any two adjacent processing regions is gradually increased in an equal gradient.
  • the set annealing temperature of any two adjacent processing regions is gradually increased in an equal gradient.
  • the temperature gradient value of the set deposition temperature of any two adjacent said process regions and the constant gradient of the set annealing temperature of any two adjacent process regions are the same gradient value.
  • the temperature gradient values are the same.
  • the set deposition temperature of the process area in the top-to-bottom direction is the same as the set anneal temperature of the process area in the bottom-to-top direction when the annealing process is performed
  • the set annealing temperature of the process region and the set deposition temperature of the process region are greater than or equal to 500°C and less than or equal to 650°C.
  • the maximum value of the set deposition temperature in performing the thin film deposition process and the maximum value of the set annealing temperature in performing the annealing process is a predetermined maximum temperature.
  • the predetermined maximum temperature may be 650°C.
  • the minimum value of the set deposition temperature in performing the thin film deposition process and the minimum value of the set annealing temperature in performing the annealing process is a predetermined minimum temperature.
  • the predetermined minimum temperature may be 500°C.
  • the time for performing the annealing process is 120min-300min.
  • the furnace tube deposition method when performing the annealing process, further includes passing an inert gas into the furnace tube.
  • the thin film is a silicon nitride thin film.
  • the thin film deposition process includes an atomic layer deposition process or a low pressure chemical vapor deposition method.
  • the thin film is deposited and formed on the surface of the substrate, the thin film is a continuous plane, and in the deposition process of the thin film, the set deposition of any two adjacent process regions There is a first temperature difference between the temperatures; in the annealing process of the thin film, there is a second temperature difference between the set annealing temperatures of any two adjacent process regions; the first temperature difference is greater than the second temperature difference.
  • a trench is formed on the substrate, the thin film is formed on the surface of the trench and extends along the surface of the substrate, and during the deposition process of the thin film, any adjacent
  • the third temperature difference is not greater than the fourth temperature difference.
  • a semiconductor device including a substrate and a thin film disposed on a surface of the substrate, the thin film formed according to the furnace tube deposition method of the thin film described in the present disclosure.
  • the temperature controller is controlled so that the set deposition temperature of each process area in the top-to-bottom direction is gradient Gradually decrease, so that the thickness of the thin film formed on the substrate surface of each process area is the same, and the annealing process is performed after the deposition process, and each temperature controller is controlled so that the set annealing temperature of each process area is gradient from top to bottom Gradually increasing, so that the properties of the films in each process area are consistent, for example, the ion blocking ability of the films formed by the substrates in different process areas is consistent, so that the thickness and properties of the deposited films in each process area can be consistent, so as to improve product yield .
  • FIG. 1 is a schematic process flow diagram of a furnace tube deposition method of a thin film according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a furnace tube of a thin-film furnace tube deposition method according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a substrate located in an upper process area after performing thin film deposition and performing an annealing process in a furnace tube deposition method for a thin film according to an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a substrate located in a lower process area after performing thin film deposition and performing an annealing process in a furnace tube deposition method for a thin film according to an embodiment of the present disclosure
  • FIG. 5 is a graph showing the etching rate of the thin film formed on the substrates in each process area under different annealing process conditions
  • FIG. 6 is a schematic structural diagram of a semiconductor device of one embodiment of depositing a thin film according to the furnace tube deposition method of the thin film of the present disclosure
  • FIG. 7 is a schematic structural diagram of a semiconductor device of another embodiment of depositing a thin film according to the furnace tube deposition method of the thin film of the present disclosure.
  • Furnace tube 100: Furnace body, 200: Process chamber, 300: Crystal boat; 400: Temperature controller; 201-204: Process area;
  • a method for depositing a furnace tube 1000 of a thin film 2 may include: providing a furnace tube 1000 , and a process chamber 200 in the furnace tube 1000 is divided into a plurality of process areas 201 - 204
  • Each temperature controller 400 corresponds to a plurality of process areas 201-204 in one-to-one correspondence to control the temperature of the plurality of process areas respectively; a substrate 1 is provided, the film 2 deposition process is performed on the substrate 1, and each temperature controller 400 is controlled such that The set deposition temperature in the process area from top to bottom gradually decreases; the annealing process is performed, and each temperature controller 400 is controlled so that the set annealing temperature in the process area from top to bottom gradually increases gradually.
  • the deposition furnace tube 1000 may include a temperature controller 400, a furnace body 100, a process chamber 200 and a wafer boat 300.
  • the wafer boat 300 is used for placing and providing It should be noted that the substrate 1 here can be a bare chip without a device or a semiconductor device with a device layer.
  • the process chamber 200 is formed in the furnace body 100, and can be divided into a plurality of process areas 201-204 in the up-down direction, the plurality of process areas are connected, and there are a plurality of temperature controllers 400, and the plurality of temperature controllers 400 are respectively connected to
  • the multiple process areas are set in one-to-one correspondence, and the temperature of the multiple process areas can be controlled, so as to set the temperature of the multiple process areas according to the needs of the process in different process stages.
  • a plurality of process regions are schematically marked with dotted lines, but this does not mean that in practical applications, the process chamber 200 is actually divided into a plurality of process regions, but for the convenience of drawing It is shown that a plurality of temperature controllers 400 can individually control the temperature of their one-to-one corresponding process areas.
  • the temperature controller 400 is controlled so that the set deposition temperature of the process area in the top-to-bottom direction gradually decreases gradually, and the set deposition temperature of the process area located at the bottom decreases gradually.
  • the set deposition temperature is the lowest, and the set deposition temperature of the uppermost process area is the highest.
  • the process chamber 200 may be four process areas, and each process area in the top-to-bottom direction is the first process area 201 , the second process area 202 , the third process area 203 and the fourth process area 204 , and the temperature controller 400 It is a first temperature controller 401 , a second temperature controller 402 , a third temperature controller 403 and a fourth temperature controller 404 .
  • T1 When performing the thin film 2 deposition process, set the first temperature controller 401 to control the set deposition temperature of the first process area 201 to be T1, set the second temperature controller 402 to control the set deposition temperature of the second process area 202 to be T2, Set the third temperature controller 403 to control the set deposition temperature of the third process area 203 to be T3, and set the fourth temperature controller 404 to control the set deposition temperature of the fourth process area 204 to be T4, then T1, T2, T3, T4 Satisfaction: T4 ⁇ T3 ⁇ T2 ⁇ T1.
  • the gas flow rate and gas concentration of the reactive gas flowing in the upper and lower directions in the process chamber 200 are different in each process area, resulting in different thicknesses of the deposited films 2, resulting in the deposition of the substrate 1 on the wafer boat 300.
  • the thickness and performance of the formed film 2 are inconsistent.
  • the deposition temperature is set to decrease in a gradient from top to bottom. The higher the temperature, the greater the deposition rate, the larger the thickness of the film 2, and the lower the temperature.
  • the annealing process is performed after the deposition process, and each temperature controller 400 is controlled so that the set annealing temperature of the process area in the top-to-bottom direction gradually increases gradually, the set annealing temperature of the process area located at the bottom is the highest, and the set annealing temperature of the process area located at the bottom is the highest.
  • the upper process region has the lowest set anneal temperature.
  • the set annealing temperature of the first process area 201 is controlled by the first temperature controller 401 to be T5
  • the set annealing temperature of the second process area 202 is controlled by the second temperature controller 402 to be T6
  • the set annealing temperature of the second process area 202 is controlled by the third temperature controller 402.
  • T5 ⁇ T6 ⁇ T7 ⁇ T8 controls the set annealing temperature of the third process area 203 to be T7, and controls the set annealing temperature of the fourth process area 204 to be T8 by the fourth temperature controller 404, then T5, T6, T7, T8 satisfy: T5 ⁇ T6 ⁇ T7 ⁇ T8.
  • FIG. 4 is a schematic diagram of the top process area (top), and the surface of the substrate 1 is deposited to form a thin film 2.
  • FIG. 5 is a schematic diagram of the bottom process area (BTM, bottom) of the substrate 1. Therefore, with reference to FIGS. 4-5 , by controlling the set annealing temperature of the process area to gradually increase from top to bottom when performing annealing, the film 2 in each process area has better compactness and consistent performance. For example, the ion blocking capability of the thin films 2 formed on the substrates 1 in different process regions can be consistent, so that the thickness and properties of the deposited thin films 2 in each process region can be consistent, so as to improve the product yield.
  • the time for performing the annealing process is 120min-300min, and the flow rate of the gas introduced during the annealing process, such as nitrogen, may be 0.1-0.3slm; when performing the annealing process, it also includes introducing an inert gas into the furnace tube 1000, so as to provide annealing
  • the process provides a relatively stable annealing environment.
  • the temperature difference of the set deposition temperature in the process area ranges from 2°C to 5°C. That is, the temperature difference between the set deposition temperature of any two adjacent process areas is 2°C-5°C, and the temperature of the set deposition area in the control process area is gradually decreased at a gradient of 2°C-5°C in the direction from top to bottom.
  • the size of the decreasing temperature gradient can be set according to the size of each process area and the position in the up-down direction.
  • the set deposition temperature of the process area gradually decreases in an equal gradient, that is, the temperature difference between the set deposition temperatures of any two adjacent process areas is the same, and the set deposition temperature of the process area is in the top-to-bottom direction with a temperature gradient.
  • the value decreases in an equal gradient. For example, if the temperature gradient value of any two adjacent process areas is 2°C, the process area decreases with a 2°C temperature gradient in the direction from top to bottom. Any process area and the adjacent process area.
  • the temperature difference is 2°C.
  • the temperature difference of the set annealing temperature in the process area can be 2°C-5°C. That is, the temperature difference of the set annealing temperature of any two adjacent process areas is 2°C-5°C, and the temperature of the set annealing zone in the control process area is gradually controlled in a temperature gradient of 2°C-5°C in the direction from top to bottom.
  • the size of the increasing and decreasing temperature gradients can be set according to the size of each process area in the up and down direction.
  • the set annealing temperature in the process area is gradually increased in an equal gradient, that is, the temperature difference between the set annealing temperatures of any two adjacent process areas is the same, and the set annealing temperature in the process area has a temperature gradient in the direction from top to bottom.
  • the value increases in an equal gradient. For example, if the temperature gradient value of any two adjacent process areas is 2°C, the process area increases with a 2°C temperature gradient in the direction from top to bottom. Any process area and the adjacent process area.
  • the temperature difference is 2°C.
  • the set deposition temperature of the process region in the top-to-bottom direction is the same as the set anneal temperature of the process region in the bottom-to-top direction when the annealing process is performed .
  • the process chamber 200 can be divided into four process regions.
  • the set deposition temperatures in the process region from top to bottom are respectively T1, T2, T3, and T4.
  • the set annealing temperatures in the process area in the top-to-bottom direction are T4, T3, T2, T1, respectively, which are opposite to the temperature when the deposition process is performed, so that the thickness of the thin film 2 formed on the surface of the substrate 1 in the different process areas and The properties are more consistent, and the etching rate is more consistent when the etching process is subsequently performed.
  • Figure 3 shows the etching rate curve of thin film 2 under different set deposition temperature and annealing temperature conditions in each process area, the ordinate is the etching rate, the abscissa is each process area (Chamber ID), CH1, CH2, CH3, CH4 and CH5 represent each process area.
  • Line A is a graph of the etching rate of the thin film 2 in each process area when the annealing process is not performed
  • line B is the thin film when the set annealing temperature of each process area when the annealing process is performed is the same as the set deposition temperature when the deposition process is performed
  • the etch rate curve diagram of 2 that is, the etch rate curve diagram of the thin film 2 in each process area when the set annealing temperature of each process area decreases in a gradient from top to bottom when the annealing process is performed.
  • Line C is a graph of the etching rate of the thin film 2 in each process area when the set annealing temperature of each process area is opposite to the set deposition temperature when the deposition process is performed when the annealing process is performed. It can be seen that when the annealing process is controlled to set the annealing temperature in the top-to-bottom direction to increase in a gradient, the etching rate of the thin film 2 formed on the surface of the substrate 1 in each process
  • the set deposition temperature of each process area may be the same as the isogradiently increasing temperature gradient value of the set annealing temperature of each process area when performing the annealing process. Therefore, the obtained thickness and performance of the thin film 2 of the substrate 1 in each process area are more consistent.
  • the set annealing temperature of each process area and the set deposition temperature of each process area are greater than or equal to 500°C and less than or equal to 650°C.
  • the maximum value of the set deposition temperature in the execution of the thin film 2 deposition process and the maximum set of the annealing temperature in the execution of the annealing process is a predetermined maximum temperature, that is, the set in the execution of the thin film 2 deposition process
  • the maximum value of the deposition temperature may be equal to the maximum value of the set annealing temperature in performing the annealing process, and may be set to a predetermined maximum temperature, and the predetermined maximum temperature may be 650°C.
  • the minimum value of the set deposition temperature in performing the thin film 2 deposition process may be equal to the minimum value of the set annealing temperature in performing the annealing process, and the set deposition temperature in the thin film 2 deposition process is performed.
  • the minimum value between the minimum value and the set annealing temperature in performing the annealing process may be a predetermined minimum temperature, and the predetermined minimum temperature may be 500°C.
  • the thin film 2 deposition process may include an atomic layer deposition process or a low pressure chemical vapor deposition method, but is not limited thereto, and can also be applied to deposition furnace tubes by adjusting reaction conditions, reaction gases, etc.
  • the thin film 2 formed in the embodiment of the present disclosure may be a silicon nitride film or the like.
  • the film 2 is deposited on the surface of the substrate 1 , and the surface of the deposited film 2 is a flat and continuous plane.
  • the deposition process of the film 2 there is a first temperature difference between the set deposition temperatures of any two adjacent process regions; in the annealing process of the thin film 2 , there is a second temperature difference between the set annealing temperatures of any two adjacent process regions.
  • the first temperature difference can be greater than the second temperature difference.
  • the first temperature difference for setting the deposition temperature during the deposition process of the film 2 is relatively large, which is beneficial to the formation of the film 2 and improves the deposition rate of the film 2. and the thickness of the thin film 2, the uniformity of the formed thin film 2 is better, and the temperature difference of the set annealing temperature in each process area is controlled to be relatively small during the annealing process, which can make the formed thin film 2 denser and have better performance.
  • the film 2 covers the surface of the substrate 1 and the inner wall surface of the trench 3 without forming a continuous plane.
  • the film 2 covers the surface of the substrate 1 and the inner wall surface of the trench 3 without forming a continuous plane.
  • the deposition process of the film 2 there is a difference between the set deposition temperatures of any two adjacent process regions.
  • the third temperature difference in the annealing process of the thin film 2, there is a fourth temperature difference between the set annealing temperatures of any two adjacent process areas; the third temperature difference is not greater than the fourth temperature difference, that is, the third temperature difference can be less than or equal to the fourth temperature difference , the thickness of the film 2 formed at this time is small.
  • the temperature difference between the set deposition temperatures of any two adjacent process areas is small, so that the deposition rate of the film 2 is relatively small, which is conducive to control
  • the thickness and deposition rate of the film 2 are formed, and during the annealing process, the temperature difference between the set annealing temperatures of any two adjacent process regions is greater than or equal to the temperature difference of the set deposition temperature, so that the film 2 can be formed more densely and has better performance. .
  • the thin film furnace tube deposition method and semiconductor device provided by the present disclosure perform a thin film deposition process on a substrate, and control a temperature controller, so that the set deposition temperature of the process area in the top-to-bottom direction is gradually gradient Decrease; perform the annealing process, and control each of the temperature controllers, so that the set annealing temperature of each of the process areas in the top-to-bottom direction increases gradually in a gradient, so that the thickness and performance of the film formed after deposition in the furnace tube are more consistent. Stable and improved product yield.

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Abstract

该公开公开了一种薄膜的炉管沉积方法及半导体器件，所述薄膜的炉管沉积方法包括：提供沉积炉管，所述炉管内的制程腔沿上下方向分为多个制程区域，多个温度控制器分别与多个制程区域一一对应以分别控制多个制程区域的温度；提供衬底，对所述衬底执行薄膜沉积工艺，控制各所述温度控制器，使得从上至下方向上的各所述制程区域的设定沉积温度呈梯度逐渐递减；执行退火工艺，控制各所述温度控制器，使得从上至下方向上的各所述制程区域的设定退火温度呈梯度逐渐递增。

Description

薄膜的炉管沉积方法及半导体器件
本公开要求在2020年12月3日提交中国专利局、申请号为202011394386.0、发明名称为“薄膜的炉管沉积方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种薄膜的炉管沉积方法及半导体器件。
背景技术
氮化物层在DRAM中的主要用于侧壁隔离、掩蔽杂质离子、支撑以及化学机械研磨的停止层，由于炉管的特殊结构，沉积相同厚度的薄膜，炉管顶部到底部的温度不相同，导致薄膜密度不同，从炉管顶部到底部形成的半导体器件的薄膜在后续的刻蚀过程中，刻蚀速率存在较大的差异，这种差异影响薄膜性能且不利于刻蚀制程的稳定，降低生产良率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开提供一种薄膜的炉管沉积方法，所述沉积方法使得炉管内沉积形成的薄膜性能较为一致稳定，有利于提高炉管沉积的产品良率。
根据本公开实施例的薄膜的炉管沉积方法包括：提供沉积炉管，所述炉管内的制程腔沿上下方向分为多个制程区域，多个温度控制器分别与多个制程区域一一对应以分别控制多个制程区域的温度；提供衬底，对所述衬底执行薄膜沉积工艺，控制所述温度控制器，使得从上至下方向上的所述制程区域的设定沉积温度呈梯度逐渐递减；执行退火工艺，控制所述温度控制器，使得从上至下方向上的所述制程区域的设定退火温度呈梯度逐渐递增。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定沉积温度呈等梯度逐渐递减。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定沉积温度的温差范围为2℃-5℃。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定沉积温度呈等梯度逐渐递减。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定退火温度的温差范围为2℃-5℃。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定退火温度呈等梯度逐渐递增。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定退火温度呈等梯度逐渐递增。
根据本公开的一些实施例，任意相邻两个所述制程区域的设定沉积温度的等梯度递减的温度梯度值与任意相邻两个所述制程区域的设定退火温度的等梯度递增的温度梯度值相同。
根据本公开的一些实施例，执行薄膜沉积工艺时，在从上至下的方向上制程区域的设定沉积温度与执行退火工艺时在从下至上方向上的制程区域的设定退火温度相同
根据本公开的一些实施例，所述制程区域的设定退火温度和所述制程区域的设定沉积温度大于等于500℃且小于等于650℃。
根据本公开的一些实施例，执行薄膜沉积工艺中的设定沉积温度的最大值与执行退火工艺中的设定退火温度的最大值为预定的最高温度。
所述预定的最高温度可以为650℃。
根据本公开的一些实施例，执行薄膜沉积工艺中的设定沉积温度的最小值与执行退火工艺中的设定退火温度的最小值为预定的最低温度。
所述预定的最低温度可以为500℃。
根据本公开的一些实施例，执行退火工艺的时间为120min-300min。
根据本公开的一些实施例，在执行退火工艺时，所述炉管沉积方法还包括向所述炉管内通入惰性气体。
根据本公开的一些实施例，所述薄膜为氮化硅薄膜。
根据本公开的一些实施例，所述薄膜沉积工艺包括原子层沉积工艺或低压 力化学气相沉积法。
根据本公开的一些实施例，所述薄膜沉积形成在所述衬底的表面，所述薄膜为连续的平面，所述薄膜的沉积工艺中，任意相邻两个所述制程区域的设定沉积温度之间具有第一温差；所述薄膜的退火工艺中，任意相邻两个所述制程区域的设定退火温度之间具有第二温差；所述第一温差大于所述第二温差。
根据本公开的一些实施例，所述衬底上形成有沟槽，所述薄膜形成在所述沟槽的表面并沿所述衬底的表面延伸，所述薄膜的沉积工艺中，任意相邻两个所述制程区域的设定沉积温度之间具有第三温差；所述薄膜的退火工艺中，任意相邻两个所述制程区域的设定退火温度之间具有第四温差；所述第三温差不大于所述第四温差。
根据本公开的一些实施例，提供了一种半导体器件，所述半导体器件包括衬底和设置在所述衬底表面的薄膜，所述薄膜根据本公开所述的薄膜的炉管沉积方法形成。
根据本公开实施例的薄膜的炉管沉积方法，在衬底置于沉积炉管内执行薄膜沉积工艺时，控制温度控制器使得从上至下方向上的各所述制程区域的设定沉积温度呈梯度逐渐递减，以使得各制程区域的衬底表面形成薄膜的厚度相同，在沉积工艺后执行退火工艺，控制各温度控制器使得从上至下方向上的各所述制程区域的设定退火温度呈梯度逐渐递增，使得各制程区域的薄膜的性质一致，例如使得不同制程区域的衬底形成的薄膜的阻挡离子能力一致，进而使得各制程区域沉积薄膜的厚度和性质能够保持一致，以提高产品良率。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为根据本公开实施例的薄膜的炉管沉积方法的工艺流程示意图；
图2为根据本公开实施例的薄膜的炉管沉积方法的炉管的结构示意图；
图3是根据本公开实施例的薄膜的炉管沉积方法的位于上方制程区域的衬底执行薄膜沉积和执行退火工艺后的结构示意图；
图4是根据本公开实施例的薄膜的炉管沉积方法的位于下方制程区域的衬底执行薄膜沉积和执行退火工艺后的结构示意图；
图5是各制程区域的衬底在不同退火工艺的条件下的形成薄膜的刻蚀率曲线图；
图6是根据本公开的薄膜的炉管沉积方法沉积薄膜的一个实施例的半导体器件的结构示意图；
图7是根据本公开的薄膜的炉管沉积方法沉积薄膜的另一个实施例的半导体器件的结构示意图。
附图标记：
1000：炉管，100：炉体，200：制程腔，300：晶舟；400：温度控制器；201-204：制程区域；
1：衬底，2：薄膜，3：沟槽。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
以下结合附图和具体实施方式对本公开提出的一种薄膜的炉管沉积方法进行说明。
如图1所示，根据本公开实施例的薄膜2的炉管1000沉积方法可以包括：提供炉管1000，炉管1000内的制程腔200沿上下方向分为多个制程区域201-204，多个温度控制器400分别与多个制程区域201-204一一对应以分别控制多个制程区域的温度；提供衬底1，对衬底1执行薄膜2沉积工艺，控制各温 度控制器400，使得从上至下方向上的制程区域的设定沉积温度呈梯度逐渐递减；执行退火工艺，控制各温度控制器400，使得从上至下方向上的制程区域的设定退火温度呈梯度逐渐递增。
如图2所示为半导体器件的制程工艺常用的立式沉积炉管1000，沉积炉管1000可以包括温度控制器400、炉体100、制程腔200和晶舟300，晶舟300用于放置提供的衬底1，需要说明说明的是这里的衬底1可以为未形成器件的裸片也可以为具有器件层的半导体器件。
制程腔200形成在炉体100内，且在上下方向上可分为多个制程区域201-204，多个制程区域是相通的，温度控制器400为多个，多个温度控制器400分别与多个制程区域一一对应设置，能够控制多个制程区域的温度，以在不同工艺阶段根据工艺需要设置多个制程区域的温度。在图1中，为了便于理解，以虚线方式示意性地标示出多个制程区域，但是这并不代表着在实际应用中，制程腔200被实际划分为多个制程区域，而是为了便于图示多个温度控制器400可以单独控制其一一对应的制程区域的温度。在衬底1置于沉积炉管1000内执行薄膜2沉积工艺时，控制温度控制器400使得从上至下方向上的制程区域的设定沉积温度呈梯度逐渐递减，位于最下方的制程区域的设定沉积温度最低，位于最上方的制程区域的设定沉积温度最高。例如制程腔200可以为四个制程区域，在从上至下的方向各制程区域为第一制程区域201、第二制程区域202、第三制程区域203和第四制程区域204，温度控制器400为第一温度控制器401、第二温度控制器402、第三温度控制器403和第四温度控制器404。在执行薄膜2沉积工艺时，设置第一温度控制器401控制第一制程区域201的设定沉积温度为T1，设置第二温度控制器402控制第二制程区域202的设定沉积温度为T2，设置第三温度控制器403控制第三制程区域203的设定沉积温度为T3，设置第四温度控制器404控制第四制程区域204的设定沉积温度为T4，则T1、T2、T3、T4满足：T4＜T3＜T2＜T1。
在执行沉积工艺时制程腔200内在上下方向的通入的反应气体在各制程区域的气体流速以及气体浓度是不同的，从而造成沉积的薄膜2的厚度不同，导致晶舟300上衬底1沉积后形成的薄膜2厚度和性能不一致，通过控制制程区域的温度在从上至下的方向上设定沉积温度成梯度递减，温度越高、沉积速率越大，薄膜2厚度越大，温度越低、沉积速率越小，薄膜2厚度越小，以控制 各制程区域的沉积速率，使得不同制程区域的衬底1的表面沉积的薄膜2厚度相同，以提高产品良率。
在沉积工艺后执行退火工艺，控制各温度控制器400使得从上至下方向上的所述制程区域的设定退火温度呈梯度逐渐递增，位于最下方的制程区域的设定退火温度最高，位于最上方的制程区域的设定退火温度最低。例如，通过第一温度控制器401控制第一制程区域201的设定退火温度为T5，通过第二温度控制器402控制第二制程区域202的设定退火温度为T6，通过第三温度控制器403控制第三制程区域203的设定退火温度为T7，通过第四温度控制器404控制第四制程区域204的设定退火温度为T8，则T5、T6、T7、T8满足：T5＜T6＜T7＜T8。
由于执行沉积工艺时控制各制程区域的沉积设定温度不同，不同沉积设定温度条件下执行沉积反应也导致了沉积形成的薄膜2性能不同，在执行退火工艺时，与执行沉积工艺时温度控制不同，在执行沉积工艺中制程区域的设定沉积温度相对较高的，在执行退火工艺时设定退火温度相对较低，在执行沉积工艺中制程区域的设定沉积温度相对较低，在执行退火工艺时设定退火温度相对较高。图4是位于最上方制程区域(top)，衬底1表面沉积形成薄膜2的示意图，图5是位于最下方制程区域(BTM，bottom)，衬底1表面沉积形成薄膜2的示意图。由此，结合图4-图5所示，通过在执行退火时控制制程区域的设定退火温度从上至下呈梯度逐渐递增，从而使得各制程区域的薄膜2致密性更好且性能一致，例如，使得不同制程区域的衬底1形成的薄膜2的阻挡离子能力一致，进而使得各制程区域沉积薄膜2的厚度和性质能够保持一致，以提高产品良率。
执行退火工艺的时间为120min-300min，执行退火工艺时通入的气体例如氮气的流速可以为0.1-0.3slm；在执行退火工艺时，还包括向炉管1000内通入惰性气体，从而为退火工艺提供较为稳定的退火环境。
在本公开的一些实施例，制程区域的设定沉积温度的温差范围为2℃-5℃。即任意相邻两个制程区域的设定沉积温度的温差范围为2℃-5℃，在从上至下的方向上控制制程区域的设定沉积区域温度以2℃-5℃呈梯度逐渐递减，递减温度梯度的大小可以根据各制程区域的大小和在上下方向的位置进行设置。
制程区域的设定沉积温度呈等梯度逐渐递减，即任意相邻两个制程区域的设定沉积温度的温度差相同，制程区域的设定沉积温度在从上至下的方向上以一温度梯度值呈等梯度递减，例如，任意相邻两个制程区域的温度梯度值为2℃，则制程区域在从上至下的方向以2℃温度差梯度递减，任一制程区域与相邻制程区域的温度差均为2℃。
对于退火设定温度，制程区域的设定退火温度的温差范围可以为2℃-5℃。即任意相邻两个制程区域的设定退火温度的温差范围为2℃-5℃，在从上至下的方向上控制制程区域的设定退火区域温度呈温度梯度2℃-5℃梯度逐渐递增，递减温度梯度的大小可以根据各制程区域的大小在上下方向的位置进行设置。
制程区域的设定退火温度呈等梯度逐渐递增，即任意相邻两个制程区域的设定退火温度的温度差相同，制程区域的设定退火温度在从上至下的方向上以一温度梯度值呈等梯度递增，例如，任意相邻两个制程区域的温度梯度值为2℃，则制程区域在从上至下的方向以2℃温度差梯度递增，任一制程区域与相邻制程区域的温度差均为2℃。
在本公开的一些实施例中，执行沉积工艺时，在从上至下的方向上，制程区域的设定沉积温度与执行退火工艺时在从下至上方向上的制程区域的设定退火温度相同。如图2所示，制程腔200可分为四个制程区域，执行沉积工艺时，在从上至下的方向制程区域的设定沉积温度分别为T1、T2、T3、T4，执行退火工艺时，在从上至下的方向上制程区域的设定退火温度分别为T4、T3、T2、T1，与执行沉积工艺时温度相反，进而使得不同制程区域的衬底1表面形成的薄膜2厚度和性质更为一致，在后续执行刻蚀工艺时，刻蚀率较为一致。
图3所示为各制程区域不同的设定沉积温度和退火温度条件下薄膜2的刻蚀率曲线图，纵坐标为刻蚀率，横坐标为各制程区域(Chamber ID)，CH1，CH2，CH3，CH4和CH5表示各制程区域。线条A为不执行退火工艺时各制程区域的薄膜2的刻蚀率的曲线图，线条B为执行退火工艺时各制程区域的设定退火温度与执行沉积工艺时设定沉积温度相同时的薄膜2的刻蚀率曲线图，即执行退火工艺时各制程区域的设定退火温度在从上至下的方向上呈梯度递减时的各制程区域的薄膜2的刻蚀率曲线图。线条C为执行退火工艺时各制程区域的设定退火温度与执行沉积工艺时设定沉积温度相反时，各制程区域的薄膜2 的刻蚀率曲线图。由此可知，在执行退火工艺时控制各制程区域在从上至下的方向上设定退火温度呈梯度递增时，各制程区域的衬底1表面形成的薄膜2的刻蚀率较为一致。
执行沉积工艺时各制程区域的设定沉积温度的等梯度递减的温度梯度值可与执行退火工艺时各制程区域的设定退火温度的等梯度递增的温度梯度值相同。从而更够使得获取的各制程区域的衬底1的薄膜2厚度和性能更为一致。
各制程区域的设定退火温度和各制程区域的设定沉积温度大于等于500℃且小于等于650℃。在一些实施例中，在执行薄膜2沉积工艺中的设定沉积温度的最大值与执行退火工艺中的设定退火温度的最大值为预定的最高温度，即执行薄膜2沉积工艺中的设定沉积温度的最大值与执行退火工艺中的设定退火温度的最大值可以相等，可以设定为预定的最高温度，预定的最高温度可以为650℃。
在本公开的一些实施例，执行薄膜2沉积工艺中的设定沉积温度的最小值与执行退火工艺中的设定退火温度的最小值可以相等，执行薄膜2沉积工艺中的设定沉积温度的最小值与执行退火工艺中的设定退火温度的最小值可以为预定的最低温度，预定的最低温度可以为500℃。
在本公开的一些实施例中，薄膜2沉积工艺可包括原子层沉积工艺或低压力化学气相沉积法，但也不限于此，通过调整反应条件、反应气体等也可应用于适于沉积炉管1000的其它制程，本公开实施例中形成的薄膜2可以为氮化硅膜等。
在本公开的一些实施例中，对于沉积薄膜厚度较厚的器件，如图6所示，薄膜2沉积形成在衬底1表面，且沉积薄膜2表面为平整连续的平面，薄膜2的沉积工艺中，任意相邻两个制程区域的设定沉积温度之间具有第一温差；薄膜2的退火工艺中，任意相邻两个制程区域的设定退火温度之间具有第二温差。第一温差可以大于第二温差，由于沉积薄膜2的厚度相对较大，在薄膜2沉积工艺时设定沉积温度的第一温差相对设置较大，有利于薄膜2的形成，提高薄膜2沉积速率和薄膜2厚度，使得形成的薄膜2均匀性更好，在退火工艺时控制各制程区域的设定退火温度的温差相对较小，能够使得形成薄膜2更加致密，性能更好。
在本公开的一些实施例中，对于沉积薄膜厚度较薄的器件，如图7所示，衬底1上形成有沟槽3，薄膜2形成在沟槽3的表面并沿衬底1的表面延伸，即薄膜2覆盖衬底1的表面和沟槽3的内壁面，而不形成连续的平面，此时薄膜2的沉积工艺中，任意相邻两个制程区域的设定沉积温度之间具有第三温差；薄膜2的退火工艺中，任意相邻两个制程区域的设定退火温度之间具有第四温差；第三温差不大于第四温差，即第三温差可以小于或等于第四温差，此时形成的薄膜2厚度较小，在薄膜2的沉积工艺中，任意相邻两个制程区域的设定沉积温度的温差较小，使得薄膜2的沉积速率相对相差较小，有利于控制形成薄膜2的厚度和沉积速率，而且在退火工艺时，任意相邻两个制程区域的设定退火温度的温差大于等于设定沉积温度的温差，从而使得形成薄膜2能够更加致密，性能更好。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。
工业实用性
本公开所提供的薄膜的炉管沉积方法以及半导体器件，炉管沉积方法，对衬底执行薄膜沉积工艺，控制温度控制器，使得从上至下方向上的制程区域的设定沉积温度呈梯度逐渐递减；执行退火工艺，控制各所述温度控制器，使得从上至下方向上的各所述制程区域的设定退火温度呈梯度逐渐递增，使得炉管内沉积后形成的薄膜的厚度和性能较为一致稳定，提高了产品良率。

Claims (20)

  1. 一种薄膜的炉管沉积方法，其中，所述薄膜的炉管沉积方法包括：
    提供炉管(1000)，所述炉管内的制程腔(200)沿上下方向分为多个制程区域(201-204)，多个温度控制器(400)分别与多个制程区域(201-204)一一对应以分别控制多个制程区域的温度；
    提供衬底(1)，对所述衬底(1)执行薄膜沉积工艺，控制所述温度控制器(400)，使得从上至下方向上的所述制程区域(201-204)的设定沉积温度呈梯度逐渐递减；
    执行退火工艺，控制所述温度控制器(400)，使得从上至下方向上的所述制程区域(201-204)的设定退火温度呈梯度逐渐递增。
  2. 根据权利要求1所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域(201-204)的设定沉积温度的温差范围为2℃-5℃。
  3. 根据权利要求1所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域(201-204)的设定沉积温度呈等梯度逐渐递减。
  4. 根据权利要求1所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域(201-204)的设定退火温度的温差范围为2℃-5℃。
  5. 根据权利要求1所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域的设定退火温度呈等梯度逐渐递增。
  6. 根据权利要求3所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域(201-204)的设定退火温度呈等梯度逐渐递增。
  7. 根据权利要求6所述的薄膜的炉管沉积方法，其中，任意相邻两个所述制程区域(201-204)的设定沉积温度的等梯度递减的温度梯度值与任意相邻两个所述制程区域(201-204)的设定退火温度的等梯度递增的温度梯度值相同。
  8. 根据权利要求6所述的薄膜的炉管沉积方法，其中，执行薄膜沉积工艺时，在从上至下的方向上制程区域的设定沉积温度与执行退火工艺时在从下至上方向上的制程区域的设定退火温度相同。
  9. 根据权利要求1所述的薄膜的炉管沉积方法，其中，所述制程区域(201-204)的设定退火温度和所述制程区域(201-204)的设定沉积温度大于等于500℃且小于等于650℃。
  10. 根据权利要求1所述的薄膜的炉管沉积方法，其中，执行薄膜沉积工艺中的设定沉积温度的最大值与执行退火工艺中的设定退火温度的最大值为预定的最高温度。
  11. 根据权利要求10所述的薄膜的炉管沉积方法，其中，所述预定的最高温度为650℃。
  12. 根据权利要求1所述的薄膜的炉管沉积方法，其中，执行薄膜沉积工艺中的设定沉积温度的最小值与执行退火工艺中的设定退火温度的最小值为预定的最低温度。
  13. 根据权利要求12所述的薄膜的炉管沉积方法，其中，所述预定的最低温度为500℃。
  14. 根据权利要求1所述的薄膜的炉管沉积方法，其中，执行退火工艺的时间为120min-300min。
  15. 根据权利要求1所述的薄膜的炉管沉积方法，在执行退火工艺时，所述炉管沉积方法还包括向所述炉管(1000)内通入惰性气体。
  16. 根据权利要求1所述的薄膜的炉管沉积方法，其中，所述薄膜(2)为氮化硅薄膜。
  17. 根据权利要求1所述的薄膜的炉管沉积方法，其中，所述薄膜沉积工艺包括原子层沉积工艺或低压力化学气相沉积法。
  18. 根据权利要求6所述的薄膜的炉管沉积方法，其中，所述薄膜(2)沉积形成在所述衬底(1)的表面，所述薄膜(2)为连续的平面，所述薄膜的沉积工艺中，任意相邻两个所述制程区域的设定沉积温度之间具有第一温差；所述薄膜的退火工艺中，任意相邻两个所述制程区域的设定退火温度之间具有第二温差；所述第一温差大于所述第二温差。
  19. 根据权利要求6所述的薄膜的炉管沉积方法，其中，所述衬底(1)上形成有沟槽(3)，所述薄膜(2)形成在所述沟槽(3)的表面并沿所述衬底的 表面延伸，所述薄膜的沉积工艺中，任意相邻两个所述制程区域(201-204)的设定沉积温度之间具有第三温差；所述薄膜(2)的退火工艺中，任意相邻两个所述制程区域(201-204)的设定退火温度之间具有第四温差；所述第三温差不大于所述第四温差。
  20. 一种半导体器件，其中，所述半导体器件包括衬底和设置在所述衬底表面的薄膜，所述薄膜根据权利要求1所述的方法形成。
PCT/CN2021/095463 2020-12-03 2021-05-24 薄膜的炉管沉积方法及半导体器件 WO2022116481A1 (zh)

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