WO2024077865A1 - 一种改善翘曲的成膜方法 - Google Patents

一种改善翘曲的成膜方法 Download PDF

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WO2024077865A1
WO2024077865A1 PCT/CN2023/081612 CN2023081612W WO2024077865A1 WO 2024077865 A1 WO2024077865 A1 WO 2024077865A1 CN 2023081612 W CN2023081612 W CN 2023081612W WO 2024077865 A1 WO2024077865 A1 WO 2024077865A1
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film forming
temperature zone
silicon wafer
furnace
inlet pipe
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PCT/CN2023/081612
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English (en)
French (fr)
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薛豪
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上海中欣晶圆半导体科技有限公司
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45561Gas plumbing upstream of the reaction chamber
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/24Deposition of silicon only
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/505Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52Controlling or regulating the coating process

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a film forming method.
  • the vertical low-pressure chemical vapor deposition technology is the main deposition method for polysilicon back seal. Due to the vertical furnace body, the warpage caused by various parts in the furnace varies greatly, and some positions are prone to cause excessive warpage of silicon wafers and result in yield loss.
  • the warpage change at M7 position is significantly larger than that at M1 position.
  • the main reasons for the adverse warpage changes in various parts of the furnace are: the reaction chamber is vertical, with a single-tube bottom air intake structure; it can meet customers' requirements for film thickness and uniformity within the product sheet, but because the gradient between the four temperature zones is relatively large: the lower the temperature is, the warp increases significantly after single-side polishing (the increase in warp also increases in a gradient pattern, the greater the increase in warp is, the closer to the BOTTOM end).
  • an embodiment of the present invention provides a film forming method with improved warping to solve at least one of the above technical problems.
  • an embodiment of the present invention provides a film forming method with improved warping, which is characterized in that when the film forming process is carried out through a low-pressure chemical vapor deposition furnace, an air inlet pipe takes in air from the bottom of the furnace chamber, and the warping rate of the silicon wafer after the film forming process is adjusted by adjusting the length of the air inlet pipe extending into the furnace chamber of the low-pressure chemical vapor deposition furnace.
  • the top of the air inlet pipe is located between the third silicon wafer arrangement layer and the seventh silicon wafer arrangement layer from top to bottom.
  • the air inlet pipe is a telescopic pipe, so that the length can be adjusted according to the requirements.
  • the air inlet pipe includes a vertical portion which is vertically arranged and located in the furnace cavity;
  • the side wall of the vertical portion is provided with an air outlet hole, and the aperture of the air outlet hole increases from top to bottom.
  • the air inlet pipe is a pipe made of quartz material.
  • the film forming process comprises the following steps:
  • Step 1 cleaning the single crystal silicon wafer
  • Step 2 Place the cleaned single crystal silicon wafer on a silicon boat made of SiC for thermal processing.
  • the principle is to deposit pure single crystal silicon on the back of the silicon wafer through the thermal decomposition of SiH4 .
  • the heat treatment method of the single crystal silicon wafer is as follows: before heating, place the cleaned single crystal silicon wafer on the silicon boat and introduce high-purity nitrogen into the furnace for 15 to 25 minutes to drive out the gas. Then, slowly heat the silicon boat to 500 to 700°C and keep it for 20 to 60 minutes. Then, slowly cool it down and take out the single crystal silicon wafer. At this time, a layer of polysilicon film is formed on the surface of the single crystal silicon.
  • step 2 during the thermal decomposition process, a polycrystalline silicon film is deposited on the single crystal silicon wafer after thermal oxidation by chemical vapor deposition using silane as the reaction gas.
  • the process parameters for depositing the polycrystalline silicon film on the single crystal silicon wafer after thermal oxidation are: RF power 100-150W, RF frequency 13.56MHz, substrate temperature 500-700°C, chamber pressure 20-35Pa, SiH4 gas with a purity of 99.999% by volume 0.8-1.2slm, and deposition time 20-60 minutes.
  • thermo zones There are four temperature zones from top to bottom in the furnace cavity, namely the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone;
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 650°C, 646°C, 640°C and 638°C respectively, and the reaction time is 20-60 min;
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 650°C, 646°C, 645°C and 647°C respectively, and the reaction time is 20-60 min;
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 640° C., 642° C., 648° C. and 651° C. respectively, and the reaction time is 20-60 min.
  • the concentrations at different positions in the furnace chamber tend to be consistent, thereby reducing the temperature difference at different positions in the furnace chamber and reducing the amount of warpage change.
  • the warpage change rate of the silicon wafer is controlled within WARPBF ⁇ 15.
  • FIG. 1 is a schematic structural diagram of a specific embodiment 1 of the present invention.
  • 1 is the intake pipe.
  • specific embodiment 1 is a film forming method for improving warpage, characterized in that when the film forming process is carried out through a low-pressure chemical vapor deposition furnace, an air inlet pipe takes in air from the bottom of the furnace chamber, and the warpage rate of the silicon wafer after the film forming process is adjusted by adjusting the length of the air inlet pipe extending into the furnace chamber of the low-pressure chemical vapor deposition furnace.
  • the seven silicon wafer layers are the first silicon wafer layer, the second silicon wafer layer, the third silicon wafer layer, the fourth silicon wafer layer, the fifth silicon wafer layer, the sixth silicon wafer layer and the seventh silicon wafer layer from top to bottom.
  • the air inlet pipe 1 is a telescopic pipe, which is convenient for adjusting the length according to needs.
  • the air inlet pipe 1 comprises a vertical portion which is vertically arranged and located in the furnace cavity; a side wall of the vertical portion is provided with air outlet holes, and the apertures of the air outlet holes increase from top to bottom.
  • the air intake pipe is made of quartz.
  • the film forming process includes the following steps:
  • Step 1 cleaning the single crystal silicon wafer
  • Step 2 Place the cleaned single crystal silicon wafer on a silicon boat made of SiC for thermal processing.
  • the principle is to deposit pure single crystal silicon on the back of the silicon wafer through the thermal decomposition of SiH4 .
  • the heat treatment method of the single crystal silicon wafer is as follows: before heating, place the cleaned single crystal silicon wafer on the silicon boat and introduce high-purity nitrogen into the furnace for 15 to 25 minutes to drive out the gas. Then, slowly heat the silicon boat to 500 to 700°C and keep it for 20 to 60 minutes. Then, slowly cool it down and take out the single crystal silicon wafer. At this time, a layer of polysilicon film is formed on the surface of the single crystal silicon.
  • step 2 during the thermal decomposition process, a polycrystalline silicon film is deposited on the single crystal silicon wafer after thermal oxidation treatment by chemical vapor deposition using silane as the reaction gas.
  • the process parameters for depositing the polycrystalline silicon film on the single crystal silicon wafer after thermal oxidation treatment are: RF power 100-150W, RF frequency 13.56MHz, substrate temperature 500-700°C, chamber pressure 20-35Pa, SiH4 gas with a purity of 99.999% by volume 0.8-1.2slm, and deposition time 20-60 minutes.
  • Specific embodiment 2 based on specific embodiment 1, during the film forming process, when the air flow rate of the air inlet pipe is controlled at 0.8-1.2slm, SiH4 gas is input, the time is controlled at 20-60 minutes, and the temperature in the furnace chamber is controlled in four temperature zones of 640 ⁇ 50°C from top to bottom.
  • thermo zones There are four temperature zones from top to bottom in the furnace cavity, namely the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone;
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 650°C, 646°C, 640°C and 638°C respectively, and the reaction time is 20-60 minutes. At this time, the top of the air inlet pipe is at the seventh silicon wafer placement layer.
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 650°C, 646°C, 645°C and 647°C respectively, and the reaction time is 20-60 minutes. At this time, the top of the air inlet pipe is at the fifth silicon wafer placement layer.
  • the reaction gas SiH 4 is input, the temperatures of the first temperature zone, the second temperature zone, the third temperature zone and the fourth temperature zone are 640°C, 642°C, 648°C and 651°C respectively, and the reaction time is 20-60 minutes. At this time, the top of the air inlet pipe is at the third silicon wafer placement layer.
  • the concentrations at different positions in the furnace chamber tend to be consistent, thereby reducing the temperature difference at different positions in the furnace chamber and reducing the amount of warpage change.
  • the distance from the furnace mouth is the bottom position of the vertical part.
  • the concentration of the reaction gas at the bottom is relatively high, it decreases in steps to the top.
  • the inlet pipe is extended into the furnace, so that the concentration in the middle is relatively high and decreases in steps to both ends, the difference between the temperature zones becomes smaller, and the warpage change amount also becomes smaller.
  • the concentration of the reaction gas in each temperature zone in the furnace was changed, thereby affecting the temperature of each temperature zone in the furnace and further improving the warping at some locations.

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Abstract

本发明涉及半导体技术领域。一种改善翘曲的成膜方法,其特征在于,通过低压化学气相沉积炉进行成膜工序时,进气管从炉腔的底部进气,通过调整进气管伸入低压化学气相沉积炉的炉腔的长度调整硅片成膜工艺后的翘曲率。由于底部反应气体浓度较大,到顶部呈阶梯式下降。本申请将进气管往炉内延伸,实现了中部浓度会偏高,向两端阶梯式下降,各温区之间的差异变小,翘曲变化量也会变小。通过改变进气管位置对炉内各温区的反应气体浓度进行了改变,从而影响炉内各温区的温度,进一步对部分位置的翘曲进行了改善。

Description

一种改善翘曲的成膜方法 技术领域
本发明涉及半导体技术领域,具体是成膜方法。
背景技术
目前使用立式的低压化学气相沉积技术是目前多晶硅背封的主要沉积手段。由于是立式的炉体,炉内各部分造成的翘曲变化差异较大,其中部分位置易导致硅片翘曲偏大而产生良率损失。
立式低压化学气相沉积炉内从上至下为四个不同温度的温区,且立式低压化学气相沉积炉内从下至上依次为用于摆放硅片的M7层、M6层、M5层、M4层、M3层、M2层以及M1层。
经过测试,M7位置相较M1位置翘曲变化显著偏大,导致炉内各部分翘曲不良变化的主要原因为:反应腔为立式、单管底部进气结构;能满足客户对于产品片内膜厚和片内均一性的要求,但由于4个温区之间的梯度比较大:越往底部(BOTTOM端),温度越低,单面抛光后(single-side polishing),翘曲(warp)明显增加(翘曲增加量也是呈梯度增加模式,越往BOTTOM端,翘曲增加量越大)。
目前缺乏一种可以实现立式低压化学气相沉积炉控制翘曲的成膜方法。
发明内容
针对现有技术存在的问题,本发明的实施例提供一种改善翘曲的成膜方法,以解决以上至少一个技术问题。
为了达到上述目的,本发明的实施例提供了一种改善翘曲的成膜方法,其特征在于,通过低压化学气相沉积炉进行成膜工序时,进气管从炉腔的底部进气,通过调整进气管伸入低压化学气相沉积炉的炉腔的长度调整硅片成膜工艺后的翘曲率。
进一步优选的,所述炉腔内从上至下设有有七层硅片摆放层;
所述进气管的顶部位于从上至下的第三层硅片摆放层与第七层硅片摆放层之间。
进一步优选的,所述进气管是伸缩管。便于根据需求进行长度的调整。
进一步优选的,所述进气管包括竖直设置且位于炉腔内的竖直部;
所述竖直部的侧壁开设有出气孔,所述出气孔的孔径从上至下递增。
进一步优选的,所述进气管为石英材质的管路。
进一步优选的,成膜工序的沉积厚度为300-1000nm时,成膜工序包括如下步骤:
步骤一,清洗单晶硅片;
步骤二,将清洗好的单晶硅片放入SiC材质的硅舟上进行热加工,其原理是通过对于通入SiH4的热分解,沉积纯净的单晶硅在硅片背面,单晶硅片进行热处理的方式是:升温前,将清洗好的单晶硅片放在硅舟上的同时向炉内通入高纯氮气并保持15~25分钟进行赶气,接着将硅舟缓慢加热至500~700℃保持20-60分钟之后,缓慢降温,取出单晶硅片,此时单晶硅表面便形成一层多晶硅薄膜。
步骤二中,热分解过程中,以硅烷为反应气体采用化学气相沉积法在热氧化处理后的单晶硅片上沉积多晶硅薄膜,在热氧化处理后的单晶硅片上沉积多晶硅薄膜的工艺参数为:射频功率100~150W,射频频率13.56MHz,基片温度为500-700℃,腔体压强20-35Pa,纯度为99.999%体积百分比的SiH4气体0.8-1.2slm,沉积时间20~60分钟。
进一步优选的,成膜过程中,进气管的进气流量控制在0.8-1.2slm时,输入SiH4气体,时间控制在20~60分钟,炉腔内的温度控制在从上至下依次为640±50℃的四个温度区域。
炉腔内从上至下依次为四个温度区域,四个温度区域分别为第一温度区域、第二温度区域、第三温度区域以及第四温度区域;
进气管输入高度为离炉口15cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、640℃、638℃,反应时间为20-60min;
进气管输入高度为离炉口35cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、645℃、647℃,反应时间为20-60min;
进气管输入高度为离炉口57cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为640℃、642℃、648℃、651℃,反应时间为20-60min。
通过改变进气管在炉腔内的不同高度来达到炉腔内不同位置的浓度趋于一致。从而缩小炉腔内不同位置的温度差异以达到减少翘曲改变量。
进一步优选的,成膜后,硅片的翘曲变化率控制在WARPBF≤15。
附图说明
图1为本发明具体实施例1的一种结构示意图。
其中:1为进气管。
具体实施方式
下面结合附图对本发明做进一步的说明。
参见图1,具体实施例1,一种改善翘曲的成膜方法,其特征在于,通过低压化学气相沉积炉进行成膜工序时,进气管从炉腔的底部进气,通过调整进气管伸入低压化学气相沉积炉的炉腔的长度调整硅片成膜工艺后的翘曲率。
炉腔内从上至下设有有七层硅片摆放层;进气管的顶部位于从上至下的第三层硅片摆放层与第七层硅片摆放层之间。七层硅片摆放层依次为从上至下设置的第一层硅片摆放层、第二层硅片摆放层、第三层硅片摆放层、第四层硅片摆放层、第五层硅片摆放层、第六层硅片摆放层以及第七层硅片摆放层。
进气管1是伸缩管。便于根据需求进行长度的调整。
进气管1包括竖直设置且位于炉腔内的竖直部;竖直部的侧壁开设有出气孔,出气孔的孔径从上至下递增。
进气管为石英材质的管路。
成膜工序的沉积厚度为300-1000nm时,成膜工序包括如下步骤:
步骤一,清洗单晶硅片;
步骤二,将清洗好的单晶硅片放入SiC材质的硅舟上进行热加工,其原理是通过对于通入SiH4的热分解,沉积纯净的单晶硅在硅片背面,单晶硅片进行热处理的方式是:升温前,将清洗好的单晶硅片放在硅舟上的同时向炉内通入高纯氮气并保持15~25分钟进行赶气,接着将硅舟缓慢加热至500~700℃保持20-60分钟之后,缓慢降温,取出单晶硅片,此时单晶硅表面便形成一层多晶硅薄膜。
步骤二中,热分解过程中,以硅烷为反应气体采用化学气相沉积法在热氧化处理后的单晶硅片上沉积多晶硅薄膜,在热氧化处理后的单晶硅片上沉积多晶硅薄膜的工艺参数为:射频功率100~150W,射频频率13.56MHz,基片温度为500-700℃,腔体压强20-35Pa,纯度为99.999%体积百分比的SiH4气体0.8-1.2slm,沉积时间为20~60分钟。
具体实施例2,在具体实施例1的基础上,成膜过程中,进气管的进气流量控制在0.8-1.2slm时,输入SiH4气体,时间控制在20~60分钟,炉腔内的温度控制在从上至下依次为640±50℃的四个温度区域。
炉腔内从上至下依次为四个温度区域,四个温度区域分别为第一温度区域、第二温度区域、第三温度区域以及第四温度区域;
进气管输入高度为离炉口15cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、640℃、638℃,反应时间为20-60min。此时进气管的顶部管口在第七层硅片放置层。
进气管输入高度为离炉口35cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、645℃、647℃,反应时间为20-60min。此时进气管的顶部管口在第五层硅片放置层。
进气管输入高度为离炉口57cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为640℃、642℃、648℃、651℃,反应时间为20-60min。此时进气管的顶部管口在第三层硅片放置层。
通过改变进气管在炉腔内的不同高度来达到炉腔内不同位置的浓度趋于一致。从而缩小炉腔内不同位置的温度差异以达到减少翘曲改变量。
离炉口也就是竖直部的底部位置。
有益效果:
由于底部反应气体浓度较大,到顶部呈阶梯式下降。本申请将进气管往炉内延伸,实现了中部浓度会偏高,向两端阶梯式下降,各温区之间的差异变小,翘曲变化量也会变小。
通过改变进气管位置对炉内各温区的反应气体浓度进行了改变,从而影响炉内各温区的温度,进一步对部分位置的翘曲进行了改善。
以上仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种改善翘曲的成膜方法,其特征在于,通过低压化学气相沉积炉进行成膜工序时,进气管从炉腔的底部进气,通过调整进气管伸入低压化学气相沉积炉的炉腔的长度调整硅片成膜工艺后的翘曲率。
  2. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:所述炉腔内从上至下设有有七层硅片摆放层;
    所述进气管的顶部位于从上至下的第三层硅片摆放层与第七层硅片摆放层之间。
  3. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:所述进气管是伸缩管。
  4. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:所述进气管包括竖直设置且位于炉腔内的竖直部;
    所述竖直部的侧壁开设有出气孔,所述出气孔的孔径从上至下递增。
  5. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:所述进气管为石英材质的管路。
  6. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:成膜工序的沉积厚度为300-1000nm时,成膜工序包括如下步骤:
    步骤一,清洗单晶硅片;
    步骤二,将清洗好的单晶硅片放入SiC材质的硅舟上进行热加工,其原理是通过对于通入SiH4的热分解,沉积纯净的单晶硅在硅片背面,单晶硅片进行热处理的方式是:升温前,将清洗好的单晶硅片放在硅舟上的同时向炉内通入氮气并保持15~25分钟进行赶气,接着将硅舟缓慢加热至500~700℃保持20-60分钟之后,缓慢降温,取出单晶硅片,此时单晶硅表面便形成一层多晶硅薄膜。
  7. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:步骤二中,热分解过程中,以硅烷为反应气体采用化学气相沉积法在热氧化处理后的单晶硅片上沉积多晶硅薄膜,在热氧化处理后的单晶硅片上沉积多晶硅薄膜的工艺参数为:射频功率100~150W,射频频率13.56MHz,基片温度为500-700℃,腔体压强为20-35Pa,纯度为99.999%体积百分比的SiH4气体流量为0.8-1.2slm,沉积时间为20~60分钟。
  8. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:成膜过程中,进气管的进气流量控制在0.8-1.2slm时,输入SiH4气体,时间控制在20~60分钟,炉腔内的温度 控制在从上至下依次为640±50℃的四个温度区域。
  9. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:炉腔内从上至下依次为四个温度区域,四个温度区域分别为第一温度区域、第二温度区域、第三温度区域以及第四温度区域;
    进气管输入高度为离炉口15cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、640℃、638℃,反应时间为20-60min;
    进气管输入高度为离炉口35cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为650℃、646℃、645℃、647℃,反应时间为20-60min;
    进气管输入高度为离炉口57cm时,输入反应气体SiH4,第一温度区域、第二温度区域、第三温度区域以及第四温度区域的温度分别为640℃、642℃、648℃、651℃,反应时间为20-60min。
  10. 根据权利要求1所述的一种改善翘曲的成膜方法,其特征在于:成膜后,硅片的翘曲变化率控制在WARPBF≤15。
PCT/CN2023/081612 2022-10-13 2023-03-15 一种改善翘曲的成膜方法 WO2024077865A1 (zh)

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CN115613007A (zh) * 2022-10-13 2023-01-17 上海中欣晶圆半导体科技有限公司 一种改善翘曲的成膜方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103663457A (zh) * 2013-11-29 2014-03-26 上海华力微电子有限公司 多晶硅反应炉
CN110257908A (zh) * 2019-05-28 2019-09-20 天津中环领先材料技术有限公司 一种多晶硅薄膜制备工艺
CN111223761A (zh) * 2020-01-14 2020-06-02 北京大学 一种沉积多晶硅表面颗粒质量改善方法
CN111834257A (zh) * 2020-06-11 2020-10-27 长江存储科技有限责任公司 炉管的进气装置及其炉管结构
CN115613007A (zh) * 2022-10-13 2023-01-17 上海中欣晶圆半导体科技有限公司 一种改善翘曲的成膜方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3900597A (en) * 1973-12-19 1975-08-19 Motorola Inc System and process for deposition of polycrystalline silicon with silane in vacuum
US4742020A (en) * 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
KR940010183A (ko) * 1992-10-24 1994-05-24 황철주 플라즈마 저압화학 증기증착방법 및 그 장치
JP3090176B2 (ja) * 1993-03-31 2000-09-18 住友大阪セメント株式会社 反り変形を有する光位相調整された光導波路型光素子チップ
JP2001102386A (ja) * 1999-10-01 2001-04-13 Toshiba Ceramics Co Ltd 半導体ウエハの製造方法
JP4929603B2 (ja) * 2005-03-10 2012-05-09 Jfeスチール株式会社 鋼板形状に優れたセラミクス被膜付き方向性電磁鋼板ストリップの製造方法
FI124354B (fi) * 2011-04-04 2014-07-15 Okmetic Oyj Menetelmä yhden tai useamman polykiteisen piikerroksen pinnoittamiseksi substraatille
JP6440853B2 (ja) * 2015-09-07 2018-12-19 三菱電機株式会社 太陽電池の製造方法
CN206887226U (zh) * 2017-06-29 2018-01-16 苏州工业园区纳米产业技术研究院有限公司 反应炉
CN109300777A (zh) * 2018-09-25 2019-02-01 上海申和热磁电子有限公司 一种改善硅片多晶硅薄膜翘曲的化学气相沉积方法
CN111270220A (zh) * 2020-03-27 2020-06-12 上海华力微电子有限公司 化学气相淀积装置及其调节方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103663457A (zh) * 2013-11-29 2014-03-26 上海华力微电子有限公司 多晶硅反应炉
CN110257908A (zh) * 2019-05-28 2019-09-20 天津中环领先材料技术有限公司 一种多晶硅薄膜制备工艺
CN111223761A (zh) * 2020-01-14 2020-06-02 北京大学 一种沉积多晶硅表面颗粒质量改善方法
CN111834257A (zh) * 2020-06-11 2020-10-27 长江存储科技有限责任公司 炉管的进气装置及其炉管结构
CN115613007A (zh) * 2022-10-13 2023-01-17 上海中欣晶圆半导体科技有限公司 一种改善翘曲的成膜方法

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