WO2023231164A1 - 半导体器件和存储器 - Google Patents

半导体器件和存储器 Download PDF

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Publication number
WO2023231164A1
WO2023231164A1 PCT/CN2022/107184 CN2022107184W WO2023231164A1 WO 2023231164 A1 WO2023231164 A1 WO 2023231164A1 CN 2022107184 W CN2022107184 W CN 2022107184W WO 2023231164 A1 WO2023231164 A1 WO 2023231164A1
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WIPO (PCT)
Prior art keywords
pull
circuit
compensation
transistor
control signal
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PCT/CN2022/107184
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English (en)
French (fr)
Inventor
刘忠来
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP22838628.0A priority Critical patent/EP4307305A4/en
Priority to US17/954,336 priority patent/US20230410889A1/en
Publication of WO2023231164A1 publication Critical patent/WO2023231164A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a memory.
  • the output circuit in the memory includes a pull-up circuit, a pull-down circuit, and a compensation circuit used to improve the output signal driving capability of the output circuit.
  • the compensation circuit is generally integrated in the integration area where the pull-up circuit and the pull-down circuit are located.
  • control line connected to the compensation circuit will form a large parasitic capacitance between the pull-up circuit or the pull-down circuit, which is not conducive to the optimization of the signal on the control line connected to the compensation circuit.
  • a semiconductor device including a pull-up circuit integrated area, a pull-down circuit integrated area, and a compensation circuit integrated area that do not overlap each other, and the semiconductor device further includes an output circuit,
  • the output circuit includes: a pull-up circuit, a pull-down circuit, and a compensation circuit.
  • the pull-up circuit is connected to the signal output line, and the pull-up circuit is located in the pull-up circuit integration area;
  • the pull-down circuit is connected to the signal output line, and the pull-down circuit is located in the pull-down circuit integration area;
  • the compensation circuit is used to enhance The signal output line outputs the driving capability of the signal, and the compensation circuit is located in the compensation circuit integration area.
  • the signal output line extends along the first direction and is used to transmit signals along the first direction; at least part of the compensation circuit integrated area is located in the pull-up circuit integrated area on one side in the first direction, and at least part of the compensation circuit integrated area is located on one side of the pull-down circuit integrated area on the first direction.
  • the compensation circuit includes at least one first pull-up compensation branch, the first pull-up compensation branch is used to pull up the output signal;
  • the compensation circuit integration area includes The first integration area, the first pull-up compensation branch is located in the first integration area; the first integration area is located on one side of the pull-up circuit integration area in the first direction.
  • the compensation circuit includes at least one first pull-down compensation branch, the first pull-down compensation branch is used to pull down the output signal; the compensation circuit integration area includes a first pull-down compensation branch. Two integration areas, the first pull-down compensation branch is located in the second integration area; the second integration area is located on one side of the pull-down circuit integration area in the first direction.
  • the first pull-up compensation branch is connected to the signal output line and the first control signal line, and the first pull-up compensation branch is used to respond to the first control signal
  • the enable signal of the line is used to pull up the output signal
  • the pull-up circuit includes a plurality of pull-up branches, the pull-up branches include a first transistor, and the first pole of the first transistor is connected to the signal output line, the second electrode of the first transistor is connected to the first high-level power supply terminal, and the gate electrode of the first transistor is connected to the pull-up control signal line.
  • the first pull-up compensation branch includes a second transistor, a first pole of the second transistor is connected to the signal output line, and a second pole of the second transistor is connected to the signal output line.
  • the gate of the second transistor is connected to the first control signal line; wherein the size of the first transistor is smaller than the size of the second transistor.
  • the number of pull-up branches in the pull-up circuit is greater than the number of the first pull-up compensation branches in the compensation circuit.
  • the first pull-down compensation branch is connected to the signal output line and the second control signal line, and the first pull-down compensation branch is used to respond to the second control signal
  • the enable signal of the line is used to pull down the output signal
  • the pull-down circuit includes a plurality of pull-down branches, the pull-down branch includes a third transistor, and the first pole of the third transistor is connected to the signal output line, so The second electrode of the third transistor is connected to the first low-level power supply terminal, and the gate electrode of the third transistor is connected to the pull-down control signal line.
  • the first pull-down compensation branch includes a fourth transistor, a first electrode of the fourth transistor is connected to the signal output line, and a second electrode of the fourth transistor is connected to the signal output line.
  • the gate of the fourth transistor is connected to the second control signal line; wherein the size of the third transistor is smaller than the size of the fourth transistor.
  • the number of pull-down branches in the pull-down circuit is greater than the number of the first pull-down compensation branches in the compensation circuit.
  • the compensation circuit includes at least one first pull-down compensation branch, and the pull-down circuit includes a plurality of pull-down branches;
  • the first pull-down compensation branch is connected to the signal output line and a second control signal line, used to pull down the output signal in response to the enable signal of the second control signal line;
  • the pull-down branch is connected to the signal output line, the first low-level power supply end, and the pull-down control A signal line, used to transmit the signal of the first low-level power supply terminal to the signal output line in response to the signal of the pull-down control signal line;
  • a plurality of the pull-up branches are distributed along the first direction, with multiple The pull-down branches are distributed along the first direction, and the area where the signal output line is located is between the pull-up circuit integrated area and the pull-down circuit integrated area;
  • the first control signal line, the pull-up control The signal line, the second control signal line, and the pull-down control signal line extend along the first direction, and the area where the first control signal line is located is between
  • the signal output line extends along the first direction and is used to transmit signals along the first direction; at least part of the compensation circuit integrated area is located in the pull-up circuit integrated area on one side in the second direction, and at least part of the compensation circuit integrated area is located on one side of the pull-down circuit integrated area on the second direction, and the second direction is opposite to the first direction.
  • the compensation circuit includes at least one second pull-up compensation branch; the compensation circuit integration area includes a third integration area, and the second pull-up compensation branch is located in the third integration area. Three integrated areas; the third integrated area is located on one side of the pull-up circuit integrated area in the second direction.
  • the compensation circuit includes at least one second pull-down compensation branch; the compensation circuit integration area includes a fourth integration area, and the second pull-down compensation branch is located in the fourth integration area. area; the fourth integration area is located on one side of the pull-down circuit integration area in the second direction.
  • the pull-up circuit includes a plurality of pull-up branches, the pull-up branches include a first transistor, and the first electrode of the first transistor is connected to the signal output line, The second pole of the first transistor is connected to the first high-level power supply terminal, the gate of the first transistor is connected to the pull-up control signal line; the second pull-up compensation branch is connected to the pull-up control signal line , the second pull-up compensation branch is used to synchronously compensate the signal on the pull-up control signal line.
  • the pull-down circuit includes a plurality of pull-down branches, the pull-down branches include a third transistor, a first electrode of the third transistor is connected to the signal output line, and the third transistor is connected to the signal output line.
  • the second pole of the three transistors is connected to the first low-level power supply terminal, and the gate of the third transistor is connected to the pull-down control signal line;
  • the second pull-down compensation branch is connected to the pull-down control signal line, and the second pull-down compensation branch is connected to the pull-down control signal line.
  • the compensation branch is used to synchronously compensate the signal on the pull-down control signal line.
  • the second pull-up compensation branch is connected to the signal output line and a third control signal line, and is used to respond to an enable signal of the third control signal line to pull up the output signal.
  • the second pull-down compensation branch is connected to the signal output line and a fourth control signal line, and is used to pull down the output in response to an enable signal of the fourth control signal line. Signal.
  • a memory including the above-mentioned semiconductor device.
  • Figure 1 is a schematic structural diagram of an output circuit in this exemplary embodiment
  • Figure 2 is an equivalent circuit diagram of the partial structure of the output circuit shown in Figure 1;
  • Figure 3 is the structural layout of the output circuit shown in Figure 1;
  • Figure 4 is a schematic structural diagram of a semiconductor device according to an exemplary embodiment of the present disclosure.
  • Figure 5 is a structural layout of the semiconductor device shown in Figure 4.
  • Figure 6 is an equivalent circuit diagram of the partial structure of the output circuit in the semiconductor device shown in Figure 4.
  • Figure 7 is a structural layout of another exemplary embodiment of a semiconductor device of the present disclosure.
  • FIG. 8 is an equivalent circuit diagram of a partial structure of the output circuit in the semiconductor device shown in FIG. 7 .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments. To those skilled in the art.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • Figure 1 is a schematic structural diagram of an output circuit in this exemplary embodiment
  • Figure 2 is an equivalent circuit diagram of a partial structure of the output circuit shown in Figure 1
  • Figure 3 is a schematic diagram of the structure of the output circuit shown in Figure 1 Structural layout of the output circuit.
  • the output circuit includes a pull-up electrode, a pull-down circuit, a switch circuit 3, a pull-up compensation circuit, and a pull-down compensation circuit.
  • the pull-up circuit includes a plurality of pull-up branches 11, the pull-down circuit includes a plurality of pull-down branches 21, the switch circuit 3 includes a plurality of switch branches 31, the pull-up compensation circuit includes a plurality of pull-up compensation branches 411, and the pull-down circuit includes a plurality of pull-down branches 21.
  • the compensation circuit includes a plurality of pull-down compensation branches 421 .
  • the pull-up branch 11 may include a first transistor T1
  • the pull-down branch 21 may include a third transistor T3
  • the pull-up compensation branch 411 may include a second transistor T2
  • the pull-down compensation circuit may Including the fourth transistor T4, the switching branch 31 may include a fifth transistor T5.
  • a pull-up branch 11, a pull-down branch 21, a switch branch 31, a pull-up compensation branch 411, and a pull-down compensation branch 421 can form an output unit.
  • the first electrode of the first transistor T1 is connected to the signal output line LDQ
  • the second electrode of the first transistor T1 is connected to the second electrode of the fifth transistor T5
  • the gate electrode of the first transistor T1 is connected to the pull-up control signal.
  • the first pole of the fifth transistor T5 is connected to the first high-level power supply terminal VDD1; the first pole of the third transistor T3 is connected to the signal output line LDQ, and the second pole of the third transistor T3 is connected to the first low-level power supply terminal VSS1, the gate is connected to the pull-down control signal line MPD; the first electrode of the second transistor T2 is connected to the signal output line LDQ, the second electrode of the second transistor T2 is connected to the second high-level power supply terminal VDD2, and the gate of the second transistor T2
  • the first pole of the fourth transistor T4 is connected to the signal output line LDQ, the second pole of the fourth transistor T4 is connected to the second low-level power supply terminal VSS2, and the gate of the fourth transistor T4 is connected to the pull-down Compensation control line BPD.
  • the pull-up control signal line MPU and the pull-down control signal line MPD select one of the input valid levels to select one to turn on the transistor connected thereto.
  • the pull-up control signal line MPU inputs a valid level to turn on the pull-up branch 11
  • the pull-down branch 21 is turned off, and the signal output line LDQ outputs a high level
  • the pull-up control signal line MPD inputs a valid level to turn on
  • the pull-up branch 11 is turned off, and the signal output line LDQ outputs a low level, so that the output circuit can controllably output a high level or a low level.
  • the pull-up compensation control line BPU can output a valid level when the pull-up control signal line MPU inputs a valid level to turn on the pull-up compensation branch 411, and the pull-up compensation branch 411 switches the second high-level power terminal VDD2 The high level is transmitted to the signal output line LDQ, thereby enhancing the pull-up driving capability of the input signal on the signal output line LDQ.
  • the pull-down compensation control line BPD can output an effective level when the pull-down control signal line MPD outputs an effective level to turn on the pull-down compensation branch 421.
  • the pull-down compensation branch 421 can transmit the low level of the second low-level power supply terminal VSS2 to The signal output line LDQ thereby enhances the pull-down driving capability of the output signal on the signal output line LDQ.
  • the stronger the pull-up driving ability of the output signal the steeper the rising edge of the output signal.
  • the stronger the pull-down driving ability of the output signal the steeper the falling edge of the output signal.
  • the pull-up driving ability and pull-down driving ability of the output signal are The stronger the capability, the higher the maximum frequency that the output signal can reach.
  • the first high-level power supply terminal VDD1 and the second high-level power supply terminal VDD2 can share the same high-level power supply terminal
  • the first low-level power supply terminal VSS1 and the second low-level power supply terminal VSS2 can share the same low-level power supply terminal. flat power terminal.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be N-type transistors or P-type transistors.
  • the effective level can be understood as the conduction level of the target circuit. For example, when the target circuit is an N-type transistor, the effective level is high level, and when the target circuit is a P-type transistor, the effective level is low level.
  • T3 and T4 are Pmos tubes
  • T1, T2 and T5 are Nmos tubes.
  • the number of pull-up compensation branches 411 can be the same as the number of pull-up branches 11 , and the pull-up compensation branches 411 can be distributed at the location where the pull-up branch 11 is located.
  • Pull-up branch integration area 01; the number of pull-down compensation branches 421 can be the same as the number of pull-down branches 21, and the pull-down compensation branches 421 can be distributed in the pull-down branch integration area 02 where the pull-down branch 21 is located.
  • the number of pull-up branches 11 and pull-down branches 21 may be the same.
  • the number of pull-up branches 11 and pull-down branches 21 may both be six.
  • the pull-up compensation branches 411 are dispersedly arranged in the pull-up branch integration area 01 where the pull-up branch 11 is located, the pull-up compensation control line BPU is wound very long, and the longer pull-up compensation control line BPU will It creates a large parasitic capacitance with other structures, which is not conducive to the optimization of signal timing on the pull-up compensation control line BPU.
  • the pull-down compensation branches 421 are dispersedly arranged in the pull-down branch integrated area 02 where the pull-down branch 21 is located, the pull-down compensation control line BPD is wound very long, and the longer pull-down compensation control line BPD will interfere with other structures. The large parasitic capacitance is not conducive to the optimization of the signal timing on the pull-down compensation control line BPD.
  • this exemplary embodiment provides a semiconductor device, as shown in Figures 4 and 5.
  • Figure 4 is a schematic structural diagram of the semiconductor device in an exemplary embodiment of the present disclosure
  • Figure 5 is a schematic diagram of the semiconductor device shown in Figure 4. Structural layout.
  • the semiconductor device includes non-overlapping pull-up circuit integrated areas 61, pull-down circuit integrated areas 62, and compensation circuit integrated areas 63.
  • the semiconductor device also includes an output circuit, and the output circuit may include: a pull-up circuit. 1. Pull-down circuit 2. Compensation circuit 4.
  • the pull-up circuit 1 is connected to the signal output line LDQ, and the pull-up circuit 1 is located in the pull-up circuit integrated area 61; the pull-down circuit 2 is connected to the signal output line LDQ, and the pull-down circuit 2 is located in the pull-down circuit integrated area. Area 62; the compensation circuit 4 is used to enhance the driving capability of the output signal on the signal output line LDQ, and the compensation circuit 4 is located in the compensation circuit integration area 63.
  • the semiconductor device centrally arranges the compensation circuit 4 in the compensation circuit integration area 63, which can reduce the capacity of the parasitic capacitance formed by the compensation control line and other structures connected to the compensation circuit 4, which can help reduce the Optimization of signal timing on the compensation control line connected to the compensation circuit 4.
  • the signal output line LDQ extends along the first direction X and is used to transmit signals along the first direction X; the compensation circuit integration area 63 may be located on the upper
  • the pull-up circuit integration area 61 is on one side in the first direction X, and the compensation circuit integration area 63 may be located on one side of the pull-down circuit integration area 62 in the first direction X.
  • the semiconductor device may further include an output pad integration area 64 , and the output pad integration area 64 may be located on a side of the compensation circuit integration area 63 away from the pull-up circuit integration area 61 .
  • the output pad DQpad may be provided in the output pad integration area 64.
  • the output pad DQpad may be connected to the signal output line LDQ.
  • the output pad Dqpad is used to output an output signal to the outside of the semiconductor device.
  • the compensation circuit 4 may include at least one first pull-up compensation branch 411, the first pull-up compensation branch 411 is used to pull up the output signal;
  • the compensation circuit integration area 63 may include a first integration area 631, and the first pull-up compensation branch 411 may be located in the first integration area 631; the first integration area 631 may be located in the pull-up circuit integration area.
  • the area 61 is on one side in the first direction X.
  • the compensation circuit 4 may also include at least one first pull-down compensation branch 421, the first pull-down compensation branch 421 is used to pull down the output signal;
  • the compensation circuit integration area 63 may also include a second integration area 632.
  • the first pull-down compensation branch 421 may be located in the second integration area 632; the second integration area 632 is located in the pull-down circuit integration area. 62 on one side in the first direction X.
  • FIG. 6 it is an equivalent circuit diagram of a partial structure of the output circuit in the semiconductor device shown in FIG. 4 .
  • the first pull-up compensation branch 411 is connected to the signal output line LDQ and the first control signal line BPU1.
  • the first pull-up compensation branch 411 is used to respond to the enable signal of the first control signal line BPU1.
  • the pull-up circuit 1 may include a plurality of pull-up branches 11, the pull-up branches 11 include a first transistor T1, the first pole of the first transistor T1 is connected to the signal
  • the second pole of the output line LDQ is connected to the first high-level power supply terminal VDD1, and the gate is connected to the pull-up control signal line MPU.
  • the first pull-up compensation branch 411 may include a second transistor T2, the first pole of the second transistor T2 is connected to the signal output line LDQ, and the second The electrode can be connected to the second high-level power supply terminal VDD2, and the gate can be connected to the first control signal line BPU1.
  • the first control signal line BPU1 can output an effective level when the pull-up control signal line MPU outputs an effective level to turn on the first pull-up compensation branch 411.
  • the turned-on first pull-up compensation branch 411 will The high-level signal of the level power supply terminal VDD2 is transmitted to the signal output line LDQ to perform pull-up compensation on the signal on the signal output line LDQ.
  • the first control signal line BPU1 can output a valid level at the starting moment when the pull-up control signal line MPU outputs a valid level.
  • the first control signal line BPU1 can output a valid level when the pull-up control signal line MPU starts to output the valid level.
  • the falling edge of the signal on the signal line MPU is controlled to output an effective level to achieve pull-up compensation for the signal on the signal output line LDQ.
  • the first control signal line BPU1 is connected to the first pull-up compensation branch 411 through a contact hole.
  • the contact hole has a small distance from other conductive structures or other contact holes in the film layer extension direction, so that the first control signal line
  • the via structure connected to BPU1 easily forms a large parasitic capacitance with other structures.
  • the number of pull-up branches 11 in the pull-up circuit 1 may be greater than the number of the first pull-up compensation branches 411 in the compensation circuit 4 .
  • the number of pull-up branches 11 in the pull-up circuit 1 may be six, and the number of the first pull-up compensation branches 411 in the compensation circuit 4 may be two.
  • the number of vias between the first control signal line BPU1 and the first pull-up compensation branch 411 can be reduced, thereby effectively reducing the number of first pull-up compensation branches 411. Control the parasitic capacitance of signal line BPU1.
  • the arrangement direction of the first pull-up compensation branch 411 may be perpendicular or parallel to the arrangement direction of the pull-up branch 11 in the pull-up circuit.
  • the arrangement direction of the second transistor T2 may be perpendicular to or parallel to the first pull-up compensation branch 411 .
  • the gate length direction of the second transistor T2 can be parallel. Or perpendicular to the gate length direction of the first transistor T1.
  • This exemplary embodiment reduces the number of the first pull-up compensation branches 411.
  • this exemplary embodiment can increase the size of the second transistor T2 accordingly. , so that the single first pull-up compensation branch 411 has stronger driving capability. Since the compensation circuit integrated area 63 is located on one side of the whole formed by the pull-up circuit integrated area 61 and the pull-down integrated area 62, increasing the size of the second transistor T2 has little impact on the first transistor T1 in the pull-up circuit 1. That is, the layout area of a certain first transistor T1 will not be occupied excessively, which makes it possible to increase the size of the second transistor T2 and reduce the number of the first pull-up compensation branches 411 . In this exemplary embodiment, the size of the second transistor T2 may be larger than the size of the first transistor T1.
  • the first pull-down compensation branch 421 can be connected to the signal output line LDQ and the second control signal line BPD2.
  • Branch 421 may be used to pull down the output signal in response to the enable signal of the second control signal line BPD2;
  • the pull-down circuit 2 may include multiple pull-down branches 21, and the pull-down branch 21 may include a third Transistor T3, the first electrode of the third transistor T3 is connected to the signal output line LDQ, the second electrode is connected to the first low-level power supply terminal VSS1, and the gate electrode is connected to the pull-down control signal line MPD.
  • the first pull-down compensation branch 421 may include a fourth transistor T4, and the first pole of the fourth transistor T4 is connected to the signal output line. LDQ, the second pole is connected to the second low-level power terminal VSS2.
  • the second control signal line BPD2 can output an effective level at the starting moment when the pull-down control signal line MPD outputs an effective level to turn on the first pull-down compensation branch 421.
  • the turned-on first pull-down compensation branch 421 can The low-level signal of the second low-level power supply terminal VSS2 is transmitted to the signal output line LDQ to pull down the signal on the signal output line LDQ.
  • the second control signal line BPD2 is connected to the first pull-down compensation branch 421 through a contact hole.
  • the contact hole connected to the second control signal line BPD2 is in the direction in which the film layer extends with other conductive structures or other contact holes. There is a small distance between them, so that the via structure connected to the second control signal line BPD2 is easy to form a large parasitic capacitance with other structures.
  • the number of pull-down branches 21 in the pull-down circuit 2 may be greater than the number of the first pull-down compensation branches 421 in the compensation circuit 4 .
  • the number of pull-down branches 21 in the pull-down circuit 2 may be six, and the number of the first pull-down compensation branches 421 in the compensation circuit 4 may be two.
  • this exemplary embodiment can reduce the number of vias between the second control signal line BPD2 and the first pull-down compensation branch 421, thereby effectively reducing the number of second pull-down compensation branches 421. Control the parasitic capacitance of signal line BPD2.
  • This exemplary embodiment reduces the number of the first pull-down compensation branches 421.
  • this exemplary embodiment can increase the size of the fourth transistor T4 accordingly. Therefore, the single first pull-down compensation branch 421 has stronger driving capability.
  • the size of the fourth transistor T4 may be larger than the size of the third transistor T3.
  • the feasibility principle of increasing the size of the fourth transistor T4 may refer to the second transistor T2.
  • the output circuit may also include a switch circuit 3.
  • the switch circuit 3 may include a plurality of switch branches 31.
  • the switch branch 31 may include a fifth transistor T5.
  • the first pole of the fifth transistor T5 may The first high-level power terminal VDD1 is connected, and the second electrode is connected to the second electrode of the first transistor T1.
  • first high-level power supply terminal VDD1 and the second high-level power supply terminal VDD2 may share the same high-level power supply terminal
  • first low-level power supply terminal VSS1 and the second low-level power supply terminal VSS1 may share the same high-level power supply terminal
  • the level power supply terminal VSS2 can share the same low-level power supply terminal.
  • a plurality of pull-up branches 11 may be distributed along the first direction X
  • a plurality of pull-down branches 21 may be distributed along the first direction X
  • the area where the signal output line LDQ is located may be located between the pull-up circuit integrated area 61 and the pull-down circuit integrated area 62; the first control signal line BPU1, the pull-up control signal line MPU, and the second control signal line BPD2 and the pull-down control signal line MPD may extend along the first direction X, and the area where the first control signal line BPU1 is located may be located between the area where the pull-up control signal line MPU is located and the area where the signal output line LDQ is located.
  • the area where the second control signal line BPD2 is located may be located between the area where the pull-down control signal line MPD is located and the area where the signal output line LDQ is located.
  • the first control signal line BPU1 can be used to shield noise interference between the pull-up control signal line MPU and the signal output line LDQ.
  • the second control signal line BPD2 can be used to shield noise interference between the pull-down control signal line MPD and the signal output line LDQ.
  • the integration area of the first pull-up compensation branch 411 in FIG. 5 can also be located on one side of the pull-up circuit integration area 61 in the second direction, and the second direction and the first One direction is opposite to X.
  • This setting can increase the distance between the first control signal line BPU1 and the output pad Dqpad, thereby reducing the parasitic capacitance between the first control signal line BPU1 and the output pad Dqpad.
  • the integration area of the first pull-down compensation branch 421 may also be located on one side of the pull-down circuit integration area 62 in the second direction.
  • FIG. 7 it is a structural layout of another exemplary embodiment of a semiconductor device of the present disclosure.
  • the signal output line LDQ extends along the first direction X and is used to transmit signals along the first direction X.
  • the compensation circuit integration area 63 may be located on one side of the pull-up circuit integration area 61 in the second direction, and the compensation circuit integration area 63 may be located on the pull-down circuit integration area 62 in the second direction. On one side, the second direction is opposite to the first direction X.
  • the compensation circuit 4 may include at least one second pull-up compensation branch 412; the compensation circuit integration area 63 may also include a third integration area 633.
  • the second pull-up compensation branch 412 may be located at the third integration area 633; the third integration area 633 may be located at one side of the pull-up circuit integration area 61 in the second direction.
  • the compensation circuit 4 may also include at least one second pull-down compensation branch 422; the compensation circuit integration area 63 may also include a fourth integration area 634, and the second pull-down compensation branch 422
  • the fourth integration area 634 may be located on one side of the pull-down circuit integration area 62 in the second direction.
  • the arrangement direction of the second pull-up compensation branch 412 and the second pull-down compensation branch 422 is parallel to the arrangement direction of the pull-up branch 11 and the pull-down branch 21 , but this is just an example. In fact, the arrangement direction of the second pull-up compensation branch 412 and the second pull-down compensation branch 422 can also be perpendicular to the arrangement direction of the pull-up branch 11 and the pull-down branch 21 .
  • FIG. 8 it is an equivalent circuit diagram of a partial structure of the output circuit in the semiconductor device shown in FIG. 7 .
  • the second pull-up compensation branch 412 may be connected to the pull-up control signal line MPU, and the second pull-up compensation branch 412 may be used to synchronously compensate the signal on the pull-up control signal line MPU.
  • the second pull-up compensation branch 412 can be set in one-to-one correspondence with the pull-up control signal line MPU.
  • the second pull-up compensation branch 412 can be used to synchronously compensate the signal on its corresponding pull-up control signal line MPU.
  • the number of transistors included in the two pull-up compensation branches 412 can be set according to actual needs.
  • the embodiment shown in FIG. 8 includes two transistors, namely a sixth transistor T6 and a seventh transistor T7.
  • the second pull-down compensation branch 422 is connected to the pull-down control signal line MPD, and the second pull-down compensation branch 422 can be used to synchronously compensate the signal on the pull-down control signal line MPD.
  • the second pull-down compensation branch 422 can be set in one-to-one correspondence with the pull-down control signal line MPD.
  • the second pull-down compensation branch 422 can be used to synchronously compensate the signal on its corresponding pull-down control signal line MPD.
  • Each second pull-down compensation branch The number of transistors included in path 422 can be set according to actual needs.
  • FIG. 8 shows only one second pull-up compensation branch 412 and one second pull-down compensation branch 422 .
  • "synchronous compensation” can be understood as: pulling up the compensated signal on the rising edge of the compensated signal, and pulling down the compensated signal on the falling edge of the compensated signal, so that the rising and falling edges of the compensated signal The edge is steeper.
  • the second pull-up compensation branch 412 may include a sixth transistor T6 and a seventh transistor T7.
  • the first pole of the sixth transistor T6 may be connected to the pull-up control signal line MPU.
  • the second pole of the sixth transistor T6 may be connected to the pull-up control signal line MPU.
  • the first pole of the seventh transistor T7 can be connected to the pull-up control signal line MPU, and the second pole of the seventh transistor T7 can be used to receive a low-level power signal.
  • the sixth transistor T6 can be turned on at the rising edge of the signal on the pull-up control signal line MPU to pull up the signal on the pull-up control signal line MPU through the high-level power signal; the seventh transistor T7 can be turned on at the rising edge of the pull-up control signal line MPU. The falling edge of the signal on the line MPU is turned on to pull down the signal on the pull-up control signal line MPU through the low-level power signal.
  • the second pull-down compensation branch 422 may include an eighth transistor T8 and a ninth transistor T9.
  • the first pole of the eighth transistor T8 may be connected to the pull-down control signal line MPD, and the second pole of the eighth transistor T8 may be used to receive A high-level power signal; the first pole of the ninth transistor T9 can be connected to the pull-down control signal line MPD, and the second pole of the ninth transistor T9 can be used to receive a low-level power signal.
  • the eighth transistor T8 can be turned on on the rising edge of the signal on the pull-down control signal line MPD to pull up the signal on the pull-down control signal line MPD through the high-level power signal; the ninth transistor T9 can be on the pull-down control signal line MPD The falling edge of the signal is turned on to pull down the signal on the pull-down control signal line MPD through the low-level power signal.
  • the second pull-up compensation branch 412 and the second pull-down compensation branch 422 each include two transistors, and one of the two transistors is used for pull-up and one for pull-down.
  • the second pull-up compensation branch 412 and the second pull-down compensation branch 422 may each include a transistor, the transistor in the second pull-up compensation branch 412 is used for pull-up, and the second pull-down compensation branch
  • the transistors in the path are used for pull-down; in parallel, the second pull-up compensation branch 412 and the second pull-down compensation branch 422 can each include multiple transistors (more than or equal to two), and the second pull-up compensation branch 412
  • the transistors are all used for pull-up, and the transistors in the second pull-down compensation branch are used for pull-down.
  • part of the structure of the pull-up control signal line MPU may be located in the third integration area 633 , and the pull-up control signal line MPU may be connected to the sixth transistor T6 and the seventh transistor T7 through the via H respectively.
  • Part of the structure of the pull-down control signal line MPD may be located in the fourth integration region 634, and the pull-down control signal line MPD may be connected to the eighth transistor T8 and the ninth transistor T9 through the via hole H respectively.
  • the pull-up control signal line MPU may also be located outside the third integration area 633
  • the pull-down control signal line MPD may also be located outside the fourth integration area 634 .
  • the semiconductor device may be provided with a first integration region 631 and a second integration region 632, and may also be provided with a third integration region 633 and a fourth integration region 634.
  • the output circuit may include a first pull-up compensation branch 411 located in the first integration area 631, a first pull-down compensation branch 421 located in the second integration area 632, and may also include a first pull-up compensation branch 421 located in the third integration area.
  • the second pull-up compensation branch 412 located in the third integration area 633 and the second pull-down compensation branch 422 located in the fourth integration area 634 can also directly perform pull-up compensation and pull-down compensation for the output signal line LDQ, that is, the third One pole of the transistor in the second pull-up compensation branch 412 and the second pull-down compensation branch 422 is directly connected to the output signal line LDQ, and the other pole is connected to a high-level power supply or a low-level power supply to implement pull-up or pull-down.
  • This exemplary embodiment also provides a memory, which may include the above-mentioned semiconductor device.
  • the memory may be dynamic random access memory.

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Abstract

一种半导体器件和存储器，半导体器件包括互不交叠的上拉电路集成区（61）、下拉电路集成区（62）、补偿电路集成区（63），半导体器件还包括输出电路，输出电路包括：上拉电路（1）、下拉电路（2）、补偿电路（4），上拉电路（1）连接于信号输出线（LDQ），上拉电路（1）位于上拉电路集成区（61）；下拉电路（2）连接于信号输出线（LDQ），下拉电路（2）位于下拉电路集成区（62）；补偿电路（4）用于增强信号输出线（LDQ）上输出信号的驱动能力，补偿电路（4）位于补偿电路集成区（63）。该半导体器件可以降低补偿电路（4）所连接控制线与其他结构之间的寄生电容，从而有利于优化补偿电路（4）所连接控制线上信号的时序。

Description

半导体器件和存储器
相关申请的交叉引用
本申请要求于2022年05月30日递交的、名称为《半导体器件和存储器》的中国专利申请第202210603574.2号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及半导体技术领域，尤其涉及一种半导体器件和存储器。
背景技术
相关技术中，存储器中的输出电路包括上拉电路、下拉电路，以及用于提高输出电路输出信号驱动能力的补偿电路。补偿电路一般集成于上拉电路和下拉电路所在的集成区内。
然而，本公开的发明人发现，补偿电路所连接的控制线会与上拉电路或下拉电路之间形成较大的寄生电容，从而不利于补偿电路所连接的控制线上信号的优化。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种半导体器件，其中，所述半导体器件包括互不交叠的上拉电路集成区、下拉电路集成区、补偿电路集成区，所述半导体器件还包括输出电路，所述输出电路包括：上拉电路、下拉电路、补偿电路。上拉电路连接于信号输出线，所述上拉电路位于所述上拉电路集成区；下拉电路连接于所述信号输出线，所述下拉电路位于所述下拉电路集成区；补偿电路用于增强所述信号输出线上输出信号的驱动能力，所述补偿电路位于所述补偿电路集成区。
本公开一种示例性实施例中，所述信号输出线沿第一方向延伸且用于沿所述第一方向传输信号；所述补偿电路集成区的至少部分区域位于所述上拉电路集成区在所述第一方向上的一侧，且所述补偿电路集成区的至少部分区域位于所述下拉电路集成区在所述第一方向上的一侧。
本公开一种示例性实施例中，所述补偿电路包括至少一个第一上拉补偿支路，所述第一上拉补偿支路用于上拉所述输出信号；所述补偿电路集成区包括第一集成区， 所述第一上拉补偿支路位于所述第一集成区；所述第一集成区位于所述上拉电路集成区在所述第一方向上的一侧。
本公开一种示例性实施例中，所述补偿电路包括至少一个第一下拉补偿支路，所述第一下拉补偿支路用于下拉所述输出信号；所述补偿电路集成区包括第二集成区，所述第一下拉补偿支路位于所述第二集成区；所述第二集成区位于所述下拉电路集成区在所述第一方向上的一侧。
本公开一种示例性实施例中，所述第一上拉补偿支路连接所述信号输出线、第一控制信号线，所述第一上拉补偿支路用于响应所述第一控制信号线的使能信号以上拉所述输出信号；所述上拉电路包括多个上拉支路，所述上拉支路包括第一晶体管，所述第一晶体管的第一极连接所述信号输出线，所述第一晶体管的第二极连接第一高电平电源端，所述第一晶体管的栅极连接上拉控制信号线。
本公开一种示例性实施例中，所述第一上拉补偿支路包括第二晶体管，所述第二晶体管的第一极连接所述信号输出线，所述第二晶体管的第二极用于接收高电平电源电压，所述第二晶体管的栅极连接所述第一控制信号线；其中，所述第一晶体管的尺寸小于所述第二晶体管的尺寸。
本公开一种示例性实施例中，所述上拉电路中上拉支路的个数大于所述补偿电路中所述第一上拉补偿支路的个数。
本公开一种示例性实施例中，所述第一下拉补偿支路连接所述信号输出线、第二控制信号线，所述第一下拉补偿支路用于响应所述第二控制信号线的使能信号以下拉所述输出信号；所述下拉电路包括多个下拉支路，所述下拉支路包括第三晶体管，所述第三晶体管的第一极连接所述信号输出线，所述第三晶体管的第二极连接第一低电平电源端，所述第三晶体管的栅极连接下拉控制信号线。
本公开一种示例性实施例中，所述第一下拉补偿支路包括第四晶体管，所述第四晶体管的第一极连接所述信号输出线，所述第四晶体管的第二极用于接收低电平电源电压，所述第四晶体管的栅极连接所述第二控制信号线；其中，所述第三晶体管的尺寸小于所述第四晶体管的尺寸。
本公开一种示例性实施例中，所述下拉电路中下拉支路的个数大于所述补偿电路中所述第一下拉补偿支路的个数。
本公开一种示例性实施例中，所述补偿电路包括至少一个第一下拉补偿支路，所述下拉电路包括多个下拉支路；所述第一下拉补偿支路连接所述信号输出线、第二控 制信号线，用于响应所述第二控制信号线的使能信号下拉所述输出信号；所述下拉支路连接所述信号输出线、第一低电平电源端、下拉控制信号线，用于响应所述下拉控制信号线的信号将所述第一低电平电源端的信号传输到所述信号输出线；多个所述上拉支路沿所述第一方向分布，多个所述下拉支路沿所述第一方向分布，所述信号输出线所在区域位于所述上拉电路集成区和所述下拉电路集成区之间；所述第一控制信号线、上拉控制信号线、第二控制信号线、下拉控制信号线沿所述第一方向延伸，所述第一控制信号线所在区域位于所述上拉控制信号线所在区域和所述信号输出线所在区域之间，所述第二控制信号线所在区域位于所述下拉控制信号线所在区域和所述信号输出线所在区域之间。
本公开一种示例性实施例中，所述信号输出线沿第一方向延伸且用于沿所述第一方向传输信号；所述补偿电路集成区的至少部分区域位于所述上拉电路集成区在第二方向上的一侧，且所述补偿电路集成区的至少部分区域位于所述下拉电路集成区在所述第二方向上的一侧，所述第二方向和所述第一方向相反。
本公开一种示例性实施例中，所述补偿电路包括至少一个第二上拉补偿支路；所述补偿电路集成区包括第三集成区，所述第二上拉补偿支路位于所述第三集成区；所述第三集成区位于所述上拉电路集成区在所述第二方向上的一侧。
本公开一种示例性实施例中，所述补偿电路包括至少一个第二下拉补偿支路；所述补偿电路集成区包括第四集成区，所述第二下拉补偿支路位于所述第四集成区；所述第四集成区位于所述下拉电路集成区在所述第二方向上的一侧。
本公开一种示例性实施例中，所述上拉电路包括多个上拉支路，所述上拉支路包括第一晶体管，所述第一晶体管的第一极连接所述信号输出线，所述第一晶体管的第二极连接第一高电平电源端，所述第一晶体管的栅极连接上拉控制信号线；所述第二上拉补偿支路连接所述上拉控制信号线，所述第二上拉补偿支路用于同步补偿所述上拉控制信号线上的信号。
本公开一种示例性实施例中，所述下拉电路包括多个下拉支路，所述下拉支路包括第三晶体管，所述第三晶体管的第一极连接所述信号输出线，所述第三晶体管的第二极连接第一低电平电源端，所述第三晶体管的栅极连接下拉控制信号线；所述第二下拉补偿支路连接所述下拉控制信号线，所述第二下拉补偿支路用于同步补偿所述下拉控制信号线上的信号。
本公开一种示例性实施例中，所述第二上拉补偿支路连接所述信号输出线、第三 控制信号线，用于响应所述第三控制信号线的使能信号以上拉所述输出信号。
本公开一种示例性实施例中，所述第二下拉补偿支路连接所述信号输出线、第四控制信号线，用于响应所述第四控制信号线的使能信号以下拉所述输出信号。
根据本公开的一个方面，提供一种存储器，所述存储器包括上述的半导体器件。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本示例性实施例中一种输出电路的结构示意图；
图2为图1所示输出电路部分结构的等效电路图；
图3为图1所示输出电路的结构版图；
图4为本公开半导体器件一种示例性实施例中的结构示意图；
图5为图4所示半导体器件的结构版图；
图6为图4所示半导体器件中输出电路部分结构的等效电路图；
图7为本公开半导体器件另一种示例性实施例的结构版图；
图8为图7所示半导体器件中输出电路部分结构的等效电路图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体位于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成 部分/等之外还可存在另外的要素/组成部分/等。
如图1、2、3所示，图1为本示例性实施例中一种输出电路的结构示意图，图2为图1所示输出电路部分结构的等效电路图，图3为图1所示输出电路的结构版图。该输出电路包括上拉电极，下拉电路、开关电路3、上拉补偿电路、下拉补偿电路。其中，上拉电路包括多个上拉支路11，下拉电路包括多个下拉支路21，开关电路3包括多个开关支路31，上拉补偿电路包括多个上拉补偿支路411，下拉补偿电路包括多个下拉补偿支路421。如图1、2、3所示，上拉支路11可以包括第一晶体管T1，下拉支路21可以包括第三晶体管T3，上拉补偿支路411可以包括第二晶体管T2，下拉补偿电路可以包括第四晶体管T4，开关支路31可以包括第五晶体管T5。如图2所示，一上拉支路11、一下拉支路21、一开关支路31、一上拉补偿支路411、一下拉补偿支路421可以形成一输出单元。在同一输出单元中，第一晶体管T1的第一极连接信号输出线LDQ，第一晶体管T1的第二极连接第五晶体管T5的第二极，第一晶体管T1的栅极连接上拉控制信号线MPU；第五晶体管T5的第一极连接第一高电平电源端VDD1；第三晶体管T3的第一极连接信号输出线LDQ，第三晶体管T3的第二极连接第一低电平电源端VSS1，栅极连接下拉控制信号线MPD；第二晶体管T2的第一极连接信号输出线LDQ，第二晶体管T2的第二极连接第二高电平电源端VDD2，第二晶体管T2的栅极连接上拉补偿控制线BPU；第四晶体管T4的第一极连接信号输出线LDQ，第四晶体管T4的第二极连接第二低电平电源端VSS2，第四晶体管T4的栅极连接下拉补偿控制线BPD。
本示例性实施例中，当开关支路31导通时，上拉控制信号线MPU和下拉控制信号线MPD择一输入有效电平，以择一导通与其连接的晶体管。当上拉控制信号线MPU输入有效电平以导通上拉支路11时，下拉支路21关断，信号输出线LDQ输出高电平；当下拉控制信号线MPD输入有效电平以导通下拉支路21时，上拉支路11关断，信号输出线LDQ输出低电平，从而该输出电路可以可控制的输出高电平或低电平。
此外，上拉补偿控制线BPU可以在上拉控制信号线MPU输入有效电平时输出有效电平以导通上拉补偿支路411，上拉补偿支路411将第二高电平电源端VDD2的高电平传输到信号输出线LDQ，从而可以增强信号输出线LDQ上输入信号的上拉驱动能力。下拉补偿控制线BPD可以在下拉控制信号线MPD输出有效电平时输出有效电平以导通下拉补偿支路421，下拉补偿支路421可以将第二低电平电源端VSS2的低电平传输到信号输出线LDQ，从而增强信号输出线LDQ上输出信号的下拉驱动能力。其中，输出信号的上拉驱动能力越强，输出信号的上升沿越陡峭，输出信号的下拉驱动能力越强，输出信号的下降沿越陡峭，相应的，输出信号的上拉驱动能力和下拉驱动能力越强，输出信号所能达到的最大频率也越高。
其中，第一高电平电源端VDD1和第二高电平电源端VDD2可以共用同一高电平电源端，第一低电平电源端VSS1和第二低电平电源端VSS2可以共用同一低电平电 源端。第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5可以为N型晶体管也可以为P型晶体管。有效电平可以理解为目标电路的导通电平，例如，当目标电路为N型晶体管时，有效电平为高电平，当目标电路为P型晶体管时，有效电平为低电平。在一实施例中，T3和T4为Pmos管，T1、T2及T5为Nmos管。
如图3所示，在同一输出电路中，上拉补偿支路411的个数可以与上拉支路11的个数相同，上拉补偿支路411可以分散设置于上拉支路11所在的上拉支路集成区01；下拉补偿支路421的个数可以与下拉支路21的个数相同，下拉补偿支路421可以分散设置于下拉支路21所在的下拉支路集成区02。在同一输出电路中，上拉支路11和下拉支路21的个数可以相同，例如，上拉支路11和下拉支路21的个数均可以为6个。然而，由于上拉补偿支路411分散设置于上拉支路11所在的上拉支路集成区01，从而导致上拉补偿控制线BPU绕线很长，较长的上拉补偿控制线BPU会与其他结构产生较大的寄生电容，从而不利于上拉补偿控制线BPU上信号时序的优化。同理，由于下拉补偿支路421分散设置于下拉支路21所在的下拉支路集成区02，从而导致下拉补偿控制线BPD绕线很长，较长的下拉补偿控制线BPD会与其他结构产生较大的寄生电容，从而不利于下拉补偿控制线BPD上信号时序的优化。
基于此，本示例性实施例提供一种半导体器件，如图4、5所示，图4为本公开半导体器件一种示例性实施例中的结构示意图，图5为图4所示半导体器件的结构版图。其中，所述半导体器件包括互不交叠的上拉电路集成区61、下拉电路集成区62、补偿电路集成区63，所述半导体器件还包括输出电路，所述输出电路可以包括：上拉电路1、下拉电路2、补偿电路4。上拉电路1连接于信号输出线LDQ，所述上拉电路1位于所述上拉电路集成区61；下拉电路2连接于所述信号输出线LDQ，所述下拉电路2位于所述下拉电路集成区62；补偿电路4用于增强所述信号输出线LDQ上输出信号的驱动能力，所述补偿电路4位于所述补偿电路集成区63。
本示例性实施例中，该半导体器件将补偿电路4集中设置在补偿电路集成区63，从而可以降低补偿电路4所连接的补偿控制线与其他结构所形成寄生电容的容量，从而可以有利于降低补偿电路4所连接的补偿控制线上信号时序的优化。
本示例性实施例中，如图5所示，所述信号输出线LDQ沿第一方向X延伸且用于沿所述第一方向X传输信号；所述补偿电路集成区63可以位于所述上拉电路集成区61在所述第一方向X上的一侧，且所述补偿电路集成区63可以位于所述下拉电路集成区62在所述第一方向X上的一侧。如图5所示，该半导体器件还可以包括一输出焊盘集成区64，输出焊盘集成区64可以位于补偿电路集成区63远离上拉电路集成区61的一侧。输出焊盘集成区64中可以设置有输出焊盘DQpad，输出焊盘DQpad可以与信号输出线LDQ连接，输出焊盘Dqpad用于向半导体器件外部输出输出信号。
本示例性实施例中，如图5所示，所述补偿电路4可以包括至少一个第一上拉补 偿支路411，所述第一上拉补偿支路411用于上拉所述输出信号；所述补偿电路集成区63可以包括第一集成区631，所述第一上拉补偿支路411可以位于所述第一集成区631；所述第一集成区631可以位于所述上拉电路集成区61在所述第一方向X上的一侧。
本示例性实施例中，如图5所示，所述补偿电路4还可以包括至少一个第一下拉补偿支路421，所述第一下拉补偿支路421用于下拉所述输出信号；所述补偿电路集成区63还可以包括第二集成区632，所述第一下拉补偿支路421可以位于所述第二集成区632；所述第二集成区632位于所述下拉电路集成区62在所述第一方向X上的一侧。
本示例性实施例中，如图6所示，为图4所示半导体器件中输出电路部分结构的等效电路图。所述第一上拉补偿支路411连接所述信号输出线LDQ、第一控制信号线BPU1，所述第一上拉补偿支路411用于响应所述第一控制信号线BPU1的使能信号以上拉所述输出信号；所述上拉电路1可以包括多个上拉支路11，所述上拉支路11包括第一晶体管T1，所述第一晶体管T1的第一极连接所述信号输出线LDQ，第二极连接第一高电平电源端VDD1、栅极连接上拉控制信号线MPU。
本示例性实施例中，如图6所示，所述第一上拉补偿支路411可以包括第二晶体管T2，所述第二晶体管T2的第一极连接所述信号输出线LDQ，第二极可以连接第二高电平电源端VDD2，栅极可以连接所述第一控制信号线BPU1。第一控制信号线BPU1可以在上拉控制信号线MPU输出有效电平时输出有效电平，以导通第一上拉补偿支路411，导通的第一上拉补偿支路411将第二高电平电源端VDD2的高电平信号传输到信号输出线LDQ，以对信号输出线LDQ上的信号进行上拉补偿。第一控制信号线BPU1可以在上拉控制信号线MPU输出有效电平的起始时刻输出有效电平，例如，当第一晶体管T1为P型晶体管时，第一控制信号线BPU1可以在上拉控制信号线MPU上信号的下降沿输出有效电平，以实现对信号输出线LDQ上信号的上拉补偿。
第一控制信号线BPU1通过接触孔与第一上拉补偿支路411连接，该接触孔与其他导电结构或其他接触孔在膜层延伸方向上具有较小的距离，从而使得第一控制信号线BPU1连接的过孔结构容易与其他结构形成较大的寄生电容。本示例性实施例中，在同一输出电路中，所述上拉电路1中上拉支路11的个数可以大于所述补偿电路4中所述第一上拉补偿支路411的个数。例如，本示例性实施例中，上拉电路1中上拉支路11的个数可以为6个，补偿电路4中所述第一上拉补偿支路411的个数可以为2个。本示例性实施例通过减少第一上拉补偿支路411的个数，可以降低第一控制信号线BPU1与第一上拉补偿支路411之间过孔的数量，从而可以有效的降低第一控制信号线BPU1的寄生电容。
其中，第一上拉补偿支路411的排列方向可以垂直于或平行于上拉电路中上拉支路11的排列方向，或者说，第二晶体管T2的排列方向可以垂直于或平行于第一晶体 管T1的排列方向。需要说明的是，排列方向的限定并不对栅长方向造成限制，示例性的，当第二晶体管T2的排列方向垂直于第一晶体管T1的排列方向时，第二晶体管T2的栅长方向可以平行于或垂直于第一晶体管T1的栅长方向。
本示例性实施例减少了第一上拉补偿支路411的数量，为了保证第一上拉补偿支路411对输出信号的上拉能力，本示例性实施例可以相应增加第二晶体管T2的尺寸，从而使得单个第一上拉补偿支路411具有更强的驱动能力。由于补偿电路集成区63位于上拉电路集成区61和下拉下路集成区62构成的整体的一侧，增大第二晶体管T2的尺寸对上拉电路1中第一晶体管T1的影响较小，即不会挤占过度某一第一晶体管T1的版图面积，这使得增大第二晶体管T2的尺寸且减少第一上拉补偿支路411的数量这一方案可以实现。本示例性实施例中，所述第二晶体管T2的尺寸可以大于所述第一晶体管T1的尺寸。
本示例性实施例中，如图4、5、6所示，所述第一下拉补偿支路421可以连接所述信号输出线LDQ、第二控制信号线BPD2，所述第一下拉补偿支路421可以用于响应所述第二控制信号线BPD2的使能信号以下拉所述输出信号；所述下拉电路2可以包括多个下拉支路21，所述下拉支路21可以包括第三晶体管T3，所述第三晶体管T3的第一极连接所述信号输出线LDQ，第二极连接第一低电平电源端VSS1，栅极连接下拉控制信号线MPD。
本示例性实施例中，如图4、5、6所示，所述第一下拉补偿支路421可以包括第四晶体管T4，所述第四晶体管T4的第一极连接所述信号输出线LDQ，第二极连接第二低电平电源端VSS2。第二控制信号线BPD2可以在下拉控制信号线MPD输出有效电平的起始时刻输出有效电平，以导通第一下拉补偿支路421，导通的第一下拉补偿支路421可以将第二低电平电源端VSS2的低电平信号传输到信号输出线LDQ，以对信号输出线LDQ上的信号进行下拉。
本示例性实施例中，第二控制信号线BPD2通过接触孔与第一下拉补偿支路421连接，第二控制信号线BPD2连接的接触孔与其他导电结构或其他接触孔在膜层延伸方向上具有较小的距离，从而使得第二控制信号线BPD2连接的过孔结构容易与其他结构形成较大的寄生电容。本示例性实施例中，在同一输出电路中，所述下拉电路2中下拉支路21的个数可以大于所述补偿电路4中所述第一下拉补偿支路421的个数。例如，本示例性实施例中，下拉电路2下拉支路21的个数可以为6个，补偿电路4中所述第一下拉补偿支路421的个数可以为2个。本示例性实施例通过减少第一下拉补偿支路421的个数，可以降低第二控制信号线BPD2与第一下拉补偿支路421之间过孔的数量，从而可以有效的降低第二控制信号线BPD2的寄生电容。
本示例性实施例减少了第一下拉补偿支路421的数量，为了保证第一下拉补偿支路421对输出信号的下拉能力，本示例性实施例可以相应增加第四晶体管T4的尺寸，从而使得单个第一下拉补偿支路421具有更强的驱动能力。例如，本示例性实施例中， 所述第四晶体管T4的尺寸可以大于所述第三晶体管T3的尺寸，增大第四晶体管T4的尺寸的可行性原理可参考第二晶体管T2。
如图4、6所示，该输出电路还可以包括开关电路3，开关电路3可以包括多个开关支路31，开关支路31可以包括第五晶体管T5，第五晶体管T5的第一极可以连接第一高电平电源端VDD1，第二极连接第一晶体管T1的第二极。
需要说明的是，本示例性实施例中，第一高电平电源端VDD1和第二高电平电源端VDD2可以共用同一高电平电源端，第一低电平电源端VSS1和第二低电平电源端VSS2可以共用同一低电平电源端。
本示例性实施例中，如图5所示，多个所述上拉支路11可以沿所述第一方向X分布，多个所述下拉支路21可以沿所述第一方向X分布，所述信号输出线LDQ所在区域可以位于所述上拉电路集成区61和所述下拉电路集成区62之间；所述第一控制信号线BPU1、上拉控制信号线MPU、第二控制信号线BPD2、下拉控制信号线MPD可以沿所述第一方向X延伸，所述第一控制信号线BPU1所在区域可以位于所述上拉控制信号线MPU所在区域和所述信号输出线LDQ所在区域之间，所述第二控制信号线BPD2所在区域可以位于所述下拉控制信号线MPD所在区域和所述信号输出线LDQ所在区域之间。第一控制信号线BPU1可以用于屏蔽上拉控制信号线MPU和信号输出线LDQ之间的噪音干扰。第二控制信号线BPD2可以用于屏蔽下拉控制信号线MPD和信号输出线LDQ之间的噪音干扰。
应该理解的是，在其他示例性实施例中，图5中第一上拉补偿支路411的集成区也可以位于上拉电路集成区61在第二方向上的一侧，第二方向和第一方向X相反。该设置可以增加第一控制信号线BPU1与输出焊盘Dqpad之间的距离，从而降低第一控制信号线BPU1与输出焊盘Dqpad之间的寄生电容。同理，第一下拉补偿支路421的集成区也可以位于下拉电路集成区62在第二方向上的一侧。如图7所示，为本公开半导体器件另一种示例性实施例的结构版图。本示例性实施例中，所述信号输出线LDQ沿第一方向X延伸且用于沿所述第一方向X传输信号。所述补偿电路集成区63可以位于所述上拉电路集成区61在第二方向上的一侧，且所述补偿电路集成区63可以位于所述下拉电路集成区62在所述第二方向上的一侧，所述第二方向和所述第一方向X相反。
本示例性实施例中，所述补偿电路4可以包括至少一个第二上拉补偿支路412；所述补偿电路集成区63还可以包括第三集成区633，所述第二上拉补偿支路412可以位于所述第三集成区633；所述第三集成区633可以位于所述上拉电路集成区61在所述第二方向上的一侧。
本示例性实施例中，所述补偿电路4还可以包括至少一个第二下拉补偿支路422；所述补偿电路集成区63还可以包括第四集成区634，所述第二下拉补偿支路422可以位于所述第四集成区634；所述第四集成区634可以位于所述下拉电路集成区62在所 述第二方向上的一侧。
需要说明的是，尽管在图7所示结构版图中，第二上拉补偿支路412和第二下拉补偿支路422的排列方向平行于上拉支路11和下拉支路21的排列方向，但这仅仅只是作为一个示例，实际上，第二上拉补偿支路412和第二下拉补偿支路422的排列方向还可以垂直于上拉支路11和下拉支路21的排列方向。
本示例性实施例中，如图8所示，为图7所示半导体器件中输出电路部分结构的等效电路图。所述第二上拉补偿支路412可以连接上拉控制信号线MPU，第二上拉补偿支路412可以用于同步补偿所述上拉控制信号线MPU上的信号。第二上拉补偿支路412可以与上拉控制信号线MPU一一对应设置，第二上拉补偿支路412可以用于同步补偿与其对应的上拉控制信号线MPU上的信号，每一第二上拉补偿支路412中包含的晶体管的数量可以根据实际需要进行设置，图8所示实施例包含两个晶体管，即第六晶体管T6、第七晶体管T7。
本示例性实施例中，所述第二下拉补偿支路422连接下拉控制信号线MPD，第二下拉补偿支路422可以用于同步补偿所述下拉控制信号线MPD上的信号。第二下拉补偿支路422可以与下拉控制信号线MPD一一对应设置，第二下拉补偿支路422可以用于同步补偿与其对应的下拉控制信号线MPD上的信号，每一第二下拉补偿支路422中包含的晶体管的数量可以根据实际需要进行设置。
图8仅示出了一个第二上拉补偿支路412和一个第二下拉补偿支路422。本示例性实施例中，“同步补偿”可以理解为：在被补偿信号的上升沿上拉被补偿信号，在被补偿信号的下降沿下拉被补偿信号，从而使得被补偿信号的上升沿和下降沿更加陡峭。
如图8所示，第二上拉补偿支路412可以包括第六晶体管T6、第七晶体管T7，第六晶体管T6的第一极可以连接上拉控制信号线MPU，第六晶体管T6的第二极可以用于接收高电平电源信号；第七晶体管T7的第一极可以连接上拉控制信号线MPU，第七晶体管T7的第二极可以用于接收低电平电源信号。第六晶体管T6可以在上拉控制信号线MPU上信号的上升沿导通，以通过高电平电源信号对上拉控制信号线MPU上信号进行上拉；第七晶体管T7可以在上拉控制信号线MPU上信号的下降沿导通，以通过低电平电源信号对上拉控制信号线MPU上信号进行下拉。
同理，第二下拉补偿支路422可以包括第八晶体管T8、第九晶体管T9，第八晶体管T8的第一极可以连接下拉控制信号线MPD，第八晶体管T8的第二极可以用于接收高电平电源信号；第九晶体管T9的第一极可以连接下拉控制信号线MPD，第九晶体管T9的第二极可以用于接收低电平电源信号。第八晶体管T8可以在下拉控制信号线MPD上信号的上升沿导通，以通过高电平电源信号对下拉控制信号线MPD上信号进行上拉；第九晶体管T9可以在下拉控制信号线MPD上信号的下降沿导通，以通过低电平电源信号对下拉控制信号线MPD上信号进行下拉。
可以理解的是，本示例性实施例仅示出了第二上拉补偿支路412和第二下拉补偿 支路422均包含两个晶体管，且两个晶体管中一个用于上拉一个用于下拉；在其他实施例中，第二上拉补偿支路412和第二下拉补偿支路422可均包含一个晶体管，第二上拉补偿支路412中的晶体管用于上拉，第二下拉补偿支路中的晶体管用于下拉；并列的，第二上拉补偿支路412和第二下拉补偿支路422可均包含多个晶体管(大于等于两个)，第二上拉补偿支路412中的晶体管均用于上拉，第二下拉补偿支路中的晶体管均用于下拉。
如图7所示，上拉控制信号线MPU的部分结构可以位于第三集成区633，上拉控制信号线MPU可以分别通过过孔H连接第六晶体管T6、第七晶体管T7。下拉控制信号线MPD的部分结构可以位于第四集成区634，下拉控制信号线MPD可以分别通过过孔H连接第八晶体管T8、第九晶体管T9。该设置可以提高输出电路的集成度，降低输出电路的版图空间。
应该理解的是，在其他示例性实施例中，上拉控制信号线MPU也可以位于第三集成区633以外，下拉控制信号线MPD也可以位于第四集成区634以外。例如，在垂直于第一方向X的方向上，第三集成区633可以位于上拉电路集成区61和下拉电路集成区62之间，第四集成区634也可以位于上拉电路集成区61和下拉电路集成区62之间。此外，在其他示例性实施例中，该半导体器件即可以设置有第一集成区631、第二集成区632，同时也可以设置有第三集成区633、第四集成区634。
相应的，该输出电路即可以包括位于第一集成区631的第一上拉补偿支路411、位于第二集成区632的第一下拉补偿支路421，同时也可以包括位于第三集成区633的第二上拉补偿支路412、位于第四集成区634的第二下拉补偿支路422。此外，位于第三集成区633的第二上拉补偿支路412、位于第四集成区634的第二下拉补偿支路422也可以直接为输出信号线LDQ进行上拉补偿和下拉补偿，即第二上拉补偿支路412和第二下拉补偿支路422中的晶体管一极直接与输出信号线LDQ连接，另一极连接高电平电源或低电平电源，以实现上拉或下拉。
本示例性实施例还提供一种存储器，所述存储器可以包括上述的半导体器件。例如，该存储器可以为动态随机存取存储器。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (19)

  1. 一种半导体器件，其中，所述半导体器件包括互不交叠的上拉电路集成区、下拉电路集成区、补偿电路集成区，所述半导体器件还包括输出电路，所述输出电路包括：
    上拉电路，连接于信号输出线，所述上拉电路位于所述上拉电路集成区；
    下拉电路，连接于所述信号输出线，所述下拉电路位于所述下拉电路集成区；
    补偿电路，用于增强所述信号输出线上输出信号的驱动能力，所述补偿电路位于所述补偿电路集成区。
  2. 根据权利要求1所述的半导体器件，其中，所述信号输出线沿第一方向延伸且用于沿所述第一方向传输信号；
    所述补偿电路集成区的至少部分区域位于所述上拉电路集成区在所述第一方向上的一侧，且所述补偿电路集成区的至少部分区域位于所述下拉电路集成区在所述第一方向上的一侧。
  3. 根据权利要求2所述的半导体器件，其中，所述补偿电路包括至少一个第一上拉补偿支路，所述第一上拉补偿支路用于上拉所述输出信号；
    所述补偿电路集成区包括第一集成区，所述第一上拉补偿支路位于所述第一集成区；
    所述第一集成区位于所述上拉电路集成区在所述第一方向上的一侧。
  4. 根据权利要求2所述的半导体器件，其中，所述补偿电路包括至少一个第一下拉补偿支路，所述第一下拉补偿支路用于下拉所述输出信号；
    所述补偿电路集成区包括第二集成区，所述第一下拉补偿支路位于所述第二集成区；
    所述第二集成区位于所述下拉电路集成区在所述第一方向上的一侧。
  5. 根据权利要求3所述的半导体器件，其中，所述第一上拉补偿支路连接所述信号输出线、第一控制信号线，所述第一上拉补偿支路用于响应所述第一控制信号线的使能信号以上拉所述输出信号；
    所述上拉电路包括多个上拉支路，所述上拉支路包括第一晶体管，所述第一晶体管的第一极连接所述信号输出线，所述第一晶体管的第二极连接第一高电平电源端，所述第一晶体管的栅极连接上拉控制信号线。
  6. 根据权利要求5所述的半导体器件，其中，所述第一上拉补偿支路包括第二晶体管，所述第二晶体管的第一极连接所述信号输出线，所述第二晶体管的第二极用 于接收高电平电源电压，所述第二晶体管的栅极连接所述第一控制信号线；
    其中，所述第一晶体管的尺寸小于所述第二晶体管的尺寸。
  7. 根据权利要求5或6所述的半导体器件，其中，所述上拉电路中上拉支路的个数大于所述补偿电路中所述第一上拉补偿支路的个数。
  8. 根据权利要求4所述的半导体器件，其中，所述第一下拉补偿支路连接所述信号输出线、第二控制信号线，所述第一下拉补偿支路用于响应所述第二控制信号线的使能信号以下拉所述输出信号；
    所述下拉电路包括多个下拉支路，所述下拉支路包括第三晶体管，所述第三晶体管的第一极连接所述信号输出线，所述第三晶体管的第二极连接第一低电平电源端，所述第三晶体管的栅极连接下拉控制信号线。
  9. 根据权利要求8所述的半导体器件，其中，所述第一下拉补偿支路包括第四晶体管，所述第四晶体管的第一极连接所述信号输出线，所述第四晶体管的第二极用于接收低电平电源电压，所述第四晶体管的栅极连接所述第二控制信号线；
    其中，所述第三晶体管的尺寸小于所述第四晶体管的尺寸。
  10. 根据权利要求8或9所述的半导体器件，其中，所述下拉电路中下拉支路的个数大于所述补偿电路中所述第一下拉补偿支路的个数。
  11. 根据权利要求5所述的半导体器件，其中，所述补偿电路包括至少一个第一下拉补偿支路，所述下拉电路包括多个下拉支路；
    所述第一下拉补偿支路连接所述信号输出线、第二控制信号线，用于响应所述第二控制信号线的使能信号下拉所述输出信号；
    所述下拉支路连接所述信号输出线、第一低电平电源端、下拉控制信号线，用于响应所述下拉控制信号线的信号将所述第一低电平电源端的信号传输到所述信号输出线；
    多个所述上拉支路沿所述第一方向分布，多个所述下拉支路沿所述第一方向分布，所述信号输出线所在区域位于所述上拉电路集成区和所述下拉电路集成区之间；
    所述第一控制信号线、上拉控制信号线、第二控制信号线、下拉控制信号线沿所述第一方向延伸，所述第一控制信号线所在区域位于所述上拉控制信号线所在区域和所述信号输出线所在区域之间，所述第二控制信号线所在区域位于所述下拉控制信号线所在区域和所述信号输出线所在区域之间。
  12. 根据权利要求1所述的半导体器件，其中，所述信号输出线沿第一方向延伸 且用于沿所述第一方向传输信号；
    所述补偿电路集成区的至少部分区域位于所述上拉电路集成区在第二方向上的一侧，且所述补偿电路集成区的至少部分区域位于所述下拉电路集成区在所述第二方向上的一侧，所述第二方向和所述第一方向相反。
  13. 根据权利要求12所述的半导体器件，其中，所述补偿电路包括至少一个第二上拉补偿支路；
    所述补偿电路集成区包括第三集成区，所述第二上拉补偿支路位于所述第三集成区；
    所述第三集成区位于所述上拉电路集成区在所述第二方向上的一侧。
  14. 根据权利要求12所述的半导体器件，其中，所述补偿电路包括至少一个第二下拉补偿支路；
    所述补偿电路集成区包括第四集成区，所述第二下拉补偿支路位于所述第四集成区；
    所述第四集成区位于所述下拉电路集成区在所述第二方向上的一侧。
  15. 根据权利要求13所述的半导体器件，其中，所述上拉电路包括多个上拉支路，所述上拉支路包括第一晶体管，所述第一晶体管的第一极连接所述信号输出线，所述第一晶体管的第二极连接第一高电平电源端，所述第一晶体管的栅极连接上拉控制信号线；
    所述第二上拉补偿支路连接所述上拉控制信号线，所述第二上拉补偿支路用于同步补偿所述上拉控制信号线上的信号。
  16. 根据权利要求14所述的半导体器件，其中，所述下拉电路包括多个下拉支路，所述下拉支路包括第三晶体管，所述第三晶体管的第一极连接所述信号输出线，所述第三晶体管的第二极连接第一低电平电源端，所述第三晶体管的栅极连接下拉控制信号线；
    所述第二下拉补偿支路连接所述下拉控制信号线，所述第二下拉补偿支路用于同步补偿所述下拉控制信号线上的信号。
  17. 根据权利要求13所述的半导体器件，其中，所述第二上拉补偿支路连接所述信号输出线、第三控制信号线，用于响应所述第三控制信号线的使能信号以上拉所述输出信号。
  18. 根据权利要求14所述的半导体器件，其中，所述第二下拉补偿支路连接所 述信号输出线、第四控制信号线，用于响应所述第四控制信号线的使能信号以下拉所述输出信号。
  19. 一种存储器，所述存储器包括权利要求1-18任一项所述的半导体器件。
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Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180204521A1 (en) * 2016-04-20 2018-07-19 Boe Technology Group Co., Ltd. Shift register unit, driving method, gate driving circuit and display device
CN112187214A (zh) * 2020-10-09 2021-01-05 上海安路信息科技有限公司 Fpga的io阻抗校准电路及其方法
CN113437962A (zh) * 2020-03-23 2021-09-24 长鑫存储技术(上海)有限公司 输出驱动电路及存储器
CN114242129A (zh) * 2020-09-09 2022-03-25 三星电子株式会社 存储设备和包括所述存储设备的存储系统

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7116129B2 (en) * 2004-07-20 2006-10-03 Micron Technology, Inc. Temperature-compensated output buffer method and circuit
US7389194B2 (en) * 2005-07-06 2008-06-17 Rambus Inc. Driver calibration methods and circuits
KR102185284B1 (ko) * 2013-12-12 2020-12-01 삼성전자 주식회사 온 다이 터미네이션 저항들의 부정합을 보상하는 버퍼 회로, 반도체 장치 반도체 장치의 동작방법
CN106356015B (zh) * 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置
US10885955B2 (en) * 2019-04-03 2021-01-05 Micron Technology, Inc. Driver circuit equipped with power gating circuit
US10693460B1 (en) * 2019-08-19 2020-06-23 Micron Technology, Inc. Fuse adjustable output driver
US11463076B1 (en) * 2021-06-29 2022-10-04 Nanya Technology Corporation Resistance-adjustable means using at a pull-up or pull-down driver of an OCD circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180204521A1 (en) * 2016-04-20 2018-07-19 Boe Technology Group Co., Ltd. Shift register unit, driving method, gate driving circuit and display device
CN113437962A (zh) * 2020-03-23 2021-09-24 长鑫存储技术(上海)有限公司 输出驱动电路及存储器
CN114242129A (zh) * 2020-09-09 2022-03-25 三星电子株式会社 存储设备和包括所述存储设备的存储系统
CN112187214A (zh) * 2020-10-09 2021-01-05 上海安路信息科技有限公司 Fpga的io阻抗校准电路及其方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4307305A4 *

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EP4307305A4 (en) 2024-05-22
EP4307305A1 (en) 2024-01-17

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