WO2023226077A1 - 反熔丝结构、反熔丝阵列及存储器 - Google Patents

反熔丝结构、反熔丝阵列及存储器 Download PDF

Info

Publication number
WO2023226077A1
WO2023226077A1 PCT/CN2022/096906 CN2022096906W WO2023226077A1 WO 2023226077 A1 WO2023226077 A1 WO 2023226077A1 CN 2022096906 W CN2022096906 W CN 2022096906W WO 2023226077 A1 WO2023226077 A1 WO 2023226077A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate structure
antifuse
unit
region
extension part
Prior art date
Application number
PCT/CN2022/096906
Other languages
English (en)
French (fr)
Inventor
侯闯明
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to JP2022552391A priority Critical patent/JP2024524780A/ja
Priority to KR1020227031205A priority patent/KR20220130243A/ko
Priority to EP22760861.9A priority patent/EP4303921A1/en
Priority to US17/929,747 priority patent/US20230386589A1/en
Publication of WO2023226077A1 publication Critical patent/WO2023226077A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • the present application relates to the field of integrated circuits, and in particular to an antifuse structure, an antifuse array and a memory.
  • fuse components are widely used in integrated circuits due to their various uses. For example, multiple circuit modules with the same function are designed in an integrated circuit as backup. When one of the circuit modules is found to be faulty, the circuit module and other functional circuits in the integrated circuit are blown out through the fuse element, and the circuit module with the same function is used. Another circuit module replaces the failed circuit module.
  • Anti-fuse With the continuous development of semiconductor technology, anti-fuse (Anti-fuse) technology has attracted the attention of many inventors and manufacturers.
  • Antifuse elements store information by changing from an insulating state to a conducting state. Writing information to the antifuse element is performed by dielectric breakdown caused by application of high voltage.
  • the antifuse memory cell has capacitive characteristics before programming, and no conduction channel is formed; when programming breakdown occurs, conduction channels will be formed at both ends of the cell, allowing current to pass through.
  • the size of the conduction current is related to the programming effect. .
  • the antifuse structure usually contains an antifuse unit (AF cell) and a selection transistor (XADD).
  • AF cell antifuse unit
  • XADD selection transistor
  • the area of the antifuse array must also be reduced to save valuable space for the memory array.
  • the design rules and manufacturability requirements of the antifuse structure it is difficult to ensure the antifuse array.
  • the area of the antifuse array cannot be reduced and cannot meet the needs of chip miniaturization.
  • the present application provides an antifuse structure, an antifuse array and a memory, which can reduce the area of the antifuse array while ensuring that the number of antifuse units remains unchanged.
  • the present application provides an antifuse structure, which includes: a first unit including a first selection transistor, a first antifuse unit and a second antifuse unit; a second unit including a second selection transistor, a third antifuse unit; Fuse unit and fourth anti-fuse unit; wherein the first unit and the second unit share an active area, and a first extension part and a third extension part that are independent of each other extend from the first side of the active area.
  • Two extension parts, a third extension part and a fourth extension part that are independent of each other extend from the second side of the active area, the first side is opposite to the second side, and the first anti-fuse unit
  • the second anti-fuse unit is disposed on the first extension part
  • the second anti-fuse unit is disposed on the second extension part
  • the third anti-fuse unit is disposed on the third extension part
  • the fourth anti-fuse unit is disposed on the second extension part.
  • the unit is provided in the fourth extension.
  • the method further includes: a first gate structure disposed on the surface of the active area; a second gate structure disposed on the surface of the active area and spaced apart from the first gate structure. ; A third gate structure, disposed on the surface of the first extension; a fourth gate structure, disposed on the surface of the second extension; a fifth gate structure, disposed on the surface of the third extension; A six-gate structure is provided on the surface of the fourth extension; a first doping region is provided in the active region between the first gate structure and the second gate structure; a second doping region A region is disposed in the active region on the side of the first gate structure away from the second gate structure and in the first extension part and the second extension part; a third doping region is disposed in the third The second gate structure is in the active area on the side away from the first gate structure and in the third extension part and the fourth extension part; wherein the first gate structure and the first doped region, the third extension part
  • the two doped regions constitute the first selection transistor, the third gate structure and the second doped regions
  • first side and the second side are oppositely arranged along a first direction
  • first gate structure and the second gate structure are arranged along the first direction
  • the third gate structure and the fourth gate structure are arranged along a second direction, and the second direction is perpendicular to or has an acute angle with the first direction.
  • the fifth gate structure and the sixth gate structure are arranged along the second direction, and the second direction is perpendicular to or has an acute angle with the first direction.
  • the method further includes: a bit line connection structure connected to a first doping region between the first gate structure and the second gate structure, and the first doping region can The bit line is connected through the bit line connection structure.
  • the method further includes: a first connection structure connected to the third gate structure, and the third gate structure can be connected to a programming line through the first connection structure, and the first A connection structure is provided on a side of the first extension part away from the second extension part; a second connection structure is connected to the fourth gate structure, and the fourth gate structure can pass through the second extension part.
  • the two connection structures are connected to another programming line, and the fourth connection structure is disposed on a side of the second extension area away from the first extension.
  • the third gate structure includes a third main region provided corresponding to the first extension part and a third sub-region protruding in a direction away from the second extension part.
  • a connection structure is connected to the third sub-region.
  • the fourth gate structure includes a fourth main region provided corresponding to the second extension part and a fourth sub-region protruding in a direction away from the first extension part. area, the second connection structure is connected to the fourth sub-area.
  • it also includes: a third connection structure connected to the fifth gate structure, and the fifth gate structure can be connected to a programming line through the third connection structure, and the third A connection structure is provided on a side of the third extension part away from the fourth extension part; a fourth connection structure is connected to the sixth gate structure, and the sixth gate structure can pass through the fourth extension part.
  • the connection structure is connected to another programming line, and the fourth connection structure is provided on a side of the fourth extension part away from the third extension part.
  • the fifth gate structure includes a fifth main region provided corresponding to the third extension part and a fifth sub-region protruding in a direction away from the fourth extension part, and the third The connection structure is connected to the fifth sub-region, and the sixth gate structure includes a sixth main region provided corresponding to the fourth extension part and a sixth sub-region protruding in a direction away from the third extension part. , the fourth connection structure is connected to the sixth sub-region.
  • the first selection transistor and the second selection transistor are arranged symmetrically about a first axis, and the first antifuse unit and the third antifuse unit are arranged symmetrically about the third axis.
  • One axis is an axis of symmetry, and the second anti-fuse unit and the third anti-fuse unit are arranged symmetrically with the first axis being an axis of symmetry.
  • an antifuse array which includes a plurality of antifuse structures as described above, and the plurality of antifuse structures are arranged in an array along the first direction and the second direction, and the The first direction is perpendicular to or has an acute angle with the second direction.
  • adjacent antifuse units of adjacent antifuse structures share the same gate structure.
  • the first selection transistors of the antifuse structure arranged along the second direction share the same gate structure, and the second selection transistors share the same gate structure.
  • a memory which includes the antifuse array as described above.
  • it also includes a plurality of programming lines arranged along the first direction and extending along the second direction.
  • One row of antifuse structures arranged along the second direction corresponds to four of the programming lines.
  • the four programming lines are respectively connected to the first anti-fuse unit, the second anti-fuse unit, the third anti-fuse unit and the fourth anti-fuse unit of the anti-fuse structure. connect.
  • a plurality of bit lines arranged along the second direction and extending along the first direction are further included, and a column of antifuse structures arranged along the first direction shares the same bit line.
  • the first unit and the second unit share the same active area, which can eliminate the negative impact caused by the first unit and the second unit using different active areas.
  • the gap between the source areas reduces the area of the antifuse structure.
  • each unit contains two antifuse units, and they are arranged in independent extensions, which can double the number under the same area. That is to say, when the number of anti-fuse units is the same, the anti-fuse structure of the present application only takes up about half of the area, which meets the need for miniaturization.
  • Figure 1A is a schematic diagram of an antifuse structure provided by some embodiments of the present application.
  • Figure 1B is a schematic diagram of an active area provided by some embodiments of the present application.
  • Figure 2 is a schematic diagram of an antifuse array provided by some embodiments of the present application.
  • Figure 3 is a schematic diagram of a memory provided by some embodiments of the present application.
  • Figure 1A is a schematic diagram of an antifuse structure provided by some embodiments of the present application.
  • 1B is a schematic diagram of an active area provided by some embodiments of the present application. Please refer to Figures 1A and 1B.
  • the antifuse structure 10 includes a first Unit 101 and second unit 102.
  • the first unit 101 includes a first selection transistor, a first antifuse unit and a second antifuse unit
  • the second unit 102 includes a second selection transistor, a third antifuse unit and a fourth antifuse. unit.
  • the first unit 101 and the second unit 102 share an active area AA, and a first extension portion AA1 and a second extension AA2 that are independent of each other extend from the first side of the active area AA, so A third extension part AA3 and a fourth extension part AA4 that are independent of each other extend from the second side of the active area AA, the first side and the second side are arranged oppositely, and the first anti-fuse unit is arranged on The first extension part AA1, the second anti-fuse unit is arranged on the second extension part AA2, the third anti-fuse unit is arranged on the third extension part AA3, and the fourth anti-fuse unit is arranged on the second extension part AA2.
  • the wire unit is provided at the fourth extension part AA4.
  • the first unit 101 and the second unit 102 share the same active area AA, which can eliminate the problem caused by using different active areas AA for the first unit 101 and the second unit 102.
  • the gap between the active areas AA reduces the area of the antifuse structure.
  • each unit contains two antifuse units, and they are arranged in independent extensions, so that the area of the antifuse structure can be increased under the same area. Double the number of anti-fuse units, that is to say, when the design number of anti-fuse units is the same, the anti-fuse structure of the present application only takes up about half of the area, meeting the need for miniaturization.
  • the first selection transistor, the first anti-fuse unit, the second anti-fuse unit, the second selection transistor, the third anti-fuse unit and the fourth anti-fuse are described in detail below.
  • a first side of the active area AA is extended with a first extension part AA1 and a second extension part AA2 that are independent of each other, and a second side of the active area AA is extended with a third extension part AA3 and a fourth extension part that are independent of each other. Extension AA4.
  • the first side and the second side are arranged oppositely along a first direction (Y direction in the figure).
  • the first side is the upper end of the active area AA
  • the The second side is the lower end of the active area AA.
  • the antifuse structure includes a first gate structure G1.
  • the first gate structure G1 is disposed on the surface of the active area AA.
  • the first gate structure G1 extends along the second direction.
  • the second direction is the horizontal direction X.
  • the antifuse structure further includes a first word line connection structure T1, and the first gate structure G1 is electrically connected to the peripheral control circuit through the first word line connection structure T1, that is, the first word line connection structure T1 is electrically connected to the peripheral control circuit.
  • the first word line connection structure T1 serves as a conductive plug to realize electrical connection between the first gate structure G1 and the peripheral control circuit.
  • the antifuse structure also includes a second gate structure G2.
  • the second gate structure G2 is disposed on the surface of the active area AA and is spaced apart from the first gate structure G1.
  • the first gate structure G1 and the second gate structure G2 are connected to different word lines to achieve separate control of the first unit 101 and the second unit 102 .
  • the first gate structure G1 and the second gate structure G2 both extend along the second direction, and the second gate structure G2 and the first gate structure G1 extend along the second direction.
  • One direction is spaced apart, and the first direction is perpendicular to or has an acute angle with the second direction.
  • the first direction is perpendicular to the second direction.
  • the second direction is the horizontal direction X
  • the first direction is the vertical direction Y.
  • the first direction and the second direction have an acute angle.
  • the second direction is the horizontal direction X
  • the first direction is an acute angle with the horizontal direction. direction.
  • the antifuse structure further includes a second word line connection structure T2, and the second gate structure G2 is electrically connected to the peripheral control circuit through the second word line connection structure T2, that is, the second gate structure G2 is electrically connected to the peripheral control circuit through the second word line connection structure T2.
  • the second word line connection structure T2 serves as a conductive plug to realize electrical connection between the second gate structure G2 and the peripheral control circuit.
  • the antifuse structure further includes a third gate structure G3, which is disposed on the surface of the first extension AA1 and can be connected to a programming line.
  • the third gate structure G3 extends along the second direction, that is, the extending direction of the third gate structure G3 and the first gate structure G1 are consistent. In the first direction, the third gate structure G3 is spaced apart from the first gate structure G1, and the third gate structure G3 is disposed away from the first gate structure G1.
  • the third gate structure G3 is only provided on the surface of the first extension part AA1 and is not provided on the surface of the second extension part AA2.
  • the antifuse structure further includes a first connection structure T3.
  • the first connection structure T3 is connected to the third gate structure G3, and the third gate structure G3 can be connected to the programming line located above it through the first connection structure T3. That is, the first connection structure T3 serves as a conductive plug to realize electrical connection between the third gate structure G3 and its upper programming line.
  • the first connection structure T3 is provided on a side of the first extension AA1 away from the second extension AA2.
  • the third gate structure G3 includes a third main region G31 provided corresponding to the first extension AA1 and a third sub-region G32 protruding in a direction away from the second extension AA2, that is, The third main area G31 is arranged opposite to the first extension part AA1, the third sub-area G32 is staggered with the first extension part AA1, and the first connection structure T3 is located away from the second extension part AA1.
  • the third sub-region G32 of the extension AA2 is connected.
  • the antifuse structure also includes a fourth gate structure G4.
  • the fourth gate structure G4 is disposed on the surface of the second extension AA2 and can be connected to the programming line.
  • the fourth gate structure G4 extends along the second direction, that is, the extending direction of the fourth gate structure G4 and the first gate structure G1 are consistent. In the first direction, the fourth gate structure G4 is spaced apart from the first gate structure G1, and the fourth gate structure G4 is disposed away from the first gate structure G1.
  • One side of the second gate structure G2; in the second direction, the fourth gate structure G4 is spaced apart from the third gate structure G3, and the fourth gate structure G4 is only provided on the third gate structure G2.
  • the surface of the second extension part AA2 is not provided on the surface of the first extension part AA1. It can be understood that in some embodiments, the lengths of the third gate structure G3 and the fourth gate structure G4 along the second direction are both smaller than the length of the first gate structure G1 along the second direction. .
  • the antifuse structure further includes a second connection structure T4.
  • the second connection structure T4 is connected to the fourth gate structure G4, and the fourth gate structure G4 can be connected to the programming line located above it through the second connection structure T4. That is, the second connection structure T4 serves as a conductive plug to realize electrical connection between the fourth gate structure G4 and its upper programming line.
  • the third gate structure G3 and the fourth gate structure G4 are connected to different programming lines to achieve separate control of the first antifuse unit and the second antifuse unit.
  • the second connection structure T4 is provided on a side of the second extension AA2 away from the first extension AA1.
  • the fourth gate structure G4 includes a fourth main region G41 provided corresponding to the second extension AA2 and a fourth sub-region G42 protruding in a direction away from the first extension AA1, that is, The fourth main area G41 is arranged opposite to the second extension part AA2, the fourth sub-area G42 is staggered with the second extension part AA2, and the second connection structure T4 is located away from the first extension part AA2.
  • the fourth subregion G42 of the extended portion AA1 is connected.
  • the antifuse structure also includes a fifth gate structure G5.
  • the fifth gate structure G5 is disposed on the surface of the third extension AA3 and can be connected to the programming line.
  • the fifth gate structure G5 extends along the second direction, that is, the extension direction of the fifth gate structure G5 and the second gate structure G2 are consistent.
  • the fifth gate structure G5 is spaced apart from the second gate structure G2, and the fifth gate structure G5 is disposed away from the second gate structure G2.
  • the fifth gate structure G5 is only provided on the surface of the third extension part AA3 but not on the surface of the fourth extension part AA4.
  • the antifuse structure further includes a third connection structure T5.
  • the third connection structure T5 is connected to the fifth gate structure G5, and the fifth gate structure G5 can be connected to the programming line located above it through the third connection structure T5. That is, the third connection structure T5 serves as a conductive plug to realize the electrical connection between the fifth gate structure G5 and its upper programming line.
  • the third connection structure T5 is provided on a side of the third extension part AA3 away from the fourth extension part AA4.
  • the fifth gate structure G5 includes a fifth main region G51 provided corresponding to the third extension portion AA3 and a fifth sub-region G52 protruding in a direction away from the fourth extension portion AA4. That is, the fifth main region G51 and the third extension part AA3 are arranged directly opposite each other, the fifth sub-region G52 and the third extension part AA3 are arranged staggeredly, and the third connection structure T5 is located away from the third extension part AA3.
  • the fifth sub-region G52 of the three extended portions AA3 is connected.
  • the antifuse structure also includes a sixth gate structure G6.
  • the sixth gate structure G6 is disposed on the surface of the fourth extension AA4 and can be connected to the programming line.
  • the sixth gate structure G6 extends along the second direction, that is, the extension direction of the sixth gate structure G6 and the second gate structure G2 are consistent.
  • the sixth gate structure G6 is spaced apart from the second gate structure G2, and the sixth gate structure G6 is disposed away from the second gate structure G2.
  • One side of the first gate structure G1; in the second direction, the sixth gate structure G6 is spaced apart from the fifth gate structure G5, and the sixth gate structure G6 is only provided on the first gate structure G1.
  • the surface of the fourth extension part AA4 is not provided on the surface of the third extension part AA3. It can be understood that in some embodiments, the lengths of the fifth gate structure G5 and the sixth gate structure G6 along the second direction are both smaller than the length of the second gate structure G2 along the second direction. .
  • the antifuse structure further includes a fourth connection structure T6.
  • the fourth connection structure T6 is connected to the sixth gate structure G6, and the sixth gate structure G6 can be connected to another programming line located above it through the fourth connection structure T6. That is, the fourth connection structure T6 serves as a conductive plug to realize electrical connection between the sixth gate structure G6 and the programming line above it.
  • the fifth gate structure G5 and the sixth gate structure G6 are connected to different programming lines to achieve independent control of the third anti-fuse unit and the fourth anti-fuse unit.
  • the fourth connection structure T6 is provided on a side of the fourth extension part AA4 away from the third extension part AA3.
  • the sixth gate structure G6 includes a sixth main region G61 provided corresponding to the fourth extension AA4 and a sixth sub-region G62 protruding in a direction away from the third extension AA3, that is, The sixth main area G61 is arranged opposite to the fourth extension part AA4, the sixth sub-area G62 is staggered with the fourth extension part AA4, and the fourth connection structure T6 and the sixth sub-area Area G62 connection.
  • the antifuse structure also includes a first doped region D1.
  • the first doped region D1 is disposed in the active area AA between the first gate structure G1 and the second gate structure G2.
  • the active region AA is a P-type well region
  • the first doped region D1 is an N-type doped region.
  • the first doping region D1 is a P-type doping region if the active region AA is an N-type well region.
  • the antifuse structure also includes a bit line connection structure BLC.
  • the bit line connection structure BLC is connected to the first doping region D1 between the first gate structure G1 and the second gate structure, and the first doping region D1 can pass through the bit line connection structure BLC.
  • the line connection structure BLC is connected to the bit lines. That is, the bit line connection structure BLC serves as a conductive plug connecting the first doped region D1 and the bit line to realize the electrical connection between the bit line and the first doped region D1.
  • the antifuse structure also includes a second doped region D2.
  • the second doped region D2 is disposed in the active area AA on the side of the first gate structure G1 away from the second gate structure G2 and in the first extension AA1 and the second extension Within AA2.
  • the second doped region D2 has the same doping type as the first doped region D1 and is opposite to the doping type of the active area AA. If the active area AA is a P-type well region, then the second doped region D2 is an N-type doped region. In other embodiments, if the active region AA is an N-type well region, the second doped region D2 is a P-type doped region.
  • the antifuse structure also includes a third doped region D3.
  • the third doped region D3 is disposed in the active area AA on the side of the second gate structure G2 away from the first gate structure G1 and in the third extension portion AA3 and the fourth extension portion AA4.
  • the third doped region D3 has the same doping type as the first doped region D1 and is opposite to the doping type of the active area AA. If the active area AA is a P-type well region, then the third doped region D3 is an N-type doped region. In other embodiments, if the active region AA is an N-type well region, the third doped region D3 is a P-type doped region.
  • the first gate structure G1, the active region AA below it, the first doping region D1, and the second doping region D2 constitute the first selection transistor.
  • the second doped region D2 is located in the first extension AA1, and the third gate structure G3 and the second doped region D2 located below it form a first antifuse unit. If the second doped region D2 is also located in the second extension AA2, the fourth gate structure G4 and the second doped region D2 located below it form a second antifuse unit.
  • the third main region G31 of the third gate structure G3 serves as an effective region and forms the first antifuse unit with the second doped region D2, and the fourth gate structure G4
  • the fourth main region G41 serves as an effective region and forms the second antifuse unit with the second doped region D2.
  • the second gate structure G2, the active region AA below it, and the first doped region D1 and the third doped region D3 form a second selection transistor.
  • the third doped region D3 is located in the third extended portion AA3, and the fifth gate structure G5 and the third doped region D3 located below it form a third antifuse unit. If the third doped region D3 is also located in the fourth extension AA4, the sixth gate structure G6 and the third doped region D3 located below it form a fourth antifuse unit.
  • the fifth main region G51 of the fifth gate structure G5 serves as an effective region and forms the third antifuse unit with the third doped region D3, and the sixth gate structure G6
  • the sixth main region G61 serves as an effective region and forms the third antifuse unit with the third doped region D3.
  • the first selection transistor and the second selection transistor are arranged symmetrically about the first axis O
  • the first anti-fuse unit and the third anti-fuse unit are arranged symmetrically about the first axis O.
  • the first axis O is arranged symmetrically about the axis of symmetry
  • the second antifuse unit and the fourth antifuse unit are arranged symmetrically about the first axis O, which is beneficial to simplifying the layout design of the antifuse structure. ,OK.
  • the first gate structure G1, the second gate structure G2, the third gate structure G3, the fourth gate structure G4, the fifth gate structure G5 and the Each six-gate structure G6 includes a gate electrode (not labeled in the drawing) and a gate dielectric layer (not labeled in the drawing) located between the gate electrode and the active area AA to realize the basic functions of the gate structure.
  • the material of the gate electrode may be polysilicon (poly)
  • the material of the gate dielectric layer may be silicon oxide, high-K dielectric material, etc.
  • the first unit 101 and the second unit 102 share the same active area AA, which can eliminate the problem caused by the first unit 101 and the second unit 102 using different active areas AA.
  • the gap between the active areas AA reduces the area of the antifuse structure.
  • each unit contains two antifuse units, and they are arranged in independent extensions, so that the area of the antifuse structure can be increased under the same area. Double the number of anti-fuse units, that is to say, when the design number of anti-fuse units is the same, the anti-fuse structure of the present application only takes up about half of the area, meeting the need for miniaturization.
  • FIG. 2 is a schematic diagram of an antifuse array.
  • the antifuse array includes a plurality of antifuse structures as described above.
  • a plurality of the antifuse structures are arranged in an array along a first direction and a second direction, and the first direction is perpendicular to or has an acute angle with the second direction.
  • the first direction is the vertical direction Y
  • the second direction is the horizontal direction X.
  • Figure 2 schematically illustrates six anti-fuse structures, namely anti-fuse structures 20A, 20B, 20C, 20D, 20E and 20F. Among them, three anti-fuse structures are arranged in a group along the second direction.
  • the antifuse structures 20A, 20B and 20C are arranged along the second direction to form the first row; the antifuse structures 20D, 20E and 20F are arranged along the second direction to form the second row; the antifuse structures 20A and 20F are arranged along the second direction to form the second row.
  • 20D is arranged along the first direction to form the first row; the antifuse structures 20B and 20E are arranged along the first direction to form the second row; the antifuse structures 20C and 20F are arranged along the first direction to form the third row. .
  • the first unit 101 please refer to FIG. 1A
  • the second unit 102 please refer to FIG. 1A
  • the gap between the active areas AA caused by the use of different active areas AA in the first unit 101 and the second unit 102 can be eliminated, reducing the area of the antifuse structure.
  • each unit Containing two anti-fuse units and disposing them in independent extensions the number of anti-fuse units can be doubled in the same area. That is to say, when the design number of anti-fuse units is the same, this Applying for an antifuse array only takes up about half the area, meeting the need for miniaturization.
  • adjacent anti-fuse units of adjacent anti-fuse structures share the same gate structure (at least share the gate electrode of the same gate structure) , removes the gap that must exist when using two gate structures, reduces the distance between adjacent antifuse structures, and further reduces the space occupied by the antifuse array.
  • the anti-fuse structure 20A is adjacent to the anti-fuse structure 20B, and the second anti-fuse unit of the anti-fuse structure 20A is adjacent to The first anti-fuse unit of the anti-fuse structure 20B is adjacent, and the fourth anti-fuse unit of the anti-fuse structure 20A is adjacent to the third anti-fuse unit of the anti-fuse structure 20B; then the anti-fuse structure 20A
  • the second antifuse unit and the first antifuse unit of the antifuse structure 20B share the same gate structure 21 , that is, the gate structure 21 extends from the second extension portion AA2 of the antifuse structure 20A (please refer to 1A) extends above the first extension AA1 (see FIG.
  • the fourth anti-fuse unit of the anti-fuse structure 20A and the third anti-fuse of the anti-fuse structure 20B The wire units share the same gate structure 22, that is, the gate structure 22 extends from above the fourth extension AA4 (please refer to FIG. 1A) of the anti-fuse structure 20A to the third extension of the anti-fuse structure 20B. above part AA3 (see Figure 1A).
  • the anti-fuse structure 20B is adjacent to the anti-fuse structure 20C, and the second anti-fuse unit of the anti-fuse structure 20B
  • the first anti-fuse unit of the anti-fuse structure 20C is adjacent
  • the fourth anti-fuse unit of the anti-fuse structure 20B is adjacent to the third anti-fuse unit of the anti-fuse structure 20C; then the anti-fuse structure 20B
  • the second anti-fuse unit and the first anti-fuse unit of the anti-fuse structure 20C share the same gate structure 23, that is, the gate structure 23 extends from the second extension AA2 (please refer to the anti-fuse structure 20B) 1A) extends above the first extension AA1 (see FIG.
  • the fuse units share the same gate structure 24, that is, the gate structure 24 extends from above the fourth extending portion AA4 (see FIG. 1A) of the anti-fuse structure 20B to the third portion of the anti-fuse structure 20C. Above extension AA3 (see Figure 1A).
  • connection structure since the second antifuse unit of the antifuse structure 20A and the first antifuse unit of the antifuse structure 20B share the same gate structure 21, only one connection structure can be provided to connect them.
  • the gate structure is electrically connected to its corresponding programming line to reduce the number of connection structures.
  • only one connection structure may be provided to electrically connect the gate structure 22 to its corresponding programming line, to electrically connect the gate structure 23 to its corresponding programming line, and to electrically connect the gate structure 24 to its corresponding programming line.
  • the programming wire is electrically connected.
  • the first selection transistors of the antifuse structure arranged along the second direction share the same gate structure, and the second selection transistors share the same gate structure, eliminating the necessity of using two gate structures.
  • the existing gaps reduce the distance between adjacent antifuse structures and further reduce the space occupied by the antifuse array.
  • the first selection transistors of the antifuse structures 20A, 20B, and 20C in the first row share the same gate structure 25 (at least share the gate of the same gate structure 25 ), and the second selection transistors share the same gate structure 25 .
  • Gate structure 26 (at least sharing the gate of the same gate structure 26); the first selection transistors of the antifuse structures 20D, 20E, and 20F located in the second row share the same gate structure 27 (at least sharing the same gate structure 27 gate), the second selection transistors share the same gate structure 28 (at least share the gate of the same gate structure 28).
  • the gates in the gate structures 25, 26, 27, and 28 are all word lines (that is, a part of the word line is used as the gate of the selection transistor), and the word lines are controlled by the peripheral control circuit, so that The first selection transistor and the second selection transistor are turned on or off.
  • FIG. 3 is a schematic structural diagram of a memory provided by some embodiments of the present disclosure.
  • the memory includes an antifuse array as described above.
  • the memory also includes a plurality of programming lines arranged along the first direction (Y direction in the figure) and extending along the second direction (X direction in the figure).
  • a row of anti-fuse structures arranged along the second direction corresponds to four of the programming lines, and the four programming lines are respectively connected to the first anti-fuse unit and the second anti-fuse unit of the anti-fuse structure.
  • the antifuse unit, the third antifuse unit and the fourth antifuse unit are connected.
  • the first anti-fuse unit, the second anti-fuse unit, the third anti-fuse unit and the fourth anti-fuse unit of the same anti-fuse structure are respectively connected to different programming lines to achieve separate control.
  • the programming lines are shown with dotted lines. It can be understood that the programming line and the antifuse structure may be located on different structural layers.
  • a row of antifuse structures arranged along the second direction includes antifuse structures 30A, 30B, 30C, 30D, 30E and 30F.
  • This row of antifuse structures corresponds to the four programming lines, which are programming line 31A, programming line 31B, programming line 31C and programming line 31D.
  • the programming line 30A is connected to the first anti-fuse unit of the anti-fuse structure 30A through the connection structure 32A, and is connected to the second anti-fuse unit of the anti-fuse structure 30B and the first anti-fuse unit of the anti-fuse structure 30C through the connection structure 32B.
  • the antifuse unit is connected to the second antifuse unit of the antifuse structure 30D and the first antifuse unit of the antifuse structure 30E through the connection structure 32C, and is connected to the third antifuse unit of the antifuse structure 30F through the connection structure 32D. Two antifuse units are connected.
  • the programming line 30B is connected to the second antifuse unit of the antifuse structure 30A and the first antifuse unit of the antifuse unit 30B through the connection structure 32E, and is connected to the second antifuse unit of the antifuse structure 30C through the connection structure 32F.
  • the antifuse unit is connected to the first antifuse unit of the antifuse structure 30D, and is connected to the second antifuse unit of the antifuse structure 30E and the first antifuse unit of the antifuse structure 30F through the connection structure 32G. .
  • the programming line 30C is connected to the fourth anti-fuse unit of the anti-fuse structure 30A and the third anti-fuse unit of the anti-fuse unit 30B through the connection structure 32H, and is connected to the fourth anti-fuse unit of the anti-fuse structure 30C through the connection structure 32I.
  • the antifuse unit is connected to the third antifuse unit of the antifuse structure 30D, and is connected to the fourth antifuse unit of the antifuse structure 30E and the third antifuse unit of the antifuse structure 30F through the connection structure 32J. .
  • the programming line 30D is connected to the third anti-fuse unit of the anti-fuse structure 30A through the connection structure 32K, and is connected to the fourth anti-fuse unit of the anti-fuse structure 30B and the third anti-fuse unit of the anti-fuse structure 30C through the connection structure 32L.
  • the antifuse unit is connected to the fourth antifuse unit of the antifuse structure 30D and the third antifuse unit of the antifuse structure 30E through the connection structure 32M, and is connected to the third antifuse unit of the antifuse structure 30F through the connection structure 32N. Quad antifuse unit connections.
  • the memory further includes a plurality of bit lines arranged along the second direction and extending along the first direction, and a column of antifuse structures arranged along the first direction shares the same bit line.
  • the bit line is connected to the antifuse structure through a bit line connection structure BLC.
  • the memory includes a plurality of bit lines BL1, BL2, arranged along the second direction (the X direction in the figure) and extending along the first direction (the Y direction in the figure).
  • the antifuse structures in the same column share the same bit line.
  • the bit line BL1 is electrically connected to the antifuse structures 30A and 30G through a bit line connection structure BLC respectively.
  • bit lines are shown with dotted lines. It can be understood that the bit line and the antifuse structure may be located on different structural layers, and the bit line and the programming line may also be located on different structural layers. In the memory provided by the embodiments of the present application, when the number of anti-fuse units is the same, the anti-fuse array only needs to occupy about half of the area, which meets the need for miniaturization.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

本申请实施例一种反熔丝结构，其包括：第一单元，包括第一选择晶体管、第一反熔丝单元及第二反熔丝单元；第二单元，包括第二选择晶体管、第三反熔丝单元及第四反熔丝单元；其中，所述第一单元与所述第二单元共用有源区，且所述有源区的第一侧延伸有彼此独立的第一延伸部及第二延伸部，所述有源区的第二侧延伸有彼此独立的第三延伸部及第四延伸部，所述第一侧与所述第二侧相对设置，所述第一反熔丝单元设置在所述第一延伸部，所述第二反熔丝单元设置在所述第二延伸部，所述第三反熔丝单元设置在所述第三延伸部，所述第四反熔丝单元设置在所述第四延伸部。所述反熔丝结构能够提高反熔丝单元的分布密度，满足了小型化的需求。

Description

反熔丝结构、反熔丝阵列及存储器
相关申请引用说明
本申请要求于2022年05月25日递交的中国专利申请号202210577084.X、申请名为“反熔丝结构、反熔丝阵列及存储器”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及集成电路领域，尤其涉及一种反熔丝结构、反熔丝阵列及存储器。
背景技术
在半导体工业中，熔丝元件由于具有多种用途而被广泛使用在集成电路中。例如，在集成电路中设计多个具有相同功能的电路模块作为备份，当发现其中一个电路模块失效时，通过熔丝元件将电路模块和集成电路中的其它功能电路烧断，而使用具有相同功能的另一个电路模块取代失效的电路模块。
随着半导体技术的不断发展，反熔丝(Anti-fuse)技术已经吸引了很多发明者和制造商的关注。反熔丝元件通过从绝缘状态变为导电状态来存储信息。通过施加高压导致的介质击穿来执行向反熔丝元件写入信息。反熔丝存储单元在编程前呈电容特性，无导通沟道形成；当发生编程击穿后，在单元两端会形成导通沟道，可以通过电流，导通电流的大小与编程效果相关。
例如，反熔丝结构中通常包含反熔丝单元(AF cell)和选择晶体管(XADD)。写入时，对反熔丝单元施加高压(约5.5～6V)，在对应的位线(BL)端置0V，并开启选择晶体管，以此使得反熔丝单元的薄栅氧化物在高压下被击穿而电阻显著下降，达到写入的目的。
随着芯片尺寸的缩小，反熔丝阵列的面积也必须随之减小为存储阵列节约出宝贵的空间，但是，受限于反熔丝结构的设计规则及可制造性的要求，在保证反熔丝单元数量不变的情况下，反熔丝阵列的面积无法缩小，无法满足芯片小型化的需求。
发明内容
本申请提供一种反熔丝结构、反熔丝阵列及存储器，其能够在保证反熔丝 单元数量不变的情况下，缩小反熔丝阵列的面积。
本申请提供了一种反熔丝结构，其包括：第一单元，包括第一选择晶体管、第一反熔丝单元及第二反熔丝单元第二单元，包括第二选择晶体管、第三反熔丝单元及第四反熔丝单元；其中，所述第一单元与所述第二单元共用有源区，且所述有源区的第一侧延伸有彼此独立的第一延伸部及第二延伸部，所述有源区的第二侧延伸有彼此独立的第三延伸部及第四延伸部，所述第一侧与所述第二侧相对设置，所述第一反熔丝单元设置在所述第一延伸部，所述第二反熔丝单元设置在所述第二延伸部，所述第三反熔丝单元设置在所述第三延伸部，所述第四反熔丝单元设置在所述第四延伸部。
在一实施例中，还包括：第一栅极结构，设置在所述有源区表面；第二栅极结构，设置在所述有源区表面，且与所述第一栅极结构间隔设置；第三栅极结构，设置在所述第一延伸部表面；第四栅极结构，设置在所述第二延伸部表面；第五栅极结构，设置在所述第三延伸部表面；第六栅极结构，设置在所述第四延伸部表面；第一掺杂区，设置在所述第一栅极结构与所述第二栅极结构之间的有源区内；第二掺杂区，设置在所述第一栅极结构远离所述第二栅极结构一侧的有源区内及所述第一延伸部与第二延伸部内；第三掺杂区，设置在所述第二栅极结构远离所述第一栅极结构的一侧的有源区内及第三延伸部与第四延伸部内；其中，所述第一栅极结构与所述第一掺杂区、第二掺杂区构成所述第一选择晶体管，所述第三栅极结构与所述第一延伸部内的第二掺杂区构成所述第一反熔丝单元，所述第四栅极结构与所述第二延伸部内的第二掺杂区构成所述第二反熔丝单元，所述第二栅极结构与所述第一掺杂区、第三掺杂区构成第二选择晶体管，所述第五栅极结构与所述第三延伸部内的第三掺杂区构成第三反熔丝单元，所述第六栅极结构与所述第四延伸部内的第三掺杂区构成第四反熔丝单元。
在一实施例中，所述第一侧及所述第二侧沿第一方向相对设置，且所述第一栅极结构及所述第二栅极结构沿所述第一方向排布。
在一实施例中，所述第三栅极结构及所述第四栅极结构沿第二方向排布，所述第二方向与所述第一方向垂直或具有锐角夹角。
在一实施例中，所述第五栅极结构及所述第六栅极结构沿所述第二方向排 布，所述第二方向与所述第一方向垂直或具有锐角夹角。
在一实施例中，还包括：位线连接结构，与位于所述第一栅极结构及所述第二栅极结构之间的第一掺杂区连接，且所述第一掺杂区能够通过所述位线连接结构与位线连接。
在一实施例中，还包括：第一连接结构，与所述第三栅极结构连接，且所述第三栅极结构能够通过所述第一连接结构与一编程线连接，所述第一连接结构设置在所述第一延伸部远离所述第第二延伸部的一侧；第二连接结构，与所述第四栅极结构连接，且所述第四栅极结构能够通过所述第二连接结构与另一编程线连接，所述第四连接结构设置在所述第二延伸部区远离所述第第一延伸部的一侧。
在一实施例中，所述第三栅极结构包括与所述第一延伸部对应设置的第三主区域及向远离所述第第二延伸部的方向突出的第三次区域，所述第一连接结构与所述第三次区域连接，所述第四栅极结构包括与所述第二延伸部对应设置的第四主区域及向远离所述第一延伸部的方向突出的第四次区域，所述第二连接结构与所述第四次区域连接。
在一实施例中，还包括：第三连接结构，与所述第五栅极结构连接，且所述第五栅极结构能够通过所述第三连接结构与一编程线连接，所述第三连接结构设置在所述第三延伸部远离所述第四延伸部的一侧；第四连接结构，与所述第六栅极结构连接，且所述第六栅极结构能够通过所述第四连接结构与另一编程线连接，所述第四连接结构设置在所述第四延伸部远离所述第三延伸部的一侧。
在一实施例中，所述第五栅极结构包括与所述第三延伸部对应设置的第五主区域及向远离所述第四延伸部的方向突出的第五次区域，所述第三连接结构与所述第五次区域连接，所述第六栅极结构包括与所述第四延伸部对应设置的第六主区域及向远离所述第三延伸部的方向突出的第六次区域，所述第四连接结构与所述第六次区域连接。
在一实施例中，所述第一选择晶体管与所述第二选择晶体管以第一轴为对称轴对称设置，所述第一反熔丝单元与所述第三反熔丝单元以所述第一轴为对称轴对称设置，所述第二反熔丝单元与所述第三反熔丝单元以所述第一轴为对 称轴对称设置。
基于本申请实施例，还提供一种反熔丝阵列，其包括多个如上所述的反熔丝结构，多个所述反熔丝结构沿第一方向及第二方向阵列排布，所述第一方向与所述第二方向垂直或具有锐角夹角。
在一实施例中，在所述第二方向上，相邻反熔丝结构的相邻反熔丝单元共用同一栅极结构。
在一实施例中，沿所述第二方向排布的反熔丝结构的第一选择晶体管共用同一栅极结构，第二选择晶体管共用同一栅极结构。
基于本申请实施例，还提供一种存储器，其包括如上所述的反熔丝阵列。
在一实施例中，还包括多条沿所述第一方向排布且沿所述第二方向延伸的编程线，沿所述第二方向排布的一行反熔丝结构对应四条所述编程线，四条所述编程线分别与所述反熔丝结构的所述第一反熔丝单元、所述第二反熔丝单元、所述第三反熔丝单元及所述第四反熔丝单元连接。
在一实施例中，还包括多条沿第二方向排布且沿第一方向延伸的位线，沿所述第一方向排布的一列反熔丝结构共用同一所述位线。
在本申请实施例提供的反熔丝结构反熔丝结构中，第一单元与第二单元共用同一有源区，则可消除第一单元与第二单元采用不同有源区而带来的有源区之间的间隔空隙，缩小了反熔丝结构的面积，同时，每一单元包含两个反熔丝单元，且分别设置在独立的延伸部，则可在相同面积下，增加一倍数量的反熔丝单元，也就是说，在反熔丝单元的设计数量相同时，本申请反熔丝结构仅需占用约一半的面积，满足了小型化的需求。
附图说明
图1A是本申请一些实施例提供的反熔丝结构的示意图；
图1B是本申请一些实施例提供的有源区的示意图；
图2是本申请一些实施例提供的反熔丝阵列的示意图；
图3是本申请一些实施例提供的存储器的示意图。
具体实施方式
下面结合附图对本申请提供的反熔丝结构、反熔丝阵列及存储器的具体实施方式做详细说明。
图1A是本申请一些实施例提供的反熔丝结构的示意图，1B是本申请一些实施例提供的有源区的示意图，请参阅图1A及图1B，所述反熔丝结构10包括第一单元101及第二单元102。
所述第一单元101包括第一选择晶体管、第一反熔丝单元及第二反熔丝单元，所述第二单元102包括第二选择晶体管、第三反熔丝单元及第四反熔丝单元。
其中，所述第一单元101与所述第二单元102共用有源区AA，且所述有源区AA的第一侧延伸有彼此独立的第一延伸部AA1及第二延伸部AA2，所述有源区AA的第二侧延伸有彼此独立的第三延伸部AA3及第四延伸部AA4，所述第一侧与所述第二侧相对设置，所述第一反熔丝单元设置在所述第一延伸部AA1，所述第二反熔丝单元设置在所述第二延伸部AA2，所述第三反熔丝单元设置在所述第三延伸部AA3，所述第四反熔丝单元设置在所述第四延伸部AA4。
本申请实施例提供的反熔丝结构中，第一单元101的与第二单元102共用同一有源区AA，则可消除第一单元101与第二单元102采用不同有源区AA而带来的有源区AA之间的间隔空隙，缩小了反熔丝结构的面积，同时，每一单元包含两个反熔丝单元，且分别设置在独立的延伸部，则可在相同面积下，增加一倍数量的反熔丝单元，也就是说，在反熔丝单元的设计数量相同时，本申请反熔丝结构仅需占用约一半的面积，满足了小型化的需求。
请继续参阅图1A及图1B，下面具体描述所述第一选择晶体管、第一反熔丝单元、第二反熔丝单元、第二选择晶体管、第三反熔丝单元及第四反熔丝单元的结构。
所述有源区AA的第一侧延伸有彼此独立的第一延伸部AA1及第二延伸部AA2，所述有源区AA的第二侧延伸有彼此独立的第三延伸部AA3及第四延伸部AA4。所述第一侧及所述第二侧沿第一方向(如图中Y方向)相对设置，例如，在本实施例中，所述第一侧为所述有源区AA的上端，所述第二侧为所述有源区AA的下端。
所述反熔丝结构包括第一栅极结构G1。所述第一栅极结构G1设置在所述有源区AA表面。在一些实施例中，所述第一栅极结构G1沿第二方向延伸。 在本实施中，所述第二方向为水平方向X方向。
在一些实施例中，所述反熔丝结构还包括第一字线连接结构T1，所述第一栅极结构G1通过所述第一字线连接结构T1与外围控制电路电连接，即所述第一字线连接结构T1作为导电插塞实现所述第一栅极结构G1与外围控制电路的电连接。
所述反熔丝结构还包括第二栅极结构G2。所述第二栅极结构G2设置在所述有源区AA表面，且与所述第一栅极结构G1间隔设置。在一些实施例中，所述第一栅极结构G1与所述第二栅极结构G2连接至不同的字线，以实现第一单元101与第二单元102的单独控制。
在本实施例中，所述第一栅极结构G1和所述第二栅极结构G2均沿第二方向延伸，且所述第二栅极结构G2与所述第一栅极结构G1沿第一方向间隔设置，所述第一方向与所述第二方向垂直或者具有锐角夹角。具体地说，在本实施例中，所述第一方向与所述第二方向垂直，例如，所述第二方向为水平方向X方向，所述第一方向为竖直方向Y方向。在另一些实施例中，所述第一方向与所述第二方向具有锐角夹角，例如，所述第二方向为水平方向X方向，所述第一方向为与水平方向呈锐角夹角的方向。
在一些实施例中，所述反熔丝结构还包括第二字线连接结构T2，所述第二栅极结构G2通过所述第二字线连接结构T2与外围控制的电路电连接，即所述第二字线连接结构T2作为导电插塞实现所述第二栅极结构G2与外围控制电路的电连接。
所述反熔丝结构还包括第三栅极结构G3，所述第三栅极结构G3设置在所述第一延伸部AA1表面，并能够连接至编程线。在一些实施例中，所述第三栅极结构G3沿第二方向延伸，即所述第三栅极结构G3与所述第一栅极结构G1的延伸方向一致。在所述第一方向上，所述第三栅极结构G3与所述第一栅极结构G1间隔设置，并且所述第三栅极结构G3设置在所述第一栅极结构G1远离所述第二栅极结构G2的一侧。所述第三栅极结构G3仅设置在所述第一延伸部AA1表面，而并未设置在第二延伸部AA2的表面。
在本实施例中，所述反熔丝结构还包括第一连接结构T3。所述第一连接结构T3与所述第三栅极结构G3连接，且所述第三栅极结构G3能够通过所述 第一连接结构T3与位于其上层的编程线连接。即所述第一连接结构T3作为导电插塞实现所述第三栅极结构G3与其上层编程线的电连接。
在本实施例中，所述第一连接结构T3设置在所述第一延伸部AA1远离所述第二延伸部AA2的一侧。具体地说，所述第三栅极结构G3包括与所述第一延伸部AA1对应设置的第三主区域G31及向远离所述第二延伸部AA2的方向突出的第三次区域G32，即所述第三主区域G31与所述第一延伸部AA1正对设置，所述第三次区域G32与所述第一延伸部AA1交错设置，所述第一连接结构T3与远离所述第二延伸部AA2的所述第三次区域G32连接。
所述反熔丝结构还包括第四栅极结构G4。所述第四栅极结构G4设置在所述第二延伸部AA2表面，并能够连接至编程线。在一些实施例中，所述第四栅极结构G4沿第二方向延伸，即所述第四栅极结构G4与所述第一栅极结构G1的延伸方向一致。在所述第一方向上，所述第四栅极结构G4与所述第一栅极结构G1间隔设置，并且所述第四栅极结构G4设置在所述第一栅极结构G1远离所述第二栅极结构G2的一侧；在第二方向上，所述第四栅极结构G4与所述第三栅极结构G3间隔设置，所述第四栅极结构G4仅设置在所述第二延伸部AA2表面，而并未设置在第一延伸部AA1的表面。可以理解的是，在一些实施例中，所述第三栅极结构G3与所述第四栅极结构G4沿第二方向的长度均小于所述第一栅极结构G1沿第二方向的长度。
在本实施例中，所述反熔丝结构还包括第二连接结构T4。所述第二连接结构T4与所述第四栅极结构G4连接，且所述第四栅极结构G4能够通过所述第二连接结构T4与位于其上层的编程线连接。即所述第二连接结构T4作为导电插塞实现所述第四栅极结构G4与其上层的编程线的电连接。在一些实施例中，所述第三栅极结构G3与所述第四栅极结构G4连接至不同编程线，以实现第一反熔丝单元与第二反熔丝单元的单独控制。
在本实施例中，所述第二连接结构T4设置在所述第二延伸部AA2远离所述第一延伸部AA1的一侧。具体地说，所述第四栅极结构G4包括与所述第二延伸部AA2对应设置的第四主区域G41及向远离所述第一延伸部AA1的方向突出的第四次区域G42，即所述第四主区域G41与所述第二延伸部AA2正对设置，所述第四次区域G42与所述第二延伸部AA2交错设置，所述第二连接 结构T4与远离所述第一延伸部AA1的所述第四次区域G42连接。
所述反熔丝结构还包括第五栅极结构G5。所述第五栅极结构G5设置在所述第三延伸部AA3表面，并能够连接至编程线。在一些实施例中，所述第五栅极结构G5沿第二方向延伸，即所述第五栅极结构G5与所述第二栅极结构G2的延伸方向一致。在所述第一方向上，所述第五栅极结构G5与所述第二栅极结构G2间隔设置，并且所述第五栅极结构G5设置在所述第二栅极结构G2远离所述第一栅极结构G1的一侧。所述第五栅极结构G5仅设置在所述第三延伸部AA3表面，而并未设置在第四延伸部AA4的表面。
在本实施例中，所述反熔丝结构还包括第三连接结构T5。所述第三连接结构T5与所述第五栅极结构G5连接，且所述第五栅极结构G5能够通过所述第三连接结构T5与位于其上层的编程线连接。即所述第三连接结构T5作为导电插塞实现所述第五栅极结构G5与其上层编程线的电连接。
在本实施例中，所述第三连接结构T5设置在所述第三延伸部AA3远离所述第四延伸部AA4的一侧。具体地说，所述第五栅极结构G5包括与所述第三延伸部AA3对应设置的第五主区域G51及向远离所述第四延伸部AA4的方向突出的第五次区域G52。即所述第五主区域G51与所述第三延伸部AA3正对设置，所述第五次区域G52与所述第三延伸部AA3交错设置，所述第三连接结构T5与远离所述第三延伸部AA3的所述第五次区域G52连接。
所述反熔丝结构还包括第六栅极结构G6。所述第六栅极结构G6设置在所述第四延伸部AA4表面，并能够连接至编程线。在一些实施例中，所述第六栅极结构G6沿第二方向延伸，即所述第六栅极结构G6与所述第二栅极结构G2的延伸方向一致。在所述第一方向上，所述第六栅极结构G6与所述第二栅极结构G2间隔设置，并且所述第六栅极结构G6设置在所述第二栅极结构G2远离所述第一栅极结构G1的一侧；在第二方向上，所述第六栅极结构G6与所述第五栅极结构G5间隔设置，所述第六栅极结构G6仅设置在所述第四延伸部AA4表面，而并未设置在第三延伸部AA3的表面。可以理解的是，在一些实施例中，所述第五栅极结构G5与所述第六栅极结构G6沿第二方向的长度均小于所述第二栅极结构G2沿第二方向的长度。
在本实施例中，所述反熔丝结构还包括第四连接结构T6。所述第四连接 结构T6与所述第六栅极结构G6连接，且所述第六栅极结构G6能够通过所述第四连接结构T6与位于其上层的另一编程线连接。即所述第四连接结构T6作为导电插塞实现所述第六栅极结构G6与其上层的编程线的电连接。在一些实施例中，所述第五栅极结构G5与所述第六栅极结构G6连接至不同编程线，以实现第三反熔丝单元与第四反熔丝单元的单独控制。
在本实施例中，所述第四连接结构T6设置在所述第四延伸部AA4远离所述第三延伸部AA3的一侧。具体地说，所述第六栅极结构G6包括与所述第四延伸部AA4对应设置的第六主区域G61及向远离所述第三延伸部AA3的方向突出的第六次区域G62，即所述第六主区域G61与所述第四延伸部AA4正对设置，所述第六次区域G62与所述第四延伸部AA4交错设置，所述第四连接结构T6与所述第六次区域G62连接。
所述反熔丝结构还包括第一掺杂区D1。所述第一掺杂区D1设置在所述第一栅极结构G1与所述第二栅极结构G2之间的有源区AA内。在本实施例中，所述有源区AA为P型阱区，则所述第一掺杂区D1为N型掺杂区。而在其他实施例中，若所述有源区AA为N型阱区，则所述第一掺杂区D1为P型掺杂区。
所述反熔丝结构还包括位线连接结构BLC。所述位线连接结构BLC与位于所述第一栅极结构G1及所述第二栅极结构之间的第一掺杂区D1连接，且所述第一掺杂区D1能够通过所述位线连接结构BLC与位线连接。即所述位线连接结构BLC作为所述第一掺杂区D1与位线连接的导电插塞，实现所述位线与所述第一掺杂区D1的电连接。
所述反熔丝结构还包括第二掺杂区D2。所述第二掺杂区D2设置在所述第一栅极结构G1远离所述第二栅极结构G2一侧的有源区AA内及所述第一延伸部AA1与所述第二延伸部AA2内。在本实施例中，所述第二掺杂区D2与所述第一掺杂区D1的掺杂类型相同，且与所述有源区AA的掺杂类型相反，若所述有源区AA为P型阱区，则所述第二掺杂区D2为N型掺杂区。而在其他实施例中，若所述有源区AA为N型阱区，则所述第二掺杂区D2为P型掺杂区。
所述反熔丝结构还包括第三掺杂区D3。所述第三掺杂区D3设置在所述第 二栅极结构G2远离所述第一栅极结构G1的一侧的有源区AA内及第三延伸部AA3与第四延伸部AA4内。在本实施例中，所述第三掺杂区D3与所述第一掺杂区D1的掺杂类型相同，且与所述有源区AA的掺杂类型相反，若所述有源区AA为P型阱区，则所述第三掺杂区D3为N型掺杂区。而在其他实施例中，若所述有源区AA为N型阱区，则所述第三掺杂区D3为P型掺杂区。
其中，所述第一栅极结构G1与其下方的有源区AA及所述第一掺杂区D1、所述第二掺杂区D2构成所述第一选择晶体管。所述第二掺杂区D2位于所述第一延伸部AA1内，则所述第三栅极结构G3与位于其下方的第二掺杂区D2构成第一反熔丝单元。所述第二掺杂区D2还位于所述第二延伸部AA2内，则所述第四栅极结构G4与位于其下方的第二掺杂区D2构成第二反熔丝单元。
在本实施例中，所述第三栅极结构G3的第三主区域G31作为有效区域与所述第二掺杂区D2成所述第一反熔丝单元，所述第四栅极结构G4的第四主区域G41作为有效区域与所述第二掺杂区D2成所述第二反熔丝单元。
所述第二栅极结构G2与其下方的有源区AA及所述第一掺杂区D1、第三掺杂区D3构成第二选择晶体管。所述第三掺杂区D3位于所述第三延伸部AA3内，则所述第五栅极结构G5与位于其下方的第三掺杂区D3构成第三反熔丝单元。所述第三掺杂区D3还位于所述第四延伸部AA4内，则所述第六栅极结构G6与位于其下方的第三掺杂区D3构成第四反熔丝单元。
在本实施例中，所述第五栅极结构G5的第五主区域G51作为有效区域与所述第三掺杂区D3成所述第三反熔丝单元，所述第六栅极结构G6的第六主区域G61作为有效区域与所述第三掺杂区D3成所述第三反熔丝单元。
在本实施例中，所述第一选择晶体管与所述第二选择晶体管以第一轴O为对称轴对称设置，所述第一反熔丝单元与所述第三反熔丝单元以所述第一轴O为对称轴对称设置，所述第二反熔丝单元与所述第四反熔丝单元以所述第一轴O为对称轴对称设置，有利于简化反熔丝结构的版图设计，提高利用率。
可以理解的是，在本申请实施例中，所述第一栅极结构G1、第二栅极结构G2、第三栅极结构G3、第四栅极结构G4、第五栅极结构G5及第六栅极结构G6均包括栅极(附图中未标示)及位于栅极与有源区AA之间的栅介质层(附图中未标示)，以实现栅极结构的基本功能。其中，所述栅极的材料可为 多晶硅(poly)，所述栅介质层的材料可为氧化硅、高K介质材料等。
本申请一些实施例提供的反熔丝结构中，第一单元101与第二单元102共用同一有源区AA，则可消除第一单元101与第二单元102采用不同有源区AA而带来的有源区AA之间的间隔空隙，缩小了反熔丝结构的面积，同时，每一单元包含两个反熔丝单元，且分别设置在独立的延伸部，则可在相同面积下，增加一倍数量的反熔丝单元，也就是说，在反熔丝单元的设计数量相同时，本申请反熔丝结构仅需占用约一半的面积，满足了小型化的需求。
本申请一些实施例还提供一种反熔丝阵列，请参阅图2，其为反熔丝阵列的示意图，所述反熔丝阵列包括多个如上所述的反熔丝结构。多个所述反熔丝结构沿第一方向及第二方向阵列排布，所述第一方向与所述第二方向垂直或具有锐角夹角。在本实施例中，所述第一方向为竖直方向Y方向，所述第二方向为水平方向X方向。在图2中示意性地绘示六个反熔丝结构，分别为反熔丝结构20A、20B、20C、20D、20E及20F，其中，三个反熔丝结构为一组沿第二方向排布，形成一行，不同行的反熔丝单元沿第一方向排布，形成一列。例如，反熔丝结构20A、20B及20C沿第二方向排布，形成第一行；反熔丝结构20D、20E及20F沿第二方向排布，形成第二行；反熔丝结构20A及20D沿第一方向排布，形成第一列；反熔丝结构20B及20E沿第一方向排布，形成第二列；反熔丝结构20C及20F沿第一方向排布，形成第三列。
本申请实施例提供的反熔丝阵列中，反熔丝结构的第一单元101(请参阅图1A)与第二单元102(请参阅图1A)共用同一有源区AA(请参阅图1A及图1B)，则可消除第一单元101与第二单元102采用不同有源区AA而带来的有源区AA之间的间隔空隙，缩小了反熔丝结构的面积，同时，每一单元包含两个反熔丝单元，且分别设置在独立的延伸部，则可在相同面积下，增加一倍数量的反熔丝单元，也就是说，在反熔丝单元的设计数量相同时，本申请反熔丝阵列仅需占用约一半的面积，满足了小型化的需求。
在本实施例中，在所述第二方向(即水平方向X方向)上，相邻反熔丝结构的相邻反熔丝单元共用同一栅极结构(至少共用同一栅极结构的栅极)，去除了采用两个栅极结构而必须存在的空隙，缩小了相邻反熔丝结构之间的距离，进一步减小了反熔丝阵列占用空间。
例如，请参阅图2，在所述第二方向(即水平方向X方向)上，反熔丝结构20A与反熔丝结构20B相邻，且反熔丝结构20A的第二反熔丝单元与反熔丝结构20B的第一反熔丝单元相邻，反熔丝结构20A的第四反熔丝单元与反熔丝结构20B的第三反熔丝单元相邻；则反熔丝结构20A的第二反熔丝单元与反熔丝结构20B的第一反熔丝单元共用同一栅极结构21，即所述栅极结构21自所述反熔丝结构20A的第二延伸部AA2(请参阅图1A)上方延伸至所述反熔丝结构20B的第一延伸部AA1(请参阅图1A)上方；反熔丝结构20A的第四反熔丝单元与反熔丝结构20B的第三反熔丝单元共用同一栅极结构22，即所述栅极结构22自所述反熔丝结构20A的第四延伸部AA4(请参阅图1A)上方延伸至所述反熔丝结构20B的第三延伸部AA3(请参阅图1A)上方。
再例如，请参阅图2，在所述第二方向(即水平方向X方向)上，反熔丝结构20B与反熔丝结构20C相邻，且反熔丝结构20B的第二反熔丝单元与反熔丝结构20C的第一反熔丝单元相邻，反熔丝结构20B的第四反熔丝单元与反熔丝结构20C的第三反熔丝单元相邻；则反熔丝结构20B的第二反熔丝单元与反熔丝结构20C的第一反熔丝单元共用同一栅极结构23，即所述栅极结构23自所述反熔丝结构20B的第二延伸部AA2(请参阅图1A)上方延伸至所述反熔丝结构20C的第一延伸部AA1(请参阅图1A)上方；反熔丝结构20B的第四反熔丝单元与反熔丝结构20C的第三反熔丝单元共用同一栅极结构24，即所述栅极结构24自所述反熔丝结构20B的第四延伸部AA4(请参阅图1A)上方延伸至所述反熔丝结构20C的第三延伸部AA3(请参阅图1A)上方。
在本实施例中，由于所述反熔丝结构20A的第二反熔丝单元与反熔丝结构20B的第一反熔丝单元共用同一栅极结构21，则可仅设置一个连接结构将所述栅极结构与其对应的编程线电连接，以减少连接结构的数量。同样地，也可仅设置一个连接结构将所述栅极结构22与其对应的编程线电连接，将所述栅极结构与23其对应的编程线电连接及将所述栅极结构24与其对应的编程线电连接。
在本实施例中，沿所述第二方向排布的反熔丝结构的第一选择晶体管共用同一栅极结构，第二选择晶体管共用同一栅极结构，去除了采用两个栅极结构而必须存在的空隙，缩小了相邻反熔丝结构之间的距离，进一步减小了反熔丝 阵列占用的空间。
例如，请参阅图2，第一行的反熔丝结构20A、20B、20C的第一选择晶体管共用同一栅极结构25(至少共用同一栅极结构25的栅极)，第二选择晶体管共用同一栅极结构26(至少共用同一栅极结构26的栅极)；位于第二行的反熔丝结构20D、20E、20F的第一选择晶体管共用同一栅极结构27(至少共用同一栅极结构27的栅极)，第二选择晶体管共用同一栅极结构28(至少共用同一栅极结构28的栅极)。可以理解的是，所述栅极结构25、26、27、28中的栅极均为字线(即将字线的一部分作为选择晶体管的栅极)，字线受到外围控制电路的控制，以使所述第一选择晶体管及第二选择晶体管导通或关断。
在本实施例中，由于沿所述第二方向排布的反熔丝结构的第一选择晶体管共用同一栅极结构，则可仅设置一个字线连接结构将所述栅极结构与外围控制电路对应连接；同样地，由于沿所述第二方向排布的反熔丝结构的第二选择晶体管共用同一栅极结构，也可仅设置一个字线连接结构将所述栅极结构与外围控制电路对应连接。
本申请实施例还提供一种存储器，请参阅图3，其为本公开一些实施例提供的存储器的结构示意图。所述存储器包括如上所述的反熔丝阵列。
所述存储器还包括多条沿所述第一方向(如图中Y方向)排布且沿所述第二方向(如图中X方向)延伸的编程线。其中，沿所述第二方向排布的一行反熔丝结构对应四条所述编程线，四条所述编程线分别与所述反熔丝结构的所述第一反熔丝单元、所述第二反熔丝单元、所述第三反熔丝单元及所述第四反熔丝单元连接。需要说明的是，同一反熔丝结构的第一反熔丝单元、第二反熔丝单元、第三反熔丝单元及第四反熔丝单元分别连接至不同的编程线，以实现分别控制。在图3中为了清楚显示本申请实施例提供的存储器的结构，所述编程线采用虚线绘示。可以理解的是，所述编程线与所述反熔丝结构可位于不同的结构层。
例如，沿所述第二方向(如图中X方向)排布的一行反熔丝结构包括反熔丝结构30A、30B、30C、30D、30E及30F。该行反熔丝结构对应四条所述编程线，分别为编程线31A、编程线31B、编程线31C及编程线31D。
所述编程线30A通过连接结构32A与反熔丝结构30A的第一反熔丝单元 连接，通过连接结构32B与反熔丝结构30B的第二反熔丝单元及反熔丝结构30C的第一反熔丝单元连接，通过连接结构32C与反熔丝结构30D的第二反熔丝单元及反熔丝结构30E的第一反熔丝单元连接，通过连接结构32D与反熔丝结构30F的第二反熔丝单元连接。
所述编程线30B通过连接结构32E与反熔丝结构30A的第二反熔丝单元及反熔丝单元30B的第一反熔丝单元连接，通过连接结构32F与反熔丝结构30C的第二反熔丝单元及反熔丝结构30D的第一反熔丝单元连接，通过连接结构32G与反熔丝结构30E的第二反熔丝单元及反熔丝结构30F的第一反熔丝单元连接。
所述编程线30C通过连接结构32H与反熔丝结构30A的第四反熔丝单元及反熔丝单元30B的第三反熔丝单元连接，通过连接结构32I与反熔丝结构30C的第四反熔丝单元及反熔丝结构30D的第三反熔丝单元连接，通过连接结构32J与反熔丝结构30E的第四反熔丝单元及反熔丝结构30F的第三反熔丝单元连接。
所述编程线30D通过连接结构32K与反熔丝结构30A的第三反熔丝单元连接，通过连接结构32L与反熔丝结构30B的第四反熔丝单元及反熔丝结构30C的第三反熔丝单元连接，通过连接结构32M与反熔丝结构30D的第四反熔丝单元及反熔丝结构30E的第三反熔丝单元连接，通过连接结构32N与反熔丝结构30F的第四反熔丝单元连接。
在本实施例中，所述存储器还包括多条沿第二方向排布且沿第一方向延伸的位线，沿所述第一方向排布的一列反熔丝结构共用同一所述位线。所述位线通过位线连接结构BLC与所述反熔丝结构连接。
具体地说，如图3所示，所述存储器包括多条沿第二方向(如图中的X方向)排布且沿第一方向(如图中Y方向)延伸的位线BL1、BL2、BL3、BL4、BL5及BL6。同一列的反熔丝结构共用同一条位线，例如，沿第一方向排布的反熔丝结构30A及30G构成一列，则反熔丝结构30A及30G共用同一位线BL1。所述位线BL1分别通过位线连接结构BLC与所述反熔丝结构30A及30G电连接。在图3中为了清楚显示本申请实施例提供的存储器的结构，所述位线采用虚线绘示。可以理解的是，所述位线与所述反熔丝结构可位于不同的结构 层，所述位线与所述编程线也可位于不同的结构层。本申请实施例提供的存储器在反熔丝单元的设计数量相同时，反熔丝阵列仅需占用约一半的面积，满足了小型化的需求。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (17)

  1. 一种反熔丝结构，包括：
    第一单元，包括第一选择晶体管、第一反熔丝单元及第二反熔丝单元；
    第二单元，包括第二选择晶体管、第三反熔丝单元及第四反熔丝单元；
    其中，所述第一单元与所述第二单元共用有源区，且所述有源区的第一侧延伸有彼此独立的第一延伸部及第二延伸部，所述有源区的第二侧延伸有彼此独立的第三延伸部及第四延伸部，所述第一侧与所述第二侧相对设置，所述第一反熔丝单元设置在所述第一延伸部，所述第二反熔丝单元设置在所述第二延伸部，所述第三反熔丝单元设置在所述第三延伸部，所述第四反熔丝单元设置在所述第四延伸部。
  2. 根据权利要求1所述的反熔丝结构，进一步，还包括：
    第一栅极结构，设置在所述有源区表面；
    第二栅极结构，设置在所述有源区表面，且与所述第一栅极结构间隔设置；
    第三栅极结构，设置在所述第一延伸部表面；
    第四栅极结构，设置在所述第二延伸部表面；
    第五栅极结构，设置在所述第三延伸部表面；
    第六栅极结构，设置在所述第四延伸部表面；
    第一掺杂区，设置在所述第一栅极结构与所述第二栅极结构之间的有源区内；
    第二掺杂区，设置在所述第一栅极结构远离所述第二栅极结构一侧的有源区内及所述第一延伸部与第二延伸部内；
    第三掺杂区，设置在所述第二栅极结构远离所述第一栅极结构的一侧的有源区内及第三延伸部与第四延伸部内；其中，
    所述第一栅极结构与所述第一掺杂区、第二掺杂区构成所述第一选择晶体管，所述第三栅极结构与所述第一延伸部内的第二掺杂区构成所述第一反熔丝单元，所述第四栅极结构与所述第二延伸部内的第二掺杂区构成所述第二反熔丝单元，所述第二栅极结构与所述第一掺杂区、第三掺杂区构成第二选择晶体管，所述第五栅极结构与所述第三延伸部内的第三掺杂区构成第三反熔丝单元，所述第六栅极结构与所述第四延伸部内的第三掺杂区构成第四反熔丝单元。
  3. 根据权利要求2所述的反熔丝结构，其中，所述第一侧及所述第二侧沿第一方向相对设置，且所述第一栅极结构及所述第二栅极结构沿所述第一方向排布。
  4. 根据权利要求3所述的反熔丝结构，其中，所述第三栅极结构及所述第四栅极结构沿第二方向排布，所述第二方向与所述第一方向垂直或具有锐角夹角。
  5. 根据权利要求3所述的反熔丝结构，其中，所述第五栅极结构及所述第六栅极结构沿所述第二方向排布，所述第二方向与所述第一方向垂直或具有锐角夹角。
  6. 根据权利要求2所述的反熔丝结构，进一步，还包括：
    位线连接结构，与位于所述第一栅极结构及所述第二栅极结构之间的第一掺杂区连接，且所述第一掺杂区能够通过所述位线连接结构与位线连接。
  7. 根据权利要求2所述的反熔丝结构，其特征在于，还包括：
    第一连接结构，与所述第三栅极结构连接，且所述第三栅极结构能够通过所述第一连接结构与一编程线连接，所述第一连接结构设置在所述第一延伸部远离所述第第二延伸部的一侧；
    第二连接结构，与所述第四栅极结构连接，且所述第四栅极结构能够通过所述第二连接结构与另一编程线连接，所述第四连接结构设置在所述第二延伸部区远离所述第第一延伸部的一侧。
  8. 根据权利要求7所述的反熔丝结构，其中，所述第三栅极结构包括与所述第一延伸部对应设置的第三主区域及向远离所述第第二延伸部的方向突出的第三次区域，所述第一连接结构与所述第三次区域连接，所述第四栅极结构包括与所述第二延伸部对应设置的第四主区域及向远离所述第一延伸部的方向突出的第四次区域，所述第二连接结构与所述第四次区域连接。
  9. 根据权利要求2所述的反熔丝结构，进一步，还包括：
    第三连接结构，与所述第五栅极结构连接，且所述第五栅极结构能够通过所述第三连接结构与一编程线连接，所述第三连接结构设置在所述第三延伸部远离所述第四延伸部的一侧；
    第四连接结构，与所述第六栅极结构连接，且所述第六栅极结构能够通过 所述第四连接结构与另一编程线连接，所述第四连接结构设置在所述第四延伸部远离所述第三延伸部的一侧。
  10. 根据权利要求9所述的反熔丝结构，其中，所述第五栅极结构包括与所述第三延伸部对应设置的第五主区域及向远离所述第四延伸部的方向突出的第五次区域，所述第三连接结构与所述第五次区域连接，所述第六栅极结构包括与所述第四延伸部对应设置的第六主区域及向远离所述第三延伸部的方向突出的第六次区域，所述第四连接结构与所述第六次区域连接。
  11. 根据权利要求1所述的反熔丝结构，其中，所述第一选择晶体管与所述第二选择晶体管以第一轴为对称轴对称设置，所述第一反熔丝单元与所述第三反熔丝单元以所述第一轴为对称轴对称设置，所述第二反熔丝单元与所述第三反熔丝单元以所述第一轴为对称轴对称设置。
  12. 一种反熔丝阵列，包括多个如权利要求1所述的反熔丝结构，多个所述反熔丝结构沿第一方向及第二方向阵列排布，所述第一方向与所述第二方向垂直或具有锐角夹角。
  13. 根据权利要求12所述的反熔丝阵列，其中，在所述第二方向上，相邻反熔丝结构的相邻反熔丝单元共用同一栅极结构。
  14. 根据权利要求12所述的反熔丝阵列，其中，沿所述第二方向排布的反熔丝结构的第一选择晶体管共用同一栅极结构，第二选择晶体管共用同一栅极结构。
  15. 一种存储器，其特征在于，包括如权利要求12所述的反熔丝阵列。
  16. 根据权利要求15所述的存储器，进一步，还包括多条沿所述第一方向排布且沿所述第二方向延伸的编程线，沿所述第二方向排布的一行反熔丝结构对应四条所述编程线，四条所述编程线分别与所述反熔丝结构的所述第一反熔丝单元、所述第二反熔丝单元、所述第三反熔丝单元及所述第四反熔丝单元连接。
  17. 根据权利要求15所述的存储器，进一步，还包括多条沿第二方向排布且沿第一方向延伸的位线，沿所述第一方向排布的一列反熔丝结构共用同一所述位线。
PCT/CN2022/096906 2022-05-25 2022-06-02 反熔丝结构、反熔丝阵列及存储器 WO2023226077A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2022552391A JP2024524780A (ja) 2022-05-25 2022-06-02 アンチヒューズ構造、アンチヒューズアレイ及びメモリ
KR1020227031205A KR20220130243A (ko) 2022-05-25 2022-06-02 안티퓨즈 구조, 안티퓨즈 어레이 및 메모리
EP22760861.9A EP4303921A1 (en) 2022-05-25 2022-06-02 Anti-fuse structure, anti-fuse array, and memory
US17/929,747 US20230386589A1 (en) 2022-05-25 2022-09-05 Anti-fuse structure, anti-fuse array and memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202210577084.X 2022-05-25
CN202210577084.XA CN117174685A (zh) 2022-05-25 2022-05-25 反熔丝结构、反熔丝阵列及存储器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/929,747 Continuation US20230386589A1 (en) 2022-05-25 2022-09-05 Anti-fuse structure, anti-fuse array and memory

Publications (1)

Publication Number Publication Date
WO2023226077A1 true WO2023226077A1 (zh) 2023-11-30

Family

ID=84901276

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/096906 WO2023226077A1 (zh) 2022-05-25 2022-06-02 反熔丝结构、反熔丝阵列及存储器

Country Status (3)

Country Link
CN (1) CN117174685A (zh)
TW (1) TWI835199B (zh)
WO (1) WO2023226077A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105609485A (zh) * 2015-12-22 2016-05-25 格科微电子（上海）有限公司 反熔丝单次可编程存储器及实现方法
US20160293612A1 (en) * 2015-04-06 2016-10-06 SK Hynix Inc. Antifuse memory cells and arrays thereof
EP3288037A1 (en) * 2016-08-25 2018-02-28 eMemory Technology Inc. Memory array having a small chip area
CN107910316A (zh) * 2017-12-04 2018-04-13 睿力集成电路有限公司 半导体器件反熔丝结构及其写入和读取方法
CN208655628U (zh) * 2018-09-10 2019-03-26 长鑫存储技术有限公司 反熔丝结构
US20210249422A1 (en) * 2020-02-10 2021-08-12 Taiwan Semiconductor Manufacturing Company Limited System and method for reducing cell area and current leakage in anti-fuse cell array
CN114284272A (zh) * 2020-09-28 2022-04-05 亿而得微电子股份有限公司 小面积低电压反熔丝元件与阵列

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102169197B1 (ko) * 2014-09-16 2020-10-22 에스케이하이닉스 주식회사 향상된 프로그램 효율을 갖는 안티퓨즈 오티피 메모리 셀 및 셀 어레이
KR102227554B1 (ko) * 2014-11-18 2021-03-16 에스케이하이닉스 주식회사 안티퓨즈 오티피 셀어레이 및 그 동작방법
US10929588B2 (en) * 2018-02-13 2021-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layout, structure, system, and methods

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293612A1 (en) * 2015-04-06 2016-10-06 SK Hynix Inc. Antifuse memory cells and arrays thereof
CN105609485A (zh) * 2015-12-22 2016-05-25 格科微电子（上海）有限公司 反熔丝单次可编程存储器及实现方法
EP3288037A1 (en) * 2016-08-25 2018-02-28 eMemory Technology Inc. Memory array having a small chip area
CN107910316A (zh) * 2017-12-04 2018-04-13 睿力集成电路有限公司 半导体器件反熔丝结构及其写入和读取方法
CN208655628U (zh) * 2018-09-10 2019-03-26 长鑫存储技术有限公司 反熔丝结构
US20210249422A1 (en) * 2020-02-10 2021-08-12 Taiwan Semiconductor Manufacturing Company Limited System and method for reducing cell area and current leakage in anti-fuse cell array
CN114284272A (zh) * 2020-09-28 2022-04-05 亿而得微电子股份有限公司 小面积低电压反熔丝元件与阵列

Also Published As

Publication number Publication date
TW202347341A (zh) 2023-12-01
TWI835199B (zh) 2024-03-11
CN117174685A (zh) 2023-12-05

Similar Documents

Publication Publication Date Title
US10347646B2 (en) Anti-fuse cell structure including reading and programming devices with different gate dielectric thickness
US10832776B2 (en) Semiconductor device and semiconductor memory device
US20090115021A1 (en) Antifuse element in which more than two values of information can be written
CN111987101B (zh) 反熔丝存储器
KR20080026631A (ko) 4.5ｆ2 ｄｒａｍ 셀들에 사용되는 접지된 게이트를 갖는트렌치 분리 트랜지스터 및 그 제조 방법
KR20180061475A (ko) 3차원 반도체 장치
TWI747528B (zh) 小面積低電壓反熔絲元件與陣列
US20240049461A1 (en) Anti-fuse array and memory
WO2023040362A1 (zh) 反熔丝阵列结构及存储器
CN219628265U (zh) 记忆体装置
WO2023226077A1 (zh) 反熔丝结构、反熔丝阵列及存储器
TWI744130B (zh) 低成本低電壓反熔絲陣列
KR20190137004A (ko) 이퓨즈
EP4303921A1 (en) Anti-fuse structure, anti-fuse array, and memory
US10727222B2 (en) Memory system and memory cell having dense layouts
WO2019124350A1 (ja) 半導体装置
TWI769095B (zh) 高寫入效率的反熔絲陣列
US6864518B1 (en) Bit cells having offset contacts in a memory array
WO2023115967A1 (zh) 反熔丝阵列结构和存储器
US11610902B1 (en) Antifuse array structure and memory
WO2024007360A1 (zh) 反熔丝单元结构、反熔丝阵列及其操作方法以及存储器
CN100559594C (zh) 非易失性存储器
KR20230045924A (ko) 반도체 집적 회로 장치 및 이에 바이어스 파워를 공급하는 방법
CN118398059A (zh) efuse存储器
CN117750757A (zh) 半导体存储装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2022552391

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20227031205

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2022760861

Country of ref document: EP

Effective date: 20220906

WWE Wipo information: entry into national phase

Ref document number: 11202252809R

Country of ref document: SG