WO2023225905A1 - 滤波器及其制作方法、电子设备 - Google Patents

滤波器及其制作方法、电子设备 Download PDF

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Publication number
WO2023225905A1
WO2023225905A1 PCT/CN2022/094988 CN2022094988W WO2023225905A1 WO 2023225905 A1 WO2023225905 A1 WO 2023225905A1 CN 2022094988 W CN2022094988 W CN 2022094988W WO 2023225905 A1 WO2023225905 A1 WO 2023225905A1
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Prior art keywords
conductive
base substrate
layer
conductive layer
line
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PCT/CN2022/094988
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English (en)
French (fr)
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WO2023225905A9 (zh
Inventor
闫浩
安齐昌
李月
车春城
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2022/094988 priority Critical patent/WO2023225905A1/zh
Priority to CN202280001426.1A priority patent/CN117461258A/zh
Publication of WO2023225905A1 publication Critical patent/WO2023225905A1/zh
Publication of WO2023225905A9 publication Critical patent/WO2023225905A9/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network

Definitions

  • the present disclosure relates to the field of electronic technology, and specifically to a filter, a manufacturing method thereof, and electronic equipment.
  • the power consumption of the device may increase significantly, but the heat dissipation cannot be effectively reduced due to the increase in integration level. If the heat cannot be effectively and quickly dissipated from the device out, it will directly cause the device to fail due to high temperature, thus seriously affecting the performance and reliability of the device.
  • the purpose of this disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a filter, a manufacturing method thereof, and electronic equipment.
  • a filter including an inductor and a capacitor.
  • a first electrode of the capacitor is connected to a first end of the inductor.
  • the filter further includes: a substrate substrate, the substrate substrate It has at least one functional hole; at least one heat dissipation column, the heat dissipation column is arranged corresponding to the functional hole, and the heat dissipation column is filled in the corresponding functional hole; a first conductive layer is located on the base substrate On one side, the first conductive layer includes: a first conductive line, part of the structure of the first conductive line is used to form the first electrode of the capacitor; a first transfer line, the first transfer line is connected to the one side of the first conductive line; a second conductive layer located on the side of the first conductive layer facing away from the base substrate; the second conductive layer includes: a second conductive line and the first conductive layer; The lines are arranged correspondingly, and the orthographic projection of the second conductive line on the base substrate is located
  • the second conductive line is used to form the capacitor. a second electrode; a third conductive line located on one side of the second conductive line and corresponding to the first adapter line; the third conductive line is connected to the first adapter line through a via hole; Three conductive wires are used to form part of the structure of the inductor coil; at least part of the heat dissipation pillars are insulated from the first conductive layer, and the thermal conductivity of the heat dissipation pillars is greater than the thermal conductivity of the base substrate.
  • the opening area of each position of the functional hole is the same; or, the opening area of the functional hole extends from one side of the base substrate to the other side of the base substrate.
  • the opening area of the functional hole gradually decreases from both sides of the base substrate to a middle position.
  • a ratio of a length of the functional hole in the thickness direction of the base substrate to an aperture of the functional hole is greater than or equal to 5 and equal to or less than 7.
  • the heat dissipation column is a hollow heat dissipation column, and the extension direction of the cavity of the heat dissipation column is the same as the extension direction of the heat dissipation column.
  • the heat dissipation pillar is a solid heat dissipation pillar.
  • the heat dissipation pillar is a conductive pillar.
  • the filter further includes: a first dielectric layer located between the first conductive layer and the second conductive layer, the first dielectric layer and the second conductive layer
  • the conductive lines are arranged correspondingly, and the orthographic projection of the first dielectric layer on the base substrate covers the orthographic projection of the second conductive line on the base substrate;
  • a first seed layer is located on the first dielectric layer and the second conductive layer, the first seed layer is used as a seed layer for generating the second conductive layer.
  • the filter further includes: a third conductive layer located on a side of the second conductive layer facing away from the base substrate; the third conductive layer includes: a fourth conductive layer. wires, the fourth conductive wires and the third conductive wires are arranged correspondingly, and the fourth conductive wires are used to form part of the structure of the inductor coil; wherein, the third conductive wires, the fourth conductive wires The arrangement is bent, the orthographic projection of the third conductive line on the base substrate and the orthographic projection of the fourth conductive line on the base substrate form a winding area; and the third conductive line of the third conductive line forms a winding area.
  • One end is connected to the first end of the fourth conductive wire through a via hole
  • the second end of the third conductive wire is connected to the first adapter wire through a via hole
  • the first end of the third conductive wire is connected to the first adapter wire through a via hole.
  • the extending direction of the two ends is the same as the extending direction from the first end to the second end of the fourth conductive line.
  • the thickness of the second conductive layer and the thickness of the third conductive layer are both greater than the thickness of the first conductive layer.
  • the ratio of the thickness of the second conductive layer to the thickness of the first conductive layer and the ratio of the thickness of the third conductive layer to the thickness of the first conductive layer are greater than Equal to 1.5 and less than or equal to 3.
  • the second conductive layer further includes: a first connection portion located between the second conductive line and the third conductive line and corresponding to the first conductive line. , the first connection part is connected to the first conductive line through a via hole; the third conductive layer further includes: a second connection part, the second connection part is provided corresponding to the second conductive line, and the The orthographic projection of the second connection portion on the base substrate at least partially overlaps the orthographic projection of the second conductive line on the base substrate, and the second connection portion is connected to the second conductive line through a via hole.
  • the filter further includes: a solder ball layer located on the third conductive layer away from the substrate On one side of the substrate, the solder ball layer includes: a first solder ball, the orthographic projection of the base substrate overlaps with the orthographic projection of the fourth conductive line on the base substrate, the first tin ball The ball is connected to one end of the fourth conductive line through a via hole; the orthographic projection of the second solder ball on the base substrate overlaps with the orthographic projection of the third connection portion on the base substrate, so The second solder ball is connected to the third connection part through a via hole; the orthographic projection of the third solder ball on the base substrate overlaps with the orthographic projection of the second connection part on the base substrate, so The third solder ball is connected to the third connection part through a via hole; the orthographic projection of the third solder ball on the base substrate overlaps with the orthographic projection of the second connection part on the base substrate, so The third solder ball is connected to the third connection part through a via hole; the orthographic projection of the third solder ball
  • the functional hole is a blind hole
  • the opening of the blind hole is located on a side of the base substrate away from the first conductive layer.
  • the functional hole is a through hole, or the functional hole is a blind hole and the opening of the blind hole is located on a side of the substrate substrate close to the first conductive layer ;
  • the filter further includes: a first insulating layer, the first insulating layer covers the base substrate on a side facing the first conductive layer.
  • the substrate substrate includes a first functional area and a second functional area
  • the first transfer line is located in the first functional area in an orthographic projection of the substrate substrate, so The orthographic projection of the first conductive line on the base substrate is located in the second functional area, both the first functional area and the second functional area include the functional hole, and the first functional area
  • the functional holes are through holes; the plurality of heat dissipation pillars located in the first functional area include a plurality of first conductive pillars and a plurality of second conductive pillars, a plurality of the first conductive pillars and a plurality of the third conductive pillars.
  • Two conductive pillars are arranged at intervals along the same direction, and the first conductive pillar and the second conductive pillar are arranged side by side.
  • the first conductive pillar and the second conductive pillar are used to form part of the inductor coil.
  • the filter further includes: a fifth conductive layer located on a side of the base substrate away from the first conductive layer, and the through hole is located on the front side of the fifth conductive layer on the base substrate.
  • the fifth conductive layer includes: a plurality of fifth conductive lines, the fifth conductive lines are connected between the first conductive pillars and the second conductive pillars in the same row; wherein,
  • the first transfer wire includes a plurality of first sub-transmission wires, the first sub-transmission wires are used to form part of the structure of the inductor coil, and the first sub-transmission wires are connected to adjacent rows of first conductive pillars. and the second conductive pillar, and each heat dissipation pillar is connected to one of the first sub-transfer lines.
  • the third conductive line includes a plurality of third sub-conductive parts, the third sub-conductive parts are provided corresponding to the first sub-transfer line, and the third sub-conductive part
  • the corresponding first sub-conducting lines are connected through via holes
  • the second conductive layer also includes: the first conductive lines include first sub-conducting lines, second sub-conducting lines and third sub-conducting lines that are connected in sequence. wire, the second sub-conductive wire is used to form the first electrode of the capacitor, the first sub-conductive wire is arranged corresponding to the first sub-transfer wire, and the first sub-conductive wire is connected to the third sub-conductive wire.
  • the filter also includes: a solder ball layer located on the side of the third conductive layer facing away from the base substrate , the solder ball layer includes: a first solder ball, the orthographic projection on the base substrate overlaps with the orthographic projection of the third sub-conductive part on the base substrate, the first solder ball passes through The hole is connected to one end of the third sub-conductive part; the orthographic projection of the second solder ball on the base substrate overlaps with the orthographic projection of the third sub-conductive line on the base substrate, and the The second solder ball is connected to the third sub-conductive line through a via hole; the orthographic projection of the third solder ball on the base substrate overlaps with the orthographic projection of the second conductive line on the base substrate, so The third solder ball is connected to the second conductive line through a via hole.
  • the pore size of the functional hole in the first functional area is larger than the pore size of the functional hole in the second functional area.
  • the ratio of the aperture of the through hole located in the first functional area to the aperture of the functional hole located in the second functional area is greater than or equal to 1.5 and less than or equal to 2.5.
  • the orthographic projection of the first sub-transmission line on the substrate substrate covers the orthographic projection of the first conductive pillar and the second conductive line connected thereto on the substrate substrate;
  • the orthographic projection of the fifth conductive line on the base substrate covers the orthographic projection of the first conductive pillar and the second conductive line connected thereto on the base substrate.
  • the functional hole in the second functional area is a blind hole, and the opening of the blind hole is located on a side of the base substrate away from the first conductive layer.
  • the functional hole in the second functional area is a through hole, or the functional hole in the second functional area is a blind hole, and the opening of the blind hole is located on the substrate.
  • a side close to the first conductive layer; the filter further includes: a first insulating layer covering the second function of the base substrate on the side facing the first conductive layer district.
  • both the thickness of the fifth conductive layer and the thickness of the second conductive layer are greater than the thickness of the first conductive layer.
  • the ratio of the thickness of the fifth conductive layer to the thickness of the first conductive layer and the ratio of the thickness of the second conductive layer to the first conductive layer are greater than or equal to 1.5 And less than or equal to 3.
  • the thickness of the second conductive layer is greater than or equal to 5 ⁇ m
  • the thickness of the first conductive layer is greater than or equal to 3 ⁇ m
  • the thickness of the third conductive layer or the fifth conductive layer is greater than equal to 5 ⁇ m.
  • the material of the heat dissipation pillar is copper.
  • the base substrate is a glass substrate or a silicon substrate.
  • a method of manufacturing a filter includes an inductor and a capacitor.
  • the first electrode of the capacitor is connected to the first end of the inductor.
  • the manufacturing method includes: providing a A base substrate; forming a plurality of functional holes on the base substrate; forming heat dissipation pillars in the functional holes; forming a first conductive layer on one side of the base substrate, the first conductive layer being at least Part of the heat dissipation column is insulated.
  • the first conductive layer includes a first conductive wire and a first transfer wire. Part of the structure of the first conductive wire is used to form the first electrode of the capacitor.
  • the first transfer wire The wiring is connected to one side of the first conductive line; a second conductive layer is formed on the side of the first conductive layer facing away from the base substrate, and the second conductive layer includes a second conductive line and a third conductive line.
  • the second conductive line is arranged corresponding to the first conductive line, and the orthographic projection of the second conductive line on the base substrate is located on the orthographic projection of the first conductive line on the base substrate.
  • the second conductive wire is used to form the second electrode of the capacitor;
  • the third conductive wire is located on one side of the second conductive wire and is provided corresponding to the first transfer wire, and the third conductive wire
  • the wires are connected to the first adapter wire through via holes, and the third conductive wire is used to form part of the structure of the inductor coil.
  • forming a plurality of functional holes on the base substrate includes: irradiating a preset position on the base substrate with a laser to irradiate molecules at the preset position. Modify the keys; use etching liquid to etch the preset positions of the base substrate to form through holes, and/or use the etching process to etch the preset positions of the base substrate according to the preset aspect ratio.
  • the position is etched to form a blind hole, and the bottom of the blind hole has a preset thickness from the other surface of the base substrate, wherein the etching speed of the etching liquid at the preset position is greater than that at all Describe the etching speed of other locations on the base substrate.
  • forming a heat dissipation pillar in the functional hole includes: sputtering a first material in the side wall of the functional hole to form an adhesion layer; The first seed material is sputtered to form a second seed layer; a heat dissipation material of a preset thickness is sputtered on the second seed layer to form a heat dissipation column.
  • the functional hole is a through hole, or the functional hole is a blind hole and the opening of the blind hole is located on a side of the substrate substrate close to the first conductive layer. side; before forming the first conductive layer on one side of the base substrate, the method further includes: depositing a first insulating material on the entire surface of the base substrate to form a first insulating layer.
  • forming a first conductive layer on one side of the base substrate includes: depositing a predetermined thickness of a first conductive material on the first insulating layer using an additive method. , forming a first conductive material layer; using a patterning process to form the first conductive material layer into a first conductive layer; and performing planarization processing on the first conductive layer.
  • the method before forming the second conductive layer on a side of the first conductive layer facing away from the base substrate, the method includes: using a plasma enhanced chemical vapor deposition process to form the second conductive layer on the first conductive layer.
  • Three insulating layers using a patterning process to process the third insulating layer to form openings to expose part of the structure of the first conductive layer and part of the first seed layer; use a sputtering process to A first seed material is deposited at the opening to form a third seed layer; a first conductive material of a predetermined thickness is electroplated on the third seed layer using an electroplating process to form a second conductive layer.
  • the filter further includes a third conductive layer, and after forming a second conductive layer on a side of the first conductive layer facing away from the base substrate, the method further includes: Deposit a second insulating material on the second conductive layer to form a fourth insulating layer; use a patterning process to process the fourth insulating layer to form openings to expose part of the first conductive line.
  • a first conductive material with a preset thickness is electroplated on the seed layer to form a third conductive layer.
  • the third conductive layer includes a fourth conductive line, and the fourth conductive line is provided corresponding to the third conductive line.
  • the orthographic projection of the four conductive lines on the base substrate at least partially overlaps the orthographic projection of the third conductive line on the base substrate, and the fourth conductive line is used to form part of the structure of the inductor coil,
  • the third conductive line and the fourth conductive line are bent and arranged, and the orthographic projection of the third conductive line on the base substrate and the orthographic projection of the fourth conductive line on the base substrate form a circle.
  • the first end of the third conductive wire is connected to the fourth conductive wire through a via hole
  • the second end of the third conductive wire is connected to the first adapter wire through a via hole.
  • the extending direction from the first end to the second end of the conductive line is the same as the extending direction from the first end to the second end of the fourth conductive line.
  • the method further includes: depositing a second insulating material on the third conductive layer to form a fifth insulating layer; using a patterning process to Three openings are formed on the fifth insulating layer corresponding to the positions of the fourth conductive lines to expose part of the structure of the fourth conductive lines respectively; solder balls are respectively implanted in the three openings to form The signal input end, signal output end and ground end of the filter.
  • the substrate substrate includes a first functional area and a second functional area, and the first transfer line is located in the first functional area in an orthographic projection of the substrate substrate, so The orthographic projection of the first conductive line on the substrate is located in the second functional area, and the functional holes in the first functional area and the second functional area are through holes;
  • the plurality of heat dissipation columns include A plurality of first conductive pillars and a plurality of second conductive pillars, the plurality of first conductive pillars and the plurality of second conductive pillars are respectively arranged at intervals along the same direction, and the first conductive pillars and the second conductive pillars Two conductive pillars are arranged side by side, and the first conductive pillar and the second conductive pillar are used to form part of the structure of the inductor coil; before forming the first conductive layer on one side of the base substrate, the method also The method includes: using a deposition process to deposit a first insulating material in the second
  • first conductive material with a predetermined thickness on the first insulating layer and the first functional area of the base substrate to form a first conductive material layer; use a patterning process to form the first conductive material layer into a first Conductive layer; perform planarization processing on the first conductive layer.
  • the filter further includes a fifth conductive layer
  • the method further includes: using a sputtering process to dispose the first function on a side of the base substrate away from the first conductive layer. Sputtering the first seed material in the area to form a fifth seed layer; using an electroplating process to electroplate a preset thickness of the first conductive material on the fifth seed layer to form a fifth conductive layer; using a patterning process to form a fifth conductive layer.
  • the layers are processed to form a plurality of first sub-transfer lines.
  • the first sub-transfer lines are used to form part of the structure of the inductor coil.
  • the first sub-transfer lines are connected to the adjacent rows of first conductive pillars and third between two conductive pillars, and each heat dissipation pillar is connected to one of the first sub-transfer lines.
  • an electronic device including the filter described in any embodiment of the present disclosure.
  • the filter provided by the present disclosure forms functional holes on the base substrate, fills the functional holes with heat dissipation pillars with high thermal conductivity, and sets at least part of the heat dissipation pillars to be insulated from the first conductive layer, so that it can pass through These heat dissipation pillars are used to improve the heat dissipation performance of the substrate substrate, thereby improving the overall heat dissipation performance of the filter.
  • Figure 1 is an equivalent circuit diagram of a filter according to an embodiment of the present disclosure
  • Figure 2 is a structural layout of a filter according to an embodiment of the present disclosure
  • Figure 3 shows the layout structure of the base substrate in Figure 2;
  • Figure 4 is the layout structure of the first conductive layer in Figure 2;
  • Figure 5 is the layout structure of the second conductive layer in Figure 2;
  • Figure 6 shows the layout structure of the third conductive layer in Figure 2;
  • Figure 7 shows the layout structure of the solder ball layer in Figure 2
  • Figure 8 is a stacked layout structure of the first conductive layer and the second conductive layer in Figure 2;
  • Figure 9 is a stacked layout structure of the second conductive layer and the third conductive layer in Figure 2;
  • Figure 10 is a stacked layout structure of the first conductive layer, the first dielectric layer and the first seed layer in Figure 2;
  • Figure 11 is a partial cross-sectional view along the dotted line MM in Figure 2;
  • Figure 12a is a cross-sectional view of a base substrate according to an embodiment of the present disclosure.
  • Figure 12b is a cross-sectional view of a base substrate according to another embodiment of the present disclosure.
  • Figure 13a is a schematic diagram of the bending of the first adapter wire, the third conductive wire and the fourth conductive wire according to an embodiment of the present disclosure
  • Figure 13b is a schematic diagram of the bending of the first adapter wire, the third conductive wire and the fourth conductive wire according to another embodiment of the present disclosure
  • Figure 14 is a structural layout of a filter according to another embodiment of the present disclosure.
  • Figure 15 is the layout structure of the base substrate in Figure 14;
  • Figure 16 is the layout structure of the first conductive layer in Figure 14;
  • Figure 17 is the layout structure of the second conductive layer in Figure 14;
  • Figure 18 shows the layout structure of the solder ball layer in Figure 14
  • Figure 19 is the layout structure of the fifth conductive layer in Figure 14;
  • Figure 20 is a cross-sectional view along the dotted line NN in Figure 14;
  • Figure 21a is a cross-sectional view of a base substrate according to an embodiment of the present disclosure.
  • Figure 21b is a cross-sectional view of a base substrate according to another embodiment of the present disclosure.
  • 22 to 27f are process flow diagrams of a filter manufacturing method according to another embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments.
  • the same reference numerals in the drawings indicate the same or similar structures, and thus their detailed descriptions will be omitted.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • FIG. 1 is an equivalent circuit diagram of a filter according to an embodiment of the present disclosure.
  • the filter may include a capacitor C, an inductor L, and a resistor R.
  • the first end of the inductor L is connected to the first electrode of the capacitor C, and the second end is connected to the signal input terminal IN through the resistor R; the second electrode of the capacitor C is connected to the ground terminal GND, and the second end of the inductor L and the first electrode of the capacitor C Connect the signal output terminal OUT.
  • the filter provided by the present disclosure may include a base substrate, a heat dissipation column, a first conductive layer and a second conductive layer.
  • the base substrate has at least one functional hole; the heat dissipation column is provided correspondingly to the functional hole, and the heat dissipation column is filled with the corresponding function In the hole; the first conductive layer is located on one side of the base substrate.
  • the first conductive layer may include a first conductive line and a first transfer line.
  • Part of the structure of the first conductive line is used to form the first electrode of the capacitor C;
  • first The transfer line is connected to one side of the first conductive line, and part of the structure of the first transfer line is used to form a partial coil structure of the inductor L;
  • the second conductive layer is located on the side of the first conductive layer away from the base substrate, and the second conductive layer It may include a second conductive line and a third conductive line, the second conductive line is arranged corresponding to the first conductive line, the orthographic projection of the second conductive line on the base substrate is located on the orthographic projection of the first conductive line on the base substrate, and the The two conductive wires are used to form the second electrode of the capacitor C; the third conductive wire is located on one side of the second conductive wire and is provided corresponding to the first transfer wire.
  • the third conductive wire is connected to the first transfer wire through a via hole.
  • the wires are used to form part of the coil structure of the inductor L; wherein at least part of the heat dissipation pillars are insulated from the first conductive layer, and the thermal conductivity of the heat dissipation pillars is greater than the thermal conductivity of the base substrate.
  • the filter provided by the present disclosure forms functional holes on the base substrate, fills the functional holes with heat dissipation pillars with high thermal conductivity, and sets at least part of the heat dissipation pillars to be insulated from the first conductive layer, so that it can pass through These heat dissipation pillars are used to improve the heat dissipation performance of the substrate substrate, thereby improving the overall heat dissipation performance of the filter.
  • the inductor L may be a three-dimensional inductor L or a two-dimensional inductor L.
  • the three-dimensional inductor L uses the conductivity of the heat dissipation pillars, and the heat dissipation pillars form part of the structure of the inductor L coil.
  • the two-dimensional inductor L completely uses the wiring of the conductive layer to form the coil structure of the inductor L, and the heat dissipation pillar only forms the heat dissipation structure of the filter.
  • a filter with a two-dimensional inductance L may include a base substrate and a first conductive layer, a second conductive layer, a third conductive layer, and a solder ball layer that are sequentially stacked on one side of the base substrate.
  • Figure 2 is a structural layout of a filter according to an embodiment of the present disclosure.
  • Figure 3 is a layout structure of the substrate in Figure 2.
  • Figure 4 is a layout of the first conductive layer in Figure 2.
  • Structure Figure 5 is the layout structure of the second conductive layer in Figure 2
  • Figure 6 is the layout structure of the third conductive layer in Figure 2
  • Figure 7 is the layout structure of the solder ball layer in Figure 2
  • Figure 8 is the layout structure of the third conductive layer in Figure 2
  • Figure 9 shows the stacked layout structure of the second conductive layer and the third conductive layer in Figure 2.
  • Figure 10 shows the first conductive layer and the first dielectric layer in Figure 2. and the stacked layout structure of the first seed layer.
  • Figure 11 is a partial cross-sectional view along the dotted line MM in Figure 2.
  • the first direction X may be the row direction X shown in the figure
  • the second direction Y may be the column direction Y shown in the figure
  • the first direction X intersects the second direction Y.
  • the base substrate 1 may be a glass substrate or a silicon substrate.
  • the base substrate 1 includes a plurality of functional holes distributed in an array, and each functional hole is filled with a heat dissipation pillar 10.
  • the thermal conductivity of the heat dissipation pillar 10 is greater than the thermal conductivity of the base substrate 1, and at least part of the heat dissipation pillar 10 is connected with the first conductive
  • the layer 2 is insulated, so that the heat dissipation pillar 10 which is insulated from the first conductive layer 2 can form a heat dissipation structure of the filter and improve the heat dissipation effect of the filter.
  • metal conductive materials have high thermal conductivity.
  • the heat dissipation pillars 10 in this exemplary embodiment may be formed of metal conductive materials.
  • copper conductive pillars may be formed of copper materials as the heat dissipation pillars 10 . It should be understood that this is only an exemplary description and should not be understood as a limitation on the material of the heat dissipation pillar 10 of the present disclosure. Any other material having a higher thermal conductivity than the base substrate 1 can form the heat dissipation pillar 10 of the present disclosure.
  • the heat dissipation pillar 10 described in this disclosure may be a hollow heat dissipation pillar 10 , and the extension direction of the cavity of the heat dissipation pillar 10 is the same as the extension direction of the heat dissipation pillar 10 .
  • the heat dissipation pillar 10 can also be a solid heat dissipation pillar 10, and the solid heat dissipation pillar 10 can have better heat dissipation effect.
  • the functional hole can be a through hole TGV or a blind hole BGV.
  • the through hole TGV is a hole that penetrates the two opposite sides of the substrate 1.
  • the heat dissipation pillar 10 is only used for heat dissipation. structure, it is necessary to electrically isolate the heat dissipation pillar 10 filled in the through hole TGV from the first conductive layer 2.
  • the filter can also include a first insulating layer 100.
  • the first insulating layer 100 can be deposited through the entire surface.
  • the first insulating layer 100 is obtained by depositing a first insulating material on the entire side of the base substrate 1 facing the first conductive layer 2.
  • the first insulating material may be, for example, SiNx.
  • Figure 12a is a cross-sectional view of a substrate according to one embodiment of the present disclosure.
  • Figure 12b is a cross-sectional view of a substrate according to another embodiment of the present disclosure.
  • the blind hole BGV is only A hole that penetrates one surface of the base substrate 1 but does not penetrate the other surface.
  • the blind via BGV has an opening and a hole bottom. The opening is located on one surface of the substrate substrate 1 and extends from the surface where the opening is located along the thickness direction of the substrate substrate to the other surface of the substrate substrate and is a distance away from the substrate.
  • the other surface of the base substrate is formed at a certain distance from the bottom of the blind hole BGV.
  • the bottom of the functional hole can be facing the first conductive layer 2 as shown in Figure 12a, that is, the hole opening is located on the side of the substrate substrate away from the first conductive layer, so as to pass through the substrate substrate 1
  • the remaining thickness is used to achieve electrical isolation between the heat dissipation pillar 10 and the first conductive layer 2 .
  • the hole bottom of the blind hole BGV can also be arranged away from the first conductive layer 2, that is, the opening of the blind hole BGV is located on the side of the substrate close to the first conductive layer.
  • the bottom of the blind hole BGV can be placed on the substrate
  • a first insulating material is deposited on the entire side of the substrate 1 facing the first conductive layer 2 to form a first insulating layer 100.
  • the first insulating layer 100 is used to achieve electrical isolation between the first conductive layer 2 and the heat dissipation pillar 10.
  • the thickness distance is The remaining thickness of the base substrate 1 at the position of the blind hole BGV.
  • the different distribution density of functional holes in the substrate 1 will affect the heat dissipation of the filter.
  • the distribution density of the functional holes is higher, it is equivalent to having more heat dissipation pillars 10 per unit area. Therefore, By increasing the distribution density of functional holes, the heat dissipation performance of the filter can be improved.
  • the first conductive layer 2 may include a first transfer line 22 and a first conductive line 21 , and the orthographic projection of the first conductive line 21 on the base substrate 1 may be along Extending in the first direction X, part of the structure of the first conductive line 21 may be used to form a first electrode of the capacitor C.
  • the first transfer wire 22 is connected to one end of the first conductive wire 21.
  • the first transfer wire 22 can be connected to the third conductive wire 33 in the second conductive layer 3 (used to form part of the structure of the inductor L coil) through a via hole, so that Through the connection between the first adapter wire 22 and the first conductive wire 21 , the first end of the inductor L is connected to the first electrode of the capacitor C.
  • the second conductive layer 3 may include a second conductive line 32 and a third conductive line 33 , and the orthographic projection of the second conductive line 32 on the base substrate 1 may be located at The first conductive line 21 is on the orthographic projection of the base substrate 1 .
  • the orthographic projection of the second conductive line 32 on the base substrate 1 is located within the orthographic projection of the first conductive line 21 on the base substrate 1 .
  • the second conductive line 32 is on the orthographic projection of the base substrate 1 .
  • 32 is arranged opposite to the first conductive line 21 to form two electrodes of the capacitor C.
  • the third conductive wire 33 can be bent to form part of the structure of the inductor L coil.
  • the third conductive wire 33 can be connected to the first conductive layer through the via hole (blackened position D2 in Figures 5 and 8).
  • the second conductive layer 3 may also include a first connection part 31.
  • the first connection part 31 is located between the second conductive line 32 and the third conductive line 33 and is provided corresponding to the first conductive line 21.
  • the first connection part 31 is at The orthographic projection of the base substrate 1 may be located on the orthographic projection of the first conductive line 21 on the base substrate 1 .
  • the first connection part 31 can be connected to the first conductive line 21 through a via hole, so that the first connection part 31 is connected to the first end of the inductor L and the first electrode of the capacitor C.
  • the first connection part 31 31 is then connected to the third connection portion 43 of the third conductive layer 4 and the second solder ball 2 of the solder ball layer 5 through via holes to form the signal output terminal OUT in FIG. 1 .
  • the third conductive layer 4 may include fourth conductive lines 44 arranged corresponding to the third conductive lines 33 .
  • the fourth conductive lines 44 are on the lining.
  • the orthographic projection of the base substrate 1 and the orthographic projection of the third conductive line 33 on the base substrate 1 may partially overlap, and the fourth conductive line 44 may be used to form a partial structure of the inductor L coil.
  • the fourth conductive line 44 may be connected to the third conductive line 33 through a via hole (blackened position D1 in FIGS. 6 and 9 ).
  • the third conductive layer 4 may also include a second connection part 42 and a third connection part 43.
  • the second connection part 42 is provided corresponding to the second conductive line 32 in the second conductive layer 3.
  • the second connection part 42 is on the base substrate.
  • the orthographic projection of 1 may overlap with the orthographic projection portion of the second conductive line 32 on the base substrate 1 .
  • the second connection part 42 can be connected to the second conductive wire 32 through a via hole to lead out the second electrode of the capacitor C and then connect to the ground terminal GND through the third solder ball 3 of the solder ball layer 5 .
  • the third connecting portion 43 is provided correspondingly to the first connecting portion 31, and the orthographic projection of the third connecting portion 43 on the base substrate 1 may overlap with the orthographic projection of the first connecting portion 31 on the base substrate 1.
  • the third connection part 43 can be connected to the first connection part 31 through a via hole.
  • the signal output in Figure 1 is formed after the third connection part 43 is connected to the second solder ball 2 at the corresponding position. terminal OUT.
  • the solder ball layer 5 may include a first solder ball 1 , a second solder ball 2 and a third solder ball 3 .
  • the first solder ball 1 is on the substrate 1
  • the orthographic projection may overlap with the orthographic projection of the fourth conductive line 44 on the base substrate 1 , and the first solder ball 1 may be connected to one end of the fourth conductive line 44 through a via hole to form the signal input in FIG. 1 Terminal IN.
  • the orthographic projection of the second solder ball 2 on the base substrate 1 can overlap with the orthographic projection of the third connecting portion 43 on the base substrate 1 , and the second solder ball 2 can be connected to the third connecting portion 43 through the via hole, forming the configuration shown in FIG.
  • the signal output terminal OUT The orthographic projection of the third solder ball 3 on the base substrate 1 may overlap with the orthographic projection of the second connection part 42 on the base substrate 1 , and the third solder ball 3 may be connected to the second connection part 42 through a via hole, so that the capacitor The second electrode of C is connected to the ground terminal GND.
  • the third conductive line 33 and the fourth conductive line 44 are bent and arranged respectively.
  • the orthographic projection of the third conductive line 33 on the substrate 1 and the fourth conductive line 44 on the substrate forms a winding area, the first end of the third conductive line 33 can be connected to the first end of the fourth conductive line 44 through the via hole, and the second end of the third conductive line 33 can be connected through the via hole.
  • the extension direction from the first end to the second end of the first adapter wire 22 and the third conductive wire 33 is the same as the extension direction from the first end to the second end of the fourth conductive wire 44. Therefore, the third conductive wire 33 and the fourth conductive wire 44 extend in the same direction.
  • the wire 44 as a whole forms a spiral wound structure.
  • extension direction of a certain conductive line from the first end to the second end described in the present disclosure can be understood as the moving direction of any point on the conductive line when it moves from the first end to the second end. It can be clockwise or counterclockwise.
  • the first connecting wire 22 can also form a partial coil structure of the inductor L.
  • the first adapter wire 22 , the third conductive wire 33 and the fourth conductive wire 44 jointly form the coil structure of the inductor L, as shown in FIG. 9 , the first adapter wire 22 , the third conductive wire 33 and the fourth conductive wire 44 A spiral structure is formed as a whole.
  • One end of the spiral structure is connected to the first conductive wire 21 by the first transfer line 22 so that the first end of the inductor L is connected to the first electrode of the capacitor C.
  • the other end of the spiral structure is connected by a fourth conductive wire.
  • the end of the line 44 is connected to the second solder ball 2 of the solder ball layer 5, so that the second end of the inductor L is connected to the signal input terminal IN through a resistor.
  • the first adapter line 22, the third conductive line 33, and the fourth conductive line 44 are respectively bent and arranged.
  • the first adapter line 22 is connected with the first The starting end of the connection of the conductive wire 21 starts to be bent in the counterclockwise direction, and its end is connected to the starting end of the third conductive wire 33 through the via hole. After the third conductive wire 33 is also bent in the counterclockwise direction, its end passes through the through hole. The hole is connected to the starting end of the fourth conductive wire 44. After the fourth conductive wire 44 is bent, its end is connected to the solder ball at the corresponding position of the solder ball layer 5.
  • the first transfer wire 22, the third conductive wire 33 and the The four conductive lines 44 form a winding area in the orthographic projection of the base substrate 1 .
  • the first transfer line 22 , the third conductive line 33 and the fourth conductive line 44 form a spirally extending winding as a whole, forming a coil structure of the inductor L.
  • Figure 13a is a schematic diagram of the bending of the first adapter wire, the third conductive wire and the fourth conductive wire according to one embodiment of the present disclosure.
  • Figure 13b is a schematic diagram of the first adapter wire, the third conductive wire according to another embodiment of the present disclosure.
  • the first transfer wire 22, the third conductive wire 33 and the fourth conductive wire 44 can be bent in regular shapes, such as U-shaped bends, circular bends, etc. Bending, etc., or it can also be irregular bending, for example, it can be bent in the manner shown in Figure 13a and Figure 13b, and the present disclosure is not limited thereto.
  • the difficulty of wiring can be simplified, which is beneficial to adjusting the inductance L parameter.
  • the base substrate 1 may further include an adhesion layer and a second seed layer.
  • a first material may be sputtered on the sidewalls of the functional holes through a sputtering process to form an adhesion layer.
  • the first material may be, for example, Ti, that is, a Ti adhesion layer is formed on the inner wall of the functional hole by sputtering Ti material.
  • the thickness of the adhesion layer can be greater than 5nm.
  • the second seed layer is then formed by sputtering the first seed material on the Ti adhesion layer.
  • the thickness of the second seed layer can be greater than 30nm.
  • the first seed material can be copper, for example, and then the through hole TGV can be formed in a butterfly shape. Double-sided Cu electroplating is performed to form a heat dissipation pillar 10 with a preset thickness. It should be understood that the first seed material can also be other materials.
  • the thickness of the base substrate 11 may be 0.25mm ⁇ 0.35mm.
  • the thickness of the base substrate 1 may be 0.25mm, 0.27mm, 0.3mm, 0.35mm, etc.
  • the cross-section of the functional hole on a plane parallel to the base substrate 1 may be circular, and the ratio of the length of the functional hole along the thickness direction of the base substrate 1 to the aperture of the functional hole may be greater than or equal to 5 and less than or equal to 7. For example, it can be 5, 5.5, 6, 6.5, 7, etc.
  • the pore diameter of the functional pores may be 50 ⁇ m to 80 ⁇ m.
  • the pore diameters of the functional pores may be 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, or 80 ⁇ m.
  • the thickness of the adhesion layer located between the second seed layer and the sidewall of the functional hole may be 5 nm to 30 nm.
  • the thickness of the adhesion layer may be 5 nm, 10 nm, 15 nm, 25 nm, 30 nm, etc.
  • the thickness of the second seed layer may be 30 nm to 80 nm.
  • the thickness of the second seed layer may be 30 nm, 50 nm, 70 nm, 80 nm, etc.
  • the cross-section of the functional hole on a plane parallel to the base substrate 1 may also be in other shapes, such as rectangle, rhombus, etc.
  • the functional holes on the base substrate 1 may have different shapes.
  • the functional holes on the base substrate 1 can be formed by laser drilling.
  • the opening areas of the functional holes at various positions in the thickness direction of the base substrate 1 can be the same.
  • the base substrate 1 can also be formed through a wet etching process.
  • a laser can be used to irradiate a preset position on the base substrate 1 to modify the molecular bonds at the preset position of the base substrate 1 so that the substrate
  • the etching speed at the preset position of the substrate 1 will be greater than the etching speed at other positions of the base substrate 1
  • the etching liquid is used to etch the preset position of the base substrate 1 to form functional holes.
  • an etching liquid can be used to etch functional holes from one side of the glass substrate to the other side.
  • the opening area of the functional holes gradually decreases from one opening to the other opening.
  • etching liquid can also be used to etch functional holes from both sides of the base substrate 1 toward the middle.
  • the opening area of the functional holes can gradually decrease from the two openings to the middle position.
  • the wet etching process can make the side walls of the functional holes smoother, thereby facilitating the bonding of the adhesion layer, the second seed layer and the side walls of the functional holes.
  • the functional hole is a through hole TGV or a blind hole BGV, it can have the functional hole structure and its effect described above.
  • the shape of the heat dissipation pillar 10 located in the functional hole can match the shape of the functional hole, that is, the radial size of each position of the heat dissipation pillar 10 is the same, or the radial size of the heat dissipation pillar 10 can be from one side of the substrate substrate 1
  • the radial size of the heat dissipation pillar 10 may gradually decrease toward the other side of the base substrate 1 , or the radial size of the heat dissipation pillar 10 may gradually decrease from both sides of the base substrate 1 to a position in the middle.
  • the thickness of the second conductive layer 3 and the thickness of the third conductive layer 4 may be greater than the thickness of the first conductive layer 2 .
  • the thickness of the second conductive layer 3 and the thickness of the third conductive layer 4 can be 1.5 times to 3 times the thickness of the first conductive layer 2 , for example, it can be 1.5 times, 2 times, 2.5 times, 3 times, etc.
  • the thickness of the first conductive layer 2 may be, for example, 3 ⁇ m or more, and the thickness of the second conductive layer 3 and the third conductive layer 4 may be, for example, 5 ⁇ m or more.
  • the second conductive layer 3 and the third conductive layer 4 are to form the coil structure of the inductor L, by increasing the thickness of the second conductive layer 3 and the third conductive layer 4, the inductance L value of the formed inductor L can be increased and reduced. The loss of the inductor L thereby improves the filtering effect of the filter.
  • the filter may further include a first dielectric layer 210 and a first seed layer 220 laminated on the first conductive layer 2 in sequence.
  • the two conductive lines 32 are arranged correspondingly, and the orthographic projection of the first dielectric layer 210 on the base substrate 1 covers the orthographic projection of the second conductive line 32 on the base substrate 1.
  • the first dielectric layer 210 is used to form the dielectric layer of the capacitor C.
  • the plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit a 120nm high-flatness SiNx film as the dielectric layer of the capacitor C to ensure the uniformity of the capacitor C.
  • a 100 nm Cu film can be deposited on the first dielectric layer 210 using magnetron sputtering as a second electrode pad for the capacitor C and a seed layer for generating the second electrode of the capacitor C.
  • a filter with a three-dimensional inductance L may include a base substrate 1, a first conductive layer 2, a second conductive layer 3, a solder ball layer 5 and a first conductive layer 2 and a second conductive layer 3 arranged sequentially on one side of the base substrate 1.
  • the fifth conductive layer 6 on the other side of the base substrate 1 .
  • Figure 14 is a structural layout of a filter according to another embodiment of the present disclosure.
  • Figure 15 is a layout structure of the base substrate in Figure 14.
  • Figure 16 is a layout of the first conductive layer in Figure 14.
  • Layout structure Figure 17 is the layout structure of the second conductive layer in Figure 14
  • Figure 18 is the layout structure of the solder ball layer in Figure 14
  • Figure 19 is the layout structure of the fifth conductive layer in Figure 14
  • Figure 20 is the layout structure of the fifth conductive layer in Figure 14 Sectional view along dashed line NN.
  • the base substrate 1 may be a glass substrate or a silicon substrate.
  • the base substrate 1 may include a first functional area A and a second functional area B.
  • the first functional area A is distributed with a plurality of first conductive pillars 101 and a plurality of second conductive pillars 102.
  • the plurality of first conductive pillars 101 and a plurality of second conductive pillars are distributed in the first functional area A.
  • the two conductive pillars 102 are arranged at intervals along the same direction, for example, they can be arranged at intervals along the second direction Y in the figure, and the first conductive pillar 101 and the second conductive pillar 102 are arranged side by side.
  • the functional holes in the first functional area A are Through-hole TGV, such that the conductive pillar located in the through-hole TGV can form an electrical connection with the conductive wires and patch wires connected thereto, so that the conductive pillar forms a part of the structure of the coil of the inductor L.
  • the heat dissipation pillar 10 located in the second functional area B is only used to form the heat dissipation structure of the filter.
  • the functional holes in the second functional area B can be through holes TGV or blind holes BGV.
  • FIG. 21 a is a cross-sectional view of a base substrate according to one embodiment of the present disclosure
  • FIG. 21 b is a cross-sectional view of a base substrate according to another embodiment of the present disclosure.
  • the functional hole in the second functional area B is a through hole TGV, or as shown in Figure 21a
  • the functional hole in the second functional area B is a blind hole BGV and the opening of the blind hole BGV is located on the substrate
  • the filter structure of the two-dimensional inductor L mentioned above it is similar to the filter structure of the two-dimensional inductor L mentioned above.
  • the insulating layer 100 electrically isolates the heat dissipation pillar 10 in the through hole TGV of the second functional area B from the first conductive layer 2 through the first insulating layer 100 .
  • the functional hole in the second functional area B is a blind hole BGV and the opening of the blind hole BGV is located on the side of the substrate 1 away from the first conductive layer 2, the blind hole BGV can be used
  • the remaining thickness of the hole bottom substrate 1 forms an electrical isolation between the heat dissipation pillar 10 and the first conductive layer 2 .
  • the aperture of the through hole in the first functional area A may be larger than the aperture of the functional hole in the second functional area B, which is beneficial to increasing the inductance value and improving the performance of the filter.
  • the functional hole in the first functional area A has a large aperture, which can adapt to the line width of the first sub-adapter line 221 in the first functional area A.
  • the line width of the first sub-transmission line 221 may be 60 ⁇ m
  • the diameter of the through hole in the first functional area A may be, for example, 50 ⁇ m
  • the diameter of the functional hole in the second functional area B may be 40 ⁇ m, 30 ⁇ m, etc.
  • the first conductive layer 2 may also include a first conductive line 21 and a first transfer line 22 , and the first transfer line 22 may include a plurality of first sub-connections.
  • Wiring 221, the first sub-transition wire 221 can be used to form a partial coil structure of the inductor L.
  • the first sub-transmission wire 221 is connected between the first conductive pillars 101 and the second conductive pillars 102 of adjacent rows, and each conductive pillar Connect a first sub-adapter line 221.
  • the first conductive line 21 may extend along the first direction Forming the first electrode of the capacitor C, the first sub-conducting line 211 is provided correspondingly to the first sub-conducting line 221.
  • the first sub-conducting line 211 is connected to the second sub-conducting line 212 and the first sub-conducting line 211 corresponding to the first sub-conducting line 211. between the sub-transition lines 221, thereby connecting the first electrode of the capacitor C to the first end of the inductor L.
  • the third sub-conductive line 213 can be connected to the second solder ball 2 of the solder ball layer through a via hole to connect the first end of the inductor L and the first electrode of the capacitor C to the second solder ball 2 to form the signal in Figure 1 Output terminal OUT.
  • the third conductive line 33 may include a plurality of third sub-conductive parts 331 , and the third sub-conductive parts 331 are different from the first sub-conductive parts 331 .
  • the transfer lines 221 are arranged in one-to-one correspondence, and the orthographic projection of the third sub-conductive part 331 on the base substrate 1 can be located on the orthographic projection of the first sub-transfer line 221 on the base substrate 1 , and the third sub-conductive part 331 can pass through
  • the holes are connected to the corresponding first sub-conducting lines 221, which is equivalent to the third conductive line 33 and the second sub-conducting line 212 forming a parallel structure.
  • the second conductive lines 32 can be arranged in one-to-one correspondence with the second sub-conductive lines 212, and the orthographic projection of the second conductive line 32 on the base substrate 1 can be located within the orthographic projection of the second sub-conductive line 212 on the base substrate 1, so that The second conductive wire 32 and the second sub-conductive wire 212 are arranged facing each other one by one to form two facing electrodes of the capacitor C.
  • the second conductive layer 3 may also include an adapter portion 34, which is located on the side of the second conductive line 32 away from the third sub-conductive portion 331, and is provided corresponding to the third sub-conductive line 213.
  • the adapter portion The orthographic projection of 34 on the base substrate can be located within the orthographic projection of the third sub-conductive line 213 on the base substrate.
  • the adapter portion 34 can connect the third sub-conductive line 213 and the solder ball through respective via holes.
  • the second solder ball 2 of the layer forms the signal output terminal OUT in Figure 1.
  • the solder ball layer 5 may include a first solder ball 1 , a second solder ball 2 and a third solder ball 3 .
  • the first solder ball 1 is on the substrate 1
  • the orthographic projection of can overlap with the orthographic projection of the third sub-conductive part 331 on the base substrate 1 , and the first solder ball 1 can be connected to the third sub-conductive part 331 of the third conductive layer 4 through a via hole to form the third sub-conductive part 331 of the third conductive layer 4 through the via hole.
  • the signal input terminal IN The orthographic projection of the second solder ball 2 on the base substrate 1 can overlap with the orthographic projection of the third sub-conductive line 213 on the base substrate 1.
  • the second solder ball 2 can be connected to the third sub-conductive line 213 through the via hole, forming The signal output terminal OUT in Figure 1.
  • the orthographic projection of the third solder ball 3 on the base substrate 1 can overlap with the orthographic projection of the second conductive line 32 on the base substrate 1 , and the third solder ball 3 can be connected to the second conductive line 32 through the via hole, so that the capacitance C
  • the second electrode is connected to the ground terminal GND.
  • the fifth conductive layer 6 is located on the other side of the base substrate 1 , and the fifth conductive layer 6 may include a plurality of fifth conductive lines 71 .
  • the orthographic projection of 71 on the base substrate 1 may extend along the first direction 71.
  • the conductive pillar, the first sub-transfer wire 221 and the second conductive wire 32 form a spiral winding as a whole, and the spiral winding forms a coil of the inductor L.
  • the line width of the fifth conductive line 71 may be greater than the width of the first conductive pillar 101 connected thereto and greater than the width of the second conductive pillar 102 connected thereto.
  • the filter may further include a first dielectric layer 210 and a first seed layer 220 laminated on the first conductive layer 2 in sequence.
  • the first dielectric layer 210 and the second conductive line 32 are arranged correspondingly, and the orthographic projection of the first dielectric layer 210 on the base substrate 1 covers the orthographic projection of the second conductive line 32 on the base substrate 1 .
  • the first dielectric layer 210 is used to form a dielectric layer of the capacitor C.
  • the material of the first dielectric layer 210 may be SiNx, for example.
  • a plasma enhanced chemical vapor deposition (PECVD) process may be used to form a second conductive line on the first conductive layer 2 .
  • PECVD plasma enhanced chemical vapor deposition
  • the thickness of the SiNx film is adjusted according to the capacitance value of the prepared capacitor C.
  • the SiNx film needs to ensure high flatness to ensure the uniformity of the capacitance C.
  • a magnetron sputtering method can be used to deposit a Cu film with a set thickness on the SiNx dielectric layer to obtain the first seed layer 220.
  • the first seed layer 220 serves as the second electrode pad of the capacitor C and forms the capacitor C. the seed layer of the second electrode.
  • the thickness of the Cu film can be greater than or equal to 100nm, so that the capacitance value of the capacitor C meets the requirements and meets the performance requirements of the filter.
  • the conductive heat dissipation pillar 10 in the through hole TGV serves as a part of the coil structure of the inductor L, and in the area corresponding to the capacitor C,
  • the function of the functional hole is the same as that of the functional hole in the filter of the two-dimensional inductor L. They are both used as the heat dissipation structure of the filter to improve the heat dissipation performance of the filter.
  • the functional holes may have the same structural features as the functional holes in the two-dimensional inductance L filter, and the characteristics of the functional holes will not be described again here.
  • the thickness of the fifth conductive layer 6 may be greater than the thickness of the first conductive layer 2 , and the thickness of the fifth conductive layer 6 may be 1.5 to 3 times the thickness of the first conductive layer 2 , for example, it may be 1.5x, 2x, 2.5x, 3x etc.
  • the thickness of the first conductive layer 2 may be, for example, 3 ⁇ m or more, and the fifth conductive layer 6 may have a thickness of 5 ⁇ m or more, for example. Because the fifth conductive layer 6 is to form the coil structure of the inductor L, by increasing the thickness of the fifth conductive layer 6, the inductance L value of the formed inductor L can be increased, and the loss of the inductor L can be reduced, thereby improving the formed filter. the overall filtering effect.
  • the present disclosure also provides a filter manufacturing method, which can be used to form the filters shown in FIGS. 2 and 14 .
  • a filter manufacturing method which can be used to form the filters shown in FIGS. 2 and 14 .
  • FIGS. 2 and 14 As shown in Figures 22 to 28, it is a process flow chart of an exemplary embodiment of the filter manufacturing method of the present disclosure.
  • the manufacturing method includes:
  • the base substrate 1 can be a glass base substrate 1 or a silicon base base substrate 1.
  • the thickness is 0.25 mm to 0.3 mm.
  • the thickness of the glass substrate can be 0.25 mm, 0.27 mm, 0.3 mm, etc.
  • the pore diameter of the functional pores can be 50 ⁇ m to 80 ⁇ m.
  • the pore diameters of the functional pores can be 50 ⁇ m, 60 ⁇ m, 70 ⁇ m, or 80 ⁇ m.
  • laser drilling or laser-induced etching can be used to make functional holes. Due to the thermal effect of laser drilling, the inner wall of the functional hole has a large roughness, which will affect the sputtering and Weakening the bonding force between the membrane layer in the hole and the hole wall is not conducive to the preparation of a highly dense adhesion layer and a second seed layer in the hole.
  • the method of laser-induced etching may include: using a laser to irradiate a preset position on the base substrate 1 to modify the molecular bonds at the preset position, and then using an etching liquid to etch the preset position on the base substrate 1 Etch to form a through hole TGV, and/or use an etching process to etch a preset position of the base substrate 1 according to a preset aspect ratio to form a blind hole BGV as shown in Figure 23b, and the blind hole BGV
  • the hole bottom has a preset thickness from the other surface of the base substrate 1 , wherein the etching speed of the etching liquid at the preset position is greater than the etching speed at other positions of the base substrate 1 .
  • the etching solution can be a mixed solution of hydrofluoric acid and nitric acid, a mixed solution of sodium hydroxide and citric acid, etc.
  • etching liquid can be used to etch functional holes from both sides of the glass substrate toward the middle.
  • the opening area of the functional holes can gradually decrease from the two openings to the middle position.
  • the wet etching process can make the sidewalls of the functional holes smoother, thereby facilitating the bonding of the subsequent adhesion layer, the second seed layer and the sidewalls of the functional holes.
  • the aspect ratio of the functional hole can be 1.5 to 3.
  • the aspect ratio can be 1.5, 2.0, 2.5, 3.0, etc.
  • the base substrate 1 with a thickness of 0.3 mm can be etched with an aspect ratio of 5:1 to form a blind hole BGV.
  • the distance between the bottom of the blind hole BGV and the other side of the base substrate 1 is 50 ⁇ m, that is, the blind hole BGV. Leave a thickness of 50 ⁇ m at the bottom of the hole.
  • the opening area of the functional hole at each position in the thickness direction of the base substrate 1 may be the same.
  • the base substrate 1 can also be formed through a wet etching process.
  • a laser can be used to irradiate a preset position on the base substrate 1 to modify the molecular bonds at the preset position of the base substrate 1 so that the substrate The etching speed at the preset position of the substrate 1 will be greater than the etching speed at other positions of the base substrate 1 , and then the etching liquid is used to etch the preset position of the base substrate 1 to form functional holes.
  • etching liquid can be used to etch functional holes from one side of the glass substrate to the other side.
  • the opening area of the functional holes moves from one opening to the other opening. slowing shrieking.
  • etching liquid can also be used to etch functional holes from both sides of the base substrate 1 toward the middle.
  • the opening area of the functional holes can be from the two openings to the middle one. The position gradually decreases.
  • the blind via BGV can be as shown in Figures 23d to 23f and have the same cross-sectional structural features as shown in Figures 23a to 23c.
  • the substrate substrate 1 when it is necessary to form a three-dimensional inductor L, the substrate substrate 1 includes a first functional area A and a second functional area B.
  • the first functional area A forms the inductor L
  • the second functional area B forms the capacitor C. Because the heat dissipation pillar 10 in the first functional area A is to form part of the structure of the inductor L coil, in the first functional area A, the functional holes need to be set as through holes TGV, while in the second functional area B, the functional holes can be It is blind hole BGV or through hole TGV.
  • the formed functional holes may be as shown in Figure 23g, with the first functional area A and the second functional area B being through-hole TGVs, or as shown in Figure 23h, with the first functional area A being a through-hole TGV, and the second functional hole being a through-hole TGV.
  • the second functional area B is a blind hole BGV, and the opening of the blind hole BGV faces downward (that is, the opening is located on the side of the substrate 1 away from the first conductive layer 2 to be formed), or as shown in Figure 23i, the first The functional hole is a through hole TGV, the second functional hole is a blind hole BGV, and the opening of the blind hole BGV faces upward, that is, the opening is located on the side of the base substrate 1 close to the first conductive layer 2 to be formed.
  • the functional holes in the first functional area A and the second functional area B may have the structures shown in Figure 23b and/or Figure 23c.
  • the thermal conductivity of the heat dissipation pillar 10 is greater than the thermal conductivity of the base substrate 1 .
  • metal conductive materials have high thermal conductivity. Therefore, in this disclosure, metal conductive materials can be used to form the heat dissipation pillars 10, which are conductive pillars. Of course, other materials with high thermal conductivity can also be used to form the heat dissipation pillars 10 , and the present disclosure is not limited thereto.
  • the first material can be sputtered in the side wall of the functional hole to form an adhesion layer; the first seed material can be sputtered on the adhesion layer to form a second seed layer;
  • the heat dissipation material with a preset thickness is ejected to form the heat dissipation column 10 .
  • the first material may be Ti, and the first seed material may be copper.
  • a Ti adhesion layer is first formed on the inner wall of the functional hole through a sputtering process, and then a copper seed layer of a certain thickness is formed on the Ti adhesion layer, and then the functional hole is filled with double-sided Cu plating in a butterfly shape to form Copper heat dissipation pillar 10.
  • the thickness of the adhesion layer may be 5 nm to 30 nm.
  • the thickness of the adhesion layer may be 5 nm, 10 nm, 15 nm, 25 nm, 30 nm, etc.
  • the thickness of the second seed layer may be 30 nm-80 nm.
  • the thickness of the second seed layer may be 30 nm, 50 nm, 70 nm, 80 nm, etc.
  • the heat dissipation pillars 1011 can also be drilled, so that the heat dissipation pillars 10 form hollow heat dissipation pillars 10 .
  • the cavity of the hollow heat dissipation pillar 10 can also be filled with materials such as resin.
  • the thermal expansion coefficient of the material filled in the cavity can be between the thermal expansion coefficient of the heat dissipation pillar 10 and the thermal expansion coefficient of the substrate substrate 1 .
  • the heat dissipation pillars 10 can be formed in the functional holes by filling conductive materials, copper core solder balls, etc.
  • the formed heat dissipation pillar 10 may have the same cross-sectional shape as the functional hole, which will not be described in detail here.
  • FIGS. 24a to 24f are schematic structural diagrams of the heat dissipation pillars of the two-dimensional inductor L
  • FIGS. 24g to 24i are schematic structural diagrams of the heat dissipation pillars of the three-dimensional inductor L, which will not be described in detail here.
  • the first conductive layer 2 is then planarized. As shown in Figure 25a, the thickness of the first conductive material may be greater than or equal to 3 ⁇ m.
  • the first conductive line 21 is formed on the first conductive layer 2 through a patterning process. Part of the structure of the first conductive line 21 is used to form the first electrode (lower surface electrode) of the capacitor C, and part of the structure forms the first transfer line 22.
  • An adapter wire 22 connects the first end of the inductor L and the first electrode of the capacitor C.
  • the flatness of the first conductive line 21 can be improved, and the uniformity of the capacitance C can be improved. It can be understood that when forming the three-dimensional inductor L, a plurality of first sub-transition lines 221 can be formed in the first functional area A, and the first sub-transmission wires 221 form part of the structure of the three-dimensional inductor L coil.
  • the first conductive layer 2 is insulated from at least part of the heat dissipation pillars 10, so that the heat dissipation pillars 10 serve as the heat dissipation structure of the filter.
  • the heat dissipation pillar 10 and the first conductive layer 2 may also be electrically isolated according to the type of functional holes.
  • a first insulating material can be deposited on the entire surface of the base substrate 1 to form a first insulating layer 100, so that the heat dissipation pillar can be exposed to the heat dissipation pillar through the first insulating layer 100.
  • 10 and the first conductive layer 2 are electrically isolated, so that the introduced heat dissipation pillar 10 will not affect the performance of the filter while improving the heat dissipation performance of the filter.
  • the functional hole has a blind hole structure as shown in Figures 25d to 25f
  • there is no need to form an additional insulating layer and the insulating material pair left between the other side of the substrate 1 and the hole bottom 101 of the blind hole BGV can be used.
  • the heat dissipation pillar 10 and the first conductive layer 2 are electrically isolated.
  • the functional hole in the first functional area A is a through hole TGV
  • the functional hole in the second functional area B can have a structure as shown in Figures 25d to 23f.
  • the first first conductive layer 2 can be deposited on the side of the substrate 1 facing the first conductive layer 2
  • the insulating material forms a first insulating layer 100 covering the second functional area B, so as to form electrical isolation between the first conductive layer 2 and the heat dissipation pillar 10 through the first insulating layer 100 .
  • the heat dissipation pillar 10 and the first conductive layer can be connected to each other through the insulating material left at the bottom of the blind hole BGV and the other side of the base substrate 1.
  • Layer 2 provides electrical isolation.
  • a first conductive material of a predetermined thickness may be deposited on the first insulating layer 100 to form the first conductive material. material layer, and then perform a patterning process on the material layer of the first conductive layer 2 to obtain the first conductive layer 2 .
  • FIGS. 25a to 25c are schematic structural diagrams of the two-dimensional inductor L with the first conductive layer
  • FIGS. 25d to 25f are schematic structural diagrams of the three-dimensional inductor L with the first conductive layer
  • the functional holes may have The structural features of the above embodiments are only exemplified here by taking the functional structure shown in Figure 23a as an example, and will not be described in detail here.
  • a deposition process may be used to deposit a second insulating material on the side of the first conductive layer 2 facing away from the base substrate 1 to form a third insulating layer PI1, and then a patterning process may be used to process the third insulating layer PI1 to form openings to expose the third insulating layer PI1.
  • a partial structure of the conductive layer 2 and then use a sputtering process to deposit a first seed material at the opening to form a third seed layer, and finally use an electroplating process to electroplate a preset thickness of the first conductive material on the third seed layer to form a third seed layer.
  • the second insulating material may be BL-301 or the like.
  • the third insulating layer PI1 entirely covers the first conductive layer 2, and then the photolithography process can be used to expose, develop, and post-bake the areas of the capacitor C and the inductor L to form openings on the third insulating layer PI1 to expose the first conductive layer 2 respectively.
  • the first seed material may be copper, for example.
  • the second conductive layer 3 is produced by first sputtering the Cu seed layer and then electroplating thick Cu. Part of the second conductive layer 3 is a trace forming the inductor L, and part is the second electrode (upper electrode) of the capacitor C. In order to reduce the loss of the inductor L, the thickness of the second conductive layer 3 may be greater than or equal to 5 ⁇ m.
  • second conductive lines 32 and third conductive lines 33 can be formed on the second conductive layer 3 through a patterning process.
  • the second conductive lines 32 correspond to the first conductive lines 21.
  • the second conductive line 32 corresponds to the first conductive line 21.
  • the orthographic projection of the conductive line 32 on the base substrate 1 is located on the orthographic projection of the first conductive line 21 on the base substrate 1 .
  • the second conductive line 32 is used to form the second electrode of the capacitor C.
  • the third conductive line 33 is located on one side of the second conductive line 32 and corresponds to the first adapter line 22 .
  • the third conductive line 33 is used to form part of the structure of the inductor L coil.
  • the third conductor 33 located in the first functional area A includes a plurality of third sub-conductive parts 331, and the third sub-conductive parts 331 and the first sub-transfer line 221 are arranged in one-to-one correspondence, and the orthographic projection of the third sub-conductive part 331 on the base substrate 1 can be located on the orthographic projection of the first sub-transfer line 221 on the base substrate 1, and the third sub-conductive part 331 can be connected thereto through a via hole.
  • the corresponding first sub-transfer line 221 is equivalent to the third conductive line 33 and the second sub-conductive line 212 forming a parallel structure.
  • the orthographic projection of the second conductive line 32 on the base substrate 1 may be located within the orthographic projection of the second sub-conductive line 212 on the base substrate 1 , so that the second conductive line 32 and the second sub-conductive line 212 are arranged facing each other one by one. , forming two facing electrodes of capacitor C.
  • the adapter portion 34 can also be formed on the second conductive layer 3 .
  • the adapter portion 34 is located on the side of the second conductive line 32 away from the third sub-conductive portion 331 and is provided corresponding to the third sub-conductive line 213 .
  • a plasma enhanced chemical vapor deposition process may also be used to deposit a preset thickness of the first insulating material on the first conductive layer 2.
  • the first insulating material may be SiNx, and the thickness of the first dielectric layer 210 may be determined according to the relative dielectric constant of the capacitance C and the value of the capacitance C.
  • a 120nm thick SiNx film with high flatness can be deposited to serve as the dielectric layer of the capacitor C structure to ensure the uniformity of the capacitor C.
  • the first seed material can be copper, for example.
  • a 100 nm thick Cu film can be deposited on the SiNx dielectric layer by magnetron sputtering as the upper electrode pad of the capacitor C and the first seed layer 220 to generate the second electrode of the capacitor C.
  • a deposition process can be used to deposit a second insulating material on the first conductive layer 2 and the first seed layer 220 to form a third insulating layer PI1; a patterning process can be used to process the third insulating layer PI1 Form an opening to expose part of the first conductive layer 2 and part of the first seed layer 220; use a sputtering process to deposit the first seed material at the opening to form a third seed layer; use an electroplating process to deposit the first seed material on the third seed layer
  • the first conductive material with a predetermined thickness is electroplated to form the second conductive layer 3 .
  • the second insulating material may be BL-301, etc.
  • the third insulating layer PI1 entirely covers the second conductive layer 3, and a photolithography process is used to expose, develop, and post-bake the areas of the capacitor C and the inductor L.
  • An opening is formed in the third insulating layer PI1 to expose part of the structure of the second conductive line 32 and the third conductive line 33 and part of the first connection part.
  • the thickness of the second conductive layer 3 can be greater than or equal to 5 ⁇ m to increase the value of the inductor L and reduce the loss of the inductor L.
  • the first insulating material can be deposited to form a third Three insulating layers PI1.
  • the third insulating layer PI1 partially covers the first seed layer 220, so that the first seed layer 220 is retracted within the third insulating layer PI1 to isolate the second electrode of the capacitor C through the third insulating layer PI1. Electrical connection to the first electrode.
  • the structure of the second conductive layer 3 formed can be as shown in Figures 26d to 26f. It can be understood that the structures shown in Figures 26d to 24f are only the structures of the formed functional holes. The difference is that the preparation process after forming the functional holes can be the same.
  • a third conductive layer 4 and a tin ball layer can also be formed on the side of the second conductive layer 3 facing away from the base substrate 1. 5.
  • a second insulating material can be deposited on the second conductive layer 3 to form a fourth insulating layer PI2; and then a patterning process is used to process the fourth insulating layer PI2 to form openings to expose the first conductive line 21.
  • the fourth conductive line 44 can be formed on the third conductive layer 4 through a patterning process.
  • the fourth conductive line 44 is provided correspondingly to the third conductive line 33.
  • the fourth conductive line 44 is used to form The partial structure of the inductor L coil and the structural features of the third conductive wire 33 and the fourth conductive wire 44 can be referred to the introduction of the above embodiment, and will not be described again here.
  • a second insulating material can be deposited on the third conductive layer 4 to form a fifth insulating layer PI3; and then a patterning process is used to form the fifth insulating layer PI3.
  • Three openings are formed on the fifth insulating layer PI3 at positions corresponding to the fourth conductive lines 44 to respectively expose part of the structure of the fourth conductive line 44, part of the structure of the second connection part 42, and part of the structure of the third connection part 43; Then implant solder balls in the three openings to form the signal input terminal IN, the signal output terminal OUT and the ground terminal of the filter.
  • a sputtering process can be used on the side of the substrate 1 away from the first conductive layer 2
  • the first seed material is sputtered in the first functional area A to form a fifth seed layer; then a preset thickness of the first conductive material is electroplated on the fifth seed layer using an electroplating process to form the fifth conductive layer 6; and then a patterning process is used
  • the fifth conductive layer 6 is processed to form a plurality of fifth conductive lines 71.
  • the fifth conductive lines 71 are used to form part of the structure of the inductor L coil.
  • the fifth conductive lines are connected to the first conductive pillars and the second conductive pillars in the same row. between the columns.
  • a third insulating material is deposited on the side of the fifth conductive layer 6 facing away from the base substrate 1 to form the lower surface insulating layer 80 .
  • the third insulating material may be, for example, polyimide or acrylic.

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Abstract

本公开提供一种滤波器及其制作方法、电子设备。该滤波器包括电感L和电容C，电容C的第一电极连接电感L的第一端，滤波器还包括：衬底基板(1)，散热柱(10)，第一导电层(2)和第二导电层(3)，衬底基板(1)具有阵列分布的多个功能孔；多个散热柱(10)与功能孔对应设置，散热柱(10)填充于与其对应的功能孔内；第一导电层(2)位于衬底基板(1)的一侧，第一导电层(2)包括：第一导电线(21)和第一转接线(22)，第一导电线(21)的部分结构用于形成电容C的第一电极；第一转接线(22)连接于第一导电线(21)的一侧；第二导电层(3)位于第一导电层(2)背离衬底基板(1)的一侧，第二导电层(3)包括：第二导电线(32)和第三导电线(33)，第二导电线(32)与第一导电线(21)对应设置，第二导电线(32)在衬底基板(1)的正投影位于第一导电线(21)在衬底基板(1)的正投影上，第二导电线(32)用于形成电容C的第二电极；第三导电线(33)位于第二导电线(32)的一侧且与第一转接线(22)对应设置，第三导电线(33)通过过孔连接第一转接线(22)，第三导电线(33)用于形成电感L线圈的部分结构；其中，至少部分散热柱(10)与第一导电层(2)绝缘设置，且散热柱(10)的热传导率大于衬底基板(1)的热传导率。

Description

滤波器及其制作方法、电子设备 技术领域
本公开涉及电子技术领域，具体而言，涉及一种滤波器及其制作方法、电子设备。
背景技术
随着器件尺寸的不断缩小，集成度越来越高，器件的功耗可能会大幅提高，而散热却因集成度的提高而无法有效的降低，如果不能有效地快速地将热量从器件中散出，将直接导致器件因高温而失效，从而严重影响器件的性能和可靠性。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种滤波器及其制作方法、电子设备。
根据本公开的一个方面，提供一种滤波器，包括电感和电容，所述电容的第一电极连接所述电感的第一端，所述滤波器还包括：衬底基板，所述衬底基板具有至少一个功能孔；至少一个散热柱，所述散热柱与所述功能孔对应设置，所述散热柱填充于与其对应的所述功能孔内；第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：第一导电线，所述第一导电线的部分结构用于形成所述电容的第一电极；第一转接线，所述第一转接线连接于所述第一导电线的一侧；第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：第二导电线，与所述第一导电线对应设置，所述第二导电线在所述衬底基板的正投影位于所述第一导电线在所述衬底基板的正投影上，所述第二导电线用于形成所述电容的第二电极；第三导电线，位于所述第二导电线的一侧且与所述第一转接线对应设置，所述第三导电线通过过孔连接所述第 一转接线，所述第三导电线用于形成所述电感线圈的部分结构；其中，至少部分散热柱与所述第一导电层绝缘设置，且所述散热柱的热传导率大于所述衬底基板的热传导率。
在本公开的示例性实施例中，所述功能孔各个位置的开孔面积相同；或者，所述功能孔的开孔面积自所述衬底基板的一侧向所述衬底基板的另一侧逐渐减小；或者，所述功能孔的开孔面积自所述衬底基板两侧向中间一位置逐渐减小。
在本公开的示例性实施例中，所述功能孔沿所述衬底基板的厚度方向的长度与所述功能孔的孔径之比大于等于5且小于等于7。
在本公开的示例性实施例中，所述散热柱为空心散热柱，所述散热柱的空腔的延伸方向和所述散热柱的延伸方向相同。
在本公开的示例性实施例中，所述散热柱为实心散热柱。
在本公开的示例性实施例中，所述散热柱为导电柱。
在本公开的示例性实施例中，所述滤波器还包括：第一介质层，位于所述第一导电层和所述第二导电层之间，所述第一介质层与所述第二导电线对应设置，且所述第一介质层在所述衬底基板的正投影覆盖所述第二导电线在所述衬底基板的正投影；第一种子层，位于所述第一介质层和所述第二导电层之间，所述第一种子层用于作为生成所述第二导电层的种子层。
在本公开的示例性实施例中，所述滤波器还包括：第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：第四导电线，所述第四导电线与所述第三导电线对应设置，所述第四导电线用于形成所述电感线圈的部分结构；其中，所述第三导电线、所述第四导电线弯折设置，所述第三导电线在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影围成绕线区；且所述第三导电线的第一端通过过孔连接所述第四导电线的第一端，所述第三导电线的第二端通过过孔连接所述第一转接线，所述第三导电线的第一端至第二端的延伸方向与所述第四导电线的第一端至第二端的延伸方向相同。在本公开的示例性实施例中，所述第二导电层的厚度、所述第三导电层的厚度均大于所述第一导电层的厚度。
在本公开的示例性实施例中，所述第二导电层的厚度与所述第一导电层的厚度之比、所述第三导电层的厚度与所述第一导电层的厚度之比大于等于1.5且小于等于3。
在本公开的示例性实施例中，所述第二导电层还包括：第一连接部，位于所述第二导电线和所述第三导电线之间且与所述第一导电线对应设置，所述第一连接部通过过孔连接所述第一导电线；所述第三导电层还包括：第二连接部，所述第二连接部与所述第二导电线对应设置，所述第二连接部在所述衬底基板的正投影与所述第二导电线在所述衬底基板的正投影至少部分交叠，且所述第二连接部通过过孔连接所述第二导电线；第三连接部，所述第三连接部与所述第一连接部对应设置，所述第三连接部在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影至少部分交叠，且所述第三连接部通过过孔连接所述第一连接部；所述滤波器还包括：锡球层，位于所述第三导电层背离所述衬底基板的一侧，所述锡球层包括：第一锡球，在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影相交叠，所述第一锡球通过过孔连接所述第四导电线的一个端部；第二锡球，在所述衬底基板的正投影与所述第三连接部在所述衬底基板的正投影相交叠，所述第二锡球通过过孔连接所述第三连接部；第三锡球，在所述衬底基板的正投影与所述第二连接部在所述衬底基板的正投影相交叠，所述第三锡球通过过孔连接所述第二连接部。
在本公开的示例性实施例中，所述功能孔为盲孔，且所述盲孔的孔口位于所述衬底基板远离所述第一导电层的一侧。
在本公开的示例性实施例中，所述功能孔为通孔，或所述功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；所述滤波器还包括：第一绝缘层，所述第一绝缘层在朝向所述第一导电层的一侧覆盖所述衬底基板。
在本公开的示例性实施例中，所述衬底基板包括第一功能区和第二功能区，所述第一转接线在所述衬底基板的正投影位于所述第一功能区，所述第一导电线在所述衬底基板的正投影位于所述第二功能区，所述第一功能区和所述第二功能区均包括所述功能孔，且所述第一功能区中的 功能孔为通孔；位于所述第一功能区的所述多个散热柱包括多个第一导电柱和多个第二导电柱，多个所述第一导电柱和多个所述第二导电柱分别沿同一方向间隔排布，且所述第一导电柱和所述第二导电柱并排设置，所述第一导电柱、所述第二导电柱用于形成所述电感线圈的部分结构；所述滤波器还包括：第五导电层，位于所述衬底基板背离所述第一导电层的一侧，所述通孔位于所述第五导电层在所述衬底基板的正投影对应的区域内，所述第五导电层包括：多条第五导电线，所述第五导电线连接于同一排的所述第一导电柱和所述第二导电柱之间；其中，所述第一转接线包括多个第一子转接线，所述第一子转接线用于形成所述电感线圈的部分结构，所述第一子转接线连接于相邻排的第一导电柱和第二导电柱之间，且每一散热柱连接一条所述第一子转接线。
在本公开的示例性实施例中，所述第三导电线包括多个第三子导电部，所述第三子导电部与所述第一子转接线对应设置，所述第三子导电部通过过孔连接与其对应的所述第一子转接线；所述第二导电层还包括：所述第一导电线包括依次连接的第一子导电线、第二子导电线和第三子导电线，所述第二子导电线用于形成所述电容的第一电极，所述第一子导电线与所述第一子转接线对应设置，所述第一子导电线连接于所述第一子导电线和与所述第二子导电线对应的第一子转接线之间；所述滤波器还包括：锡球层，位于所述第三导电层背离所述衬底基板的一侧，所述锡球层包括：第一锡球，在所述衬底基板的正投影与所述第三子导电部在所述衬底基板的正投影相交叠，所述第一锡球通过过孔连接所述第三子导电部的一个端部；第二锡球，在所述衬底基板的正投影与所述第三子导电线在所述衬底基板的正投影相交叠，所述第二锡球通过过孔连接所述第三子导电线；第三锡球，在所述衬底基板的正投影与所述第二导电线在所述衬底基板的正投影相交叠，所述第三锡球通过过孔连接所述第二导电线。
在本公开的示例性实施例中，所述第一功能区中功能孔的孔径大于所述第二功能区中功能孔的孔径。
在本公开的示例性实施例中，位于第一功能区的通孔的孔径与位于第二功能区的功能孔的孔径之比大于等于1.5小于等于2.5。
在本公开的示例性实施例中，所述第一子转接线在所述衬底基板的正投影覆盖与其连接的第一导电柱、第二导电线在所述衬底基板的正投影；所述第五导电线在所述衬底基板的正投影覆盖与其连接的第一导电柱、第二导电线在所述衬底基板的正投影。
在本公开的示例性实施例中，所述第二功能区中的功能孔为盲孔，且所述盲孔的孔口位于所述衬底基板远离所述第一导电层的一侧。
在本公开的示例性实施例中，所述第二功能区的功能孔为通孔，或所述第二功能区的功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；所述滤波器还包括：第一绝缘层，所述第一绝缘层在朝向所述第一导电层的一侧覆盖所述衬底基板的第二功能区。
在本公开的示例性实施例中，所述第五导电层的厚度、所述第二导电层的厚度均大于所述第一导电层的厚度。
在本公开的示例性实施例中，所述第五导电层的厚度与所述第一导电层的厚度之比、所述第二导电层与所述第一导电层的厚度之比大于等于1.5且小于等于3。
在本公开的示例性实施例中，所述第二导电层的厚度大于等于5μm，所述第一导电层的厚度大于等于3μm；所述第三导电层或所述第五导电层的厚度大于等于5μm。
在本公开的示例性实施例中，所述散热柱的材料为铜。
在本公开的示例性实施例中，所述衬底基板为玻璃基板或硅基板。
根据本公开的第二方面，还提供一种滤波器制作方法，所述滤波器包括电感和电容，所述电容的第一电极连接所述电感的第一端，所述制作方法包括：提供一衬底基板；在所述衬底基板上形成多个功能孔；在所述功能孔内形成散热柱；在所述衬底基板的一侧面形成第一导电层，所述第一导电层至少与部分所述散热柱绝缘设置，所述第一导电层包括第一导电线和第一转接线，所述第一导电线的部分结构用于形成所述电容的第一电极，所述第一转接线连接于所述第一导电线的一侧；在所述第一导电层背离所述衬底基板的一侧形成第二导电层，所述第二导电层包括第二导电线和第三导电线，所述第二导电线与所述第一导电线对应设置，所述第二导电线在所述衬底基板的正投影位于所述第一导电线在 所述衬底基板的正投影上，所述第二导电线用于形成所述电容的第二电极；所述第三导电线位于所述第二导电线的一侧且与所述第一转接线对应设置，所述第三导电线通过过孔连接所述第一转接线，所述第三导电线用于形成所述电感线圈的部分结构。
在本公开的示例性实施例中，所述在所述衬底基板上形成多个功能孔，包括：利用激光照射所述衬底基板上的预设位置，以对所述预设位置的分子键进行改性；利用刻蚀液对所述衬底基板的预设位置进行刻蚀以形成通孔，和/或，利用刻蚀工艺根据预设深宽比对所述衬底基板的预设位置进行刻蚀以形成盲孔，且所述盲孔的孔底距离所述衬底基板的另一表面具有预设厚度，其中，刻蚀液对所述预设位置的刻蚀速度大于对所述衬底基板其他位置的刻蚀速度。
在本公开的示例性实施例中，所述在所述功能孔内形成散热柱，包括：在所述功能孔的侧壁内溅射第一材料形成粘附层；在所述粘附层上溅射第一种子材料形成第二种子层；在所述第二种子层上溅射预设厚度的散热材料，形成散热柱。
在本公开的示例性实施例中，所述功能孔为通孔，或者，所述功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；所述在所述衬底基板的一侧面形成第一导电层之前，所述方法还包括：在所述衬底基板上整面沉积第一绝缘材料形成第一绝缘层。
在本公开的示例性实施例中，所述在所述衬底基板的一侧面形成第一导电层，包括：利用加成法在所述第一绝缘层上沉积预设厚度的第一导电材料，形成第一导电材料层；利用构图工艺将所述第一导电材料层形成第一导电层；对所述第一导电层进行平坦化处理。
在本公开的示例性实施例中，所述在第一导电层背离所述衬底基板的一侧形成第二导电层之前，所述方法包括：利用等离子体增强化学气相沉积工艺在所述第一导电层上沉积预设厚度的第一绝缘材料，形成第一介质层；利用磁控溅射工艺在所述第一介质层上沉积预设厚度的第一种子材料，形成第一种子层；所述在第一导电层背离所述衬底基板的一侧形成第二导电层，包括：利用沉积工艺在所述第一导电层和所述第一种子层上沉积第二绝缘材料，形成第三绝缘层；利用构图工艺将对所述 第三绝缘层进行处理形成开孔，以露出所述第一导电层的部分结构以及露出所述第一种子层的部分结构；利用溅射工艺在所述开孔处沉积第一种子材料，形成第三种子层；利用电镀工艺在所述第三种子层上电镀预设厚度的第一导电材料形成第二导电层。
在本公开的示例性实施例中，所述滤波器还包括第三导电层，在所述第一导电层背离所述衬底基板的一侧形成第二导电层之后，所述方法还包括：在所述第二导电层上沉积第二绝缘材料形成第四绝缘层；利用构图工艺对所述第四绝缘层进行处理形成开孔，以露出位于所述第一导电线上的部分所述第二导电层；利用溅射工艺在位于所述第三导电线上的第四绝缘层处以及所述开孔处溅射第一种子材料，形成第四种子层；利用电镀工艺在所述第四种子层上电镀预设厚度的第一导电材料，形成第三导电层，所述第三导电层包括第四导电线，所述第四导电线与所述第三导电线对应设置，所述第四导电线在所述衬底基板的正投影与所述第三导电线在所述衬底基板的正投影至少部分交叠，所述第四导电线用于形成所述电感线圈的部分结构，所述第三导电线、所述第四导电线弯折设置，所述第三导电线在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影围成绕线区，所述第三导电线的第一端通过过孔连接所述第四导电线，所述第三导电线的第二端通过过孔连接所述第一转接线，所述第三导电线的第一端至第二端的延伸方向与所述第四导电线的第一端至第二端的延伸方向相同。
在本公开的示例性实施例中，在形成所述第三导电层之后，所述方法还包括：在所述第三导电层上沉积第二绝缘材料形成第五绝缘层；利用构图工艺在所述第五绝缘层上对应所述第四导电线的位置形成三个开孔，以分别露出部分所述第四导电线的部分结构；在三个所述开孔处分别植入锡球，形成所述滤波器的信号输入端、信号输出端和接地端。
在本公开的示例性实施例中，所述衬底基板包括第一功能区和第二功能区，所述第一转接线在所述衬底基板的正投影位于所述第一功能区，所述第一导电线在所述衬底基板的正投影位于所述第二功能区，所述第一功能区、所述第二功能区的功能孔均为通孔；所述多个散热柱包括多个第一导电柱和多个第二导电柱，多个所述第一导电柱和多个所述第二 导电柱分别沿同一方向间隔排布，且所述第一导电柱和所述第二导电柱并排设置，所述第一导电柱、所述第二导电柱用于形成所述电感线圈的部分结构；在所述衬底基板的一侧面形成第一导电层之前，所述方法还包括：利用沉积工艺在所述衬底基板的第二功能区沉积第一绝缘材料形成第一绝缘层；所述在所述衬底基板的一侧面形成第一导电层，包括：利用加成法在所述第一绝缘层上以及所述衬底基板的第一功能区沉积预设厚度的第一导电材料，形成第一导电材料层；利用构图工艺将所述第一导电材料层形成第一导电层；对所述第一导电层进行平坦化处理。
在本公开的示例性实施例中，所述滤波器还包括第五导电层，所述方法还包括：利用溅射工艺在所述衬底基板背离所述第一导电层一侧的第一功能区溅射第一种子材料，形成第五种子层；利用电镀工艺在所述第五种子层上电镀预设厚度的第一导电材料，形成第五导电层；利用构图工艺对所述第五导电层进行处理，形成多个第一子转接线，所述第一子转接线用于形成所述电感线圈的部分结构，所述第一子转接线连接于相邻排的第一导电柱和第二导电柱之间，且每一散热柱连接一条所述第一子转接线。
根据本公开的第三方面，还提供一种电子设备，包括本公开任意实施例所述的滤波器。
本公开提供的滤波器，通过在衬底基板上形成功能孔，并在功能孔内填充热传导率较高的散热柱，通过将至少部分的散热柱设置为与第一导电层绝缘，从而可以通过这些散热柱来提高衬底基板的散热性能，进而提高滤波器的整体散热性。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他 的附图。
图1为根据本公开一种实施方式的滤波器的等效电路图；
图2为根据本公开一种实施方式的滤波器的结构版图；
图3为图2中衬底基板的版图结构；
图4为图2中第一导电层的版图结构；
图5为图2中第二导电层的版图结构；
图6为图2中第三导电层的版图结构；
图7为图2中锡球层的版图结构；
图8为图2中第一导电层和第二导电层的叠层版图结构；
图9为图2中第二导电层和第三导电层的叠层版图结构；
图10为图2中第一导电层、第一介质层和第一种子层的叠层版图结构；
图11为图2中沿虚线MM的部分剖视图；
图12a为根据本公开一种实施方式的衬底基板的剖视图；
图12b为根据本公开另一种实施方式的衬底基板的剖视图；
图13a为根据本公开一种实施方式的第一转接线、第三导电线和第四导电线的弯折示意图；
图13b为根据本公开另一种实施方式的第一转接线、第三导电线和第四导电线的弯折示意图；
图14为根据本公开另一种实施方式的滤波器的结构版图；
图15为图14中衬底基板的版图结构；
图16为图14中第一导电层的版图结构；
图17为图14中第二导电层的版图结构；
图18为图14中锡球层的版图结构；
图19为图14中第五导电层的版图结构；
图20为图14中沿虚线NN的剖视图；
图21a为根据本公开一种实施方式的衬底基板的剖视图；
图21b为根据本公开另一种实施方式的衬底基板的剖视图；
图22～图27f为根据本公开另一种实施方式的滤波器制作方法的工艺流程图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
本示例性实施例提供一种滤波器，图1为根据本公开一种实施方式的滤波器的等效电路图，如图1所示，该滤波器可以包括电容C、电感L和电阻R。电感L的第一端连接电容C的第一电极，第二端通过电阻R连接信号输入端IN；电容C的第二电极连接接地端GND，电感L的第二端和电容C的第一电极连接信号输出端OUT。
本公开提供的滤波器可以包括衬底基板、散热柱、第一导电层和第二导电层，衬底基板具有至少一个功能孔；散热柱与功能孔对应设置，散热柱填充于与其对应的功能孔内；第一导电层位于衬底基板的一侧，第一导电层可以包括第一导电线、第一转接线，第一导电线的部分结构用于形成电容C的第一电极；第一转接线连接于第一导电线的一侧，第一转接线的部分结构用于形成电感L的部分线圈结构；第二导电层位于第一导电层背离衬底基板的一侧，第二导电层可以包括第二导电线和第三导电线，第二导电线与第一导电线对应设置，第二导电线在衬底基板的正投影位于第一导电线在衬底基板的正投影上，第二导电线用于形成电容C的第二电极；第三导电线位于第二导电线的一侧且与第一转接线对应设置，第三导电线通过过孔连接第一转接线，第三导电线用于形成电感L的部分线圈结构；其中，至少部分散热柱与第一导电层绝缘设置，且散热柱的热传导率大于衬底基板的热传导率。
本公开提供的滤波器，通过在衬底基板上形成功能孔，并在功能孔内填充热传导率较高的散热柱，通过将至少部分的散热柱设置为与第一导电层绝缘，从而可以通过这些散热柱来提高衬底基板的散热性能，进而提高滤波器的整体散热性。
本公开提供的滤波器中，电感L可以为三维电感L或者可以为二维电 感L。三维电感L是利用散热柱的导电性，散热柱形成电感L线圈的部分结构。二维电感L则是完全利用导电层的走线形成电感L的线圈结构，散热柱仅形成滤波器的散热结构。考虑到三维电感L和二维电感L的结构版图具有一定的差异，下面结合附图分别对具有三维电感L的滤波器结构和具有二维电感L的滤波器结构进行分别说明。
在示例性实施例中，具有二维电感L的滤波器可以包括衬底基板以及在衬底基板一侧依次层叠设置的第一导电层、第二导电层、第三导电层、锡球层。
如图2-12所示，图2为根据本公开一种实施方式的滤波器的结构版图，图3为图2中衬底基板的版图结构，图4为图2中第一导电层的版图结构，图5为图2中第二导电层的版图结构，图6为图2中第三导电层的版图结构，图7为图2中锡球层的版图结构，图8为图2中第一导电层和第二导电层的叠层版图结构，图9为图2中第二导电层和第三导电层的叠层版图结构，图10为图2中第一导电层、第一介质层和第一种子层的叠层版图结构，图11为图2中沿虚线MM的部分剖视图。
在示例性实施例中，第一方向X可以为图中所示的行方向X，第二方向Y可以为图中所示的列方向Y，第一方向X与第二方向Y相交。
在示例性实施例中，如图2、图3所示，衬底基板1可以为玻璃基板或者硅基板。衬底基板1包括多个阵列分布的功能孔，每个功能孔内填充有散热柱10，散热柱10的热传导率大于衬底基板1的热传导率，并且将至少部分散热柱10与第一导电层2绝缘设置，从而与第一导电层2绝缘设置的散热柱10可以形成滤波器的散热结构，提高滤波器的散热效果。通常，金属导电材料具有较高的热传导率，因此，本示例性实施例中的散热柱10可以由金属导电材料形成，例如可以由铜材料形成的铜导电柱作为散热柱10。应该理解的是，此处仅为示例性说明，不应理解为对本公开散热柱10材料的限定。任何其他具有比衬底基板1的热传导率高的材料均可以形成本公开所述的散热柱10。本公开所述的散热柱10可以为空心散热柱10，并且散热柱10的空腔的延伸方向和散热柱10的延伸方向相同。散热柱10还可以为实心散热柱10，实心散热柱10可以具有更好的散热效果。
功能孔可以为通孔TGV或盲孔BGV，通孔TGV即为贯穿衬底基板1的相对的两个面的孔，在由二维电感L组成的滤波器结构中，散热柱10仅作为散热结构，因此需要将填充于通孔TGV内的散热柱10与第一导电层2进行电气隔离，相应地，滤波器还可以包括第一绝缘层100，该第一绝缘层100可以通过整面沉积的工艺得到，即通过在衬底基板1朝向第一导电层2的一侧整面沉积第一绝缘材料得到第一绝缘层100，第一绝缘材料例如可以为SiNx等。
图12a为根据本公开一种实施方式的衬底基板的剖视图，图12b为根据本公开另一种实施方式的衬底基板的剖视图，如图12a、图12b所示，盲孔BGV即为仅贯穿衬底基板1的一个面，而不贯穿另一个面的孔。换言之，盲孔BGV具有孔口和孔底，孔口位于衬底基板1的一个面上，自孔口所在的面沿衬底基板的厚度方向向衬底基板的另一个面延伸，并距离衬底基板的另一个面一定距离形成盲孔BGV的孔底。当功能孔为盲孔BGV时，可以如图12a所示将功能孔的孔底朝向第一导电层2，即孔口位于衬底基板远离第一导电层的一侧，以通过衬底基板1保留的厚度来实现散热柱10与第一导电层2之间的电气隔离。当然，也可以如图12b所示将盲孔BGV的孔底背离第一导电层2设置，即盲孔BGV的孔口位于衬底基板靠近第一导电层的一侧，此时可以在衬底基板1朝向第一导电层2的一侧整面沉积第一绝缘材料形成第一绝缘层100，通过第一绝缘层100来实现第一导电层2与散热柱10的电气隔离。
可以理解的是，当盲孔BGV的孔口位于衬底基板远离第一导电层的一侧时，盲孔BGV的孔底孔底与该结构之间具有一定的厚度距离，该厚度距离即为盲孔BGV位置的衬底基板1的所剩余厚度。
此外，可以理解的是，衬底基板1中功能孔的分布密度不同会影响滤波器的散热性，当功能孔的分布密度较高时，相当于单位面积内具有的散热柱10更多，因此通过提高功能孔的分布密度可以提升对滤波器的散热性能。
在示例性实施例中，如图2、图4所示，第一导电层2可以包括第一转接线22和第一导电线21，第一导电线21在衬底基板1的正投影可以沿第一方向X延伸，第一导电线21的部分结构可以用于形成电容C 的第一电极。第一转接线22连接于第一导电线21的一端，第一转接线22可通过过孔连接第二导电层3中的第三导电线33(用于形成电感L线圈的部分结构)，从而通过第一转接线22与第一导电线21的连接，实现了电感L的第一端连接电容C的第一电极。
在示例性实施例中，如图2、图5所示，第二导电层3可以包括第二导电线32和第三导电线33，第二导电线32在衬底基板1的正投影可以位于第一导电线21在衬底基板1的正投影上，例如，第二导电线32在衬底基板1的正投影位于第一导电线21在衬底基板1的正投影内，第二导电线32与第一导电线21正对设置，形成电容C的两个电极。第三导电线33可以进行弯折设置，形成电感L线圈的部分结构，如上所述，第三导电线33可以通过过孔(图5、图8中的加黑位置D2)连接第一导电层2中的第一转接线22。第二导电层3还可以包括第一连接部31，第一连接部31位于第二导电线32和第三导电线33之间且与第一导电线21对应设置，例如第一连接部31在衬底基板1的正投影可以位于第一导电线21在衬底基板1的正投影上。如图11所示，第一连接部31可通过过孔连接第一导电线21，以使得第一连接部31与电感L的第一端和电容C的第一电极相连接，第一连接部31再通过过孔连接位于第三导电层4的第三连接部43、锡球层5的第二锡球2，形成图1中的信号输出端OUT。
在示例性实施例中，如图2、图6所示，第三导电层4可以包括第四导电线44，第四导电线44与第三导电线33对应设置，第四导电线44在衬底基板1的正投影与第三导电线33在衬底基板1的正投影可以部分交叠，第四导电线44可用于形成电感L线圈的部分结构。第四导电线44可以通过过孔(图6、图9中的加黑位置D1)连接第三导电线33。第三导电层4还可以包括第二连接部42和第三连接部43，第二连接部42与第二导电层3中的第二导电线32对应设置，第二连接部42在衬底基板1的正投影可以与第二导电线32在衬底基板1的正投影部分交叠。如图11所示，第二连接部42可通过过孔连接第二导电线32，以将电容C的第二电极引出后通过锡球层5的第三锡球3连接接地端GND。第三连接部43与第一连接部31对应设置，第三连接部43在衬底基板1的正 投影可以与第一连接部31在衬底基板1的正投影部分交叠。如图11所示，第三连接部43可通过过孔连接第一连接部31，如上所述，由第三连接部43与对应位置的第二锡球2连接后形成图1中的信号输出端OUT。
在示例性实施例中，如图2、图7所示，锡球层5可以包括第一锡球1、第二锡球2和第三锡球3，第一锡球1在衬底基板1的正投影可以与第四导电线44在衬底基板1的正投影部分交叠，第一锡球1可以通过过孔连接第四导电线44的一个端部，以形成图1中的信号输入端IN。第二锡球2在衬底基板1的正投影可以与第三连接部43在衬底基板1的正投影相交叠，第二锡球2可以通过过孔连接第三连接部43，形成图1中的信号输出端OUT。第三锡球3在衬底基板1的正投影可以与第二连接部42在衬底基板1的正投影部分交叠，第三锡球3可通过过孔连接第二连接部42，使得电容C的第二电极连接接地端GND。
如图2、图5、图6所示，第三导电线33、第四导电线44分别弯折设置，第三导电线33在衬底基板1的正投影与第四导电线44在衬底基板1的正投影围成一绕线区，第三导电线33的第一端可通过过孔连接第四导电线44的第一端，第三导电线33的第二端可通过过孔连接第一转接线22，第三导电线33的第一端至第二端的延伸方向与第四导电线44的第一端至第二端的延伸方向相同，由此第三导电线33和第四导电线44整体上形成螺旋绕线结构。
可以理解的是，本公开所述的某一导电线由第一端至第二端的延伸方向可以理解为，该导电线上的任意一点从第一端向第二端移动时的移动方向。其可以为顺时针方向或逆时针方向。
在示例性实施例中，通过将第一导电层2的第一转接线22弯折设置，可使得第一转接线22也可以形成电感L的部分线圈结构。在第一转接线22、第三导电线33和第四导电线44共同形成电感L的线圈结构时，如图9所示，第一转接线22、第三导电线33和第四导电线44整体上形成螺旋结构，该螺旋结构的一端由第一转接线22与第一导电线21连接，使得电感L的第一端连接电容C的第一电极，该螺旋结构的另一端由第四导电线44的末端与锡球层5的第二锡球2连接，使得电感L的第二端通过电阻连接信号输入端IN。
示例性的，如图4～图6、图8、图9所示，第一转接线22、第三导电线33和第四导电线44分别弯折设置，第一转接线22由与第一导电线21连接的起始端开始沿逆时针方向进行弯折，其末端通过过孔连接第三导电线33的起始端，第三导电线33同样沿逆时针方向进行弯折后，其末端通过过孔连接第四导电线44的起始端，第四导电线44进行弯折后，其末端连接锡球层5对应位置的锡球，此时，第一转接线22、第三导电线33和第四导电线44在衬底基板1的正投影形成绕线区，第一转接线22、第三导电线33和第四导电线44整体上形成螺旋延伸的绕线，构成电感L的线圈结构。
图13a为根据本公开一种实施方式的第一转接线、第三导电线和第四导电线的弯折示意图，图13b为根据本公开另一种实施方式的第一转接线、第三导电线和第四导电线的弯折示意图，可以理解的是，第一转接线22、第三导电线33和第四导电线44可以进行规则形状的弯折，例如进行U型弯折，圆形弯折等，或者也可以为不规则弯折，例如可以按照图13a、图13b所示的方式进行弯折，本公开不以此为限。通过将第三导电线33和第四导电线44设置为规则的弯折形状，可以简化布线难度，有利于调节电感L参数。
在示例性实施例中，衬底基板1还可以包括粘附层和第二种子层，可通过溅射工艺在功能孔的侧壁溅射第一材料形成粘附层，第一材料例如可以为Ti，即通过溅射Ti材料在功能孔的内壁形成Ti粘附层，粘附层的厚度可以大于5nm。再通过在Ti粘附层上溅射第一种子材料形成第二种子层，第二种子层的厚度可以大于30nm，第一种子材料例如可以为铜，然后可以以蝶形的方式对通孔TGV进行双面Cu电镀填充，形成具有预设厚度的散热柱10。应该理解的是，第一种子材料还可以为其他材料。
在示例性实施例中，衬底基板11的厚度可以为0.25mm～0.35mm，例如，衬底基板1的厚度可以为0.25mm、0.27mm、0.3mm、0.35mm等。功能孔在与衬底基板1平行平面上的横截面可以为圆形，功能孔沿衬底基板1的厚度方向的长度与功能孔的孔径之比可以大于等于5且小于等 于7。例如可以为5，5.5，6，6.5，7等。功能孔的孔径可以为50μm～80μm，例如，功能孔的孔径可以为50μm、60μm、70μm、80μm。位于第二种子层和功能孔侧壁之间粘附层的厚度可以为5nm～30nm，例如，粘附层的厚度可以为5nm、10nm、15nm、25nm、30nm等。第二种子层的厚度可以为30nm～80nm，例如，第二种子层的厚度可以为30nm、50nm、70nm、80nm等。应该理解的是，在其他示例性实施例中，功能孔在与衬底基板1平行平面上的横截面还可以为其他形状，例如，矩形、菱形等。
在上述实施例的基础上，衬底基板1上的功能孔可以具有不同的形状。示例性的，衬底基板1上的功能孔可以通过激光打孔形成，相应的，功能孔在衬底基板1的厚度方向上各个位置的开孔面积可以相同。此外，衬底基板1还可以通过湿刻工艺形成，例如，可以利用激光照射衬底基板1上的预设位置，以对衬底基板1预设位置的分子键进行改性，以使衬底基板1预设位置的刻蚀速度会大于衬底基板1其他位置的刻蚀速度，然后利用刻蚀液对衬底基板1的预设位置进行刻蚀以形成功能孔。在一示例性实施例中，可以利用刻蚀液从玻璃基板的一侧面向另一侧面刻蚀功能孔，相应的，功能孔的开孔面积自一个开口向另一开口逐渐减小。在另一示例性实施例中，还可以利用刻蚀液从衬底基板1的两侧面向中间刻蚀功能孔，相应的，功能孔的开孔面积可以自两个开口向中间一位置逐渐减小。其中，湿刻工艺可以使得功能孔侧壁更加光滑，从而有助于粘附层、第二种子层和功能孔侧壁粘结。
应该理解的是，不管功能孔是通孔TGV还是盲孔BGV，其均可以具有上文所描述的功能孔结构及其效果。
此外，位于功能孔中的散热柱10的性状可以与功能孔的性状相匹配，即散热柱10各个位置的径向尺寸相同，或者散热柱10的径向尺寸可以自衬底基板1的一侧向衬底基板1的另一侧逐渐减小，或者散热柱10的径向尺寸可以自衬底基板1两侧向中间一位置逐渐减小。
在示例性实施例中，第二导电层3的厚度、第三导电层4的厚度可以大于第一导电层2的厚度。第二导电层3的厚度、第三导电层4的厚度可以为第一导电层2的厚度的1.5倍～3倍，例如可以为1.5倍，2倍， 2.5倍，3倍等。第一导电层2的厚度例如可以大于等于3μm，第二导电层3的厚度、第三导电层4的厚度例如可以大于等于5μm。第二导电层3和第三导电层4因为要形成电感L的线圈结构，通过增加第二导电层3和第三导电层4的厚度，可以提高所形成的电感L的电感L值，减小电感L的损耗，从而提升滤波器的滤波效果。
在示例性实施例中，如图10、图11所示，滤波器还可以包括依次层叠于第一导电层2上的第一介质层210和第一种子层220，第一介质层210与第二导电线32对应设置，且第一介质层210在衬底基板1的正投影覆盖第二导电线32在衬底基板1的正投影，第一介质层210用于形成电容C的介质层，可以使用等离子体增强化学气相沉积(PECVD)工艺沉积120nm的高平整度的SiNx薄膜，作为电容C的介质层，以保障电容C的均一性。可利用磁控溅射的方法在第一介质层210上沉积100nm的Cu薄膜作为电容C的第二电极底垫及生成电容C的第二电极的种子层。
在示例性实施例中，具有三维电感L的滤波器可以包括衬底基板1、在衬底基板1一侧依次层叠设置的第一导电层2、第二导电层3、锡球层5以及位于衬底基板1另一侧的第五导电层6。
如图14～23所示，图14为根据本公开另一种实施方式的滤波器的结构版图，图15为图14中衬底基板的版图结构，图16为图14中第一导电层的版图结构，图17为图14中第二导电层的版图结构，图18为图14中锡球层的版图结构，图19为图14中第五导电层的版图结构，图20为图14中沿虚线NN的剖视图。
在示例性实施例中，如图14、图15所示，衬底基板1可以为玻璃基板或者硅基板。衬底基板1可以包括第一功能区A和第二功能区B，第一功能区A分布有多个第一导电柱101和第二导电柱102，多个第一导电柱101和多个第二导电柱102分别沿同一方向间隔排布，例如可以沿图中的第二方向Y间隔排列，且第一导电柱101和第二导电柱102并排设置，第一功能区A中的功能孔为通孔TGV，这样位于通孔TGV中的导电柱能够和与其连接的导电线和转接线形成电连接，使得导电柱形成电 感L的线圈的部分结构。
位于第二功能区B的散热柱10则仅用于形成滤波器的散热结构，第二功能区B的功能孔可以为通孔TGV或盲孔BGV。
图21a为根据本公开一种实施方式的衬底基板的剖视图，图21b为根据本公开另一种实施方式的衬底基板的剖视图。如图20所示，第二功能区B的功能孔为通孔TGV时，或者如图21a所示，第二功能区B的功能孔为盲孔BGV且盲孔BGV的孔口位于衬底基板1靠近第一导电层2的一侧时，则与上述二维电感L的滤波器结构类似，可通过在衬底基板1的第二功能区B朝向第一导电层2的一侧形成第一绝缘层100，由第一绝缘层100将第二功能区B通孔TGV中的散热柱10与第一导电层2进行电气隔离。或者，如图21b所示，当第二功能区B的功能孔为盲孔BGV且盲孔BGV的孔口位于衬底基板1远离第一导电层2的一侧时，则可以利用盲孔BGV位置的孔底衬底基板1的剩余厚度对散热柱10和第一导电层2形成电气隔离。有关第一绝缘层100、通孔TGV、盲孔BGV的特征可参见上述实施例的介绍，此处不再详述。
此外，如图20所示，在示例性实施例中，第一功能区A中通孔的孔径可以大于第二功能区B中功能孔的孔径，有利于提高电感值，提高滤波器的性能。第一功能区A中功能孔的孔径大，其可以适配第一功能区A中的第一子转接线221的线宽。例如，第一子转接线221的线宽可以为60μm，第一功能区A中通孔的孔径例如可以为50μm等，第二功能区B中的功能孔的孔径可以为40μm，30μm等。
在示例性实施例中，如图14、图16所示，第一导电层2中同样可以包括第一导电线21和第一转接线22，第一转接线22可以包括多条第一子转接线221，第一子转接线221可用于形成电感L的部分线圈结构，第一子转接线221连接于相邻排的第一导电柱101和第二导电柱102之间，且每一导电柱连接一条第一子转接线221。第一导电线21可以沿第一方向X延伸，第一导电线21可以包括依次连接的第一子导电线211、第二子导电线212和第三子导电线213，第二子导电线212形成电容C的第一电极，第一子导电线211与第一子转接线221对应设置，第一子导电线211连接于第二子导电线212和与第一子导电线211对应的第一 子转接线221之间，从而将电容C的第一电极连接电感L的第一端。第三子导电线213可以通过过孔连接锡球层的第二锡球2，以将电感L的第一端和电容C的第一电极连接至第二锡球2，形成图1中的信号输出端OUT。
在示例性实施例中，如图14、图17所示，在第二导电层3中，第三导电线33可以包括多个第三子导电部331，第三子导电部331与第一子转接线221一一对应设置，并且第三子导电部331在衬底基板1的正投影可以位于第一子转接线221在衬底基板1的正投影上，第三子导电部331可以通过过孔连接与其对应的第一子转接线221，相当于第三导电线33与第二子导电线212形成并联结构。第二导电线32可以与第二子导电线212一一对应设置，第二导电线32在衬底基板1的正投影可以位于第二子导电线212在衬底基板1的正投影内，使得第二导电线32与第二子导电线212一一正对设置，形成电容C的两个正对的电极。第二导电层3还可以包括转接部34，转接部34位于第二导电线32远离第三子导电部331的一侧，且与第三子导电线213对应设置，例如，转接部34在衬底基板的正投影可以位于第三子导电线213在衬底基板的正投影内，如图20所示，转接部34可通过分别过孔连接第三子导电线213和锡球层的第二锡球2，形成图1中的信号输出端OUT。
在示例性实施例中，如图18、图20所示，锡球层5可以包括第一锡球1、第二锡球2和第三锡球3，第一锡球1在衬底基板1的正投影可以与第三子导电部331在衬底基板1的正投影交叠，第一锡球1可以通过过孔连接第三导电层4的第三子导电部331，以形成图1中的信号输入端IN。第二锡球2在衬底基板1的正投影可以与第三子导电线213在衬底基板1的正投影交叠，第二锡球2可通过过孔连接第三子导电线213，形成图1中的信号输出端OUT。第三锡球3在衬底基板1的正投影可以与第二导电线32在衬底基板1的正投影交叠，第三锡球3可通过过孔连接第二导电线32，使得电容C的第二电极连接接地端GND。
在示例性实施例中，如图14、图19所示，第五导电层6位于衬底基板1的另一侧，第五导电层6可以包括多条第五导电线71，第五导电线71在衬底基板1的正投影可以沿第一方向X延伸，第五导电线71可 以连接同一排的第一导电柱101和第二导电柱102，从而第一功能A中的第五导电线71、导电柱、第一子转接线221、第二导电线32整体上形成螺旋绕线，该螺旋绕线形成电感L的线圈。此外，第五导电线71的线宽可以大于与其连接的第一导电柱101的宽度以及大于与其连接的第二导电柱102的宽度。
在示例性实施例中，如图20所示，滤波器还可以包括依次层叠于第一导电层2上的第一介质层210和第一种子层220，第一介质层210与第二导电线32对应设置，且第一介质层210在衬底基板1的正投影覆盖第二导电线32在衬底基板1的正投影。第一介质层210用于形成电容C的介质层，第一介质层210的材料例如可以为SiNx，可以使用等离子体增强化学气相沉积(PECVD)工艺在第一导电层2上对应第二导电线32的位置沉积一定厚度的SiNx薄膜得到电容C的介质层。SiNx薄膜的厚度根据所制备的电容C的容值进行调节。SiNx薄膜需要保证高平整度，以保障电容C的均一性。示例性的，可使用磁控溅射的方法在SiNx介质层上沉积设定厚度的Cu薄膜得到第一种子层220，该第一种子层220作为电容C的第二电极底垫以及形成电容C的第二电极的种子层。Cu薄膜的厚度可以大于等于100nm，以使得电容C的容值达到要求，满足滤波器的性能要求。
与二维电感L形成的滤波器的不同之处在于，在三维电感L中，通孔TGV中具有导电性的散热柱10作为电感L线圈结构的一部分，而在电容C所对应的区域中，功能孔的作用则与二维电感L的滤波器中功能孔的作用相同，均作为滤波器的散热结构，用以提升滤波器的散热性能。应该理解的是，在具有三维电感L的滤波器中，功能孔可以与二维电感L滤波器中的功能孔具有相同的结构特征，有关功能孔的特征此处不再赘述。
在示例性实施例中，第五导电层6的厚度可以大于第一导电层2的厚度，第五导电层6的厚度可以为第一导电层2的厚度的1.5倍～3倍，例如可以为1.5倍，2倍，2.5倍，3倍等。第一导电层2的厚度例如可以大于等于3μm，第五导电层6的厚度例如可以大于等于5μm。第五导电层6因为要形成电感L的线圈结构，通过增加第五导电层6的厚度， 可以提高所形成的电感L的电感L值，减小电感L的损耗，从而提升所形成的滤波器的整体滤波效果。
本公开还提供一种滤波器制作方法，该制作方法可用于形成图2和图14所示的滤波器。如图22～28所示，为本公开滤波器制作方法一种示例性实施例的工艺流程图，所述制作方法包括：
S10：提供一衬底基板1。
如图22所示，衬底基板1可以是玻璃衬底基板1或者硅基衬底基板1。0.25mm～0.3mm，例如，玻璃基板的厚度可以为0.25mm、0.27mm、0.3mm等。
S20、在衬底基板1上形成至少一个功能孔。
如图23a所示，功能孔的孔直径可以为50μm～80μm，例如，功能孔的孔径可以为50μm、60μm、70μm、80μm。在示例性实施例中，可以使用激光打孔或激光诱导刻蚀的方法制作功能孔，由于激光打孔的热效应使得功能孔内壁粗糙度较大，这会影响功能孔内膜层的溅射及削弱孔内膜层与孔壁的结合力，不利于孔内高致密的粘附层和第二种子层的制备。激光诱导刻蚀的方法可以包括：利用激光照射衬底基板1上的预设位置，以对预设位置的分子键进行改性，然后利用刻蚀液对衬底基板1的预设位置进行刻蚀以形成通孔TGV，和/或，利用刻蚀工艺根据预设深宽比对衬底基板1的预设位置进行刻蚀以形成如图23b所示的盲孔BGV，且盲孔BGV的孔底距离衬底基板1的另一表面具有预设厚度，其中，刻蚀液对预设位置的刻蚀速度大于对衬底基板1其他位置的刻蚀速度。刻蚀液可以为氢氟酸和硝酸混合溶液、氢氧化钠和柠檬酸混合溶液等。其中，可以利用刻蚀液从玻璃基板的两侧面向中间刻蚀功能孔，相应的，功能孔的开孔面积可以自两个开口向中间一位置逐渐减小。湿刻工艺可以使得功能孔侧壁更加光滑，从而有助于后续粘附层、第二种子层和功能孔侧壁粘结。功能孔的深宽比可以为1.5～3，例如深宽比可以为1.5，2.0，2.5，3.0等。例如，可以以5:1的深宽比对厚度为0.3㎜的衬底基板1进行刻蚀以形成盲孔BGV，盲孔BGV的孔底距离衬底基板1的另一面50μm，即盲孔BGV的孔底留厚50μm。
在示例性实施例中，如图23a所示，功能孔在衬底基板1的厚度方向上各个位置的开孔面积可以相同。此外，衬底基板1还可以通过湿刻工艺形成，例如，可以利用激光照射衬底基板1上的预设位置，以对衬底基板1预设位置的分子键进行改性，以使衬底基板1预设位置的刻蚀速度会大于衬底基板1其他位置的刻蚀速度，然后利用刻蚀液对衬底基板1的预设位置进行刻蚀以形成功能孔。在一示例性实施例中，可以利用刻蚀液从玻璃基板的一侧面向另一侧面刻蚀功能孔，相应的，如图23b所示，功能孔的开孔面积自一个开口向另一开口逐渐减小。在另一示例性实施例中，还可以利用刻蚀液从衬底基板1的两侧面向中间刻蚀功能孔，如图23c所示，功能孔的开孔面积可以自两个开口向中间一位置逐渐减小。应该理解的是，盲孔BGV可以如图23d～图23f所示，具有与图23a～图23c所示的截面结构特征。
在示例性实施例中，当需要形成三维电感L时，衬底基板1包括第一功能区A和第二功能区B，第一功能区A形成电感L，第二功能区B形成电容C，第一功能区A中的散热柱10因为要形成电感L线圈的部分结构，因此在第一功能区A，需要将功能孔设置为通孔TGV，而在第二功能区B，功能孔则可以为盲孔BGV或通孔TGV。例如，所形成的功能孔可以如图23g所示，第一功能区A和第二功能区B均为通孔TGV，或者可以如图23h所示，第一功能区A为通孔TGV，第二功能区B为盲孔BGV，且盲孔BGV的孔口朝下(即孔口位于衬底基板1远离所要形成的第一导电层2的一侧)，或者如图23i所示，第一功能孔为通孔TGV，第二功能孔为盲孔BGV，且盲孔BGV的孔口朝上，即孔口位于衬底基板1靠近所要形成的第一导电层2的一侧。并且可以理解的是，第一功能区A和第二功能区B中的功能孔均可以具有图23b和/或图23c所示的结构。
S30、在功能孔内形成散热柱10。
其中，散热柱10的热传导率大于衬底基板1的热传导率。通常金属导电材料的热传导率较高，因此，本公开可以采用金属导电材料形成散热柱10，即为导电柱。当然，也可以采用其他热传导率高的材料形成散热柱10，本公开不限于此。
如图24a～24i所示，可以在功能孔的侧壁内溅射第一材料形成粘附层；在粘附层上溅射第一种子材料形成第二种子层；在第二种子层上溅射预设厚度的散热材料，形成散热柱10。示例性的，第一材料可以为Ti，第一种子材料可以为铜。例如，首先通过溅射工艺在功能孔的内壁形成Ti粘附层，然后在Ti粘附层上形成一定厚度的铜种子层，再以蝶形的方式对功能孔进行双面Cu电镀填充，形成铜散热柱10。粘附层的厚度可以为5nm～30nm，例如，粘附层的厚度可以为5nm、10nm、15nm、25nm、30nm等。第二种子层的厚度可以为30nm-80nm，例如，第二种子层的厚度可以为30nm、50nm、70nm、80nm等。在其他实施例中，还可以对散热柱1011进行打孔，以使散热柱10形成空心散热柱10。空心散热柱10的空腔内还可以填充树脂等材料，填充于空腔的材料的热膨胀系数可以位于散热柱10的热膨胀系数和衬底基板1的热膨胀系数之间。应该理解的是，在功能孔中形成散热柱10还可以有其他方式，例如，可以通过填充导电材料、铜芯焊锡球等方式在功能孔中形成散热柱10。
可以理解的是，所形成的散热柱10可以与功能孔具有相同的截面形状，此处不在详述。
可以理解是，图24a～24f所示为二维电感L的散热柱的结构示意图，图24g～24i所示为三维电感L的散热柱的结构示意图，此处不再详述。
S40、在衬底基板1的一侧面形成第一导电层2。可利用加成法在第一导电层2的一侧沉积预设厚度的第一导电材料，形成第一导电材料层；然后利用构图工艺将所述第一导电材料层形成第一导电层2；再对所述第一导电层2进行平坦化处理。如图25a所示，第一导电材料的厚度可以大于等于3μm。通过构图工艺在第一导电层2形成第一导电线21，第一导电线21的部分结构用于形成电容C的第一电极(下表面电极)，部分结构形成第一转接线22，由第一转接线22连接电感L的第一端和电容C的第一电极。通过对第一导电材料层进行平坦化，可以提高第一导电线21的平整度，提高电容C的均一性。可以理解的是，当形成三维电感L时，可在第一功能区A形成多条第一子转接线221，第一子转接线221形成三维电感L线圈的部分结构。
第一导电层2至少与部分散热柱10绝缘设置，以使得散热柱10作 为滤波器的散热结构。在示例性实施例中，在形成第一导电层2之前，还可以根据功能孔的类型，对散热柱10和第一导电层2进行电气隔离处理。例如，当散热柱10具有如图24a～24c所示的结构时，可以在衬底基板1上整面沉积第一绝缘材料形成第一绝缘层100，以通过该第一绝缘层100对散热柱10和第一导电层2进行电气隔离，使得所引入的散热柱10在提高滤波器的散热性能的同时不会影响滤波器的性能。或者，当功能孔如图25d～25f所示的盲孔结构时，则无需额外形成绝缘层，可利用衬底基板1的另一面与盲孔BGV的孔底101之间留有的绝缘材料对散热柱10和第一导电层2进行电气隔离。
可以理解的是，当电感L为三维电感L时，第一功能区A的功能孔为通孔TGV，第二功能区B的功能孔可以具有如图25d～23f所示的结构，具体而言，当第二功能区B的功能孔如图25d所示为通孔TGV，或者如图24i所示的盲孔结构时，可以在衬底基板1朝向第一导电层2的一侧沉积第一绝缘材料形成覆盖第二功能区B第一绝缘层100，以通过该第一绝缘层100对第一导电层2和散热柱10形成电气隔离。或者当第二功能区B的功能孔具有如图24h所示的结构时，可通过该盲孔BGV的孔底与衬底基板1的另一面留有的绝缘材料对散热柱10和第一导电层2进行电气隔离。
可以理解的是，在通过第一绝缘层100对散热柱10和第一导电层2进行电气隔离时，可以是在第一绝缘层100上沉积预设厚度的第一导电材料而形成第一导电材料层，再对第一导电层2材料层进行构图工艺得到第一导电层2。
可以理解是，图25a～25c所示为二维电感L的具有第一导电层的结构示意图，图25d～25f所示为三维电感L的具有第一导电层的结构示意图，并且功能孔可以具有上述实施例的结构特征，此处仅以图23a所示的功能结构为例进行示例性说明，此处不再详述。
S50、在第一导电层2背离衬底基板1的一侧形成第二导电层3。可以利用沉积工艺在第一导电层2背离衬底基板1的一侧沉积第二绝缘材料形成第三绝缘层PI1，再利用构图工艺将对第三绝缘层PI1进行处理形成开孔，以露出第一导电层2的部分结构，再利用溅射工艺在开孔处沉 积第一种子材料，形成第三种子层，最后利用电镀工艺在第三种子层上电镀预设厚度的第一导电材料形成第二导电层3。其中，第二绝缘材料可以材料可以为BL-301等。第三绝缘层PI1整体覆盖第一导电层2，然后可以使用光刻工艺对电容C、电感L区域进行曝光、显影、后烘烤，在第三绝缘层PI1上形成开孔，分别露出第一导电层2的部分结构。第一种子材料例如可以为铜，通过先溅射Cu种子层，再电镀厚Cu的方法制作第二导电层3。第二导电层3的一部分为形成电感L的走线，一部分为电容C的第二电极(上电极)，为了减小电感L损耗，第二导电层3的厚度可以大于等于5μm。
如图26a～图26c所示，通过构图工艺可以在第二导电层3上形成第二导电线32和第三导电线33，第二导电线32与第一导电线21对应，例如，第二导电线32在衬底基板1的正投影位于第一导电线21在衬底基板1的正投影上，第二导电线32用于形成电容C的第二电极。第三导电线33位于第二导电线32的一侧且与第一转接线22对应，第三导电线33用于形成电感L线圈的部分结构。
如图26d～图26f所示，当形成三维电感L时，位于第一功能区A的第三导线33包括多个第三子导电部331，第三子导电部331与第一子转接线221一一对应设置，并且第三子导电部331在衬底基板1的正投影可以位于第一子转接线221在衬底基板1的正投影上，第三子导电部331可以通过过孔连接与其对应的第一子转接线221，相当于第三导电线33与第二子导电线212形成并联结构。第二导电线32可以在衬底基板1的正投影可以位于第二子导电线212在衬底基板1的正投影内，使得第二导电线32与第二子导电线212一一正对设置，形成电容C的两个正对的电极。还可以在第二导电层3形成转接部34，转接部34位于第二导电线32远离第三子导电部331的一侧，且与第三子导电线213对应设置。
如图26a～24f所示，在示例性实施例中，在形成第二导电层3之前，还可以利用等离子体增强化学气相沉积工艺在第一导电层2上沉积预设厚度的第一绝缘材料，形成电容C的第一介质层210；利用磁控溅射工艺在第一介质层210上沉积预设厚度的第一种子材料，形成第一种子层 220。示例性的，第一绝缘材料例如可以为SiNx，第一介质层210的厚度可以根据电容C的相对介电常数和电容C值进行确定。例如可以沉积120nm厚的高平整度的SiNx薄膜，充当电容C结构的介质层，以保障电容C的均一性。第一种子材料例如可以为铜，可用磁控溅射的方法在SiNx介质层上沉积100nm厚的Cu薄膜作为电容C的上电极底垫及生成电容C的第二电极的第一种子层220。在得到第一种子层220后，可以利用沉积工艺在第一导电层2和第一种子层220上沉积第二绝缘材料，形成第三绝缘层PI1；利用构图工艺对第三绝缘层PI1进行处理形成开孔，以露出部分第一导电层2以及露出部分第一种子层220；利用溅射工艺在开孔处沉积第一种子材料，形成第三种子层；利用电镀工艺在第三种子层上电镀预设厚度的第一导电材料形成第二导电层3。示例性的，第二绝缘材料例如可以为BL-301等，第三绝缘层PI1整体覆盖第二导电层3，使用光刻工艺对电容C、电感L区域进行曝光、显影、后烘烤，在第三绝缘层PI1上形成开孔，露出第二导电线32和第三导电线33的部分结构，以及露出第一连接部的部分结构。
同样地，第二导电层3因为部分结构要形成电感L的线圈结构，第二导电层3的厚度可以大于等于5μm，以提高电感L值，降低电感L的损耗。
应该理解的是，图26a～图26c所示的结构仅是功能孔的结构存在差异，在形成功能孔之后的制备工艺可以相同。
如图26d～图26f所示，在三维电感L的滤波器结构中，在形成电容C的第二电极底垫作为生成电容C的第二电极的种子层后，可以沉积第一绝缘材料形成第三绝缘层PI1，该第三绝缘层PI1部分覆盖第一种子层220，使得第一种子层220内缩于第三绝缘层PI1内，以通过该第三绝缘层PI1隔绝电容C的第二电极与第一电极的电气连接。
当电感L为三维电感L时，所形成的第二导电层3的结构可以如图26d～26f所示，可以理解的是，图26d～24f所示的结构仅是形成的功能孔的结构存在差异，在形成功能孔后的制备工艺可以相同。
在示例性实施例中，如图27a～27c所示，在形成第二导电层3后，还可以在第二导电层3背离衬底基板1的一侧形成第三导电层4、锡球 层5。示例性的，可以在第二导电层3上沉积第二绝缘材料形成第四绝缘层PI2；然后利用构图工艺对第四绝缘层PI2进行处理形成开孔，以露出位于第一导电线21上的部分第二导电层3；再利用溅射工艺在位于第三导电线33上的第四绝缘层PI2处以及开孔处溅射第一种子材料，形成第四种子层；最后利用电镀工艺在第四种子层上电镀预设厚度的第一导电材料，形成第三导电层4。其中，在二维电感L结构中，可通过构图工艺可在第三导电层4形成第四导电线44，第四导电线44与第三导电线33对应设置，第四导电线44用于形成电感L线圈的部分结构，第三导电线33、第四导电线44的结构特征可参见上述实施例的介绍，此处不再赘述。
在示例性实施例中，如图27a～27c所示，在形成第三导电层4后，可在第三导电层4上沉积第二绝缘材料形成第五绝缘层PI3；然后利用构图工艺在第五绝缘层PI3上对应第四导电线44的位置形成三个开孔，以分别露出部分第四导电线44的部分结构、第二连接部42的部分结构以及第三连接部43的部分结构；再在三个开孔处分别植入锡球，形成滤波器的信号输入端IN、信号输出端OUT和接地端。
在示例性实施例中，如图27d～27f所示，在三维电感L的结构中，在形成第二导电层3后，可以利用溅射工艺在衬底基板1背离第一导电层2一侧的第一功能区A溅射第一种子材料，形成第五种子层；然后利用电镀工艺在第五种子层上电镀预设厚度的第一导电材料，形成第五导电层6；再利用构图工艺对第五导电层6进行处理，形成多多条第五导电线71，第五导电线71用于形成电感L线圈的部分结构，第五导电线连接于同一排的第一导电柱和第二导电柱之间。再在第五导电层6背离衬底基板1的一侧沉积第三绝缘材料形成下表面绝缘层80，第三绝缘材料例如可以为聚酰亚胺或亚克力等。在形成第五导电层6和下表面绝缘层80后，可在衬底基板1上表面的对应开孔处植入锡球，形成滤波器的信号输入端IN、信号输出端OUT和接地端。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或 者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (36)

  1. 一种滤波器，其中，包括电感和电容，所述电容的第一电极连接所述电感的第一端，所述滤波器还包括：
    衬底基板，所述衬底基板具有至少一个功能孔；
    至少一个散热柱，所述散热柱与所述功能孔对应设置，所述散热柱填充于与其对应的所述功能孔内；
    第一导电层，位于所述衬底基板的一侧，所述第一导电层包括：
    第一导电线，所述第一导电线的部分结构用于形成所述电容的第一电极；
    第一转接线，所述第一转接线连接于所述第一导电线的一侧；
    第二导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：
    第二导电线，与所述第一导电线对应设置，所述第二导电线在所述衬底基板的正投影位于所述第一导电线在所述衬底基板的正投影上，所述第二导电线用于形成所述电容的第二电极；
    第三导电线，位于所述第二导电线的一侧且与所述第一转接线对应设置，所述第三导电线通过过孔连接所述第一转接线，所述第三导电线用于形成所述电感线圈的部分结构；
    其中，至少部分散热柱与所述第一导电层绝缘设置，且所述散热柱的热传导率大于所述衬底基板的热传导率。
  2. 根据权利要求1所述的滤波器，其中，所述功能孔各个位置的开孔面积相同；或者，
    所述功能孔的开孔面积自所述衬底基板的一侧向所述衬底基板的另一侧逐渐减小；或者，
    所述功能孔的开孔面积自所述衬底基板两侧向中间一位置逐渐减小。
  3. 根据权利要求2所述的滤波器，其中，所述功能孔沿所述衬底基板的厚度方向的长度与所述功能孔的孔径之比大于等于5且小于等于7。
  4. 根据权利要求1所述的滤波器，其中，所述散热柱为空心散热柱，所述散热柱的空腔的延伸方向和所述散热柱的延伸方向相同。
  5. 根据权利要求1所述的滤波器，其中，所述散热柱为实心散热柱。
  6. 根据权利要求4或5所述的滤波器，其中，所述散热柱为导电柱。
  7. 根据权利要求6所述的滤波器，其中，所述滤波器还包括：
    第一介质层，位于所述第一导电层和所述第二导电层之间，所述第一介质层与所述第二导电线对应设置，且所述第一介质层在所述衬底基板的正投影覆盖所述第二导电线在所述衬底基板的正投影；
    第一种子层，位于所述第一介质层和所述第二导电层之间，所述第一种子层用于作为生成所述第二导电层的种子层。
  8. 根据权利要求7所述的滤波器，其中，所述滤波器还包括：
    第三导电层，位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括：
    第四导电线，所述第四导电线与所述第三导电线对应设置，所述第四导电线用于形成所述电感线圈的部分结构；
    其中，所述第三导电线、所述第四导电线弯折设置，所述第三导电线在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影围成绕线区；
    且所述第三导电线的第一端通过过孔连接所述第四导电线的第一端，所述第三导电线的第二端通过过孔连接所述第一转接线，所述第三导电线的第一端至第二端的延伸方向与所述第四导电线的第一端至第二端的延伸方向相同。
  9. 根据权利要求7所述的滤波器，其中，所述第二导电层的厚度、所述第三导电层的厚度均大于所述第一导电层的厚度。
  10. 根据权利要求9所述的滤波器，其中，所述第二导电层的厚度与所述第一导电层的厚度之比、所述第三导电层的厚度与所述第一导电层的厚度之比大于等于1.5且小于等于3。
  11. 根据权利要求8所述的滤波器，其中，
    所述第二导电层还包括：
    第一连接部，位于所述第二导电线和所述第三导电线之间且与所述第一导电线对应设置，所述第一连接部通过过孔连接所述第一导电线；
    所述第三导电层还包括：
    第二连接部，所述第二连接部与所述第二导电线对应设置，所述第 二连接部在所述衬底基板的正投影与所述第二导电线在所述衬底基板的正投影至少部分交叠，且所述第二连接部通过过孔连接所述第二导电线；
    第三连接部，所述第三连接部与所述第一连接部对应设置，所述第三连接部在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影至少部分交叠，且所述第三连接部通过过孔连接所述第一连接部；
    所述滤波器还包括：
    锡球层，位于所述第三导电层背离所述衬底基板的一侧，所述锡球层包括：
    第一锡球，在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影相交叠，所述第一锡球通过过孔连接所述第四导电线的一个端部；
    第二锡球，在所述衬底基板的正投影与所述第三连接部在所述衬底基板的正投影相交叠，所述第二锡球通过过孔连接所述第三连接部；
    第三锡球，在所述衬底基板的正投影与所述第二连接部在所述衬底基板的正投影相交叠，所述第三锡球通过过孔连接所述第二连接部。
  12. 根据权利要求11所述的滤波器，其中，所述功能孔为盲孔，且所述盲孔的孔口位于所述衬底基板远离所述第一导电层的一侧。
  13. 根据权利要求11所述的滤波器，其中，所述功能孔为通孔，或所述功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；
    所述滤波器还包括：
    第一绝缘层，所述第一绝缘层在朝向所述第一导电层的一侧覆盖所述衬底基板。
  14. 根据权利要求7所述的滤波器，其中，所述衬底基板包括第一功能区和第二功能区，所述第一转接线在所述衬底基板的正投影位于所述第一功能区，所述第一导电线在所述衬底基板的正投影位于所述第二功能区，所述第一功能区和所述第二功能区均包括所述功能孔，且所述第一功能区中的功能孔为通孔；
    位于所述第一功能区的所述多个散热柱包括多个第一导电柱和多个第二导电柱，多个所述第一导电柱和多个所述第二导电柱分别沿同一方 向间隔排布，且所述第一导电柱和所述第二导电柱并排设置，所述第一导电柱、所述第二导电柱用于形成所述电感线圈的部分结构；
    所述滤波器还包括：
    第五导电层，位于所述衬底基板背离所述第一导电层的一侧，所述通孔位于所述第五导电层在所述衬底基板的正投影对应的区域内，所述第五导电层包括：
    多条第五导电线，所述第五导电线连接于同一排的所述第一导电柱和所述第二导电柱之间；
    其中，所述第一转接线包括多个第一子转接线，所述第一子转接线用于形成所述电感线圈的部分结构，所述第一子转接线连接于相邻排的第一导电柱和第二导电柱之间，且每一散热柱连接一条所述第一子转接线。
  15. 根据权利要求14所述的滤波器，其中，
    所述第三导电线包括多个第三子导电部，所述第三子导电部与所述第一子转接线对应设置，所述第三子导电部通过过孔连接与其对应的所述第一子转接线；
    所述第二导电层还包括：
    所述第一导电线包括依次连接的第一子导电线、第二子导电线和第三子导电线，所述第二子导电线用于形成所述电容的第一电极，所述第一子导电线与所述第一子转接线对应设置，所述第一子导电线连接于所述第一子导电线和与所述第二子导电线对应的第一子转接线之间；
    所述滤波器还包括：
    锡球层，位于所述第三导电层背离所述衬底基板的一侧，所述锡球层包括：
    第一锡球，在所述衬底基板的正投影与所述第三子导电部在所述衬底基板的正投影相交叠，所述第一锡球通过过孔连接所述第三子导电部的一个端部；
    第二锡球，在所述衬底基板的正投影与所述第三子导电线在所述衬底基板的正投影相交叠，所述第二锡球通过过孔连接所述第三子导电线；
    第三锡球，在所述衬底基板的正投影与所述第二导电线在所述衬底 基板的正投影相交叠，所述第三锡球通过过孔连接所述第二导电线。
  16. 根据权利要求14所述的滤波器，其中，所述第一功能区中功能孔的孔径大于所述第二功能区中功能孔的孔径。
  17. 根据权利要求16所述的滤波器，其中，位于第一功能区的通孔的孔径与位于第二功能区的功能孔的孔径之比大于等于1.5小于等于2.5。
  18. 根据权利要求14所述的滤波器，其中，所述第一子转接线在所述衬底基板的正投影覆盖与其连接的第一导电柱、第二导电线在所述衬底基板的正投影；
    所述第五导电线在所述衬底基板的正投影覆盖与其连接的第一导电柱、第二导电线在所述衬底基板的正投影。
  19. 根据权利要求14所述的滤波器，其中，所述第二功能区中的功能孔为盲孔，且所述盲孔的孔口位于所述衬底基板远离所述第一导电层的一侧。
  20. 根据权利要求14所述的滤波器，其中，所述第二功能区的功能孔为通孔，或所述第二功能区的功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；
    所述滤波器还包括：
    第一绝缘层，所述第一绝缘层在朝向所述第一导电层的一侧覆盖所述衬底基板的第二功能区。
  21. 根据权利要求1所述的滤波器，其中，所述第五导电层的厚度、所述第二导电层的厚度均大于所述第一导电层的厚度。
  22. 根据权利要求21所述的滤波器，其中，所述第五导电层的厚度与所述第一导电层的厚度之比、所述第二导电层与所述第一导电层的厚度之比大于等于1.5且小于等于3。
  23. 根据权利要求10或20所述的滤波器，其中，所述第二导电层的厚度大于等于5μm，所述第一导电层的厚度大于等于3μm；
    所述第三导电层或所述第五导电层的厚度大于等于5μm。
  24. 根据权利要求1所述的滤波器，其中，所述散热柱的材料为铜。
  25. 根据权利要求1所述的滤波器，其中，所述衬底基板为玻璃基板或硅基板。
  26. 一种滤波器制作方法，其中，所述滤波器包括电感和电容，所述电容的第一电极连接所述电感的第一端，所述制作方法包括：
    提供一衬底基板；
    在所述衬底基板上形成至少一个功能孔；
    在所述功能孔内形成散热柱；
    在所述衬底基板的一侧面形成第一导电层，所述第一导电层至少与部分所述散热柱绝缘设置，所述第一导电层包括第一导电线和第一转接线，所述第一导电线的部分结构用于形成所述电容的第一电极，所述第一转接线连接于所述第一导电线的一侧；
    在所述第一导电层背离所述衬底基板的一侧形成第二导电层，所述第二导电层包括第二导电线和第三导电线，所述第二导电线与所述第一导电线对应设置，所述第二导电线在所述衬底基板的正投影位于所述第一导电线在所述衬底基板的正投影上，所述第二导电线用于形成所述电容的第二电极；所述第三导电线位于所述第二导电线的一侧且与所述第一转接线对应设置，所述第三导电线通过过孔连接所述第一转接线，所述第三导电线用于形成所述电感线圈的部分结构。
  27. 根据权利要求26所述的方法，其中，所述在所述衬底基板上形成至少一个功能孔，包括：
    利用激光照射所述衬底基板上的预设位置，以对所述预设位置的分子键进行改性；
    利用刻蚀液对所述衬底基板的预设位置进行刻蚀以形成通孔，和/或，利用刻蚀工艺根据预设深宽比对所述衬底基板的预设位置进行刻蚀以形成盲孔，且所述盲孔的孔底距离所述衬底基板的另一表面具有预设厚度，其中，刻蚀液对所述预设位置的刻蚀速度大于对所述衬底基板其他位置的刻蚀速度。
  28. 根据权利要求26所述的方法，其中，所述在所述功能孔内形成散热柱，包括：
    在所述功能孔的侧壁内溅射第一材料形成粘附层；
    在所述粘附层上溅射第一种子材料形成第二种子层；
    在所述第二种子层上溅射预设厚度的散热材料，形成散热柱。
  29. 根据权利要求28所述的方法，其中，所述功能孔为通孔，或者，所述功能孔为盲孔且所述盲孔的孔口位于所述衬底基板靠近所述第一导电层的一侧；所述在所述衬底基板的一侧面形成第一导电层之前，所述方法还包括：
    在所述衬底基板上整面沉积第一绝缘材料形成第一绝缘层。
  30. 根据权利要求29所述的方法，其中，所述在所述衬底基板的一侧面形成第一导电层，包括：
    利用加成法在所述第一绝缘层上沉积预设厚度的第一导电材料，形成第一导电材料层；
    利用构图工艺将所述第一导电材料层形成第一导电层；
    对所述第一导电层进行平坦化处理。
  31. 根据权利要求26所述的方法，其中，所述在所述第一导电层背离所述衬底基板的一侧形成第二导电层之前，所述方法包括：
    利用等离子体增强化学气相沉积工艺在所述第一导电层上沉积预设厚度的第一绝缘材料，形成第一介质层；
    利用磁控溅射工艺在所述第一介质层上沉积预设厚度的第一种子材料，形成第一种子层；
    所述在所述第一导电层背离所述衬底基板的一侧形成第二导电层，包括：
    利用沉积工艺在所述第一导电层和所述第一种子层上沉积第二绝缘材料，形成第三绝缘层；
    利用构图工艺将对所述第三绝缘层进行处理形成开孔，以露出所述第一导电层的部分结构以及露出所述第一种子层的部分结构；
    利用溅射工艺在所述开孔处沉积第一种子材料，形成第三种子层；
    利用电镀工艺在所述第三种子层上电镀预设厚度的第一导电材料形成第二导电层。
  32. 根据权利要求26所述的方法，其中，所述滤波器还包括第三导电层，在所述第一导电层背离所述衬底基板的一侧形成第二导电层之后，所述方法还包括：
    在所述第二导电层上沉积第二绝缘材料形成第四绝缘层；
    利用构图工艺对所述第四绝缘层进行处理形成开孔，以露出位于所述第一导电线上的部分所述第二导电层；
    利用溅射工艺在位于所述第三导电线上的第四绝缘层处以及所述开孔处溅射第一种子材料，形成第四种子层；
    利用电镀工艺在所述第四种子层上电镀预设厚度的第一导电材料，形成第三导电层，所述第三导电层包括第四导电线，所述第四导电线与所述第三导电线对应设置，所述第四导电线在所述衬底基板的正投影与所述第三导电线在所述衬底基板的正投影至少部分交叠，所述第四导电线用于形成所述电感线圈的部分结构，所述第三导电线、所述第四导电线弯折设置，所述第三导电线在所述衬底基板的正投影与所述第四导电线在所述衬底基板的正投影围成绕线区，所述第三导电线的第一端通过过孔连接所述第四导电线，所述第三导电线的第二端通过过孔连接所述第一转接线，所述第三导电线的第一端至第二端的延伸方向与所述第四导电线的第一端至第二端的延伸方向相同。
  33. 根据权利要求32所述的方法，其中，在形成所述第三导电层之后，所述方法还包括：
    在所述第三导电层上沉积第二绝缘材料形成第五绝缘层；
    利用构图工艺在所述第五绝缘层上对应所述第四导电线的位置形成三个开孔，以分别露出部分所述第四导电线的部分结构；
    在三个所述开孔处分别植入锡球，形成所述滤波器的信号输入端、信号输出端和接地端。
  34. 根据权利要求26所述的方法，其中，所述衬底基板包括第一功能区和第二功能区，所述第一转接线在所述衬底基板的正投影位于所述第一功能区，所述第一导电线在所述衬底基板的正投影位于所述第二功能区，所述第一功能区、所述第二功能区的功能孔均为通孔；
    所述多个散热柱包括多个第一导电柱和多个第二导电柱，多个所述第一导电柱和多个所述第二导电柱分别沿同一方向间隔排布，且所述第一导电柱和所述第二导电柱并排设置，所述第一导电柱、所述第二导电柱用于形成所述电感线圈的部分结构；
    在所述衬底基板的一侧面形成第一导电层之前，所述方法还包括：
    利用沉积工艺在所述衬底基板的第二功能区沉积第一绝缘材料形成第一绝缘层；
    所述在所述衬底基板的一侧面形成第一导电层，包括：
    利用加成法在所述第一绝缘层上以及所述衬底基板的第一功能区沉积预设厚度的第一导电材料，形成第一导电材料层；
    利用构图工艺将所述第一导电材料层形成第一导电层；
    对所述第一导电层进行平坦化处理。
  35. 根据权利要求34所述的方法，其中，所述滤波器还包括第五导电层，所述方法还包括：
    利用溅射工艺在所述衬底基板背离所述第一导电层一侧的第一功能区溅射第一种子材料，形成第五种子层；
    利用电镀工艺在所述第五种子层上电镀预设厚度的第一导电材料，形成第五导电层；
    利用构图工艺对所述第五导电层进行处理，形成多个第一子转接线，所述第一子转接线用于形成所述电感线圈的部分结构，所述第一子转接线连接于相邻排的第一导电柱和第二导电柱之间，且每一散热柱连接一条所述第一子转接线。
  36. 一种电子设备，其中，包括权利要求1-25任一项所述的滤波器。
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US20020064029A1 (en) * 2000-11-29 2002-05-30 Nokia Mobile Phones Ltd. Stacked power amplifier module
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