WO2023221767A9 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2023221767A9
WO2023221767A9 PCT/CN2023/091435 CN2023091435W WO2023221767A9 WO 2023221767 A9 WO2023221767 A9 WO 2023221767A9 CN 2023091435 W CN2023091435 W CN 2023091435W WO 2023221767 A9 WO2023221767 A9 WO 2023221767A9
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Prior art keywords
pixel electrode
substrate
pattern
pixel
sub
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PCT/CN2023/091435
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English (en)
French (fr)
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WO2023221767A1 (zh
Inventor
谢蒂旎
王久石
姚舜禹
王利波
吴仲远
董学
于静
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京东方科技集团股份有限公司
北京京东方技术开发有限公司
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Publication of WO2023221767A1 publication Critical patent/WO2023221767A1/zh
Publication of WO2023221767A9 publication Critical patent/WO2023221767A9/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0005—Production of optical devices or components in so far as characterised by the lithographic processes or materials used therefor

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a preparation method thereof, and a display device.
  • PPI high-resolution liquid crystal display products
  • embodiments of the present disclosure provide a method for preparing an array substrate, which includes:
  • the plurality of pixel electrodes are arranged in an array; along the row direction and/or column direction of the array, the distance between any two adjacent pixel electrodes is less than or equal to a set value; the 2n-1th The pixel electrode is the first pixel electrode; the 2nth pixel electrode is the second pixel electrode;
  • Preparing the pixel electrode includes: preparing the first pixel electrode through a first patterning process; and preparing the second pixel electrode through a second patterning process; where n is a positive integer.
  • preparing the first pixel electrode and the second pixel electrode includes:
  • the pattern of the first insulating layer is formed by etching.
  • preparing the first pixel electrode and the second pixel electrode includes:
  • a local area of the first insulating layer film is thinned through an etching process; the local area is an area of the first insulating layer film other than the pattern covering the first pixel electrode;
  • the pattern of the first insulating layer is formed by etching.
  • preparing the first pixel electrode and the second pixel electrode includes:
  • a patterning process is used to form the pattern of the second pixel electrode.
  • preparing the first pixel electrode and the second pixel electrode includes:
  • a patterning process is used to form a pattern of the first pixel electrode on the insulating flat layer while retaining a first photoresist pattern on the pattern of the first pixel electrode; the first photoresist pattern is formed on the The orthographic projection on the substrate only covers the pattern of the first pixel electrode;
  • the orthographic projection of the second photoresist pattern on the substrate only covers the pattern of the second pixel electrode;
  • preparing the first pixel electrode and the second pixel electrode includes:
  • the orthographic projection of the positive photoresist pattern on the substrate only covers the pattern of the first pixel electrode;
  • An exposure process is used to form a negative photoresist pattern on the pixel electrode film layer; the orthographic projection of the negative photoresist pattern on the substrate only covers the pattern of the second pixel electrode;
  • the method further includes: depositing and forming a second insulating layer on a side of the pattern of the first pixel electrode and the pattern of the second pixel electrode facing away from the substrate.
  • embodiments of the present disclosure also provide an array substrate, which includes: a base;
  • a pixel driving circuit located on the substrate
  • An insulating flat layer is located on the side of the pixel driving circuit facing away from the substrate; the surface of the insulating flat layer facing away from the substrate is a horizontal surface;
  • a plurality of pixel electrodes are located on the side of the insulating flat layer facing away from the substrate, and are respectively connected to the pixel driving circuit through via holes opened in the insulating flat layer;
  • the plurality of pixel electrodes are arranged in an array
  • any two adjacent pixel electrodes is less than or equal to 2 ⁇ m; any two adjacent pixel electrodes are the first pixel electrode and the third pixel electrode respectively.
  • Two pixel electrodes the distance between the side surface of the first pixel electrode facing away from the substrate and the substrate, and the distance between the side surface of the second pixel electrode facing away from the substrate and the substrate.
  • the absolute value of the distance difference ranges from 0 to 1500 Angstroms.
  • the pixel electrode includes a first sub-portion extending along a row direction of the array and a second sub-portion extending along a column direction of the array. , and the first sub-part and the second sub-part are connected;
  • the extension length of the first sub-section is less than the extension length of the second sub-section
  • the orthographic projection of the via hole in the insulating flat layer on the substrate is located within the orthographic projection of the first sub-portion on the substrate, and the first sub-portion passes through the via hole in the insulating flat layer. Connect the pixel drive circuit.
  • the second sub-portion of the first pixel electrode and the second sub-portion of the second pixel electrode have the same thickness
  • the first pixel electrode is in contact with the horizontal surface of the insulating flat layer
  • a first insulating layer is further provided between the second pixel electrode and the horizontal surface of the insulating flat layer;
  • the orthographic projection of the first insulating layer on the substrate coincides with the orthographic projection of the second pixel electrode on the substrate;
  • the second pixel electrode is in contact with a horizontal surface of the insulating flat layer.
  • the thickness of the second sub-portion of the first pixel electrode is greater than the thickness of the second sub-portion of the second pixel electrode
  • the first pixel electrode is in contact with the horizontal surface of the insulating flat layer
  • a first insulating layer is further provided between the second pixel electrode and the horizontal surface of the insulating flat layer; the orthographic projection of the first insulating layer on the substrate is consistent with the projection of the second pixel electrode on the substrate.
  • the orthographic projections on coincide with each other;
  • the thickness of the second sub-portion of the first pixel electrode is equal to the sum of the thicknesses of the second sub-portion of the second pixel electrode and the first insulating layer.
  • a second insulating layer is further included, located on a side of the pixel electrode facing away from the substrate, and an orthographic projection of the second insulating layer on the substrate covers the entire substrate.
  • an embodiment of the present disclosure further provides a display device, which includes the above array substrate.
  • FIG. 1 is a schematic top view of the arrangement of pixel electrodes in a display panel in the disclosed technology.
  • FIG. 2 is a schematic structural top view of an array substrate in an embodiment of the present disclosure.
  • Figure 3 is a structural cross-sectional view along the AA' section line in Figure 2.
  • Figure 4 is another structural cross-sectional view along the AA' section line in Figure 2.
  • Figure 5 is another structural cross-sectional view along the AA' section line in Figure 2.
  • Figure 6 is another structural cross-sectional view along the AA' section line in Figure 2.
  • Figure 7 is a structural cross-sectional flow chart of a method for preparing the array substrate shown in Figures 3-5.
  • FIG. 8 is a structural top view flow chart of the array substrate preparation method in FIG. 7 .
  • Figure 9 is a structural cross-sectional flow chart of another preparation method for preparing the array substrate in Figure 3.
  • FIG. 10 is a structural cross-sectional flow chart of a method for preparing the array substrate in FIG. 6 .
  • FIG. 11 is a structural cross-sectional flow chart of another preparation method for preparing the array substrate in FIG. 6 .
  • FIG. 12 is a structural cross-sectional flow chart of yet another preparation method for preparing the array substrate in FIG. 6 .
  • first and second are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
  • the high-resolution pixel arrangement will compress the distance between pixel electrodes.
  • the pixel electrode is prepared by first depositing a single layer of light-transmitting conductive film (such as ITO film), and then forming the pattern of the pixel electrode through the steps of exposure, development, and wet etching. Limited by the exposure accuracy of the exposure equipment itself (currently, the exposure accuracy of the exposure equipment is micron level), when the distance between adjacent pixel electrodes is small (such as less than 1 ⁇ m or 2 ⁇ m), it is difficult to completely expose the photoresist.
  • FIG. 1 a schematic top view of the arrangement of pixel electrodes in a display panel in the public technology is shown; in a high-resolution display panel, the gap between adjacent pixel electrodes 3 is very small, and a relatively large pattern needs to be made when preparing the pattern of the pixel electrodes 3.
  • the gap pattern between small pixel electrodes 3 for example, the gap width a is less than or equal to 0.9 ⁇ m; in the disclosed technology, in the preparation process of the pixel electrode 3 pattern, when the gap width a between adjacent pixel electrodes 3 is 0.9 ⁇ m , the gap width between the adjacent photoresist patterns corresponding to the adjacent pixel electrode 3 patterns formed previously is required to be 0.4 ⁇ m to achieve, and the pixel electrode 3 pattern is formed by wet etching under such a small adjacent photoresist pattern gap. It is easy to cause etching residues of the pixel electrode film layer in the photoresist pattern gaps.
  • the gap width value between adjacent photoresist patterns of 0.4 ⁇ m is input to the digital exposure equipment, and it is also necessary to subtract 0.5 experience from 0.4 ⁇ m. value, so that in theory, a gap width of 0.9 ⁇ m between adjacent pixel electrodes can be finally obtained; but at this time, the input value of the digital exposure equipment becomes -0.1, so the digital exposure equipment cannot achieve an adjacent photoresist of 0.4 ⁇ m at all.
  • the gap width between patterns makes it impossible to prepare a gap width of 0.9 ⁇ m between adjacent pixel electrodes.
  • an embodiment of the present disclosure provides an array substrate.
  • Figure 2 is a schematic structural top view of the array substrate in an embodiment of the present disclosure
  • Figure 3 is a schematic diagram along the A structural cross-sectional view of the AA' section line in Figure 2; which includes: substrate 1; pixel driving circuit 2, located on the substrate 1; insulating flat layer 4, located on the side of the pixel driving circuit 2 away from the substrate 1; insulating flat layer
  • the side surface of 4 facing away from the substrate 1 is a horizontal surface;
  • a plurality of pixel electrodes 3 are located on the side of the insulating flat layer 4 facing away from the substrate 1, and are respectively connected to the pixel driving circuit 2 through via holes 40 opened in the insulating flat layer 4 ;
  • Multiple pixel electrodes 3 are arranged in an array; along the row direction X and/or column direction Y of the array, the distance b between any two adjacent pixel electrodes 3 is less than or equal to the set value;
  • the setting value is 0.9 ⁇ m. In some embodiments, the setting value is 1 ⁇ m. In some embodiments, the setting value is 1.2 ⁇ m.
  • the description is based on the assumption that the separation distance b between the first pixel electrode 31 and the second pixel electrode 32 along the row direction X of the array is less than the set value.
  • the separation distance b between the first pixel electrode 31 and the second pixel electrode 32 is 0.9 ⁇ m.
  • the distance between the side surface of the first pixel electrode 31 facing away from the substrate 1 and the substrate 1 is h1
  • the distance between the side surface of the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is h2, then 0 ⁇
  • the array substrate provided in this embodiment is applied to a TN (Twisted Nematic) liquid crystal display panel, that is, the array substrate and the cell-matching substrate form a gap, and the gap is filled with liquid crystal.
  • a common electrode is arranged on the entire surface of the cell substrate, and an electric field capable of deflecting the liquid crystal is formed between the common electrode and the pixel electrode on the array substrate.
  • a backlight source is provided on the side of the array substrate away from the box substrate. The backlight provided by the backlight source passes through the pixel electrodes, the liquid crystal layer and the common electrode to realize the display of the entire liquid crystal display panel.
  • the pixel driving circuit 2 includes a transistor 20 , the active layer 201 , the gate electrode 202 , the source electrode 203 and the drain electrode 204 of the transistor 20 are disposed on the substrate 1 , the source electrode 203 and the drain electrode 204 are located on the same film layer, and the active layer 201, gate electrode 202 and source electrode 203 are distributed away from the substrate 1 in order; a gate insulation layer 205 is also provided between the gate electrode 202 and the active layer 201; the source electrode 203 and the drain electrode 204 In the same layer arrangement, an intermediate dielectric layer 206 is also provided between the gate electrode 202 and the source electrode 203 and drain electrode 204; the insulating flat layer 4 is located on the source electrode 203 and the drain electrode 204, and the insulating flat layer 4 can connect the entire source electrode 203
  • the surface of the substrate 1 where the drain electrode 204 is located is flattened, and the side surface of the insulating flat layer 4 facing away from the substrate 1 is a
  • a light-shielding metal layer 207 is also provided on the side of the active layer 201 close to the substrate 1, and a buffer layer 208 is provided between the light-shielding metal layer 207 and the active layer 201; the light-shielding metal layer 207 can block irradiation to the active layer. 201 to ensure that the switching performance of the transistor 20 is not affected by the light.
  • the pixel electrode 3 includes a first sub-portion 301 and a second sub-portion 302 .
  • the first sub-portion 301 extends along the row direction X of the array, and the second sub-portion 302 extends along the column direction Y of the array.
  • the first sub-portion 301 extends, and the first sub-portion 301 and the second sub-portion 302 are connected; the extension length of the first sub-portion 301 is less than the extension length of the second sub-portion 302; the orthographic projection of the via hole 40 in the insulating flat layer 4 on the substrate 1 Located within the orthographic projection of the first sub-portion 301 on the substrate 1 , the first sub-portion 301 is connected to the pixel driving circuit 2 through the via hole 40 in the insulating planar layer 4 .
  • the first sub-section 301 is connected to the drain 204 of the transistor 20 in the pixel driving circuit 2 through the via hole 40 in the insulating flat layer 4 .
  • the second sub-section 302 of the first pixel electrode 31 and the second sub-section 302 of the second pixel electrode 32 are parallel to each other and arranged sequentially along the row direction X of the array; the first pixel The first sub-portion 301 of the electrode 31 and the first sub-portion 301 of the second pixel electrode 32 are parallel to each other and are sequentially arranged along the column direction Y of the array.
  • Such arrangement can make the pixel electrodes 3 on the array substrate more densely arranged, thereby improving the resolution of the display panel using the array substrate.
  • the orthographic projection shape of the first sub-portion 301 on the substrate 1 is a rectangle
  • the orthographic projection shape of the second sub-portion 302 on the substrate 1 is a rectangle
  • the orthographic projection of the pixel driving circuit on the substrate 1 is located in the spacing area between adjacent pixel electrodes 3 along the column direction Y of the array; the orthographic projection of the transistor 20 on the substrate 1 is in contact with the pixel electrode.
  • the first sub-part 301 of 3 partially overlaps; the orthographic projection of the pixel driving circuit on the substrate 1 does not overlap with the second sub-part 302 of the pixel electrode 3, thereby ensuring that the backlight light can normally pass through the pixel electrode 3 for display.
  • the array substrate also includes a plurality of gate lines 7 and a plurality of data lines 8.
  • the gate lines 7 extend along the row direction X of the array, and the plurality of gate lines 7 are located in two adjacent rows. between the pixel electrodes 3; the orthographic projection of the gate line 7 on the substrate 1 may partially overlap with the first sub-section 301 of the pixel electrode 3; the orthographic projection of the gate line 7 on the substrate 1 and the second sub-section of the pixel electrode 3 302 does not overlap.
  • the data lines 8 extend along the column direction Y of the array, and the plurality of data lines 8 are respectively located between two adjacent columns of pixel electrodes 3; the orthographic projection of the data lines 8 on the substrate 1 can be aligned with the second sub-section of the pixel electrodes 3 302 Partial overlap or no overlap. For example: when the width of the data line 8 along the array row direction X is 1.2 ⁇ m, since the distance between two adjacent pixel electrodes 3 along the row direction The second sub-portions 302 of the pixel electrodes 3 partially overlap.
  • the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 are equal; the first pixel electrode 31 is in contact with the horizontal surface of the insulating flat layer 4; A first insulating layer 5 is also provided between the second pixel electrode 32 and the horizontal surface of the insulating flat layer 4; the orthographic projection of the first insulating layer 5 on the substrate 1 coincides with the orthographic projection of the second pixel electrode 32 on the substrate 1 .
  • insulating planar layer 4 includes an organic insulating layer.
  • the thickness of the organic insulating layer can be made thicker, thereby facilitating the formation of a horizontal surface on the side facing away from the substrate 1 .
  • the material of the organic insulating layer may be PI (polyimide), PC (polycarbonate), PMMA (polymethylmethacrylate) and other materials.
  • the thickness of the second sub-portion of the first pixel electrode 31 ranges from 400 to 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 ranges from 400 to 1200 angstroms. In some embodiments, the thickness of the first insulating layer 5 ranges from 50 to 800 angstroms.
  • the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 800 angstroms respectively; correspondingly, the thickness of the first insulating layer 5 may be 50 angstroms or 800 Angstroms. In some embodiments, the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 may be 400 angstroms respectively; correspondingly, the thickness of the first insulating layer 5 may be 600 angstroms.
  • the material of the first pixel electrode 31 and the second pixel electrode 32 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide. In some embodiments, the material of the first insulating layer 5 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the insulating flat layer 4 includes an organic insulating layer 41 and an inorganic insulating layer 42, and the organic insulating layer 41 and the inorganic insulating layer 42 Stack them away from base 1 in turn.
  • the provision of the inorganic insulating layer 42 can improve or avoid damage to the organic insulating layer 41 caused by etching to form the pattern of the first insulating layer 5 .
  • the material of the inorganic insulating layer 42 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.
  • FIG. 5 is another structural cross-sectional view along the AA′ sectional line in FIG. 2 ; the thickness of the second sub-portion of the first pixel electrode 31 is greater than that of the second sub-portion of the second pixel electrode 32 thickness; the first pixel electrode 31 is in contact with the horizontal surface of the insulating flat layer 4; a first insulating layer 5 is also provided between the second pixel electrode 32 and the horizontal surface of the insulating flat layer 4; the first insulating layer 5 is on the substrate 1
  • the orthographic projection of the second pixel electrode 32 coincides with the orthographic projection of the second pixel electrode 32 on the substrate 1; the thickness of the second sub-portion of the first pixel electrode 31 is the sum of the thickness of the second sub-portion of the second pixel electrode 32 and the first insulating layer 5 and equal.
  • an electric field is formed between the first pixel electrode 31 and the second pixel electrode 32 respectively and an entire surface of the common electrode provided on the side of the opposite cell substrate.
  • the above arrangement can make the side surface of the first pixel electrode 31 away from the substrate 1
  • the surface of the side of the second pixel electrode 32 away from the substrate 1 is flush, so that the sub-pixel using the first pixel electrode 31 and the sub-pixel using the second pixel electrode 32 display the same brightness when displaying grayscale signals of the same size.
  • Improve or avoid display stripes that is, improve or avoid grayscale mura phenomenon
  • the thickness of the second sub-portion of the first pixel electrode 31 is 1200 angstroms; the thickness of the second sub-portion of the second pixel electrode 32 is 400 angstroms; and the thickness of the first insulating layer 5 is 800 Angstroms.
  • FIG. 6 is another structural cross-sectional view along the AA' section line in FIG. 2 ; the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 are equal. ; The first pixel electrode 31 is in contact with the horizontal surface of the insulating flat layer 4 ; the second pixel electrode 32 is in contact with the horizontal surface of the insulating flat layer 4 .
  • the material of the first pixel electrode 31 includes any one of crystallized indium tin oxide, crystallized indium zinc oxide, and crystallized indium gallium zinc oxide; the material of the second pixel electrode 32 includes any one of crystallized indium tin oxide, crystallized indium zinc oxide, and crystallized indium gallium zinc oxide. Any one of indium tin, indium zinc oxide, and indium gallium zinc oxide.
  • the material of the first pixel electrode 31 includes any one of indium tin oxide, indium zinc oxide, and indium gallium zinc oxide; the material of the second pixel electrode 32 includes indium tin oxide, indium zinc oxide, or indium oxide. Any of gallium zinc.
  • the first pixel electrode 31 and the second pixel electrode 32 are made of the same material.
  • the array substrate further includes a second insulating layer 6 located on the side of the pixel electrode 3 facing away from the substrate 1 , and the orthographic projection of the second insulating layer 6 on the substrate 1 covers the entire substrate 1 .
  • the arrangement of the second insulating layer 6 facilitates the subsequent formation of structures such as alignment films and spacers thereon.
  • the material of the second insulating layer 6 includes any one of silicon nitride, silicon oxide, and silicon oxynitride.
  • the thickness of the second insulating layer 6 ranges from 800 to 2000 angstroms.
  • the insulating flat layer 4 when the insulating flat layer 4 only includes an organic insulating layer, when etching to form the pattern of the first insulating layer 5 , the area of the insulating flat layer 4 that is not covered by the pixel electrode 3 will be etched. Etching is caused, so in the area of the insulating flat layer 4 that is not covered by the pixel electrode 3 , the second insulating layer 6 partially penetrates deep into the insulating flat layer 4 .
  • embodiments of the present disclosure also provide a method for preparing the array substrate, which includes: step S01: preparing a pixel driving circuit on the substrate.
  • Step S02 Prepare an insulating flat layer on the substrate that has completed the above steps.
  • Step S03 Prepare multiple pixel electrodes on the substrate that has completed the above steps.
  • multiple pixel electrodes are connected to the pixel driving circuit through via holes opened in the insulating flat layer; multiple pixel electrodes are arranged in an array; along the row direction and/or column direction of the array, between any two adjacent pixel electrodes The spacing distance between them is less than or equal to the set value; the 2n-1th pixel electrode is the first pixel electrode; the 2nth pixel electrode is the second pixel electrode; preparing the pixel electrode includes: passing the first pixel electrode through the first patterning process Preparation; the second pixel electrode is prepared through a second patterning process; where n is a positive integer.
  • the setting value is 2 ⁇ m.
  • the first pixel electrode is prepared through the first patterning process; the second pixel electrode is prepared through the second patterning process.
  • all pixel electrodes are prepared through one patterning process.
  • the prepared solution can realize the preparation of ultra-small gaps between adjacent pixel electrodes under the exposure accuracy of current exposure equipment, thereby forming a precise pattern of pixel electrodes and ensuring the uniformity of the pixel electrode pattern within the array substrate.
  • the pixel driving circuit can adopt the pixel driving circuit structure in Figure 3.
  • FIG. 7 a structural cross-sectional flow chart of a preparation method for the array substrate in Figures 3 to 5 is shown;
  • Figure 8 is a structural top view flow chart of the preparation method of the array substrate in Figure 7; wherein, above the insulating flat layer 4
  • Preparing the first pixel electrode 31 and the second pixel electrode 32 includes: step S101: using a patterning process to form a pattern of the first pixel electrode 31 on the insulating flat layer 4; and depositing the first insulating layer film 9.
  • the pattern of the first pixel electrode 31 is formed through sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • the first insulating layer film 9 of silicon nitride material is deposited by chemical vapor deposition.
  • Step S102 Use a patterning process to form a pattern of the second pixel electrode 32 on the first insulating layer film 9.
  • the pattern of the second pixel electrode 32 is formed through sputtering and depositing an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • Step S103 Use the pattern of the second pixel electrode 32 as a mask to form the pattern of the first insulating layer 5 by etching.
  • the pattern of the first insulating layer 5 is etched through a dry etching process.
  • This dry etching process affects the areas of the insulating flat layer 4 of organic insulating material that are not covered by the first pixel electrode 31 and the second pixel electrode 32 . Damage risk: If the dry etching process causes damage to the insulating flat layer 4 of the organic insulating material, the edge end slope angle of the second pixel electrode 32 and the first insulating layer 5 will increase and the slope will become steeper.
  • Step S104 Deposit and form a second insulating layer 6 on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 away from the substrate 1.
  • the second insulating layer 6 is formed by chemical vapor deposition.
  • the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 are both 800 angstroms; the thickness of the first insulating layer 5 is 800 Angstroms.
  • the step difference between the first pixel electrode 31 and the second pixel electrode 32 is relatively high, and the etching of the first insulating layer 5 has a greater risk of damage to the insulating flat layer 4. If the etching of the first insulating layer 5 damages the insulating flat layer 4 4 causes greater damage, the edge end surface of the second pixel electrode 32 will form a steep slope, and the slope angle will be large, causing a high risk of climbing and fracture of the second insulating layer 6.
  • the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 is both 400 angstroms; the thickness of the first insulating layer 5 is 600 Angstroms.
  • the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 is reduced, so that the sub-pixels using the first pixel electrode 31 and the sub-pixels using the first pixel electrode 31 are reduced.
  • the display brightness difference is reduced, which can improve the display stripe phenomenon (ie, the display mura phenomenon); at the same time, the etching of the first insulating layer 5 has a negative impact on the insulating flat layer 4 The risk of injury has also improved.
  • the thickness of the second sub-section of the first pixel electrode 31 is 1200 angstroms; the thickness of the second sub-section of the second pixel electrode 32 is 400 angstroms; the first insulation The thickness of layer 5 is 800 Angstroms.
  • the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is 0, so that the first pixel electrode 31
  • the sub-pixels and the sub-pixels using the second pixel electrode 32 display the same brightness when displaying grayscale signals of the same size, which can further improve or avoid the display stripe phenomenon (ie, display the mura phenomenon); however, due to the thickness of the first pixel electrode 31 It is relatively thick.
  • the heat accumulation effect may easily lead to local crystallization of the first pixel electrode film layer, resulting in etching residues when etching to form the pattern of the first pixel electrode 31; in addition, the first insulating layer The etching of 5 will have a certain risk of damage to the insulating flat layer 4.
  • preparing the insulating flat layer 4 includes preparing an organic insulating layer and an inorganic insulating layer on the substrate 1, using the preparation method of the array substrate in Figure 7, the first insulating layer 5 etching will reduce the damage to the insulating flat layer 4; however, since the insulating flat layer 4 is composed of an organic insulating layer and an inorganic insulating layer, the transmittance of the array substrate will be reduced, and a mask process will be added to prepare it.
  • a via hole in the inorganic insulating layer which is a via hole that enables the connection between the pixel electrode and the drain of the transistor.
  • Figure 9 is a structural cross-sectional flow chart of another preparation method for preparing the array substrate in Figure 3; the first pixel electrode 31 and the second pixel electrode 32 are prepared above the insulating flat layer 4, including : Step S201: Use a patterning process to form a pattern of the first pixel electrode 31 on the insulating flat layer 4 .
  • the pattern of the first pixel electrode 31 is formed through sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • Step S202 Deposit the first insulating layer film 9 .
  • the first insulating layer film 9 of silicon nitride material is deposited by chemical vapor deposition.
  • Step S203 Thin a local area of the first insulating layer film 9 through an etching process; the local area is an area of the first insulating layer film 9 other than the pattern covering the first pixel electrode 31.
  • a local area of the first insulating layer film 9 is formed by 800 through a half-tone mask dry etching process. Angstrom thinning to tens of angstroms.
  • Step S204 Use a patterning process to form a pattern of the second pixel electrode 32 in the area where the first insulating layer film 9 is thinned.
  • the pattern of the second pixel electrode 32 is formed through sputtering and depositing an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • Step S205 Use the pattern of the second pixel electrode 32 as a mask to form the pattern of the first insulating layer 5 by etching.
  • the pattern of the first insulating layer 5 is formed through a dry etching process.
  • Step S206 Deposit and form a second insulating layer 6 on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 away from the substrate 1.
  • the second insulating layer 6 is formed by chemical vapor deposition.
  • the thickness of the second sub-portion of the first pixel electrode 31 and the second sub-portion of the second pixel electrode 32 are respectively 800 angstroms; the thickness of the first insulating layer 5 It's tens of angstroms.
  • the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is reduced, thereby making the sub-pixel electrode using the first pixel electrode 31
  • the display brightness difference is reduced, which can improve the display stripe phenomenon (ie, the display mura phenomenon) and improve the display effect of the display panel using the array substrate.
  • the edge end surface of the second pixel electrode 32 will form a steep slope. The larger angle increases the risk of the second insulating layer 6 climbing and breaking.
  • Figure 10 is a structural cross-sectional flow chart of a preparation method for preparing the array substrate in Figure 6; preparing the first pixel electrode 31 and the second pixel electrode 32 above the insulating flat layer 4, including: Step S301: Use a patterning process to form a pattern of the first pixel electrode 31 on the insulating flat layer 4.
  • the pattern of the first pixel electrode 31 is formed through sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • Step S302 Perform annealing treatment on the first pixel electrode 31 to crystallize the first pixel electrode 31.
  • the first pixel electrode 31 is annealed using a high temperature of 230°C.
  • the annealing process can crystallize the material of the first pixel electrode 31, such as indium tin oxide material.
  • the crystallized first pixel electrode 31 material will not be etched when the second pixel electrode film layer 10 is subsequently etched to form a pattern. Remove.
  • Step S303 Deposit and form the second pixel electrode film layer 10.
  • sputtering deposition is used to form the second pixel electrode film layer 10 , and the orthographic projection of the second pixel electrode film layer 10 on the substrate 1 covers the entire substrate 1 .
  • Step S304 Use a patterning process to form a pattern of the second pixel electrode 32.
  • the pattern of the second pixel electrode 32 is formed through sputtering and depositing an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes. During this etching process, etching damage will not be caused to the pattern of the first pixel electrode 31 .
  • Step S305 Deposit and form a second insulating layer 6 on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 away from the substrate 1.
  • the second insulating layer 6 is formed by chemical vapor deposition.
  • the preparation method of the array substrate in FIG. 10 is such that the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is 0, so that the first pixel electrode is used.
  • the sub-pixels 31 and the sub-pixels using the second pixel electrode 32 display the same brightness when displaying grayscale signals of the same size, which can avoid the display stripe phenomenon (ie, display the mura phenomenon) and improve the display effect of the display panel using the array substrate. .
  • the preparation method does not affect the organic insulating material and/or inorganic insulating material not covered by the first pixel electrode 31 and the second pixel electrode 32.
  • the insulating flat layer 4 does not cause any damage, so that the second insulating layer 6 does not have the risk of climbing fracture.
  • Figure 11 is a structural cross-sectional flow chart of another preparation method for preparing the array substrate in Figure 6; the first pixel electrode 31 and the second pixel electrode 32 are prepared above the insulating flat layer 4, including : Step S401: Use a patterning process to form a pattern of the first pixel electrode 31 on the insulating flat layer 4 while retaining the first photoresist pattern 11 on the pattern of the first pixel electrode 31; the first photoresist pattern 11 is on the substrate The orthographic projection on 1 only covers the pattern of the first pixel electrode 31.
  • the pattern of the first pixel electrode 31 is formed through sputtering deposition of an indium tin oxide film layer, photoresist coating, exposure, development, and wet etching processes.
  • Step S402 Deposit and form the second pixel electrode film layer 10.
  • sputtering deposition is used to form the second pixel electrode film layer 10 , and the orthographic projection of the second pixel electrode film layer 10 on the substrate 1 covers the entire substrate 1 .
  • Step S403 Use an exposure process to form the second photoresist pattern 12; the orthographic projection of the second photoresist pattern 12 on the substrate 1 only covers the pattern of the second pixel electrode 32.
  • the exposure process includes steps of exposure and development.
  • first photoresist pattern 11 and the second photoresist pattern 12 can both use positive photoresist or negative photoresist.
  • Step S404 Etch and remove the second pixel electrode film layer 10 in areas other than the area covered by the second photoresist pattern 12 to form a pattern of the second pixel electrode 32.
  • the pattern of the second pixel electrode 32 is formed through a wet etching process.
  • Step S405 Develop and remove the first photoresist pattern and the second photoresist pattern.
  • Step S406 Deposit and form a second insulating layer 6 on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 away from the substrate 1.
  • the second insulating layer 6 is formed by chemical vapor deposition.
  • the preparation method of the array substrate in FIG. 11 is such that the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is 0, so that the first pixel electrode is used.
  • the sub-pixels 31 and the sub-pixels using the second pixel electrode 32 display the same brightness when displaying grayscale signals of the same size, which can avoid the display stripe phenomenon (ie, display the mura phenomenon) and improve the display effect of the display panel using the array substrate. .
  • the preparation method does not affect the organic insulating material and/or inorganic insulating material not covered by the first pixel electrode 31 and the second pixel electrode 32.
  • the insulating flat layer 4 does not cause any damage, so that the second insulating layer 6 does not have the risk of climbing fracture.
  • Figure 12 is a structural cross-sectional flow chart of yet another preparation method for preparing the array substrate in Figure 6; the first pixel electrode 31 and the second pixel electrode 32 are prepared above the insulating flat layer 4, including : Step S501: Deposit the pixel electrode film layer 13 on the insulating flat layer 4 .
  • sputtering deposition is used to form the pixel electrode film layer 13 , and the orthographic projection of the pixel electrode film layer 13 on the substrate 1 covers the entire substrate 1 .
  • Step S502 Use an exposure process to form a positive photoresist pattern 14 on the pixel electrode film layer 13; the orthographic projection of the positive photoresist pattern 14 on the substrate 1 only covers the pattern of the first pixel electrode.
  • the exposure process includes film coating, exposure using the mask 16, and development.
  • Step S503 Use an exposure process to form a negative photoresist pattern 15 on the pixel electrode film layer 13; the orthographic projection of the negative photoresist pattern 15 on the substrate 1 only covers the pattern of the second pixel electrode.
  • the exposure process includes film coating, exposure using the mask 16, and development.
  • Step S504 Etch to form the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32.
  • the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 are formed through a wet etching process.
  • Step S505 Develop to remove the positive photoresist pattern and the negative photoresist pattern.
  • Step S506 Deposit and form a second insulating layer 6 on the side of the pattern of the first pixel electrode 31 and the pattern of the second pixel electrode 32 away from the substrate 1.
  • the second insulating layer 6 is formed by chemical vapor deposition.
  • the preparation method of the array substrate in FIG. 12 is such that the distance difference between the surface of the first pixel electrode 31 and the second pixel electrode 32 facing away from the substrate 1 and the substrate 1 is 0, so that the first pixel electrode is used.
  • the sub-pixels 31 and the sub-pixels using the second pixel electrode 32 display the same brightness when displaying grayscale signals of the same size, which can avoid the display stripe phenomenon (ie, display the mura phenomenon) and improve the display effect of the display panel using the array substrate. .
  • the preparation method does not affect the organic insulating material and/or inorganic insulating material not covered by the first pixel electrode 31 and the second pixel electrode 32.
  • the insulating flat layer 4 does not cause any damage, so that the second insulating layer 6 does not have the risk of climbing fracture.
  • the developer can easily cause damage to the positive photoresist pattern 14, causing defects in the pattern of the first pixel electrode 31.
  • the 2n-1th pixel electrode is prepared through the first patterning process along the row direction and/or column direction of the pixel electrode array; the 2nth pixel electrode Through the second patterning process, compared with the solution in the public technology that all pixel electrodes are prepared through one patterning process, ultra-small gaps between adjacent pixel electrodes can be prepared under the exposure accuracy of the current exposure equipment, thereby forming a precise The pattern of the pixel electrode ensures the uniformity of the pixel electrode pattern within the array substrate; thereby better realizing the preparation of high-resolution array substrate.
  • an embodiment of the present disclosure further provides a display panel, which includes the array substrate in the above embodiment.
  • the display panel further includes a cell-aligned substrate, the array substrate and the cell-aligned substrate form a gap to the cell, and the gap is filled with liquid crystal. That is, the display panel in this embodiment is a liquid crystal display panel.
  • the display panel is a TN (Twisted Nematic) liquid crystal display panel, that is, an entire common electrode is provided on the cell substrate, and a liquid crystal is formed between the common electrode and the pixel electrode on the array substrate. deflected electric field.
  • a backlight source is provided on the side of the array substrate away from the box substrate. The backlight provided by the backlight source passes through the pixel electrodes, the liquid crystal layer and the common electrode to realize the display of the entire liquid crystal display panel.
  • an embodiment of the present disclosure further provides a display device, including the display panel in the above embodiment.
  • the display device can be any product or component with a display function such as an LCD panel, LCD TV, mobile phone, tablet computer, notebook computer, monitor, digital photo frame, navigator, etc.

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Abstract

一种阵列基板的制备方法，其中，包括：在基底（1）上制备像素驱动电路（2）；在基底（1）上制备绝缘平坦层（4）；在基底上（1）制备多个像素电极（3）；多个像素电极（3）分别通过开设在绝缘平坦层（4）中的过孔（40）连接像素驱动电路（2）；多个像素电极（3）排布呈阵列；沿阵列的行方向和/或列方向，任意相邻两个像素电极（3）之间的间隔距离（b）小于或等于设定值；第2n-1个像素电极为第一像素电极（31）；第2n个像素电极为第二像素电极（32）；制备像素电极（3）包括：第一像素电极（32）通过第一次构图工艺制备；第二像素电极（32）通过第二次构图工艺制备；其中，n为正整数。

Description

阵列基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种阵列基板及其制备方法、显示装置。
背景技术
随着显示技术的发展，高分辨率(PPI)液晶显示产品由于其画面显示更加细腻，显示效果更佳，越来越受到人们的欢迎。
发明内容
一方面，本公开实施例提供一种阵列基板的制备方法，其中，包括：
在基底上制备像素驱动电路；
在完成上述步骤的所述基底上制备绝缘平坦层；
在完成上述步骤的所述基底上制备多个像素电极；所述多个像素电极分别通过开设在所述绝缘平坦层中的过孔连接所述像素驱动电路；
所述多个像素电极排布呈阵列；沿所述阵列的行方向和/或列方向，任意相邻两个所述像素电极之间的间隔距离小于或等于设定值；第2n-1个像素电极为第一像素电极；第2n个像素电极为第二像素电极；
制备所述像素电极包括：所述第一像素电极通过第一次构图工艺制备；所述第二像素电极通过第二次构图工艺制备；其中，n为正整数。
在一些实施例中，制备所述第一像素电极和所述第二像素电极，包括：
采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；沉积第一绝缘层膜；
采用构图工艺在所述第一绝缘层膜上形成所述第二像素电极的图形；
以所述第二像素电极的图形为掩膜，刻蚀形成第一绝缘层的图形。
在一些实施例中，制备所述第一像素电极和所述第二像素电极，包括：
采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；
沉积第一绝缘层膜；
通过刻蚀工艺对所述第一绝缘层膜的局部区域进行减薄；所述局部区域为所述第一绝缘层膜的除覆盖所述第一像素电极的图形以外的区域；
采用构图工艺在所述第一绝缘层膜减薄的区域形成所述第二像素电极的图形；
以所述第二像素电极的图形为掩膜，刻蚀形成第一绝缘层的图形。
在一些实施例中，制备所述第一像素电极和所述第二像素电极，包括：
采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；
对所述第一像素电极进行退火处理，使所述第一像素电极结晶；
沉积形成第二像素电极膜层；
采用构图工艺形成所述第二像素电极的图形。
在一些实施例中，制备所述第一像素电极和所述第二像素电极，包括：
采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形，同时保留所述第一像素电极的图形上的第一光刻胶图形；所述第一光刻胶图形在所述基底上的正投影只覆盖所述第一像素电极的图形；
沉积形成第二像素电极膜层；
采用曝光工艺形成第二光刻胶图形；所述第二光刻胶图形在所述基底上的正投影只覆盖所述第二像素电极的图形；
刻蚀去除所述第二光刻胶图形覆盖区域以外区域的所述第二像素电极膜层，形成所述第二像素电极的图形；
显影去除所述第一光刻胶图形和所述第二光刻胶图形。
在一些实施例中，制备所述第一像素电极和所述第二像素电极，包括：
在所述绝缘平坦层上沉积像素电极膜层；
采用曝光工艺在所述像素电极膜层上形成正性光刻胶图形；所述正性光刻胶图形在所述基底上的正投影只覆盖所述第一像素电极的图形；
采用曝光工艺在所述像素电极膜层上形成负性光刻胶图形；所述负性光刻胶图形在所述基底上的正投影只覆盖所述第二像素电极的图形；
刻蚀形成所述第一像素电极的图形和所述第二像素电极的图形；
显影去除所述正性光刻胶图形和所述负性光刻胶图形。
在一些实施例中，还包括：在所述第一像素电极的图形和所述第二像素电极的图形的背离所述基底的一侧沉积形成第二绝缘层。
第二方面，本公开实施例还提供一种阵列基板，其中，包括：基底；
像素驱动电路，位于所述基底上；
绝缘平坦层，位于所述像素驱动电路背离所述基底的一侧；所述绝缘平坦层的背离所述基底的一侧表面为水平表面；
多个像素电极，位于所述绝缘平坦层背离所述基底的一侧，且分别通过开设在所述绝缘平坦层中的过孔连接所述像素驱动电路；
所述多个像素电极排布呈阵列；
沿所述阵列的行方向和/或列方向，任意相邻两个所述像素电极之间的间隔距离小于或等于2μm；任意相邻的两个所述像素电极分别为第一像素电极和第二像素电极；所述第一像素电极的背离所述基底的一侧表面与所述基底之间的距离和所述第二像素电极的背离所述基底的一侧表面与所述基底之间的距离之差的绝对值范围为0～1500埃。
在一些实施例中，所述像素电极包括第一子部和第二子部，所述第一子部沿所述阵列的行方向延伸，所述第二子部沿所述阵列的列方向延伸，且所述第一子部和所述第二子部连接；
所述第一子部的延伸长度小于所述第二子部的延伸长度；
所述绝缘平坦层中的过孔在所述基底上的正投影位于所述第一子部在所述基底上的正投影内，所述第一子部通过所述绝缘平坦层中的过孔连接所述像素驱动电路。
在一些实施例中，所述第一像素电极的所述第二子部与所述第二像素电极的所述第二子部的厚度相等；
所述第一像素电极与所述绝缘平坦层的水平表面接触；
所述第二像素电极与所述绝缘平坦层的水平表面之间还设置有第一绝缘层；
所述第一绝缘层在所述基底上的正投影与所述第二像素电极在所述基底上的正投影重合；
或者，所述第二像素电极与所述绝缘平坦层的水平表面接触。
在一些实施例中，所述第一像素电极的所述第二子部的厚度大于所述第二像素电极的所述第二子部的厚度；
所述第一像素电极与所述绝缘平坦层的水平表面接触；
所述第二像素电极与所述绝缘平坦层的水平表面之间还设置有第一绝缘层；所述第一绝缘层在所述基底上的正投影与所述第二像素电极在所述基底上的正投影重合；
所述第一像素电极的所述第二子部的厚度与所述第二像素电极的所述第二子部和所述第一绝缘层的厚度之和相等。
在一些实施例中，还包括第二绝缘层，位于所述像素电极背离所述基底的一侧，所述第二绝缘层在所述基底上的正投影覆盖整个所述基底。
第三方面，本公开实施例还提供一种显示装置，其中，包括上述阵列基板。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1为公开技术中显示面板中像素电极的排布俯视示意图。
图2为本公开实施例中阵列基板的结构俯视示意图。
图3为沿图2中AA＇剖切线的一种结构剖视图。
图4为沿图2中AA＇剖切线的另一种结构剖视图。
图5为沿图2中AA＇剖切线的又一种结构剖视图。
图6为沿图2中AA＇剖切线的又一种结构剖视图。
图7为制备图3-图5中阵列基板的一种制备方法的结构剖视流程图。
图8为图7中阵列基板制备方法的结构俯视流程图。
图9为制备图3中阵列基板的另一种制备方法的结构剖视流程图。
图10为制备图6中阵列基板的一种制备方法的结构剖视流程图。
图11为制备图6中阵列基板的另一种制备方法的结构剖视流程图。
图12为制备图6中阵列基板的又一种制备方法的结构剖视流程图。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例提供的阵列基板及其制备方法、显示装置作进一步详细描述。
在下文中将参考附图更充分地描述本公开实施例，但是所示的实施例可以以不同形式来体现，且不应当被解释为限于本公开阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。
本公开实施例不限于附图中所示的实施例，而是包括基于制造工艺而形成的配置的修改。因此，附图中例示的区具有示意性属性，并且图中所示区的形状例示了区的具体形状，但并不是旨在限制性的。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
对于同样尺寸的液晶显示面板，高分辨率的像素排布会压缩像素电极之间的距离。公开技术中，像素电极的制备是通过先一次沉积单层透光导电膜(如ITO膜)，然后经过曝光、显影、湿刻的步骤形成像素电极的图形。受曝光设备自身曝光精度的限制(目前，曝光设备的曝光精度为微米级)，当相邻像素电极之间的间隔距离较小(如小于1μm或2μm)时，很难将光刻胶彻底曝光形成图形，如只能将光刻胶局部曝光形成图形，在某些较小的图形间隙处会发生光刻胶图形粘连(即图形与图形之间无法彻底曝开)，以致无法保证显示面板内像素电极图形的均匀性。
参照图1，为公开技术中显示面板中像素电极的排布俯视示意图；在高分辨率的显示面板中，相邻像素电极3之间的间隙很小，制备像素电极3的图形时需要制作较小的像素电极3之间的间隙图形；如间隙宽度a小于或等于0.9μm；公开技术中，像素电极3图形的制备工艺中，当相邻像素电极3之间的间隙宽度a为0.9μm时，需要前续形成的对应相邻像素电极3图形的相邻光刻胶图形之间的间隙宽度为0.4μm才能实现，在如此小的相邻光刻胶图形间隙下湿刻形成像素电极3图形很容易造成像素电极膜层在光刻胶图形间隙处的刻蚀残留。
当上述制备像素电极图形的工艺过程采用数字曝光设备时，向数字曝光设备输入相邻光刻胶图形之间的间隙宽度值0.4μm，同时还需要在0.4μm的基础上再减去0.5的经验值，这样理论上才能最终获得相邻像素电极之间0.9μm的间隙宽度；但此时数字曝光设备的输入值就成了-0.1，因而数字曝光设备根本无法实现0.4μm的相邻光刻胶图形之间的间隙宽度，从而也根本无法实现0.9μm的相邻像素电极之间的间隙宽度的制备。
为了解决公开技术中存在的上述问题，第一方面，本公开实施例提供一种阵列基板，参照图2和图3，图2为本公开实施例中阵列基板的结构俯视示意图；图3为沿图2中AA＇剖切线的一种结构剖视图；其中，包括：基底1；像素驱动电路2，位于基底1上；绝缘平坦层4，位于像素驱动电路2背离基底1的一侧；绝缘平坦层4的背离基底1的一侧表面为水平表面；多个像素电极3，位于绝缘平坦层4背离基底1的一侧，且分别通过开设在绝缘平坦层4中的过孔40连接像素驱动电路2；多个像素电极3排布呈阵列；沿阵列的行方向X和/或列方向Y，任意相邻两个像素电极3之间的间隔距离b小于或等于设定值；任意相邻的两个像素电极3分别为第一像素电极31和第二像素电极32；第一像素电极31的背离基底1的一侧表面与基底1之间的距离和第二像素电极32的背离基底1的一侧表面与基底1之间的距离之差的绝对值范围为0～1500埃；设定值为2μm。
在一些实施例中，设定值为0.9μm。在一些实施例中，设定值为1μm。在一些实施例中，设定值为1.2μm。
本实施例中，以沿阵列的行方向X，第一像素电极31和第二像素电极32之间的间隔距离b小于设定值进行说明。例如：本实施例中，第一像素电极31和第二像素电极32之间的间隔距离b为0.9μm。第一像素电极31的背离基底1的一侧表面与基底1之间的距离为h1，第二像素电极32的背离基底1的一侧表面与基底1之间的距离为h2，则0≤∣h1-h2∣≤1500埃。
本实施例中提供的阵列基板应用于TN型(Twisted Nematic扭曲向列型)液晶显示面板，即该阵列基板与对盒基板对盒形成间隙，间隙中填充液晶。对盒基板上设置整面公共电极，公共电极与阵列基板上的像素电极之间形成能使液晶偏转的电场。阵列基板背离对盒基板的一侧设置背光源，背光源提供的背光通过像素电极、液晶层和公共电极后实现整个液晶显示面板的显示。
在一些实施例中，参照图3，像素驱动电路2包括晶体管20，晶体管20的有源层201、栅极202、源极203和漏极204设置于基底1上，源极203和漏极204位于同一膜层上，且有源层201、栅极202和源极203依次远离基底1分布；栅极202与有源层201之间还设置有栅绝缘层205；源极203和漏极204同层设置，栅极202与源极203和漏极204之间还设置有中间介电层206；绝缘平坦层4位于源极203和漏极204上，绝缘平坦层4能够将整个源极203和漏极204所在的基底1表面填平，绝缘平坦层4的背离基底1的一侧表面为水平表面，以便后续在该水平表面上形成像素电极3的图形。另外，有源层201的靠近基底1的一侧还设置有遮光金属层207，遮光金属层207与有源层201之间还设置有缓冲层208；遮光金属层207能够遮挡照射至有源层201上的光线，从而确保晶体管20的开关性能不被光照影响。
在一些实施例中，参照图2，像素电极3包括第一子部301和第二子部302，第一子部301沿阵列的行方向X延伸，第二子部302沿阵列的列方向Y延伸，且第一子部301和第二子部302连接；第一子部301的延伸长度小于第二子部302的延伸长度；绝缘平坦层4中的过孔40在基底1上的正投影位于第一子部301在基底1上的正投影内，第一子部301通过绝缘平坦层4中的过孔40连接像素驱动电路2。其中，第一子部301通过绝缘平坦层4中的过孔40连接像素驱动电路2中晶体管20的漏极204。
在一些实施例中，参照图2，第一像素电极31的第二子部302与第二像素电极32的第二子部302相互平行，且沿阵列的行方向X依次排布；第一像素电极31的第一子部301与第二像素电极32的第一子部301相互平行，且沿阵列的列方向Y依次排布。如此设置，能使阵列基板上像素电极3的排布更加密集，从而提高采用该阵列基板的显示面板的分辨率。
在一些实施例中，第一子部301在基底1上的正投影形状为矩形，第二子部302在基底1上的正投影形状为矩形。
在一些实施例中，参照图2，像素驱动电路在基底1上的正投影位于沿阵列的列方向Y相邻像素电极3之间的间隔区域；晶体管20在基底1上的正投影与像素电极3的第一子部301局部交叠；像素驱动电路在基底1上的正投影与像素电极3的第二子部302不交叠，从而确保背光光线能正常透过像素电极3用于显示。
在一些实施例中，参照图2，阵列基板还包括多条栅线7和多条数据线8，栅线7沿阵列的行方向X延伸，且多条栅线7分别位于相邻的两行像素电极3之间；栅线7在基底1上的正投影可与像素电极3的第一子部301局部交叠；栅线7在基底1上的正投影与像素电极3的第二子部302不交叠。数据线8沿阵列的列方向Y延伸，且多条数据线8分别位于相邻的两列像素电极3之间；数据线8在基底1上的正投影可与像素电极3的第二子部302局部交叠或者不交叠。例如：当数据线8的沿阵列行方向X的宽度为1.2μm时，由于沿行方向X相邻两像素电极3之间间隔距离为0.9μm，所以数据线8在基底1上的正投影与像素电极3的第二子部302局部交叠。
在一些实施例中，参照图3，第一像素电极31的第二子部与第二像素电极32的第二子部的厚度相等；第一像素电极31与绝缘平坦层4的水平表面接触；第二像素电极32与绝缘平坦层4的水平表面之间还设置有第一绝缘层5；第一绝缘层5在基底1上的正投影与第二像素电极32在基底1上的正投影重合。
在一些实施例中，参照图3，绝缘平坦层4包括有机绝缘层。有机绝缘层的厚度可以做的较厚，从而有利于形成其背离基底1一侧的水平表面。
在一些实施例中，有机绝缘层的材料可以是PI(聚酰亚胺)、PC(聚碳酸酯)、PMMA(聚甲基丙烯酸甲酯)等材料。
在一些实施例中，第一像素电极31的第二子部的厚度范围为400～1200埃；第二像素电极32的第二子部的厚度范围为400～1200埃。在一些实施例中，第一绝缘层5的厚度范围为50～800埃。
在一些实施例中，第一像素电极31的第二子部和第二像素电极32的第二子部的厚度可以分别是800埃；相应地，第一绝缘层5的厚度可以是50埃或者800埃。在一些实施例中，第一像素电极31的第二子部和第二像素电极32的第二子部的厚度可以分别是400埃；相应地，第一绝缘层5的厚度可以是600埃。
在一些实施例中，第一像素电极31和第二像素电极32的材料包括氧化铟锡、氧化铟锌、氧化铟镓锌中的任意一种。在一些实施例中，第一绝缘层5的材料包括氮化硅、氧化硅、氮氧化硅中的任意一种。
在一些实施例中，参照图4，为沿图2中AA＇剖切线的另一种结构剖视图；绝缘平坦层4包括有机绝缘层41和无机绝缘层42，有机绝缘层41和无机绝缘层42依次远离基底1叠置。无机绝缘层42的设置，能够改善或避免刻蚀形成第一绝缘层5的图形时对有机绝缘层41造成的损伤。
在一些实施例中，无机绝缘层42的材料包括氮化硅、氧化硅、氮氧化硅中的任意一种。
在一些实施例中，参照图5，为沿图2中AA＇剖切线的又一种结构剖视图；第一像素电极31的第二子部的厚度大于第二像素电极32的第二子部的厚度；第一像素电极31与绝缘平坦层4的水平表面接触；第二像素电极32与绝缘平坦层4的水平表面之间还设置有第一绝缘层5；第一绝缘层5在基底1上的正投影与第二像素电极32在基底1上的正投影重合；第一像素电极31的第二子部的厚度与第二像素电极32的第二子部和第一绝缘层5的厚度之和相等。
其中，第一像素电极31和第二像素电极32分别与设置于对盒基板侧的一整面公共电极之间形成电场，上述设置，能使第一像素电极31的背离基底1的一侧表面与第二像素电极32背离基底1的一侧表面平齐，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度相同，改善或避免出现显示条纹(即改善或避免灰阶mura现象)，提升采用该阵列基板的显示面板的显示效果。
在一些实施例中，参照图5，第一像素电极31的第二子部的厚度为1200埃；第二像素电极32的第二子部的厚度为400埃；第一绝缘层5的厚度为800埃。
在一些实施例中，参照图6，为沿图2中AA＇剖切线的又一种结构剖视图；第一像素电极31的第二子部与第二像素电极32的第二子部的厚度相等；第一像素电极31与绝缘平坦层4的水平表面接触；第二像素电极32与绝缘平坦层4的水平表面接触。
在一些实施例中，第一像素电极31的材料包括结晶化的氧化铟锡、结晶化的氧化铟锌、结晶化的氧化铟镓锌中的任意一种；第二像素电极32的材料包括氧化铟锡、氧化铟锌、氧化铟镓锌中的任意一种。
在一些实施例中，第一像素电极31的材料包括氧化铟锡、氧化铟锌、氧化铟镓锌中的任意一种；第二像素电极32的材料包括氧化铟锡、氧化铟锌、氧化铟镓锌中的任意一种。其中，第一像素电极31和第二像素电极32的材料相同。
在一些实施例中，参照图3-图6，阵列基板还包括第二绝缘层6，位于像素电极3背离基底1的一侧，第二绝缘层6在基底1上的正投影覆盖整个基底1。第二绝缘层6的设置，便于后续在其上形成取向膜以及隔垫物等结构。
在一些实施例中，第二绝缘层6材料包括氮化硅、氧化硅、氮氧化硅中的任意一种。
在一些实施例中，第二绝缘层6的厚度范围为800～2000埃。
在一些实施例中，参照图3，当绝缘平坦层4仅包括有机绝缘层时，在刻蚀形成第一绝缘层5的图形时，会对绝缘平坦层4的未被像素电极3覆盖的区域造成刻蚀，所以在绝缘平坦层4的未被像素电极3覆盖的区域，第二绝缘层6部分深入至绝缘平坦层4中。
基于阵列基板的上述结构，第二方面，本公开实施例还提供一种该阵列基板的制备方法，其中，包括：步骤S01：在基底上制备像素驱动电路。
步骤S02：在完成上述步骤的基底上制备绝缘平坦层。
步骤S03：在完成上述步骤的基底上制备多个像素电极。
其中，多个像素电极分别通过开设在绝缘平坦层中的过孔连接像素驱动电路；多个像素电极排布呈阵列；沿阵列的行方向和/或列方向，任意相邻两个像素电极之间的间隔距离小于或等于设定值；第2n-1个像素电极为第一像素电极；第2n个像素电极为第二像素电极；制备像素电极包括：第一像素电极通过第一次构图工艺制备；第二像素电极通过第二次构图工艺制备；其中，n为正整数。
本实施例中，设定值为2μm。通过使沿阵列的行方向和/或列方向，第一像素电极通过第一次构图工艺制备；第二像素电极通过第二次构图工艺制备，相比于公开技术中所有像素电极通过一次构图工艺制备的方案，能在目前曝光设备的曝光精度下实现相邻像素电极之间的超小间隙制备，从而形成精准的像素电极的图形，确保阵列基板内像素电极图形的均匀性。
在一些实施例中，在阵列基板制备方法步骤的后续结构剖视图中，仅示出了绝缘平坦层上第一像素电极、第二像素电极、第一绝缘层和第二绝缘层的制备过程，像素驱动电路的结构以及制备步骤在结构剖视图中未示出，像素驱动电路都可以采用图3中的像素驱动电路结构。参照图7，为制备图3-图5中阵列基板的一种制备方法的结构剖视流程图；图8为图7中阵列基板制备方法的结构俯视流程图；其中，在绝缘平坦层4上方制备第一像素电极31和第二像素电极32，包括：步骤S101：采用构图工艺在绝缘平坦层4上形成第一像素电极31的图形；沉积第一绝缘层膜9。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第一像素电极31的图形。通过化学气相沉积氮化硅材料的第一绝缘层膜9。
步骤S102：采用构图工艺在第一绝缘层膜9上形成第二像素电极32的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第二像素电极32的图形。
步骤S103：以第二像素电极32的图形为掩膜，刻蚀形成第一绝缘层5的图形。
该步骤中，通过干刻工艺刻蚀形成第一绝缘层5的图形，此干刻过程对有机绝缘材料的绝缘平坦层4的未被第一像素电极31和第二像素电极32覆盖的区域有损伤风险，如果干刻过程对有机绝缘材料的绝缘平坦层4造成损伤，会使第二像素电极32与第一绝缘层5的边缘端面坡度角增大，坡度变陡。
步骤S104：在第一像素电极31的图形和第二像素电极32的图形的背离基底1的一侧沉积形成第二绝缘层6。
该步骤中，通过化学气相沉积形成第二绝缘层6。
在一些实施例中，制备图3中的阵列基板时，第一像素电极31的第二子部和第二像素电极32的第二子部的厚度均为800埃；第一绝缘层5的厚度为800埃。第一像素电极31和第二像素电极32的段差较高，并且第一绝缘层5的刻蚀对绝缘平坦层4有较大的损伤风险，如果第一绝缘层5的刻蚀对绝缘平坦层4造成较大的损伤，会使第二像素电极32的边缘端面形成陡峭的坡度，坡度角较大，使第二绝缘层6的爬坡断裂风险高。
在一些实施例中，制备图3中的阵列基板时，第一像素电极31的第二子部和第二像素电极32的第二子部的厚度均为400埃；第一绝缘层5的厚度为600埃。相较于上述像素电极厚度方案，第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差减小，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度差异减小，可改善显示条纹现象(即显示mura现象)；同时，第一绝缘层5的刻蚀对绝缘平坦层4的损伤风险也有所改善。
在一些实施例中，制备图5中的阵列基板时，第一像素电极31的第二子部的厚度为1200埃；第二像素电极32的第二子部的厚度为400埃；第一绝缘层5的厚度为800埃。相较于上述像素电极第二子部的厚度方案，第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差为0，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度相同，可进一步改善或避免显示条纹现象(即显示mura现象)；但，第一像素电极31由于厚度较厚，在沉积第一像素电极膜层时由于热累积效应容易导致第一像素电极膜层局部晶化，以致刻蚀形成第一像素电极31图形时出现刻蚀残留；另外，第一绝缘层5的刻蚀对绝缘平坦层4会有一定的损伤风险。
在一些实施例中，在制备图4中的阵列基板时，制备绝缘平坦层4包括先后在基底1上方制备有机绝缘层和无机绝缘层，采用图7中阵列基板的制备方法，第一绝缘层5的刻蚀对绝缘平坦层4的损伤会减小；但由于绝缘平坦层4由有机绝缘层和无机绝缘层两层构成，会使阵列基板透过率降低，同时需要增加一道掩膜工艺制备无机绝缘层中的过孔，该过孔是能实现像素电极与晶体管漏极连接的过孔。
在一些实施例中，参照图9，为制备图3中阵列基板的另一种制备方法的结构剖视流程图；在绝缘平坦层4上方制备第一像素电极31和第二像素电极32，包括：步骤S201：采用构图工艺在绝缘平坦层4上形成第一像素电极31的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第一像素电极31的图形。
步骤S202：沉积第一绝缘层膜9。
该步骤中，通过化学气相沉积氮化硅材料的第一绝缘层膜9。
步骤S203：通过刻蚀工艺对第一绝缘层膜9的局部区域进行减薄；局部区域为第一绝缘层膜9的除覆盖第一像素电极31的图形以外的区域。
该步骤中，在形成第一绝缘层膜9中连接第二像素电极32与晶体管漏极的过孔图形的同时，通过半色调掩膜干刻工艺使第一绝缘层膜9的局部区域由800埃减薄至几十埃。
步骤S204：采用构图工艺在第一绝缘层膜9减薄的区域形成第二像素电极32的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第二像素电极32的图形。
步骤S205：以第二像素电极32的图形为掩膜，刻蚀形成第一绝缘层5的图形。
该步骤中，通过干刻工艺形成第一绝缘层5的图形。
步骤S206：在第一像素电极31的图形和第二像素电极32的图形的背离基底1的一侧沉积形成第二绝缘层6。
该步骤中，通过化学气相沉积形成第二绝缘层6。
在一些实施例中，制备图3中的阵列基板时，第一像素电极31的第二子部和第二像素电极32的第二子部的厚度分别是800埃；第一绝缘层5的厚度是几十埃。相较于图7中像素电极的制备方案，第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差减小，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度差异减小，可改善显示条纹现象(即显示mura现象)，提升采用该阵列基板的显示面板的显示效果。但刻蚀形成第一绝缘层5的图形时对有机绝缘材料的绝缘平坦层4有较大的损伤风险，如果造成较大损伤，会使第二像素电极32的边缘端面形成陡峭的坡度，坡度角较大，使第二绝缘层6的爬坡断裂风险高。
在一些实施例中，参照图10，为制备图6中阵列基板的一种制备方法的结构剖视流程图；在绝缘平坦层4上方制备第一像素电极31和第二像素电极32，包括：步骤S301：采用构图工艺在绝缘平坦层4上形成第一像素电极31的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第一像素电极31的图形。
步骤S302：对第一像素电极31进行退火处理，使第一像素电极31结晶。
该步骤中，采用230℃的高温对第一像素电极31进行退火处理。退火处理能使第一像素电极31的材料结晶，如使氧化铟锡材料结晶，结晶后的第一像素电极31材料在后续对第二像素电极膜层10刻蚀形成图形时不会被刻蚀去除。
步骤S303：沉积形成第二像素电极膜层10。
该步骤中，采用溅射沉积形成第二像素电极膜层10，第二像素电极膜层10在基底1上的正投影覆盖整个基底1。
步骤S304：采用构图工艺形成第二像素电极32的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第二像素电极32的图形。在此刻蚀过程中，不会对第一像素电极31的图形造成刻蚀损伤。
步骤S305：在第一像素电极31的图形和第二像素电极32的图形的背离基底1的一侧沉积形成第二绝缘层6。
该步骤中，通过化学气相沉积形成第二绝缘层6。
本实施例中，图10中阵列基板的制备方法，使第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差为0，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度相同，可避免显示条纹现象(即显示mura现象)，提升采用该阵列基板的显示面板的显示效果。同时，图10中阵列基板的制备方法无需形成第一绝缘层，从而使该制备方法不会对未被第一像素电极31和第二像素电极32覆盖的有机绝缘材料和/或无机绝缘材料的绝缘平坦层4造成任何损伤，进而使第二绝缘层6不会出现爬坡断裂风险。
在一些实施例中，参照图11，为制备图6中阵列基板的另一种制备方法的结构剖视流程图；在绝缘平坦层4上方制备第一像素电极31和第二像素电极32，包括：步骤S401：采用构图工艺在绝缘平坦层4上形成第一像素电极31的图形，同时保留第一像素电极31的图形上的第一光刻胶图形11；第一光刻胶图形11在基底1上的正投影只覆盖第一像素电极31的图形。
该步骤中，通过溅射沉积氧化铟锡膜层、光刻胶涂覆、曝光、显影、湿刻工艺形成第一像素电极31的图形。
步骤S402：沉积形成第二像素电极膜层10。
该步骤中，采用溅射沉积形成第二像素电极膜层10，第二像素电极膜层10在基底1上的正投影覆盖整个基底1。
步骤S403：采用曝光工艺形成第二光刻胶图形12；第二光刻胶图形12在基底1上的正投影只覆盖第二像素电极32的图形。
该步骤中，曝光工艺包括曝光、显影的步骤。
其中，第一光刻胶图形11和第二光刻胶图形12可以都采用正性光刻胶或者负性光刻胶。
步骤S404：刻蚀去除第二光刻胶图形12覆盖区域以外区域的第二像素电极膜层10，形成第二像素电极32的图形。
该步骤中，通过湿刻工艺形成第二像素电极32的图形。
步骤S405：显影去除第一光刻胶图形和所述第二光刻胶图形。
步骤S406：在第一像素电极31的图形和第二像素电极32的图形的背离基底1的一侧沉积形成第二绝缘层6。
该步骤中，通过化学气相沉积形成第二绝缘层6。
本实施例中，图11中阵列基板的制备方法，使第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差为0，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度相同，可避免显示条纹现象(即显示mura现象)，提升采用该阵列基板的显示面板的显示效果。同时，图11中阵列基板的制备方法无需形成第一绝缘层，从而使该制备方法不会对未被第一像素电极31和第二像素电极32覆盖的有机绝缘材料和/或无机绝缘材料的绝缘平坦层4造成任何损伤，进而使第二绝缘层6不会出现爬坡断裂风险。但该制备方法在沉积形成第二像素电极膜层10时，容易使第一光刻胶图形11的光刻胶材料溅出，污染沉积腔室，造成第二像素电极膜层10的沉积不良。
在一些实施例中，参照图12，为制备图6中阵列基板的又一种制备方法的结构剖视流程图；在绝缘平坦层4上方制备第一像素电极31和第二像素电极32，包括：步骤S501：在绝缘平坦层4上沉积像素电极膜层13。
该步骤中，采用溅射沉积形成像素电极膜层13，像素电极膜层13在基底1上的正投影覆盖整个基底1。
步骤S502：采用曝光工艺在像素电极膜层13上形成正性光刻胶图形14；正性光刻胶图形14在基底1上的正投影只覆盖第一像素电极的图形。
该步骤中，曝光工艺包括膜层涂覆、采用掩膜板16进行曝光、显影的步骤。
步骤S503：采用曝光工艺在像素电极膜层13上形成负性光刻胶图形15；负性光刻胶图形15在基底1上的正投影只覆盖第二像素电极的图形。
该步骤中，曝光工艺包括膜层涂覆、采用掩膜板16进行曝光、显影的步骤。
步骤S504：刻蚀形成第一像素电极31的图形和第二像素电极32的图形。
该步骤中，通过湿刻工艺形成第一像素电极31的图形和第二像素电极32的图形。
步骤S505：显影去除正性光刻胶图形和负性光刻胶图形。
步骤S506：在第一像素电极31的图形和第二像素电极32的图形的背离基底1的一侧沉积形成第二绝缘层6。
该步骤中，通过化学气相沉积形成第二绝缘层6。
本实施例中，图12中阵列基板的制备方法，使第一像素电极31和第二像素电极32背离基底1一侧表面与基底1之间的距离差为0，从而使采用第一像素电极31的子像素和采用第二像素电极32的子像素在显示相同大小的灰阶信号时显示亮度相同，可避免显示条纹现象(即显示mura现象)，提升采用该阵列基板的显示面板的显示效果。同时，图12中阵列基板的制备方法无需形成第一绝缘层，从而使该制备方法不会对未被第一像素电极31和第二像素电极32覆盖的有机绝缘材料和/或无机绝缘材料的绝缘平坦层4造成任何损伤，进而使第二绝缘层6不会出现爬坡断裂风险。但该制备方法在负性光刻胶膜层涂覆、显影形成负性光刻胶图形15时，显影液容易对正性光刻胶图形14造成损伤，造成第一像素电极31图形的不良。
本公开实施例中所提供的阵列基板及其制备方法，通过使沿像素电极阵列的行方向和/或列方向，第2n-1个像素电极通过第一次构图工艺制备；第2n个像素电极通过第二次构图工艺制备，相比于公开技术中所有像素电极通过一次构图工艺制备的方案，能在目前曝光设备的曝光精度下实现相邻像素电极之间的超小间隙制备，从而形成精准的像素电极的图形，确保阵列基板内像素电极图形的均匀性；进而能够更好地实现高分辨率阵列基板的制备。
第三方面，本公开实施例还提供一种显示面板，其中，包括上述实施例中的阵列基板。
在一些实施例中，该显示面板还包括对盒基板，阵列基板与对盒基板对盒形成间隙，间隙中填充液晶。即本实施例中的显示面板为液晶显示面板。
在一些实施例中，该显示面板为TN型(Twisted Nematic扭曲向列型)液晶显示面板，即对盒基板上设置整面公共电极，公共电极与阵列基板上的像素电极之间形成能使液晶偏转的电场。阵列基板背离对盒基板的一侧设置背光源，背光源提供的背光通过像素电极、液晶层和公共电极后实现整个液晶显示面板的显示。
通过采用上述实施例中的阵列基板，能够实现该显示面板的高分辨率显示，从而提升了该显示面板的显示品质。
第四方面，本公开实施例还提供一种显示装置，包括上述实施例中的显示面板。
通过采用上述实施例中的显示面板，能够实现该显示装置的高分辨率显示，从而提升了该显示装置的显示品质。
该显示装置可以为：LCD面板、LCD电视、手机、平板电脑、笔记本电脑、显示器、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (13)

  1. 一种阵列基板的制备方法，其中，包括：
    在基底上制备像素驱动电路；
    在完成上述步骤的所述基底上制备绝缘平坦层；
    在完成上述步骤的所述基底上制备多个像素电极；所述多个像素电极分别通过开设在所述绝缘平坦层中的过孔连接所述像素驱动电路；
    所述多个像素电极排布呈阵列；沿所述阵列的行方向和/或列方向，任意相邻两个所述像素电极之间的间隔距离小于或等于设定值；第2n-1个像素电极为第一像素电极；第2n个像素电极为第二像素电极；
    制备所述像素电极包括：所述第一像素电极通过第一次构图工艺制备；所述第二像素电极通过第二次构图工艺制备；其中，n为正整数。
  2. 根据权利要求1所述的阵列基板的制备方法，其中，制备所述第一像素电极和所述第二像素电极，包括：
    采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；沉积第一绝缘层膜；
    采用构图工艺在所述第一绝缘层膜上形成所述第二像素电极的图形；
    以所述第二像素电极的图形为掩膜，刻蚀形成第一绝缘层的图形。
  3. 根据权利要求1所述的阵列基板的制备方法，其中，制备所述第一像素电极和所述第二像素电极，包括：
    采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；
    沉积第一绝缘层膜；
    通过刻蚀工艺对所述第一绝缘层膜的局部区域进行减薄；所述局部区域为所述第一绝缘层膜的除覆盖所述第一像素电极的图形以外的区域；
    采用构图工艺在所述第一绝缘层膜减薄的区域形成所述第二像素电极的图形；
    以所述第二像素电极的图形为掩膜，刻蚀形成第一绝缘层的图形。
  4. 根据权利要求1所述的阵列基板的制备方法，其中，制备所述第一像素电极和所述第二像素电极，包括：
    采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形；
    对所述第一像素电极进行退火处理，使所述第一像素电极结晶；
    沉积形成第二像素电极膜层；
    采用构图工艺形成所述第二像素电极的图形。
  5. 根据权利要求1所述的阵列基板的制备方法，其中，制备所述第一像素电极和所述第二像素电极，包括：
    采用构图工艺在所述绝缘平坦层上形成所述第一像素电极的图形，同时保留所述第一像素电极的图形上的第一光刻胶图形；所述第一光刻胶图形在所述基底上的正投影只覆盖所述第一像素电极的图形；
    沉积形成第二像素电极膜层；
    采用曝光工艺形成第二光刻胶图形；所述第二光刻胶图形在所述基底上的正投影只覆盖所述第二像素电极的图形；
    刻蚀去除所述第二光刻胶图形覆盖区域以外区域的所述第二像素电极膜层，形成所述第二像素电极的图形；
    显影去除所述第一光刻胶图形和所述第二光刻胶图形。
  6. 根据权利要求1所述的阵列基板的制备方法，其中，制备所述第一像素电极和所述第二像素电极，包括：
    在所述绝缘平坦层上沉积像素电极膜层；
    采用曝光工艺在所述像素电极膜层上形成正性光刻胶图形；所述正性光刻胶图形在所述基底上的正投影只覆盖所述第一像素电极的图形；
    采用曝光工艺在所述像素电极膜层上形成负性光刻胶图形；所述负性光刻胶图形在所述基底上的正投影只覆盖所述第二像素电极的图形；
    刻蚀形成所述第一像素电极的图形和所述第二像素电极的图形；
    显影去除所述正性光刻胶图形和所述负性光刻胶图形。
  7. 根据权利要求1-6任意一项所述的阵列基板的制备方法，其中，还包括：在所述第一像素电极的图形和所述第二像素电极的图形的背离所述基底的一侧沉积形成第二绝缘层。
  8. 一种阵列基板，其中，包括：基底；
    像素驱动电路，位于所述基底上；
    绝缘平坦层，位于所述像素驱动电路背离所述基底的一侧；所述绝缘平坦层的背离所述基底的一侧表面为水平表面；
    多个像素电极，位于所述绝缘平坦层背离所述基底的一侧，且分别通过开设在所述绝缘平坦层中的过孔连接所述像素驱动电路；
    所述多个像素电极排布呈阵列；
    沿所述阵列的行方向和/或列方向，任意相邻两个所述像素电极之间的间隔距离小于或等于2μm；任意相邻的两个所述像素电极分别为第一像素电极和第二像素电极；所述第一像素电极的背离所述基底的一侧表面与所述基底之间的距离和所述第二像素电极的背离所述基底的一侧表面与所述基底之间的距离之差的绝对值范围为0～1500埃。
  9. 根据权利要求1所述的阵列基板，其中，所述像素电极包括第一子部和第二子部，所述第一子部沿所述阵列的行方向延伸，所述第二子部沿所述阵列的列方向延伸，且所述第一子部和所述第二子部连接；
    所述第一子部的延伸长度小于所述第二子部的延伸长度；
    所述绝缘平坦层中的过孔在所述基底上的正投影位于所述第一子部在所述基底上的正投影内，所述第一子部通过所述绝缘平坦层中的过孔连接所述像素驱动电路。
  10. 根据权利要求9所述的阵列基板，其中，所述第一像素电极的所述第二子部与所述第二像素电极的所述第二子部的厚度相等；
    所述第一像素电极与所述绝缘平坦层的水平表面接触；
    所述第二像素电极与所述绝缘平坦层的水平表面之间还设置有第一绝缘层；
    所述第一绝缘层在所述基底上的正投影与所述第二像素电极在所述基底上的正投影重合；
    或者，所述第二像素电极与所述绝缘平坦层的水平表面接触。
  11. 根据权利要求9所述的阵列基板，其中，所述第一像素电极的所述第二子部的厚度大于所述第二像素电极的所述第二子部的厚度；
    所述第一像素电极与所述绝缘平坦层的水平表面接触；
    所述第二像素电极与所述绝缘平坦层的水平表面之间还设置有第一绝缘层；所述第一绝缘层在所述基底上的正投影与所述第二像素电极在所述基底上的正投影重合；
    所述第一像素电极的所述第二子部的厚度与所述第二像素电极的所述第二子部和所述第一绝缘层的厚度之和相等。
  12. 根据权利要求10-11任意一项所述的阵列基板，其中，还包括第二绝缘层，位于所述像素电极背离所述基底的一侧，所述第二绝缘层在所述基底上的正投影覆盖整个所述基底。
  13. 一种显示装置，其中，包括权利要求8-12任意一项所述的阵列基板。
PCT/CN2023/091435 2022-05-20 2023-04-28 阵列基板及其制备方法、显示装置 WO2023221767A1 (zh)

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