WO2023206637A1 - 驱动电路、显示面板及其驱动方法 - Google Patents

驱动电路、显示面板及其驱动方法 Download PDF

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Publication number
WO2023206637A1
WO2023206637A1 PCT/CN2022/093308 CN2022093308W WO2023206637A1 WO 2023206637 A1 WO2023206637 A1 WO 2023206637A1 CN 2022093308 W CN2022093308 W CN 2022093308W WO 2023206637 A1 WO2023206637 A1 WO 2023206637A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
electrode
node
module
Prior art date
Application number
PCT/CN2022/093308
Other languages
English (en)
French (fr)
Inventor
霍雯雪
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Application filed by 惠州华星光电显示有限公司, Tcl华星光电技术有限公司 filed Critical 惠州华星光电显示有限公司
Priority to US17/756,465 priority Critical patent/US20240169892A1/en
Publication of WO2023206637A1 publication Critical patent/WO2023206637A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0633—Adjustment of display parameters for control of overall brightness by amplitude modulation of the brightness of the illumination source
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection

Definitions

  • the present application relates to the field of display technology, and specifically to a driving circuit, a display panel and a driving method thereof.
  • a pulse amplitude modulation drive circuit is used to control the amplitude of the drive current of the light-emitting diode, that is, to control the brightness through the current size.
  • the threshold voltage drift of the drive transistor will cause current changes and cause color shift problems.
  • Another pulse width modulation drive circuit is currently used to control the brightness by controlling the light-emitting time of the light-emitting diode and dim the light-emitting diode.
  • the threshold voltage drift of the driving transistor will cause changes in the light-emitting time.
  • the pulse width modulation drive circuit can solve the color shift problem of light-emitting diodes.
  • the driver has high efficiency and can be accurately controlled. However, its compensation range for the drive circuit is small and its long occupation time is not conducive to ensuring the lighting time of the drive circuit.
  • This application provides a driving circuit, a display panel and a driving method thereof, which can realize mixed driving of pulse amplitude modulation and pulse width modulation, and enable the control module to have an internal compensation function and the light-emitting module to have an external compensation function.
  • a driving circuit including: a light-emitting module, a data signal writing module and a control module.
  • the light-emitting module emits light when driven by a driving current; the data signal writing module accesses the first data signal and the first scanning signal.
  • the data signal writing module is connected to the light-emitting module and is used to control the size of the driving current; the control module is connected to the second data signal, the lighting time control signal, and the second scanning signal. and a third scan signal, and is electrically connected to the data signal writing module and the light-emitting module.
  • the control module is used to control the light-emitting time of the light-emitting module under the control of the light-emitting time control signal.
  • the light-emitting module includes a first transistor and a light-emitting device, the first electrode of the first transistor is electrically connected to the first power terminal, and the gate of the first transistor is electrically connected to the first node, the second electrode of the first transistor is electrically connected to the second node; the anode of the light-emitting device is electrically connected to the second node, and the cathode of the light-emitting device is electrically connected on the second power terminal.
  • the data signal writing module includes a second transistor and a first capacitor, the gate of the second transistor is connected to the first scan signal, and the second The first electrode of the transistor is connected to the first data signal, and the second electrode of the second transistor is connected to the first node; one end of the first capacitor is electrically connected to the first node, and the second electrode of the second transistor is connected to the first node. The other end of a capacitor is electrically connected to the second node.
  • the control module includes a second capacitor, a third transistor, a fourth transistor, and a fifth transistor, and one end of the second capacitor is connected to the lighting time control signal, The other end of the second capacitor is electrically connected to the third node; the gate of the third transistor is connected to the second scan signal, and the first electrode of the third transistor is electrically connected to the third node.
  • the light-emitting module further includes a threshold voltage detection sub-module.
  • the threshold voltage detection sub-module is connected to the fourth scanning signal and the third data signal.
  • the threshold voltage The detection sub-module is used to detect the threshold voltage of the first transistor and compensate the data voltage corresponding to the first data signal.
  • the threshold voltage detection sub-module includes a sixth transistor, the gate of the sixth transistor is connected to the fourth scan signal, and the gate of the sixth transistor is connected to the fourth scan signal.
  • An electrode is connected to the third data signal, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the first electrode of the second transistor and the first electrode of the fifth transistor are electrically connected to the fifth node, and the first data signal and the first electrode of the fifth transistor are electrically connected to the fifth node.
  • the two data signals are the same signal.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are transistors of the same type.
  • the present application also provides a display panel, including a plurality of pixel units arranged in an array.
  • the pixel units include a drive circuit.
  • the drive circuit includes: a light-emitting module that emits light when driven by a driving current; a data signal
  • the writing module is connected to the first data signal and the first scanning signal.
  • the data signal writing module is connected to the light-emitting module and is used to control the size of the driving current.
  • the control module is connected to the second data signal and the light-emitting module.
  • the time control signal, the second scan signal and the third scan signal are electrically connected to the data signal writing module and the light emitting module.
  • the control module is used to control all the parameters under the control of the light emitting time control signal. Describe the lighting time of the light-emitting module.
  • the light-emitting module includes a first transistor and a light-emitting device, the first electrode of the first transistor is electrically connected to the first power terminal, and the gate of the first transistor is electrically connected to the first node, the second electrode of the first transistor is electrically connected to the second node; the anode of the light-emitting device is electrically connected to the second node, and the cathode of the light-emitting device is electrically connected on the second power terminal.
  • the data signal writing module includes a second transistor and a first capacitor, the gate of the second transistor is connected to the first scan signal, and the second The first electrode of the transistor is connected to the first data signal, and the second electrode of the second transistor is connected to the first node; one end of the first capacitor is electrically connected to the first node, and the second electrode of the second transistor is connected to the first node. The other end of a capacitor is electrically connected to the second node.
  • the control module includes a second capacitor, a third transistor, a fourth transistor, and a fifth transistor, and one end of the second capacitor is connected to the lighting time control signal, The other end of the second capacitor is electrically connected to the third node; the gate of the third transistor is connected to the second scan signal, and the first electrode of the third transistor is electrically connected to the third node.
  • the light-emitting module further includes a threshold voltage detection sub-module.
  • the threshold voltage detection sub-module is connected to the fourth scanning signal and the third data signal.
  • the threshold voltage The detection sub-module is used to detect the threshold voltage of the first transistor and compensate the data voltage corresponding to the first data signal.
  • the threshold voltage detection sub-module includes a sixth transistor, the gate of the sixth transistor is connected to the fourth scan signal, and the gate of the sixth transistor is connected to the fourth scan signal.
  • An electrode is connected to the third data signal, and a second electrode of the sixth transistor is electrically connected to the second node.
  • the first electrode of the second transistor and the first electrode of the fifth transistor are electrically connected to the fifth node, and the first data signal and the first electrode of the fifth transistor are electrically connected to the fifth node.
  • the two data signals are the same signal.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are transistors of the same type.
  • the present application provides a driving method for a display panel.
  • the display panel includes a plurality of pixel units arranged in an array.
  • the pixel units include a driving circuit.
  • the driving method of the driving circuit includes: through a first The data signal and the first scan signal control the data signal writing module to be turned on.
  • the data signal writing module is connected to the light-emitting module and used to control the size of the driving current; through the second data signal, the light-emitting time control signal, and the second scan signal And the third scan signal control module is turned on, the control module is electrically connected to the data signal writing module and the light-emitting module, and the control module is used to control the light-emitting module under the control of the light-emitting time control signal.
  • the light-emitting time; the driving current drives the light-emitting module to emit light.
  • the light-emitting module includes a first transistor and a light-emitting device, the first electrode of the first transistor is electrically connected to the first power terminal, and the gate of the first transistor is electrically connected to the first node, the second electrode of the first transistor is electrically connected to the second node; the anode of the light-emitting device is electrically connected to the second node, and the cathode of the light-emitting device is electrically connected on the second power terminal.
  • the data signal writing module includes a second transistor and a first capacitor, the gate of the second transistor is connected to the first scan signal, and the second The first electrode of the transistor is connected to the first data signal, and the second electrode of the second transistor is connected to the first node; one end of the first capacitor is electrically connected to the first node, and the second electrode of the second transistor is connected to the first node. The other end of a capacitor is electrically connected to the second node.
  • the control module includes a second capacitor, a third transistor, a fourth transistor, and a fifth transistor, and one end of the second capacitor is connected to the lighting time control signal, The other end of the second capacitor is electrically connected to the third node; the gate of the third transistor is connected to the second scan signal, and the first electrode of the third transistor is electrically connected to the third node.
  • the present application provides a driving circuit, a display panel and a driving method thereof.
  • the light-emitting module emits light when driven by a driving current;
  • the data signal writing module is connected to the first data signal and the first scanning signal, and the data signal writing module
  • the input module is connected to the light-emitting module and used to control the size of the driving current;
  • the control module is connected to the second data signal, the lighting time control signal, the second scanning signal and the third scanning signal, and is connected with the data signal
  • the writing module is electrically connected to the light-emitting module, and the control module is used to control the light-emitting time of the light-emitting module under the control of the light-emitting time control signal. It can realize mixed driving of pulse amplitude modulation and pulse width modulation, and enables the control module to have internal compensation function and the light-emitting module to have external compensation function.
  • Figure 1 is a schematic structural diagram of a driving circuit provided by the first embodiment of the present application.
  • Figure 2 is a schematic structural diagram of a driving circuit provided by the second embodiment of the present application.
  • Figure 3 is a circuit diagram of a driving circuit provided by the second embodiment of the present application.
  • Figure 4 is one of the timing diagrams of the driving circuit provided by the second embodiment of the present application.
  • Figure 5 is the second timing diagram of the driving circuit provided by the second embodiment of the present application.
  • Figure 6 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • Embodiments of the present application provide a driving circuit, a display panel and a driving method thereof.
  • the GOA circuit has a simple structure, can reduce the space of the circuit layout while ensuring the circuit function, increase the aperture ratio of the display panel, and meet the needs of narrow borders and narrow borders of the display panel. High resolution requirements.
  • the transistors used in all embodiments of this application can be thin film transistors, field effect transistors, or other devices with the same characteristics. Since the sources and drains of the transistors used here are symmetrical, their sources and drains are interchangeable. of. In the description of this application, the middle terminal of the switching transistor is the gate, the signal input terminal is the drain, and the output terminal is the source according to the form in the drawing. It can be understood that those skilled in the art may refer to the signal input terminal as the source and the signal output terminal as the drain according to their understanding. In addition, the transistors used in the embodiments of the present application are N-type transistors or P-type transistors.
  • the N-type transistor is turned on when the gate is at a high potential and is turned off when the gate is at a low potential; the P-type transistor is turned off when the gate is at a low potential. It is turned on when the gate is at a high potential and turned off when the gate is at a high potential.
  • the light-emitting device D may be a Mini Light Emitting Diode (Mini LED for short) or a Micro Light Emitting Diode (Micro Light Emitting Diode for short). LED), or organic light emitting diode (OLED for short).
  • FIG. 1 is a schematic structural diagram of a driving circuit provided by a first embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a driving circuit provided by a second embodiment of the present application.
  • the driving circuit provided by the embodiment of the present application includes a light emitting module 101, a data signal writing module 102, and a control module 103.
  • the light-emitting module 101 is connected in series to the light-emitting circuit formed by the first power supply terminal VDD and the second power supply terminal VSS, and emits light when driven by a driving current.
  • the data signal writing module 102 is connected to the first data signal DATA1 and the first scanning signal SCAN1, and is electrically connected to the first node G.
  • the data signal writing module 102 is connected to the light emitting module 101 and is used to control the size of the driving current; control
  • the module 103 receives the second data signal DATA2, the lighting time control signal Sweep, the second scanning signal SCAN2 and the third scanning signal SCAN3, and is electrically connected to the data signal writing module 102 and the lighting module 101.
  • the control module 103 is used to The light-emitting time of the light-emitting module 101 is controlled under the control of the light-emitting time control signal Sweep.
  • the light-emitting module 101 also includes a threshold voltage detection sub-module 1011.
  • the threshold voltage detection sub-module 1011 is connected to the fourth scanning signal SCAN4 and the third data signal DATA3.
  • the detection sub-module 1011 is used to detect the threshold voltage value and compensate the data voltage corresponding to the first data signal DATA1 based on the threshold voltage value.
  • the first data signal DATA1 and the second data signal DATA2 are the same signal.
  • the driving circuit provided by this application includes independent control module 103 and threshold voltage detection sub-module 1011.
  • the control module 103 controls the lighting time of the light-emitting module 101 and performs internal compensation to improve display uniformity; through the threshold voltage detection
  • the detection sub-module 1011 detects the threshold voltage of the first transistor T1 and compensates the data voltage corresponding to the first data signal DATA1, thereby realizing pulse width modulation and pulse amplitude modulation hybrid driving.
  • FIG. 3 is a circuit diagram of a driving circuit provided by a second embodiment of the present application.
  • the driving circuit provided by the embodiment of the present application includes: the light-emitting module 101 includes a first transistor T1 and a light-emitting device D; the data signal writing module 102 includes a second transistor T2 and a first capacitor C1; the control module 103 includes The third transistor T3, the fourth transistor T4, the fifth transistor T5 and the second capacitor C2; the light-emitting module 101 also includes a threshold voltage detection sub-module 1011, and the threshold voltage detection sub-module 1011 includes a sixth transistor T6.
  • the first electrode of the first transistor T1 is electrically connected to the first power terminal VDD
  • the gate of the first transistor T1 is electrically connected to the first node G
  • the second electrode of the first transistor T1 is electrically connected to the second node G.
  • the gate of the second transistor T2 is connected to the first scan signal SCAN1.
  • the first electrode of the second transistor T2 and the first electrode of the fifth transistor are electrically connected to the fifth node V to connect the first data signal DATA1.
  • the second electrode of the two transistors T2 is connected to the first node G.
  • the gate of the third transistor T3 is connected to the second scan signal SCAN2, the first electrode of the third transistor T3 is electrically connected to the third node P, and the second electrode of the third transistor T3 is electrically connected to the data signal writing module 102 and the light emitting module 101.
  • the gate of the fourth transistor T4 is electrically connected to the third node P, the first electrode of the fourth transistor T4 is electrically connected to the fourth node Q, the second electrode of the fourth transistor T4 and the second electrode of the third transistor T3 Electrical connection.
  • the gate of the fifth transistor T5 is connected to the third scan signal SCAN3, the first electrode of the fifth transistor T5 is connected to the first data signal DATA1, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node Q.
  • the gate of the sixth transistor T6 is connected to the fourth scan signal SCAN4, the first electrode of the sixth transistor T6 is connected to the second data signal DATA2, and the second electrode of the sixth transistor T6 is electrically connected to the second node S.
  • One end of the first capacitor C1 is electrically connected to the first node G, and the other end of the first capacitor C1 is electrically connected to the second node S.
  • One end of the second capacitor C2 is connected to the lighting time control signal Sweep, and the other end of the second capacitor C2 is electrically connected to the third node P.
  • the anode of the light-emitting device D is electrically connected to the second node S, and the cathode of the light-emitting device D is electrically connected to the second power terminal VSS.
  • both the first power supply terminal VDD and the second power supply terminal VSS are used to output a preset voltage value.
  • the potential of the first power supply terminal VDD is greater than the potential of the second power supply terminal VSS.
  • the potential of the second power supply terminal VSS may be the potential of the ground terminal.
  • the potential of the second power supply terminal VSS can also be other.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are transistors of the same type.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all P-type transistors or N-type transistors. It can be understood that, subject to the efficiency of the manufacturing process, each of the transistors may also be different types of transistors.
  • first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 may be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon.
  • first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 may be low-temperature polysilicon thin film transistors, oxide semiconductor thin film transistors or amorphous silicon.
  • One or more types of thin film transistors and field effect transistors are examples of thin film transistors.
  • the driving circuit provided in the embodiment of the present application improves display uniformity by controlling the light-emitting time of the light-emitting device D and internally compensating the threshold voltage of the fourth transistor T4; at the same time, by controlling the driving current flowing through the light-emitting device D size, and externally compensates the threshold voltage of the first transistor T1, thereby achieving pulse width modulation and pulse amplitude modulation hybrid driving, thereby enhancing product competitiveness.
  • Figure 4 is the first timing diagram of the driving circuit provided by the second embodiment of the present application
  • Figure 5 is the second timing diagram of the driving circuit provided by the second embodiment of the present application
  • the internal compensation process includes using the first scan signal SCAN1, the second scan signal SCAN2, the third scan signal SCAN3 and the fourth scan signal.
  • the driving control sequence of the driving circuit includes a first writing compensation stage t1, a second writing compensation stage t2, a third writing compensation stage t3, a fourth writing compensation stage and Luminous stage t5. It should be noted that the light-emitting device D emits light in the light-emitting stage t5.
  • the third scan signal SCAN3 is at a low level
  • the first scan signal SCAN1 the second scan signal SCAN2 and the fourth scan signal SCAN4 are at a high level.
  • the magnitude of the first data signal DATA1 is the first voltage.
  • the first scan signal SCAN1 is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first scan signal SCAN1, thereby charging the potential of the first node G to the first voltage through the first data signal DATA1
  • the second scan signal SCAN2 is at a high potential
  • the third transistor T3 is turned on under the control of the high potential of the second scan signal SCAN2, thereby charging the potential of the third node P to the first voltage through the first data signal DATA1
  • the fourth scan signal SCAN4 is at a high potential
  • the sixth transistor T6 is turned on under the high-potential control of the fourth scan signal SCAN4, thereby transmitting the third data signal DATA3 to the second node S.
  • the first scan signal SCAN1 is at a low level
  • the second scan signal SCAN2 the third scan signal SCAN3 and the fourth scan signal SCAN4 are at a high level
  • the magnitude of the first data signal DATA1 is the second voltage.
  • the second scan signal SCAN2 is at a high potential
  • the third transistor T3 is turned on under the control of the high potential of the second scan signal SCAN2, and the gate electrode of the fourth transistor T4 and the second electrode of the fourth transistor T4 pass through the turned-on third transistor T3 short-circuited and in a floating state;
  • the third scan signal SCAN3 is at a high potential
  • the fifth transistor T5 is turned on under the control of the high potential of the third scan signal SCAN3, thereby charging the potential of the fourth node Q through the first data signal DATA1 to the second voltage and maintained.
  • the gate of the fourth transistor T4 The voltage difference between (the third node P) and the source (the fourth node Q) is the threshold voltage of the fourth transistor T4. Therefore, the magnitude of the current flowing between the source and drain of the fourth transistor T4 is the same as that of the fourth transistor T4.
  • the threshold voltage is independent to complete the internal compensation of the fourth transistor T4.
  • the fourth scan signal SCAN4 is at a high potential
  • the sixth transistor T6 is turned on under the control of the high potential of the fourth scan signal SCAN4, thereby transmitting the third data signal DATA3 to the second node S.
  • the second scan signal SCAN2 and the third scan signal SCAN3 are at a low level
  • the first scan signal SCAN1 and the fourth scan signal SCAN4 are at a high level
  • the magnitude of the first data signal DATA1 is the third voltage.
  • the first scan signal SCAN1 is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first scan signal SCAN1
  • the fourth scan signal SCAN4 is at a high potential
  • the sixth transistor T6 is controlled by the high potential of the fourth scan signal SCAN4. It is turned on, so that the potential of the gate terminal of the sixth transistor T6 is charged to the third voltage through the first data signal DATA1 and the first capacitor C1 is charged.
  • the size of the third voltage determines the size of the driving current in the subsequent light-emitting stage.
  • the first scan signal SCAN1 and the second scan signal SCAN2 are at a low level
  • the third scan signal SCAN3 and the fourth scan signal SCAN4 are at a high level
  • the magnitude of the first data signal DATA1 is the fourth voltage.
  • the third scan signal SCAN3 is at a high potential
  • the fifth transistor T5 is turned on under the control of the high potential of the third scan signal SCAN3, thereby charging the potential of the fourth node Q to the fourth voltage through the first data signal DATA1, which exists as a pull-down potential.
  • the first scanning signal SCAN1, the second scanning signal SCAN2, the third scanning signal SCAN3 and the fourth scanning signal SCAN4 are all low potential.
  • the first transistor T1 is turned on, and the light-emitting device D emits light.
  • the coupling effect of the second capacitor C2 is used to generate the light-emitting time control signal Sweep.
  • the conduction time of the fourth transistor T4 is controlled. Then, the potential of the first node G is pulled down, causing the first transistor T1 to turn off and thereby controlling the lighting duration of the light-emitting module.
  • the threshold voltage detection sub-module 1011 can detect the threshold voltage of the first transistor T1 through an external driver chip, and compensate the data voltage corresponding to the first data signal DATA1, that is, so that the first transistor T1 and the The threshold voltages of the four transistors T4 are independently compensated in the control module 103 and the threshold voltage detection sub-module 1011.
  • the detection process includes a writing phase t1 and a compensation phase t2 which are sequentially combined by the first scanning signal SCAN1, the second scanning signal SCAN2, the third scanning signal SCAN3 and the fourth scanning signal SCAN4.
  • the second scan signal SCAN2 and the third scan signal SCAN3 are at low potential, and the first scan signal SCAN1 and the fourth scan signal SCAN4 are at high potential.
  • the first scan signal SCAN1 is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first scan signal SCAN1, thereby writing the first data signal DATA1 to the first node G
  • the fourth scan signal SCAN4 is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first scan signal SCAN1.
  • the six-transistor T6 is turned on under the high-potential control of the fourth scan signal SCAN4, thereby writing the third data signal DATA3 to the second node S.
  • the second scan signal SCAN2, the third scan signal SCAN3 and the fourth scan signal SCAN4 are at a low level, and the first scan signal SCAN1 is at a high level.
  • the first scan signal SCAN1 is at a high potential
  • the second transistor T2 is turned on under the control of the high potential of the first scan signal SCAN1, and the sixth transistor T6 is turned on.
  • the first power supply terminal VDD charges the second node S until the sixth transistor T6 is turned off.
  • the threshold voltage value of the sixth transistor T6 is stored in the first capacitor C1, and the threshold voltage value is obtained through detection by the external driver chip, or the threshold voltage value of the first transistor T1 is calculated by detecting the voltage of the second node S, Because the voltage of the second node S at this time is equal to the difference between the original voltage value provided by the first data signal DATA1 and the threshold voltage of the first transistor T1, the detection is completed and the voltage value provided by the first data signal DATA1 terminal is adjusted.
  • the threshold voltage compensation of the first transistor T1 is implemented as the sum of the threshold voltage of the first transistor T1 and the original voltage value provided by the first data signal DATA1.
  • the driving circuit provided by the embodiment of the present application independently and simultaneously controls the light-emitting time and the driving current of the light-emitting device D, so that the driving circuit has a longer charging time; secondly, the demand for data bandwidth is not high, and has the same characteristics as ordinary driving
  • the driving method is similar to the circuit; again, there is no need to consider the threshold voltage drift and compensation issues in the thin film transistor.
  • the driving current is not sensitive to the threshold voltage; finally, since the light-emitting device D is driven at a constant The current emits light, so it can solve the wavelength drift problem of the D light source of the light-emitting device.
  • FIG. 6 is a schematic structural diagram of a backlight module provided by an embodiment of the present application.
  • the embodiment of the present application also provides a backlight module 100, which includes a first data line 20, a first scanning signal line 30, a second scanning signal line 40, a third scanning signal line 50, a fourth scanning signal line 60, Two data signal lines 70, a light emission time control signal line 80 and the above driving circuit 10.
  • the first data line 20 is used to provide the first data signal DATA1.
  • the first scan signal line 30 is used to provide the first scan signal SCAN1.
  • the second scan signal line 40 is used to provide the second scan signal SCAN2.
  • the third scan signal line 50 is used to provide the third scan signal SCAN3.
  • the fourth scan signal line 60 is used to provide the fourth scan signal SCAN4.
  • the second data signal line 70 is used to provide a constant reference voltage, and the lighting time control signal line 80 is used to provide a sweep voltage Sweep.
  • the driving circuit 10 and the first data line 20, the first scanning signal line 30, the second scanning signal line 40, the third scanning signal line 50, the fourth scanning signal line 60, the second data signal line 70, and the emission time control signal line 80 are connected.
  • the light-emitting device D can be Mini-LED or Micro-LED.
  • the driving circuit 10 reference may be made to the above description of the driving circuit, and no further description will be given here.
  • FIG. 7 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • An embodiment of the present application also provides a display panel 200, including a plurality of pixel units 210 arranged in an array.
  • Each pixel unit 210 includes the above driving circuit 10, wherein the light-emitting device D may be a Mini-LED, Micro- LED.
  • the light-emitting device D may be a Mini-LED, Micro- LED.
  • the display panel can be: electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other product or component with a display function.

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Abstract

本申请公开了一种驱动电路、显示面板及其驱动方法，该驱动电路包括发光模块、数据信号写入模块及控制模块，发光模块在驱动电流驱动下发光；数据信号写入模块连接于发光模块并用于控制驱动电流的大小；控制模块与数据信号写入模块以及发光模块电性连接，控制模块用于在发光时间控制信号的控制下控制发光模块的发光时间。

Description

驱动电路、显示面板及其驱动方法 技术领域
本申请涉及显示技术领域，具体涉及一种驱动电路、显示面板及其驱动方法。
 背景技术
发光二极管在不同的电流密度下，发光波普会发生偏移。具体来说，采用脉冲幅度调制驱动电路控制发光二极管的驱动电流的振幅，也即通过电流大小控制亮度，但其驱动晶体管的阈值电压漂移会引起电流变化导致色偏问题。现有的还使用另外一种脉冲宽度调制驱动电路，通过控制发光二极管的发光时间控制亮度，对发光二极管进行调光，但其驱动晶体管的阈值电压漂移会导致发光时间的变化。脉冲宽度调制驱动电路可以解决发光二极管的色偏问题，驱动器的效率较高，并且能够进行精确控制，但其对驱动电路的补偿范围小，且占用时间长不利于确保驱动电路的发光时长。
因此，亟需提出一种驱动电路，可以实现脉冲幅度调制与脉冲宽度调制混合驱动，使得脉冲宽度调制模块具备内部补偿功能，脉冲幅度调制模块具备外部补偿功能。
 技术问题
本申请提供一种驱动电路、显示面板及其驱动方法，可以实现脉冲幅度调制与脉冲宽度调制混合驱动，并使得控制模块具备内部补偿功能，发光模块具备外部补偿功能。
 技术解决方案
一方面，本申请实施例提供一种驱动电路，包括：发光模块、数据信号写入模块以及控制模块，所述发光模块在驱动电流驱动下发光；所述数据信号写入模块接入第一数据信号以及第一扫描信号，所述数据信号写入模块连接于所述发光模块并用于控制所述驱动电流的大小；所述控制模块接入第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号，并与所述数据信号写入模块以及所述发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间。
可选地，在本申请的一些实施例中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
可选地，在本申请的一些实施例中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
可选地，在本申请的一些实施例中，所述发光模块还包括阈值电压侦测子模块，所述阈值电压侦测子模块接入第四扫描信号以及第三数据信号，所述阈值电压侦测子模块用于侦测所述第一晶体管的阈值电压大小，并对所述第一数据信号对应的数据电压进行补偿。
可选地，在本申请的一些实施例中，所述阈值电压侦测子模块包括第六晶体管，所述第六晶体管的栅极接入所述第四扫描信号，所述第六晶体管的第一电极接入所述第三数据信号，所述第六晶体管的第二电极电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述第二晶体管的第一电极与所述第五晶体管的第一电极电性连接于第五节点，所述第一数据信号和所述第二数据信号为相同信号。
可选地，在本申请的一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管为同类型晶体管。
本申请还提供一种显示面板，包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：发光模块，所述发光模块在驱动电流驱动下发光；数据信号写入模块，接入第一数据信号以及第一扫描信号，所述数据信号写入模块连接于所述发光模块并用于控制所述驱动电流的大小；控制模块，接入第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号，并与所述数据信号写入模块以及所述发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间。
可选地，在本申请的一些实施例中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
可选地，在本申请的一些实施例中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
可选地，在本申请的一些实施例中，所述发光模块还包括阈值电压侦测子模块，所述阈值电压侦测子模块接入第四扫描信号以及第三数据信号，所述阈值电压侦测子模块用于侦测所述第一晶体管的阈值电压大小，并对所述第一数据信号对应的数据电压进行补偿。
可选地，在本申请的一些实施例中，所述阈值电压侦测子模块包括第六晶体管，所述第六晶体管的栅极接入所述第四扫描信号，所述第六晶体管的第一电极接入所述第三数据信号，所述第六晶体管的第二电极电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述第二晶体管的第一电极与所述第五晶体管的第一电极电性连接于第五节点，所述第一数据信号和所述第二数据信号为相同信号。
可选地，在本申请的一些实施例中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管为同类型晶体管。
另一方面，本申请提供一种显示面板的驱动方法，所述显示面板包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路的驱动方法包括：通过第一数据信号以及第一扫描信号控制数据信号写入模块导通，所述数据信号写入模块连接于发光模块并用于控制驱动电流的大小；通过第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号控制模块导通，所述控制模块与所述数据信号写入模块以及发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间；所述驱动电流驱动所述发光模块发光。
可选地，在本申请的一些实施例中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
可选地，在本申请的一些实施例中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
可选地，在本申请的一些实施例中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
 有益效果
本申请提供一种驱动电路、显示面板及其驱动方法，所述发光模块在驱动电流驱动下发光；所述数据信号写入模块接入第一数据信号以及第一扫描信号，所述数据信号写入模块连接于所述发光模块并用于控制所述驱动电流的大小；所述控制模块接入第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号，并与所述数据信号写入模块以及所述发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间。可以实现脉冲幅度调制与脉冲宽度调制混合驱动，并使得控制模块具备内部补偿功能，发光模块具备外部补偿功能。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例提供的驱动电路的结构示意图；
图2为本申请第二实施例提供的驱动电路的结构示意图；
图3是本申请第二实施例提供的驱动电路的电路图；
图4是本申请第二实施例提供的驱动电路的时序图之一；
图5是本申请第二实施例提供的驱动电路的时序图之二；
图6为本申请实施例提供的背光模组的结构示意图；
图7为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种驱动电路、显示面板及其驱动方法，该GOA电路结构简单，能够在保证电路功能的情况下缩小电路布局的空间，增加显示面板的开口率，满足显示面板窄边框及高分辨率的要求。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。另外，在本申请的描述中，术语“包括”是指“包括但不限于”。术语“第一”、“第二”、“第三”等仅仅作为标示使用，其用于区别不同对象，而不是用于描述特定顺序。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请的描述中，按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为漏极、输出端为源极。可以理解的是，本领域技术人员可以按照其理解将信号输入端称为源极，将信号输出端称为漏极。此外本申请实施例所采用的晶体管为N型晶体管或P型晶体管，其中，N型晶体管为在栅极为高电位时导通，在栅极为低电位时截止；P型晶体管为在栅极为低电位时导通，在栅极为高电位时截止。在本申请实施例中，发光器件D可以是，发光器件D可以是迷你发光二极管(Mini Light Emitting Diode，简称Mini LED)，或者，可以是微型发光二极管(Micro Light Emitting Diode，简称Micro LED)，也可以是有机发光二极管(Organic Light Emitting Diode，简称OLED)。
请参阅图1，图1为本申请第一实施例提供的驱动电路的结构示意图；图2为本申请第二实施例提供的驱动电路的结构示意图。如图1所示，本申请实施例提供的驱动电路包括发光模块101、数据信号写入模块102、控制模块103。
其中，发光模块101串接于第一电源端VDD与第二电源端VSS构成的发光回路，并在驱动电流驱动下发光。数据信号写入模块102接入第一数据信号DATA1以及第一扫描信号SCAN1，并电性连接于第一节点G，数据信号写入模块102连接于发光模块101并用于控制驱动电流的大小；控制模块103接入第二数据信号DATA2、发光时间控制信号Sweep、第二扫描信号SCAN2以及第三扫描信号SCAN3，并与数据信号写入模块102以及发光模块101电性连接，控制模块103用于在发光时间控制信号Sweep的控制下控制发光模块101的发光时间。
在本申请实施例中，如图2所示，发光模块101还包括阈值电压侦测子模块1011，阈值电压侦测子模块1011接入第四扫描信号SCAN4以及第三数据信号DATA3，阈值电压侦测子模块1011用于侦测阈值电压大小，并基于阈值电压值对第一数据信号DATA1对应的数据电压进行补偿。
在本申请实施例中，如图2所示，第一数据信号DATA1和第二数据信号DATA2为相同信号。
本申请提供的驱动电路，包括相互独立的控制模块103和阈值电压侦测子模块1011，通过控制模块103控制发光模块101的发光时间，并进行内部补偿，以改善显示均匀性；通过阈值电压侦测子模块1011侦测第一晶体管T1的阈值电压大小，并对第一数据信号DATA1对应的数据电压进行补偿，进而实现脉冲宽度调制和脉冲幅度调制混合驱动。
请参阅图3，图3是本申请第二实施例提供的驱动电路的电路图。如图3所示，本申请实施例提供的驱动电路包括：发光模块101包括第一晶体管T1以及发光器件D；数据信号写入模块102包括第二晶体管T2以及第一电容C1；控制模块103包括第三晶体管T3、第四晶体管T4、第五晶体管T5以及第二电容C2；发光模块101还包括阈值电压侦测子模块1011，阈值电压侦测子模块1011包括第六晶体管T6。
具体地，第一晶体管T1的第一电极与第一电源端VDD电连接，第一晶体管T1的栅极电性连接于第一节点G，第一晶体管T1的第二电极电性连接于第二节点S。第二晶体管T2的栅极接入第一扫描信号SCAN1，第二晶体管T2的第一电极与第五晶体管的第一电极电性连接于第五节点V，以接入第一数据信号DATA1，第二晶体管T2的第二电极接入第一节点G。第三晶体管T3的栅极接入第二扫描信号SCAN2，第三晶体管T3的第一电极电性连接于第三节点P，第三晶体管T3的第二电极电性连接于数据信号写入模块102与发光模块101之间。第四晶体管T4的栅极电性连接于第三节点P，第四晶体管T4的第一电极电性连接于第四节点Q，第四晶体管T4的第二电极与第三晶体管T3的第二电极电性连接。第五晶体管T5的栅极接入第三扫描信号SCAN3，第五晶体管T5的第一电极接入第一数据信号DATA1，第五晶体管T5的第二电极电性连接于第四节点Q。第六晶体管T6的栅极接入第四扫描信号SCAN4，第六晶体管T6的第一电极接入第二数据信号DATA2，第六晶体管T6的第二电极电性连接于第二节点S。第一电容C1的一端与第一节点G电连接，第一电容C1的另一端电性连接于第二节点S。第二电容C2的一端接入发光时间控制信号Sweep，第二电容C2的另一端电性连接于第三节点P。发光器件D的阳极电性连接于第二节点S，发光器件D的阴极电性连接于第二电源端VSS。
需要说明的是，第一电源端VDD和第二电源端VSS均用于输出一预设电压值。此外，在本申请实施例中，第一电源端VDD的电位大于第二电源端VSS的电位。具体的，第二电源端VSS的电位可以为接地端的电位。当然，可以理解地，第二电源端VSS的电位还可以为其它。
本申请的实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6为同类型晶体管。具体地，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6均为P型晶体管或N型晶体管。可以理解的是，在制程工艺的效率允许下，所述各个晶体管也可以为不同类型的晶体管。
需要说明的是，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5以及第六晶体管T6可以为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管或非晶硅薄膜晶体管、场效应晶体管中的一种或者多种。
本申请实施例提供的驱动电路，通过控制发光器件D的发光时间，并对第四晶体管T4的阈值电压进行内部补偿，以改善显示均匀性；同时，通过控制流经发光器件D的驱动电流的大小，并对第一晶体管T1的阈值电压进行外部补偿，进而实现脉冲宽度调制和脉冲幅度调制混合驱动，提升产品竞争力。
请参阅图4和图5，图4是本申请第二实施例提供的驱动电路的时序图之一；图5是本申请第二实施例提供的驱动电路的时序图之二；如图4所示，一方面，控制模块103可以通过补偿第四晶体管T4的阈值电压控制发光时间，该内部补偿过程包括由第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3以及第四扫描信号SCAN4以及发光时间控制信号Sweep相组合先后对应的第一写入补偿阶段t1、第二写入补偿阶段t2、第三写入补偿阶段t3、第四写入补偿阶段及发光阶段t5；也即，在一帧时间内，本申请实施例提供的驱动电路的驱动控制时序包括第一写入补偿阶段t1、第二写入补偿阶段t2、第三写入补偿阶段t3、第四写入补偿阶段及发光阶段t5。需要说明的是，发光器件D在发光阶段t5发光。
具体的，如图3和图4所示，在第一写入补偿阶段t1，第三扫描信号SCAN3为低电位，第一扫描信号SCAN1、第二扫描信号SCAN2以及第四扫描信号SCAN4为高电位，第一数据信号DATA1的大小为第一电压。
第一扫描信号SCAN1为高电位，第二晶体管T2在第一扫描信号SCAN1的高电位控制下打开，从而通过第一数据信号DATA1将第一节点G的电位充至第一电压；第二扫描信号SCAN2为高电位，第三晶体管T3在第二扫描信号SCAN2的高电位控制下打开，从而通过第一数据信号DATA1将第三节点P的电位充至第一电压；第四扫描信号SCAN4为高电位，第六晶体管T6在第四扫描信号SCAN4的高电位控制下打开，从而将第三数据信号DATA3传输至第二节点S。
在第二写入补偿阶段t2，第一扫描信号SCAN1为低电位，第二扫描信号SCAN2、第三扫描信号SCAN3以及第四扫描信号SCAN4为高电位，第一数据信号DATA1的大小为第二电压。
第二扫描信号SCAN2为高电位，第三晶体管T3在第二扫描信号SCAN2的高电位控制下打开，第四晶体管T4的栅极和第四晶体管T4的第二电极通过导通的第三晶体管T3短接，且处于浮置状态；第三扫描信号SCAN3为高电位，第五晶体管T5在第三扫描信号SCAN3的高电位控制下打开，从而通过第一数据信号DATA1将第四节点Q的电位充至第二电压且保持，当流经第四晶体管T4的栅极端电压变为第二电压和第四晶体管T4的阈值电压之和时，第四晶体管T4关闭，此时第四晶体管T4的栅极（第三节点P）和源极（第四节点Q）之间的电压差为第四晶体管T4的阈值电压，因此流经第四晶体管T4源漏极之间的电流大小与第四晶体管T4的阈值电压无关，以完成对第四晶体管T4的内部补偿。另外，第四扫描信号SCAN4为高电位，第六晶体管T6在第四扫描信号SCAN4的高电位控制下打开，从而将第三数据信号DATA3传输至第二节点S。
在第三写入补偿阶段t3，第二扫描信号SCAN2和第三扫描信号SCAN3为低电位，第一扫描信号SCAN1和第四扫描信号SCAN4为高电位，第一数据信号DATA1的大小为第三电压。
第一扫描信号SCAN1为高电位，第二晶体管T2在第一扫描信号SCAN1的高电位控制下打开，第四扫描信号SCAN4为高电位，第六晶体管T6在第四扫描信号SCAN4的高电位控制下打开，从而通过第一数据信号DATA1将第六晶体管T6的栅极端的电位充至第三电压并对第一电容C1充电，第三电压的大小决定了后面的发光阶段中驱动电流的大小。
在第四写入补偿阶段t4，第一扫描信号SCAN1和第二扫描信号SCAN2为低电位，第三扫描信号SCAN3以及第四扫描信号SCAN4为高电位，第一数据信号DATA1的大小为第四电压。
第三扫描信号SCAN3为高电位，第五晶体管T5在第三扫描信号SCAN3的高电位控制下打开，从而通过第一数据信号DATA1将第四节点Q的电位充至第四电压，作为下拉电位存在第四节点Q；另外，第四扫描信号SCAN4为高电位，第六晶体管T6在第四扫描信号SCAN4的高电位控制下打开，从而将第三数据信号DATA3传输至第二节点S。
在发光阶段t5，第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3以及第四扫描信号SCAN4均为低电位。此时，第一晶体管T1打开，发光器件D发光。
进一步地，在发光时段内，利用第二电容C2的耦合效应产生发光时间控制信号Sweep，通过控制发光时间控制信号Sweep对应的扫频电压大小以及持续时间，控制第四晶体管T4的导通时间，进而将第一节点G的电位拉低，导致第一晶体管T1关闭进而控制发光模块的发光时长。
另一方面，阈值电压侦测子模块1011可以通过外部驱动芯片侦测第一晶体管T1的阈值电压，并对第一数据信号DATA1对应的数据电压进行补偿，也即，使得第一晶体管T1和第四晶体管T4的阈值电压在控制模块103和阈值电压侦测子模块1011中分别独立地补偿。具体地，侦测过程包括由第一扫描信号SCAN1、第二扫描信号SCAN2、第三扫描信号SCAN3以及第四扫描信号SCAN4相组合先后对应的写入阶段t1、补偿阶段t2。
具体的，如图5所示，在写入阶段t1，第二扫描信号SCAN2和第三扫描信号SCAN3为低电位，第一扫描信号SCAN1以及第四扫描信号SCAN4为高电位。
第一扫描信号SCAN1为高电位，第二晶体管T2在第一扫描信号SCAN1的高电位控制下打开，从而将第一数据信号DATA1写入第一节点G；第四扫描信号SCAN4为高电位，第六晶体管T6在第四扫描信号SCAN4的高电位控制下打开，从而将第三数据信号DATA3写入第二节点S。
在侦测阶段t2，第二扫描信号SCAN2、第三扫描信号SCAN3以及第四扫描信号SCAN4为低电位，第一扫描信号SCAN1为高电位。
第一扫描信号SCAN1为高电位，第二晶体管T2在第一扫描信号SCAN1的高电位控制下打开，且第六晶体管T6打开，第一电源端VDD给第二节点S充电至第六晶体管T6关闭，第六晶体管T6的阈值电压值存入第一电容C1内，通过外部驱动芯片侦测获得该阈值电压值，或者通过侦测第二节点S的电压以计算出第一晶体管T1的阈值电压，因为此时的第二节点S的电压等于第一数据信号DATA1提供的原始电压值与第一晶体管T1的阈值电压的差值，从而完成侦测，并调整第一数据信号DATA1端提供的电压值为第一晶体管T1的阈值电压和第一数据信号DATA1提供的原始电压值之和，实现对第一晶体管T1的阈值电压补偿。
本申请实施例提供的驱动电路，通过对发光器件D的发光时间和驱动电流大小的独立且同时控制，使得驱动电路具有较长的充电时间；其次，对数据带宽需求不高，具有与普通驱动电路相似的驱动方法；再次，不需要考虑薄膜晶体管中阈值电压漂移及补偿问题，当第二数据信号DATA2的电压适当大时，驱动电流对阈值电压不敏感；最后，由于发光器件D以恒定驱动电流发光，因此可以解决发光器件D光源的波长漂移问题。
请参阅图6，图6为本申请实施例提供的背光模组的结构示意图。本申请实施例还提供一种背光模组100，其包括第一数据线20、第一扫描信号线30、第二扫描信号线40、第三扫描信号线50、第四扫描信号线60、第二数据信号线70、发光时间控制信号线80以及以上的驱动电路10。其中，第一数据线20用于提供第一数据信号DATA1。第一扫描信号线30用于提供第一扫描信号SCAN1。第二扫描信号线40用于提供第二扫描信号SCAN2。第三扫描信号线50用于提供第三扫描信号SCAN3。第四扫描信号线60用于提供第四扫描信号SCAN4。第二数据信号线70用于提供恒定的参考电压、发光时间控制信号线80用于提供扫频电压Sweep。驱动电路10与第一数据线20、第一扫描信号线30、第二扫描信号线40、第三扫描信号线50、第四扫描信号线60、第二数据信号线70、发光时间控制信号线80均连接。其中，发光器件D可以是Mini-LED、Micro-LED。驱动电路10具体可参照以上对该驱动电路的描述，在此不做赘述。
请参阅图7，图7为本申请实施例提供的显示面板的结构示意图。本申请实施例还提供一种显示面板200，包括多个呈阵列排布的像素单元210，每一像素单元210均包括以上的驱动电路10，其中，发光器件D可以是Mini-LED、Micro-LED。具体可参照以上对该驱动电路10的描述，在此不做赘述。
该显示面板可以为：电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上对本申请实施例所提供的一种驱动电路、显示面板及其驱动方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种驱动电路，其包括：
    发光模块，所述发光模块在驱动电流驱动下发光；
    数据信号写入模块，接入第一数据信号以及第一扫描信号，所述数据信号写入模块连接于所述发光模块并用于控制所述驱动电流的大小；
    控制模块，接入第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号，并与所述数据信号写入模块以及所述发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间。
  2. 根据权利要求1所述的驱动电路，其中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；
    所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
  3. 根据权利要求2所述的驱动电路，其中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
  4. 根据权利要求3所述的驱动电路，其中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；
    所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；
    所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；
    所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
  5. 根据权利要求2所述的驱动电路，其中，所述发光模块还包括阈值电压侦测子模块，所述阈值电压侦测子模块接入第四扫描信号以及第三数据信号，所述阈值电压侦测子模块用于侦测所述第一晶体管的阈值电压大小，并对所述第一数据信号对应的数据电压进行补偿。
  6. 根据权利要求5所述的驱动电路，其中，所述阈值电压侦测子模块包括第六晶体管，所述第六晶体管的栅极接入所述第四扫描信号，所述第六晶体管的第一电极接入所述第三数据信号，所述第六晶体管的第二电极电性连接于所述第二节点。
  7. 根据权利要求4所述的驱动电路，其中，所述第二晶体管的第一电极与所述第五晶体管的第一电极电性连接于第五节点，所述第一数据信号和所述第二数据信号为相同信号。
  8. 根据权利要求7所述的驱动电路，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管为同类型晶体管。
  9. 一种显示面板，其包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路包括：
    发光模块，所述发光模块在驱动电流驱动下发光；
    数据信号写入模块，接入第一数据信号以及第一扫描信号，所述数据信号写入模块连接于所述发光模块并用于控制所述驱动电流的大小；
    控制模块，接入第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号，并与所述数据信号写入模块以及所述发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间。
  10. 根据权利要求9所述的显示面板，其中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；
    所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
  11. 根据权利要求10所述的显示面板，其中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
  12. 根据权利要求11所述的显示面板，其中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；
    所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；
    所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；
    所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
  13. 根据权利要求10所述的显示面板，其中，所述发光模块还包括阈值电压侦测子模块，所述阈值电压侦测子模块接入第四扫描信号以及第三数据信号，所述阈值电压侦测子模块用于侦测所述第一晶体管的阈值电压大小，并对所述第一数据信号对应的数据电压进行补偿。
  14. 根据权利要求13所述的显示面板，其中，所述阈值电压侦测子模块包括第六晶体管，所述第六晶体管的栅极接入所述第四扫描信号，所述第六晶体管的第一电极接入所述第三数据信号，所述第六晶体管的第二电极电性连接于所述第二节点。
  15. 根据权利要求12所述的显示面板，其中，所述第二晶体管的第一电极与所述第五晶体管的第一电极电性连接于第五节点，所述第一数据信号和所述第二数据信号为相同信号。
  16. 根据权利要求15所述的显示面板，其中，所述第一晶体管、所述第二晶体管、所述第三晶体管、所述第四晶体管、所述第五晶体管为同类型晶体管。
  17. 一种显示面板的驱动方法，所述显示面板包括多个呈阵列排布的像素单元，所述像素单元包括驱动电路，所述驱动电路的驱动方法包括：
    通过第一数据信号以及第一扫描信号控制数据信号写入模块导通，所述数据信号写入模块连接于发光模块并用于控制驱动电流的大小；
    通过第二数据信号、发光时间控制信号、第二扫描信号以及第三扫描信号控制模块导通，所述控制模块与所述数据信号写入模块以及发光模块电性连接，所述控制模块用于在所述发光时间控制信号的控制下控制所述发光模块的发光时间；
    所述驱动电流驱动所述发光模块发光。
  18. 根据权利要求17所述的显示面板的驱动方法，其中，所述发光模块包括第一晶体管以及发光器件，所述第一晶体管的第一电极与第一电源端电连接，所述第一晶体管的栅极电性连接于第一节点，所述第一晶体管的第二电极电性连接于第二节点；
    所述发光器件的阳极电性连接于所述第二节点，所述发光器件的阴极电性连接于第二电源端。
  19. 根据权利要求18所述的显示面板的驱动方法，其中，所述数据信号写入模块包括第二晶体管以及第一电容，所述第二晶体管的栅极接入所述第一扫描信号，所述第二晶体管的第一电极接入所述第一数据信号，所述第二晶体管的第二电极接入所述第一节点；所述第一电容的一端与所述第一节点电连接，所述第一电容的另一端电性连接于所述第二节点。
  20. 根据权利要求19所述的显示面板的驱动方法，其中，所述控制模块包括第二电容、第三晶体管、第四晶体管以及第五晶体管，所述第二电容的一端接入所述发光时间控制信号，所述第二电容的另一端电性连接于第三节点；
    所述第三晶体管的栅极接入所述第二扫描信号，所述第三晶体管的第一电极电性连接于所述第三节点，所述第三晶体管的第二电极电性连接于所述数据信号写入模块与所述发光模块之间；
    所述第四晶体管的栅极电性连接于所述第三节点，所述第四晶体管的第一电极电性连接于第四节点，所述第四晶体管的第二电极与所述第三晶体管的第二电极电性连接；
    所述第五晶体管的栅极接入所述第三扫描信号，所述第五晶体管的第一电极接入所述第二数据信号，所述第五晶体管的第二电极电性连接于所述第四节点。
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