WO2023203688A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2023203688A1
WO2023203688A1 PCT/JP2022/018307 JP2022018307W WO2023203688A1 WO 2023203688 A1 WO2023203688 A1 WO 2023203688A1 JP 2022018307 W JP2022018307 W JP 2022018307W WO 2023203688 A1 WO2023203688 A1 WO 2023203688A1
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WO
WIPO (PCT)
Prior art keywords
wiring member
brazing material
semiconductor device
internal wiring
conductive pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2022/018307
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English (en)
French (fr)
Japanese (ja)
Inventor
宏哉 山内
裕児 井本
直弘 大串
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to DE112022007088.9T priority Critical patent/DE112022007088T5/de
Priority to CN202280094905.2A priority patent/CN119032419A/zh
Priority to JP2024515974A priority patent/JP7668958B2/ja
Priority to PCT/JP2022/018307 priority patent/WO2023203688A1/ja
Priority to US18/850,310 priority patent/US20250219007A1/en
Publication of WO2023203688A1 publication Critical patent/WO2023203688A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present disclosure relates to a semiconductor device, and particularly relates to a technique for simultaneously connecting wiring members to a plurality of semiconductor elements mounted on a substrate.
  • IGBTs Insulated Gate Bipolar Transistors
  • MOSFETs Metal Oxide Semiconductor Field-Effect Transistors
  • diodes diodes
  • Metal upper and lower electrodes are formed on the front surface (hereinafter referred to as the "upper surface") and the back surface (hereinafter referred to as the "lower surface”) of the semiconductor element, respectively.
  • the upper surface electrode is bonded to the wiring member, and the lower surface electrode are bonded to a substrate, and a brazing material such as solder is generally used for their bonding (for example, Patent Document 1 below).
  • brazing filler metal whose main component is aluminum (Al), which has better heat dissipation and heat resistance than solder (hereinafter referred to as "Al brazing filler metal”).
  • SiC semiconductor elements can have a high current density, so the chip size can be reduced, but as the chip size is reduced, the thermal resistance increases, so it is necessary to devise ways to lower the thermal resistance of the surrounding structure. Further, although SiC semiconductor elements can operate at high temperatures, the melting point of the solder is low, and the operating temperature is limited by the melting point of the solder.
  • the present disclosure has been made to solve the above-mentioned problems, and aims to provide a semiconductor device that can contribute to reducing manufacturing steps, reducing thermal resistance, and increasing operating temperature.
  • a semiconductor device includes: an insulating substrate having a conductive pattern on an upper surface; a semiconductor element having an upper surface electrode on the upper surface and a lower surface electrode on the lower surface; the lower surface electrode being bonded to the conductive pattern of the insulating substrate; an internal wiring member bonded to the top electrode of the semiconductor element, and the bond between the bottom electrode and the conductive pattern and the bond between the top electrode and the internal wiring member contain Al as a main component. It is made of Al brazing material, which is a brazing material.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1.
  • FIG. 1 is a plan view showing an example of the overall configuration of a semiconductor device according to a first embodiment;
  • FIG. It is a figure showing an example of composition of a switching element.
  • It is a figure showing the example of composition of a freewheeling diode.
  • 3 is a flowchart for explaining a method for manufacturing a semiconductor device according to Embodiment 1.
  • FIG. 1 is a diagram for explaining a method for manufacturing a semiconductor device according to a first embodiment;
  • FIG. FIG. 3 is a plan view showing the configuration of a semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device according to a second embodiment.
  • FIG. 3 is a cross-sectional view showing the configuration of a semiconductor device according to a third embodiment.
  • FIG. 1 is a cross-sectional view showing the configuration of a semiconductor device according to the first embodiment.
  • the semiconductor device according to the first embodiment includes a base plate 1, an insulating substrate 3 mounted on the base plate 1 and having a conductive pattern 2 on the upper and lower surfaces, and a conductive pattern on the insulating substrate 3. 2 and a semiconductor element 4 mounted on the semiconductor element 4.
  • the base plate 1 shown in FIG. 1 has a flat plate shape, a base plate 1 with pin fins may be used.
  • the semiconductor element 4 has a top electrode (not shown) on the top surface and a bottom electrode (not shown) on the bottom surface, and the bottom electrode is bonded to the conductive pattern 2 of the insulating substrate 3 using Al brazing material 81. There is. Furthermore, the internal wiring member 5 is bonded to the upper surface electrode of the semiconductor element 4 using an Al brazing material 82 . In other words, both the bonding between the bottom electrode and the conductive pattern 2 and the bonding between the top electrode and the internal wiring member 5 are made using an Al-based brazing material.
  • the composition of the Al brazing material 81 that joins the bottom electrode and the conductive pattern 2 may be the same as the composition of the Al brazing material 82 that joins the top electrode and the internal wiring member 5. Thereby, the melting points of the Al brazing material 81 and the Al brazing material 82 can be made the same. Furthermore, the conductive pattern 2 of the insulating substrate 3, the upper and lower electrodes of the semiconductor element 4, and the internal wiring member 5 are preferably formed of a material containing Al as a main component.
  • brazing filler metal 83 does not necessarily have to be an Al brazing filler metal, but is preferably an Al brazing filler metal.
  • a case 11 containing an insulating substrate 3, a semiconductor element 4, and an internal wiring member 5 is adhered to the base plate 1 using an adhesive 10.
  • the case 11 is sealed with a sealing material 12 filled inside the case 11 .
  • the case 11 includes an external wiring member 6 that is an external connection terminal formed integrally with the case 11, and the external wiring member 6 is bonded to the conductive pattern 2 of the insulating substrate 3 using a brazing material 84. ing.
  • this brazing material 84 does not necessarily have to be an Al brazing material, it is preferably an Al brazing material.
  • the portion of the internal wiring member 5 that connects to the semiconductor element 4 has a size that is the same as or larger than the external shape of the semiconductor element 4. That is, it is preferable that the width of the joint portion of the internal wiring member 5 with the upper surface electrode of the semiconductor element 4 is equal to or greater than the width of the semiconductor element 4.
  • both the bonding between the conductive pattern 2 and the semiconductor element 4 and the bonding between the semiconductor element 4 and the internal wiring member 5 are made using Al brazing material. Since the thermal conductivity of Al brazing material (170 W/m ⁇ K) is higher than that of conventional solder (55 W/m ⁇ K), it can contribute to reducing the thermal resistance of semiconductor devices. Furthermore, since the melting point of Al brazing material (approximately 600° C.) is higher than that of conventional solder (approximately 220° C.), it can also contribute to increasing the operating temperature of semiconductor devices. Therefore, the first embodiment is particularly effective for a semiconductor device including a semiconductor element 4 made of a wide bandgap semiconductor such as SiC or GaN that can operate at high temperatures.
  • FIG. 2 is a plan view showing an example of the overall configuration of the semiconductor device according to the first embodiment.
  • the cross-sectional view shown in FIG. 1 corresponds to the cross-section taken along line AB shown in FIG.
  • the semiconductor device shown in FIG. 2 constitutes a three-phase inverter circuit, and includes six switching elements 4a to 4f and six freewheeling diodes 4g to 4l as semiconductor elements 4. Further, as the internal wiring members 5, an internal wiring member 5a connected to the switching element 4a and the freewheeling diode 4g, an internal wiring member 5b connected to the switching element 4b and the freewheeling diode 4h, and an internal wiring member 5b connected to the switching element 4c and the freewheeling diode 4i.
  • An internal wiring member 5f joined to is provided.
  • external wiring members 6a and 6b that serve as input terminals of the inverter and external wiring members 6c, 6d, and 6e that serve as output terminals of the inverter are provided.
  • all six internal wiring members 5 (5a to 5f) joined to the plurality of semiconductor elements 4 (4a to 4l) have the same shape. Thereby, the cost (for example, manufacturing cost and management cost) required for the internal wiring member 5 can be suppressed. All of the plurality of internal wiring members 5 do not have to have the same shape, and as long as two or more of the plurality of internal wiring members 5 have the same shape, the effect of cost reduction can be obtained.
  • the semiconductor device in FIG. 2 also includes a plurality of signal terminals 7 for inputting control signals for the switching elements 4a to 4f.
  • Each of the signal terminals 7 is connected to a signal pad (signal pad 14 in FIG. 3, which will be described later) of the switching elements 4a to 4f via a bonding wire 9.
  • the switching elements 4a to 4f are, for example, IGBTs or MOSFETs.
  • FIG. 3 shows a configuration example of the switching elements 4a to 4f, and shows a top view and a sectional view of the switching elements 4a to 4f.
  • an insulating layer 13 is formed on the ineffective region of the switching elements 4a to 4f, and an electrode 15 made of an Al-based material (hereinafter referred to as "Al electrode”) serves as an upper surface electrode for switching.
  • Al electrode Al-based material
  • the freewheeling diodes 4g to 4l are, for example, Schottky barrier diodes or PN junction diodes.
  • FIG. 4 shows a configuration example of the freewheeling diodes 4g to 4l, and shows a top view and a cross-sectional view of the freewheeling diodes 4g to 4l.
  • an insulating layer 13 is formed on the ineffective region of the freewheeling diodes 4g to 4l, and an Al electrode 15 as an upper surface electrode is formed on the entire upper surface of the freewheeling diodes 4g to 4l. Layer 13 is covered with an Al electrode 15.
  • the semiconductor element 4 which is a switching element
  • the semiconductor element 4 which is a free-wheeling diode
  • It may also be a MOSFET or RC-IGBT (Reverse Conducting IGBT) with a built-in.
  • the insulating substrate 3 mounted on the base plate 1 is prepared, and the Al brazing material 81, which is the first Al brazing material, is placed on the conductive pattern 2 of the insulating substrate 3 (Step S1).
  • the semiconductor element 4 is placed on the first Al brazing material (Al brazing material 81) (Step S2).
  • an Al brazing material 82 which is a second Al brazing material, is placed on the semiconductor element 4 (step S3).
  • the internal wiring member 5 is placed on the second Al brazing material (Al brazing material 82) (Step S4).
  • Al brazing material 81, semiconductor element 4, Al brazing material 82, and internal wiring member 5 are laminated in this order on conductive pattern 2 of insulating substrate 3.
  • the Al brazing material 81, the semiconductor element 4, the Al brazing material 82, and the internal wiring member 5 placed in steps S1 to S4 may be temporarily fixed with an adhesive or the like so that the positions do not shift.
  • step S5 heat treatment is performed while applying pressure to the internal wiring member 5 from above (step S5).
  • the semiconductor element 4 and the conductive pattern 2 are bonded using the first Al brazing material (Al brazing material 81), and the semiconductor element 4 and the internal wiring member 5 are bonded together using the second Al brazing material (Al brazing material 81). material 82).
  • the conductive pattern 2 and the semiconductor element 4 can be bonded together, and the semiconductor element 4 and the internal wiring member 5 can be bonded at the same time, and the manufacturing process can be simplified. It can contribute to reduction.
  • solder as a brazing material, it is necessary to provide a layer for solder bonding (for example, a Ni layer) on the surfaces of the upper and lower electrodes of the semiconductor element 4, but this is also unnecessary. , it can contribute to the reduction of manufacturing processes.
  • the brazing material 83 for the bonding is also an Al brazing material.
  • the internal wiring member 5 and the conductive pattern 2 can be joined together at the same time as step S5.
  • the brazing filler metal 83 also has the same composition as the Al brazing filler metal 81 and the Al brazing filler metal 82.
  • the brazing material 84 that joins the external wiring member 6 and the conductive pattern 2 of the insulating substrate 3 is also an Al brazing material.
  • the brazing filler metal 84 also has the same composition as the Al brazing filler metal 81 and the Al brazing filler metal 82.
  • the Al brazing material 81 may be made into an integral component with the insulating substrate 3 by forming the conductive pattern 2 of the insulating substrate 3 with a cladding material of Al brazing material and Al alloy.
  • “Clad material” refers to a material made by bonding two or more different metals together.
  • the Al brazing material 82 may be made into an integral component with the internal wiring member 5 by forming the internal wiring member 5 with a cladding material of an Al brazing material and an Al alloy.
  • step S3 described above can be omitted, which can further contribute to reducing the number of manufacturing steps. Additionally, reducing the number of parts can also contribute to reducing parts management costs.
  • an upper surface electrode is formed on almost the entire upper surface of the semiconductor element 4, and furthermore, the width of the joint portion of the internal wiring member 5 with the upper surface electrode of the semiconductor element 4 is the same as that of the semiconductor element 4. It is preferably equal to or greater than the width. By doing so, pressure can be applied to the entire semiconductor element 4 in the heat treatment in step S5 described above, and the semiconductor element 4, conductive pattern 2, and internal wiring member 5 can be stably bonded.
  • the heat treatment in step S5 may be performed on the plurality of semiconductor elements 4 at the same time. Therefore, even if the number of semiconductor elements 4 increases, the increase in takt time is suppressed.
  • the semiconductor device according to the first embodiment can contribute to reducing the number of manufacturing steps, reducing thermal resistance, and increasing the operating temperature.
  • FIG. 7 is a plan view showing the configuration of a semiconductor device according to the second embodiment. 7 corresponds to a part of the plan view of the semiconductor device shown in FIG. ing. Further, FIG. 8 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment, and shows a cross section taken along line CD shown in FIG. 7, that is, a cross section including the signal wiring member 17.
  • the signal wiring member 17 and the semiconductor element 4 are joined by an Al brazing material 85, and the signal wiring member 17 and the signal terminal 7 are joined by an Al brazing material 86. It is preferable that the Al brazing material 85 and the Al brazing material 86 have the same composition as the Al brazing material 81 and the Al brazing material 82. Furthermore, like the internal wiring member 5, the signal wiring member 17 is preferably formed of a material containing Al as a main component.
  • connection between the semiconductor element 4 and the signal terminal 7 (that is, the connection between the semiconductor element 4 and the signal wiring member 17 and the connection between the signal terminal 7 and the signal wiring member 17) ) can be performed at the same time as step S5 in FIG. 5, which can further contribute to reducing the number of manufacturing steps.
  • FIG. 9 is a plan view showing the configuration of a semiconductor device according to the third embodiment.
  • the core material 19 having a certain thickness is inserted into the inside of the material 82.
  • the material of the core material 19 for example, Al or a cladding material of an Al brazing material and an Al alloy can be used.
  • the thickness of the Al brazing material 81 and the Al brazing material 82 can be ensured. , the thicknesses of the Al brazing filler metal 81 and the Al brazing filler metal 82 become uniform, and it is possible to prevent the semiconductor element 4 from tilting. Eliminating the tilt of the semiconductor element 4 can contribute to stabilizing the thermal resistance of the semiconductor device and stabilizing the manufacturing process.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
PCT/JP2022/018307 2022-04-20 2022-04-20 半導体装置および半導体装置の製造方法 Ceased WO2023203688A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE112022007088.9T DE112022007088T5 (de) 2022-04-20 2022-04-20 Halbleitervorrichtung und Produktionsverfahren für eine Halbleitervorrichtung
CN202280094905.2A CN119032419A (zh) 2022-04-20 2022-04-20 半导体装置及半导体装置的制造方法
JP2024515974A JP7668958B2 (ja) 2022-04-20 2022-04-20 半導体装置および半導体装置の製造方法
PCT/JP2022/018307 WO2023203688A1 (ja) 2022-04-20 2022-04-20 半導体装置および半導体装置の製造方法
US18/850,310 US20250219007A1 (en) 2022-04-20 2022-04-20 Semiconductor device and method of manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
PCT/JP2022/018307 WO2023203688A1 (ja) 2022-04-20 2022-04-20 半導体装置および半導体装置の製造方法

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013071873A (ja) * 2011-09-28 2013-04-22 Nhk Spring Co Ltd 接合体
JP2016072575A (ja) * 2014-10-02 2016-05-09 三菱電機株式会社 半導体装置およびその製造方法
JP2016082048A (ja) * 2014-10-16 2016-05-16 三菱電機株式会社 半導体装置
JP2016139635A (ja) * 2015-01-26 2016-08-04 三菱電機株式会社 電力用半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013071873A (ja) * 2011-09-28 2013-04-22 Nhk Spring Co Ltd 接合体
JP2016072575A (ja) * 2014-10-02 2016-05-09 三菱電機株式会社 半導体装置およびその製造方法
JP2016082048A (ja) * 2014-10-16 2016-05-16 三菱電機株式会社 半導体装置
JP2016139635A (ja) * 2015-01-26 2016-08-04 三菱電機株式会社 電力用半導体装置

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US20250219007A1 (en) 2025-07-03
JP7668958B2 (ja) 2025-04-25
JPWO2023203688A1 (https=) 2023-10-26
CN119032419A (zh) 2024-11-26
DE112022007088T5 (de) 2025-04-10

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