Definitions

• the present invention relates to a columnar semiconductor memory device and a manufacturing method thereof.
• the channel In a typical planar MOS transistor, the channel extends in the horizontal direction along the upper surface of the semiconductor substrate. In contrast, the channel of the SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Patent Document 1 and Non-Patent Document 1). Therefore, the SGT allows higher density semiconductor devices than planar MOS transistors.
• This SGT is used as a selection transistor to create a DRAM (Dynamic Random Access Memory) connected to a capacitor (see, for example, Non-Patent Document 2), a PCM (Phase change Memory) connected to a variable resistance element (see, for example, Non-Patent Document 3). ), RRAM (Resistive Random Access memory, see e.g. Non-Patent Document 4), MRAM (Magneto-resistive Random Access memory, see e.g. Non-Patent Document 5), which changes the resistance by changing the direction of magnetic spin using an electric current. ), etc. can be highly integrated.
• FIG. 8 shows a schematic structural diagram of an N-channel SGT.
• a semiconductor pillar 100 (hereinafter, a silicon semiconductor pillar will be referred to as a "semiconductor pillar") having a conductivity type of P type or i type (intrinsic type) is provided at the upper and lower positions in which one becomes a source and the other becomes a drain.
• N + layers 101a and 101b (hereinafter, a semiconductor region containing a high concentration of donor impurities will be referred to as an "N + layer”) are formed.
• a gate insulating layer 103 is formed to surround this channel region 102.
• a gate conductor layer 104 is formed to surround this gate insulating layer 103.
• N + layers 101a and 101b, which serve as sources and drains, a channel region 102, a gate insulating layer 103, and a gate conductor layer 104 are formed into a columnar shape as a whole.
• a capacitor is connected to the N + layer 101b in a DRAM, and a variable resistance element 105 is connected in a PCM, RRAM, and MRAM.
• the area occupied by the SGT corresponds to the area occupied by a single source or drain N + layer of a planar MOS transistor.
• the circuit chip having the SGT can achieve further reduction in chip size compared to the circuit chip having the planar MOS transistor.
• a method for manufacturing a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; forming the first impurity region in a strip-like manner in a first direction when viewed from above; forming the semiconductor pillar so as to overlap at least a portion of the first impurity region in a plan view;
• the substrate and the first impurity region at the bottom of the semiconductor pillar are etched, and the etched region consisting of the substrate and the first impurity region and extending in the first direction is used as a semiconductor board.
• the first conductor layer has a shape extending in a band shape in the second direction so as to connect the gate conductor layers adjacent to each other in a second direction perpendicular to the first direction in a plan view. process and etching the first conductor layer so that the upper surface position thereof is the same as or lower than the upper end of the gate conductor layer; It is characterized
• the method for manufacturing the columnar semiconductor device includes: After polishing and planarizing the first insulating layer, The first insulating layer is formed such that at least a portion of the upper surface of the gate conductor layer is exposed and a band-shaped groove extends in a second direction perpendicular to the first direction in plan view.
• the method for manufacturing the columnar semiconductor device includes: After polishing and planarizing the first insulating layer, At least the upper surface of the gate conductor layer is exposed, and extends in a band shape in the second direction perpendicular to the first direction in plan view, and the width of the groove bottom is wider than the width of the groove top. etching the first insulating layer so that it becomes smaller; Covering the entire surface with a first conductor layer; polishing and planarizing the first conductor layer; etching so that the upper surface position of the first conductor layer is the same as or lower than the upper end of the gate conductor layer, and forming the first conductor layer at the bottom of the band-shaped groove. , It is desirable that it be characterized by:
• a method for manufacturing a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; forming the first impurity region in a strip-like manner in a first direction when viewed from above; forming the semiconductor pillar so as to overlap at least a portion of the first impurity region in a plan view;
• the substrate and the first impurity region at the bottom of the semiconductor pillar are etched, and the etched region consisting of the substrate and the first impurity region and extending in the first direction is used as a semiconductor board.
• a method for manufacturing a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; forming the first impurity region in a strip-like manner in a first direction when viewed from above; forming the semiconductor pillar so as to overlap at least a portion of the first impurity region in a plan view;
• the substrate and the first impurity region at the bottom of the semiconductor pillar are etched, and the etched region consisting of the substrate and the first impurity region and extending in the first direction is used as a semiconductor board.
• a method for manufacturing a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; forming the semiconductor pillar so as to overlap at least a portion of the first impurity region in a plan view; The substrate and the first impurity region at the bottom of the semiconductor pillar are etched, and the etched region consisting of the substrate and the first impurity region and extending in a band shape in a first direction is used as the semiconductor base.
• a step of forming it so as to be connected to the bottom of the semiconductor pillar After forming the gate conductor layer, covering the entire surface with a first insulating layer and polishing and planarizing; In a plan view, a contact hole extending in a band shape in the first direction is formed in the first insulating layer, overlapping the first impurity region on the semiconductor mount, and having a bottom in contact with the first impurity region.
• a step of forming into a layer forming a second conductor layer extending in a strip shape in the first direction in contact with the first impurity region at the bottom of the contact hole; forming a fourth insulating layer containing holes or made of a low dielectric constant material in the contact hole on the second conductor layer; etching the fourth insulating layer so that an upper part of the gate conductor layer is exposed; forming a first conductor layer covering the entire surface, being in contact with the upper side surface of the gate conductor layer, and on the fourth insulating layer, the upper end of the hole being in contact with the upper side surface of the gate conductor layer, and forming a first conductor layer on the fourth insulating layer; formed lower than the conductor layer, It is characterized by
• a method for manufacturing a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; forming a semiconductor pillar so as to overlap at least a portion of the first impurity region in plan view using a first mask material layer as an etching mask; forming a fifth insulating layer that surrounds the semiconductor pillar and whose upper surface is located at the bottom of the first mask material layer or at the top of the semiconductor pillar; forming a second mask material layer that surrounds the exposed first mask material layer on the fifth insulating layer and the top of the semiconductor pillar with equal width in a plan view; forming a third mask material layer on the fifth insulating layer, partially overlapping the second mask material layer in plan view and extending in a band shape in the first direction; Using the first mask material layer, the second mask material layer, and the third mask material layer as
• a contact hole extending in a band shape in the first direction is formed in the gate conductor layer, overlapping with the first impurity region on the semiconductor pedestal and having its bottom in contact with the first impurity region.
• a first insulating layer covering the forming a second conductor layer extending in a strip shape in the first direction in contact with the first impurity region at the bottom of the contact hole; forming a fourth insulating layer containing holes or made of a low dielectric constant material in the contact hole on the second conductor layer; etching the fourth insulating layer so that the upper part of the gate conductor layer is exposed; forming a first conductor layer covering the entire surface, in contact with the upper side surface of the gate conductor layer, and on the fourth insulating layer; In a plan view, a portion of the third mask material layer extends in a second direction perpendicular to the first direction, with the semiconductor column in between, and the second mask material layer is located on the opposite side of the first conductor layer.
• the contact hole is characterized in that it protrudes from the mask material layer, and the contact hole is formed in the protruding region.
• the method for manufacturing the columnar semiconductor device includes: In the vertical direction, an upper end position of the second conductor layer is formed lower than a lower end position of the gate conductor layer. It is desirable that it be characterized by:
• the method for manufacturing the columnar semiconductor device includes: In the vertical direction, the upper end position of the hole is formed lower than the upper end position of the gate conductor layer. It is desirable that it be characterized by:
• the method for manufacturing the columnar semiconductor device includes: In the first direction in a plan view, the width of the first conductor layer is the most within the distance between two points where the outer circumferential line of the gate conductor layer intersects the straight line extending in the first direction. formed smaller than a long line segment, It is desirable that it be characterized by:
• a columnar semiconductor device includes: A semiconductor pillar standing perpendicular to the substrate, a first impurity region at the bottom of the semiconductor pillar functioning as a source or a drain, and a second impurity region functioning as a source or drain at the top of the semiconductor pillar.
• a columnar semiconductor device comprising: a gate conductor layer surrounding the gate insulating layer; a first conductor layer that is in contact with the upper part of the gate conductor layer and extends in a band shape so as to connect the adjacent gate conductor layers to each other in a plan view;
• the first conductor layer is formed spaced apart from the substrate when viewed vertically. It is characterized by
• the columnar semiconductor device includes: In plan view, a semiconductor pedestal connected to the bottom of the semiconductor column, including the first impurity region, and extending in a strip shape in the first direction; a first insulating layer on the outer periphery of the gate conductor layer; In the first insulating layer, in a plan view, a band-shaped layer extends in the first direction, overlaps with the first impurity region in the semiconductor mount, and has a bottom in contact with the first impurity region.
• a first material layer extending and vertically connected; a first conductor layer on the bottom of the first material layer, which extends in a strip shape in the first direction in contact with the first impurity region; a second insulating layer that is on the first conductor layer and includes holes whose upper surface is lower than the upper end of the gate conductor layer, or is made of a low dielectric constant material; a second conductor layer that is on the second insulating layer, is in contact with the gate conductor layer, and extends in a strip shape in a second direction perpendicular to the first direction in plan view. , It is desirable that it be characterized by:
• the columnar semiconductor device includes: In a plan view, a part of the semiconductor mount surrounding the semiconductor pillar in contact with the first conductor layer protrudes in the second direction from the semiconductor mount on the opposite side with the semiconductor pillar in between. It is desirable that it be characterized by:
• the columnar semiconductor device includes: In the vertical direction, an upper end position of the second conductor layer is lower than a lower end position of the gate conductor layer. It is desirable that it be characterized by:
• the columnar semiconductor device includes: In the vertical direction, the upper end position of the hole is formed lower than the upper end position of the gate conductor layer. It is desirable that it be characterized by:
• the columnar semiconductor device includes: In a plan view, the width of the first conductor layer in the first direction is the longest line among the distances between two points where the outer circumferential line of the gate conductor layer and a straight line extending in the first direction intersect. less than a minute, It is desirable that it be characterized by:
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a second embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a second embodiment.
• FIG. 1A and 1B are a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a first embodiment
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a second embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a third embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a third embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fourth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fifth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fifth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fifth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a sixth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a sixth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a sixth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fifth embodiment.
• FIG. 7 is a plan view and a cross-sectional structure diagram for explaining a method of manufacturing a memory semiconductor device having an SGT according to a fifth embodiment.
• FIG. 3 is a three-dimensional structure diagram for explaining a conventional example.
• FIGS. 1A to 1N shows a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• N + layers 2a and 2b extending in a band shape in the Y-Y' line direction in plan view are provided.
• a P layer 4 is formed by epitaxial growth.
• Mask material layers 5a, 5b, 5c, and 5d each having a circular shape in plan view are formed on P layer 4 so as to partially overlap N + layers 2a and 2b in plan view.
• the upper parts of the P layer 4, the P layer substrate 1, the N + layers 2a and 2b are etched, and the semiconductor pillars 7a and 7b are etched.
• 7c, and 7d (which are examples of "semiconductor pillars" in the claims).
• a silicon nitride (SiN) layer 9 is formed around the outer periphery of the semiconductor pillars 7a to 7d so that its upper surface is at the top of the semiconductor pillars 7a to 7d.
• silicon oxide (SiO 2 ) layers 10a, 10b, 10c, and 10d are formed to surround the tops of the semiconductor pillars 7a to 7d and the side surfaces of the mask material layers 5a to 5d with the same width in a plan view.
• the SiO 2 layers 10a to 10d may be formed by covering the mask material layers 5a to 5d with a SiO 2 layer (not shown) and then etching by, for example, an RIE (Reactive Ion Etching) method. good. Thereby, in plan view, the SiO 2 layers 10a to 10d are formed with equal width around the mask material layers 5a to 5d.
• the SiO 2 layers 10a to 10d are formed in a self-aligned manner with respect to the semiconductor pillars 7a to 7d.
• the SiN layer 9 may be formed after forming a thin SiO 2 layer (not shown) on the side surfaces of the semiconductor pillars 7a to 7d.
• the SiO 2 layers 10a to 10d and the SiN layers 9a and 9b are removed.
• the SiO 2 layer 13 is formed to surround the P-layer tables 12a and 12b so that its top surface is above the top surface of the P-layer tables 12a and 12b.
• a hafnium oxide (HfO 2 ) layer 14 (which is an example of a "gate insulating layer” in the claims) is formed as a gate insulating layer by, for example, an ALD (Atomic Layer Deposition) method, surrounding the semiconductor pillars 7a to 7d. do.
• a TiN layer (not shown) is formed to cover the HfO 2 layer 14 and serve as a gate conductor layer.
• the upper surface is polished to the upper surface of mask material layers 5a to 5d by a CMP (Chemical Mechanical Polishing) method.
• the TiN layer is etched by anisotropic etching until the upper surface reaches the top of the semiconductor pillars 7a to 7d, thereby forming the TiN layer 15.
• the entire surface is covered with a SiN layer (not shown), and the SiN layer is etched by RIE to form side surfaces of the mask material layers 5a to 5d and the tops of the semiconductor pillars 7a to 7d.
• SiN sidewall layers 17a, 17b, 17c, and 17d are formed.
• the TiN layer 15 is etched by RIE to remove the TiN layers 15a, 15b, 15c, and 15d, which are gate conductor layers ( (this is an example of a "gate conductor layer").
• the SiN layers 17a to 17d which are etching masks, are formed in self-alignment with respect to the semiconductor pillars 7a to 7d
• the TiN layers 15a to 15d are also formed in self-alignment with respect to the semiconductor pillars 7a to 7d. is formed.
• a SiO 2 layer (not shown, which is an example of the "first insulating layer” in the claims) is formed to cover the entire surface, and the top surface position is adjusted by CMP.
• the SiO 2 layer 16 is formed by polishing to the upper surface position of the mask material layers 5a to 5d.
• the SiO 2 layer is recess-etched so that its top surface is lower than the tops of the gate electrodes 15a and 15b, thereby forming the SiO 2 layer 16.
• a W layer (not shown) is formed to cover the entire surface, and is polished by CMP so that the upper surface position corresponds to the upper surface position of the mask material layers 5a to 5d.
• Form layer 26 is formed to cover the entire surface, and is polished by CMP so that the upper surface position corresponds to the upper surface position of the mask material layers 5a to 5d.
• a photolithography method is used to form a mask material layer 27a that partially overlaps the mask material layers 5a and 5b in plan view and extends in a band shape in the XX' line direction.
• a mask material layer 27b is formed which partially overlaps the mask material layers 5c and 5d and extends in a band shape in the direction of the XX' line.
• the W layer is etched using the mask material layers 27a and 27b as a mask.
• the W layer is recess-etched.
• the word line W layer 26a (which is an example of the "second direction” in the claims) is connected to the layers 15a and 15b and extends in the XX' line direction (which is an example of the "second direction” in the claims) in plan view. (which is an example of the "first conductor layer”) and the TiN layers 15c and 15d, and in the XX' line direction (which is an example of the "second direction” in the claims) in plan view.
• a word line W layer 26b (which is an example of a "first conductor layer” in the claims) is formed.
• the width L1 of the W layers 26a and 26b in the YY' line direction is formed to be smaller than the width L2 of the outer periphery of the gate TiN layers 15a and 15b in the YY' line direction.
• L2 is the longest line segment among the distances between two points where the outer periphery of the gate TiN layers 15a, 15b and the straight line extending in the YY' line direction intersect.
• the SiN layers 17a to 17d serving as etching masks are removed, the entire surface is covered with a SiO 2 layer 28, and the upper surface is polished by CMP until the upper surface of the mask material layers 5a to 5d. Then, as shown in FIG. 1M, recess etching is performed so that the upper surface of the SiO 2 layer 28 is higher than the upper end positions of the TiN layers 15a and 15b.
• N + layers 29a, 29b, 29c, and 29d are formed by, for example, selective epitaxial method, covering the tops of the semiconductor pillars 7a to 7d. do.
• N + layers 30a, 30b, 30c, and 30d are formed on the tops of the semiconductor pillars 7a to 7d by thermal diffusion. .
• the N + layers 2aa and 2bb become bit lines, and the W layers 26a and 26b become word lines.
• a capacitor is connected to the N + layers 29a to 29d.
• a DRAM device is formed on the P layer substrate 1a.
• silicide may be formed on the upper surfaces of the N + layers 2aa and 2bb. Further, a metal buried layer may be formed so as to be in contact with a portion of the N + layers 2aa and 2bb. Further, although an example has been described in which the N + layers 2aa and 2bb are formed partially inside the semiconductor pillars 7a to 7d in plan view, they may be formed over the entire surface. Furthermore, in RRAM, MRAM, PCM, etc., instead of the capacitor of DRAM, a variable resistance element whose resistance changes depending on the applied voltage is connected to each of them.
• the N + layers 2aa and 2bb may be formed on the entire inside of the semiconductor pillars 7a to 7d in plan view. Further, in a capacitorless DRAM (for example, see Non-Patent Document 6), the N + layers 2aa and 2bb may be formed over the entire surface of the semiconductor pillars 7a to 7d in plan view. Further, in a capacitorless DRAM or a tunnel type SGT, the polarity of the impurity regions serving as the upper and lower sources or drains of the SGT may be different (see, for example, Non-Patent Document 7).
• the W layers 22a and 22b are bit line electrodes, but in RRAM, MRAM, PCM, etc., the W layers 22a and 22b are used as source line electrodes, ground line electrodes, etc. It may also be used as an electrode.
• the N + layers 30a to 30d formed on the tops of the semiconductor pillars 7a to 7d are formed, for example, after the P layer 4 is formed in FIG. 1B and before the mask material layers 5a to 5d are formed.
• An N + layer formed by epitaxial crystal growth on layer 4 may also be used.
• the step shown in FIG. 1N of performing heat treatment to diffuse donor impurities from the N + layers 29a to 29d to the tops of the semiconductor pillars 7a to 7d to form the N + layers 30a to 30d becomes unnecessary. .
• the SiO 2 layer 28 When the SiO 2 layer 28 is thick, if a long heat treatment is performed at high temperature so that the lower ends of the N + layers 30a to 30d become the upper ends of the gate TiN layers 15a to 15d in the vertical direction, the gate TiN layers 15a to 15d, the gate Damage to the HfO 2 layer 14, which is an insulating layer, becomes a problem.
• an N + layer is formed on the P layer 4, and these impurity layers form the N + layers 30a to 30d. Heat damage to the layers 15a to 15d and the HfO 2 layer 14, which is the gate insulating layer, can be avoided.
• N + layers 30a to 30d since it is not necessary to form N + layers 30a to 30d by thermal diffusion on the tops of the semiconductor pillars 7a to 7d at the stage of FIG. 1N, it becomes easy to form impurity regions on the tops of the semiconductor pillars 7a to 7d. Further, in this case, the N + layers 29a to 29d may or may not be formed. Further, in this case, a conductive layer such as a metal or an alloy may be used instead of the N + layers 29a to 29d.
• the TiN layer 15 is used as the gate conductor layer, but the thickness of the TiN layer 15 is made thinner than the SiN layers 17a, 17b, 17c, and 17d, and a conductor such as TaN is formed on the outside of the TiN layer 15. or an insulating layer such as a SiN layer may be provided as a protective layer for the TiN layer 15.
• this protective layer is left surrounding the side surfaces of the gate TiN layers 15a to 15d. If an insulating layer is formed on this protective layer, the protective layer on the top side surfaces of the gate TiN layers 15a to 15d is removed before forming the W layers 26a and 26b in FIG. 1L.
• boron (B) impurities are contained in the N + layers 2a and 2b in a smaller amount than phosphorus (P) impurities, and then the B impurities are diffused into the P layer substrate 1 by heat treatment .
• a P + layer may be formed outside the layers 2a and 2b.
• this P + layer may be formed by epitaxial crystal growth before forming N + layers 2a and 2b by epitaxial crystal growth.
• this P + layer may be formed by other methods as long as they meet the purpose.
• an impurity region having a polarity opposite to that of the upper or lower impurity region may be formed outside one of the upper or lower impurity regions by the same method.
• the SiO 2 layer 16 is formed around the semiconductor pillars 7a to 7d, but it does not have to be SiO 2 and can be formed by using a low dielectric film according to the purpose of this patent. , a greater effect on reducing parasitic capacitance can be obtained.
• the first embodiment has the following features. 1. As shown in FIG. 1L, the word line 26a is connected to the gate conductor layers 15a and 15b, the word line 26b is connected to the gate electrodes 15c and 15d, and the lower surface thereof is connected to the P layer substrates 1a and 1b, the bit line N + Since it is formed apart from the layers 2aa and 2bb, the parasitic capacitance between the word line, the substrate, and the bit line is reduced, and high performance can be achieved. 2. Similarly, since the film thickness of the word line is also formed thin, the parasitic capacitance between the word lines 26a and 26b is also reduced, and high performance can be achieved as in the previous section.
• FIGS. 2A to 2C show a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• a resist layer (not shown) is formed so as to extend in the X direction and at least the tops of the SiN layers 17a, 17b, 17c, and 17d are exposed in a plan view, and using this as a mask, As shown in FIG. 3A, the SiN hard mask layer 19 is etched to form band-shaped SiN layers 19a, 19b, and 19c.
• the SiO 2 layer 16 is anisotropically etched so that the top side walls of the gate conductor layers 15a to 15d are exposed. Etching is performed to form word line groove portions 18a and 18b (which are an example of a "band-shaped groove” in the claims) extending in the X direction in plan view.
• the entire surface is covered with a W layer 26, and the entire surface is polished by CMP until the upper surface position becomes the upper surface of the mask material layers 5a to 5d (not shown), and as shown in FIG. 2C.
• recess etching is performed at the bottoms of the word line grooves 18a, 18b so that the W layer 26 has a desired thickness, thereby forming the W layers 26a, 26b which will become word lines.
• the second embodiment has the following features. Compared to the first embodiment, the number of recess etching steps with low controllability is reduced by one, which is advantageous in terms of cost reduction and process controllability, and greatly contributes to the cost and yield of the semiconductor device.
• FIGS. 3A and 3B show a method for manufacturing a DRAM circuit according to a third embodiment of the present invention.
• (a) shows a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• the steps from FIG. 1A to FIG. 1H of the first embodiment and the steps of FIG. 2A of the second embodiment are performed, and then, as shown in FIG. 3A, the SiO 2 layer is 16 is etched by taper etching so that the side walls at the tops of the gate electrodes 15a to 15d are exposed, thereby forming word line grooves 23a and 23b extending in the X direction in plan view.
• the entire surface is covered with a W layer 26, and the entire surface is polished by CMP until the upper surface position becomes the upper surface of the mask material layers 5a to 5d (not shown), and as shown in FIG. 3B.
• recess etching is performed at the bottoms of the word line grooves 23a, 23b so that the W layer 26 has a desired thickness, thereby forming the W layers 26a, 26b which will become word lines.
• the third embodiment has the following features. Compared to the second embodiment, as shown in FIG. 3A, by performing taper etching, the distance between the word lines 26a and 26b can be further increased, and the parasitic capacitance between the word lines can be further reduced. High performance can be achieved.
• FIGS. 4A to 4E show a method for manufacturing a DRAM circuit according to a fourth embodiment of the present invention.
• (a) shows a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• the entire surface is covered with, for example, an amorphous Si layer 42 (an example of a "gate dummy layer” in the claims) that will serve as a dummy gate layer, and an anisotropic
• the amorphous Si layer 42 is etched by etching to leave the amorphous Si layer 42 around the semiconductor pillars 7a to 7d, forming 42a to 42d.
• the semiconductor pillars 7a to 7d are surrounded and their upper surfaces are placed at the desired position of the upper end of the gate conductor layer.
• a SiO 2 layer 44 (which is an example of the "third insulating layer” in the claims) is formed so as to be lower than the upper end position.
• the amorphous Si layers 42a to 42d are removed, and the exposed SiN layer 40 is sequentially removed to form donut-shaped slits 46a, 46b, 46c, and 46d.
• the entire surface is covered with a HfO 2 layer 48 that will become a gate insulating layer and a TiN layer 42 that will become a gate conductor layer, and the donut-shaped slits 46a, 46b, 46c, and 46d are filled, and then word lines and Then, the top surfaces of the TiN layer 42 and the W layer 50 are polished by CMP until they become the top surfaces of mask material layers 5a to 5d, and then photolithography is applied as shown in FIG. 4D.
• the TiN layer 42 and the W layer 50 are etched to remove the mask material layers 27a and 27b, and as shown in FIG. 4E, the remaining TiN layer 42 and the W layer are etched.
• the etching is performed so that the upper surface of the semiconductor pillar 50 is lower than the top of the semiconductor pillars 7a to 7d when viewed vertically.
• the fourth embodiment has the following features.
• the TiN layer 42 that will become the gate conductor layer and the W layer 50 that will become the word line are continuously coated, and after that, both materials are processed simultaneously. Therefore, it greatly contributes to improving the yield of such semiconductor products and reducing costs by reducing the number of manufacturing steps.
• FIGS. 5A to 5C show a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• the steps up to FIG. 4C of the fourth embodiment are performed, and then the entire surface is sequentially covered with an HfO 2 layer 48 that will become a gate insulating layer and a TiN layer 52 that will become a gate conductor layer, and then as shown in FIG. 5A.
• the TiN layer 52 is polished by CMP until the top surface of the TiN layer 52 becomes the top surface of the mask material layers 5a to 5d.
• the TiN layer 52 is etched so that the SiO 2 layer 44 is exposed, thereby forming gate conductor layers 52a to 52d surrounding the semiconductor pillars 7a to 7d. Then, the entire surface is covered with a W layer 54 that will become a word line, and the top surface of the W layer 54 is polished by CMP until it becomes the top surface of the mask material layers 5a to 5d, as shown in FIG. 5B.
• a mask material layer 27a and a mask material layer 27a which partially overlaps the mask material layers 5a and 5b and extends in a band shape in the XX' line direction, and the mask material layers 5c and 5d are formed.
• a mask material layer 27b is formed which partially overlaps and extends in a band shape in the direction of the XX' line.
• etching the TiN layer 52 it may be etched so that the HfO 2 layer 48 on the SiO 2 layer 44 is exposed.
• the W layer 54 is etched using the mask material layers 27a and 27b as a mask, so that the upper surface of the remaining W layer 50 is lower than the tops of the semiconductor columns 7a to 7d in vertical view, as shown in FIG. 5C.
• Word line W layers 54a and 54b are formed by etching to form word line W layers 54a and 54b.
• the fifth embodiment has the following features.
• the thickness of the gate conductor layer corresponding to the gate length of the transistor is determined by controlled etching of the gate conductor layer TiN layer 42 and the word line W layer 50, it is difficult to control the gate length.
• the SiO 2 layer 44 is exposed during etching of the gate conductor layer TiN layer 52, etching using end point detection becomes possible, gate length can be easily controlled, and the yield of such products is reduced. This greatly contributes to improved performance.
• FIGS. 6A to 6C show a method for manufacturing a DRAM circuit according to a sixth embodiment of the present invention.
• (a) shows a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• the steps up to FIG. 1H of the first embodiment are performed, and then, in plan view, the N + layer 2aa, which partially overlaps the N + layers 2aa and 2bb, extends in a band shape in the YY' line direction, and whose bottom part is the N + layer 2aa, 2bb.
• Contact holes 21a and 21b are formed at 2bb.
• FIG. 6A after depositing a tungsten (W) layer (not shown) on the entire surface, it is polished by CMP so that the upper surface becomes the upper surface of mask material layers 5a to 5d, and then by RIE method.
• the W layers in the contact holes 21a, 21b are etched to form W layers 22a, 22b ("second conductor layer" in the claims) at the bottoms of the contact holes 21a, 21b, in contact with the N + layers 2aa, 2bb. is an example).
• the upper surface positions of the W layers 22a and 22b are formed to be below the lower end positions of the TiN layers 15a and 15b.
• a buffer metal layer such as TaN may be formed to reduce the contact resistance between the W layers 22a and 22b and the N + layers 2aa and 2bb.
• SiO 2 layers 24a and 24b (which are an example of the "fourth insulating layer” in the claims) have holes 25a and 25b inside the contact holes 21a and 21b. form.
• the upper end positions of the holes 25a and 25b are formed lower than the upper end positions of the TiN layers 15a and 15b.
• the SiO 2 layers 24a and 24b may be formed of a low dielectric constant material layer such as silicon carbide oxide (SiOC). In this case, the holes 25a and 25b may or may not be formed.
• the SiO 2 layer 16 is recess-etched so that its top surface is lower than the tops of the gate electrodes 15a and 15b, and then a W layer (not shown) is formed to cover the entire surface, and a W layer (not shown) is formed by CMP.
• the W layer 26 is formed by polishing so that the upper surface position corresponds to the upper surface position of the mask material layers 5a to 5d, and as shown in FIG. 6C, using a photolithography method, the mask material layer 5a is .
• a mask material layer 27b is formed.
• the SiO 2 layer 20 This is preferable because the etching rate is low.
• a material layer serving as an etching stopper may be used.
• a thin insulating layer such as a SiN layer that serves as an etching stopper is coated inside the contact holes 21a and 21b, and the SiN layer at the bottom of the contact holes 21a and 21b is removed by RIE. , and then the W layers 22a and 22b may be formed.
• the sixth embodiment has the following features. 1. Since the SiO 2 layers 24aa and 24bb, which are effectively low dielectric constant layers containing holes 25a and 25b, and the bit line W layers 22a and 22b are formed in the contact holes 21a and 21b, the bit line W layers are formed inside the contact holes 21a and 21b. The SiO 2 layers 22a and 22b and the low dielectric constant layers 24aa and 24bb are formed in self-alignment. This allows for higher integration of DRAM memory cells. In plan view, in the overlapping region of the bit line W layers 22a, 22b and the word line W layers 26a, 26b, there are SiO 2 layers 24aa, 24bb, which are effectively low dielectric constant layers.
• Bit line W layers 26a and 26b are connected only to the upper portions of gate electrodes 15a to 15d in the height direction. As a result, the height between the word line W layers 26a and 26b facing each other becomes smaller compared to, for example, a structure in which the word line W layers 26a and 26b are formed at the same height as the gate electrodes 15a and 15b. Capacitance between word lines can be significantly reduced. 3. Since the SiO 2 layers 25a and 25b containing holes 25a and 25b, which serve as low dielectric constant layers, are formed between the word line W layers 26a and 26b, the capacitance between the word line W layers 26a and 26b is reduced. .
• FIGS. 7A and 7B show a method for manufacturing a DRAM circuit according to a seventh embodiment of the present invention.
• (a) shows a plan view
• (b) shows a cross-sectional structure diagram along line XX' in (a)
• (c) shows a cross-sectional structure diagram along line YY'.
• silicon nitride is applied to the outer periphery of the semiconductor pillars 7a to 7d so that the upper surface position is the top of the semiconductor pillars 7a to 7d.
• a (SiN) layer 9 (which is an example of the "fifth insulating layer” in the claims) is formed.
• silicon oxide (SiO 2 ) layers 10a, 10b, 10c, and 10d surround the tops of the semiconductor pillars 7a to 7d and the side surfaces of the mask material layers 5a to 5d with the same width in plan view (" (this is an example of "second mask material layer").
• mask material layers 11a and 11b are formed which overlap part of the mask material layers 5a to 5d and the SiO 2 layers 10a to 10d and extend in a band shape in the YY' line direction.
• the SiO 2 layers 10a to 10d may be formed by covering the mask material layers 5a to 5d with a SiO 2 layer (not shown) and then etching by, for example, an RIE (Reactive Ion Etching) method. good.
• the SiO 2 layers 10a to 10d are formed with equal width around the mask material layers 5a to 5d.
• the SiO 2 layers 10a to 10d are formed in a self-aligned manner with respect to the semiconductor pillars 7a to 7d.
• the SiN layer 9 may be formed after forming a thin SiO 2 layer (not shown) on the side surfaces of the semiconductor pillars 7a to 7d.
• FIG. 7B shows a plan view of the formed P layer stands 12a, 12b.
• the P layer bases 12a and 12b include N + layers 2aa and 2bb extending in a band shape in the Y-Y' line direction, and part of the outer periphery of the semiconductor pillars 7a to 7d, as shown in FIG. 7B(d). becomes a protruding shape.
• the P layer bases 12a and 12b which are parts of the outer periphery of the semiconductor pillars 7a to 7d, are formed by using the SiN layers 9a and 9b formed in self-alignment with the semiconductor pillars 7a to 7d as an etching mask. It is formed in self-alignment with the semiconductor pillars 7a to 7d.
• the seventh embodiment has the following features.
• contact holes 21a and 21b are formed which extend in a band shape and whose bottom portions are in the N + layers 2aa and 2bb. If the contact area is small, the contact resistance will increase, which is unfavorable in terms of the performance of the semiconductor product.
• FIG. 7B of this embodiment by forming N + layers 2aa and 2bb using mask material layers 11a and 11b and SiO 2 layers 10a to 10d as masks, N + + It becomes possible to expand the areas of layers 2aa and 2bb. This makes it possible to reduce contact resistance, which greatly contributes to improving the performance of such semiconductor products.
• the semiconductor pillars 7a to 7d are formed, but the semiconductor pillars may be made of other semiconductor materials. This also applies to other embodiments of the present invention.
• the N + layers 2aa, 2bb, 29a, and 29b in the first embodiment may be formed of Si containing donor impurities or other semiconductor material layers. Furthermore, the N + layers 2aa, 2bb, 29a, and 29b may be formed from different semiconductor material layers. This also applies to other embodiments of the present invention.
• the mask material layers 5a to 5d, 11a, and 11b may include other material layers including a single layer or multiple layers of organic or inorganic materials, as long as they are suitable for the purpose of the present invention. May be used.
• the SiO 2 layers 9a, 9b and SiN layers 10a to 10d used as etching masks may also be formed of other material layers including a single layer or multiple layers of organic or inorganic materials, as long as they are suitable for the purpose of the present invention. may also be used. This also applies to other embodiments of the present invention.
• the material of the W layers 22a and 22b in the second embodiment is not limited to metal, but may also be a conductive material layer such as an alloy, an acceptor, or a semiconductor layer containing a large amount of donor impurities. It may be composed of a single layer or a combination of multiple layers. This also applies to other embodiments of the present invention.
• TiN layers 15a to 15d were used as the gate conductor layers.
• a single layer or a plurality of material layers can be used as long as the material meets the purpose of the present invention.
• the TiN layers 15a to 15d can be formed from a conductive layer such as a single layer or multiple metal layers having at least a desired work function.
• Other conductive layers, such as a W layer, may be formed outside this.
• a single layer or a plurality of metal layers may be used in addition to the W layer.
• word line W layers 26a and 26b connected to the TiN layers 15a to 15d in the first embodiment may be formed by stacking with other conductor layers or from other conductor layers. This also applies to other embodiments of the present invention.
• HfO 2 layer 14 is used as the gate insulating layer, other material layers each consisting of a single layer or multiple layers may be used. This also applies to other embodiments of the present invention.
• SiO 2 layers 24a and 24b having holes 25a and 25b were formed.
• the holes 25a and 25b may be formed by covering the upper portions of the contact holes 21a and 21b with a SiN layer formed by, for example, CVD (Chemical Vapor Deposition).
• the insulating layer made of an inorganic or organic layer having holes 25a and 25b may be formed by other methods.
• the shape of the semiconductor pillars 7a to 7d in plan view was circular.
• the semiconductor pillars 7A to 7D have a rectangular shape in plan view.
• the shape of these semiconductor pillars in plan view may be not only circular or rectangular, but also elliptical or letter-shaped. Further, a mixture of these shapes may be formed on the same P layer substrate 1a. This also applies to other embodiments of the present invention.
• one memory cell is formed from one selection SGT, but in order to obtain a large drive current or to reduce the effective SGT series resistance, a plurality of SGTs may be formed. They may be connected in parallel. This also applies to other embodiments of the present invention.
• the present embodiment has been described with respect to an XY address type memory device such as DRAM, capacitorless DRAM, RRAM, MRAM, and PCM.
• the present invention can also be applied to other XY address type memory devices.
• a plurality of SGTs may be used in one memory cell.
• a plurality of RRAM, MRAM, and PCM variable resistance elements may be connected to one SGT.
• the SGT was formed on the P-layer substrate 1, but an SOI (Silicon On Insulator) substrate may be used instead of the P-layer substrate 1.
• SOI Silicon On Insulator
• a substrate made of another material may be used as long as it serves as a substrate. This also applies to other embodiments of the present invention.
• N + layers 2aa, 2bb, 29a to 29d, and 30a to 30d having the same polarity conductivity are used above and below the semiconductor pillars 7a to 7d.
• the present invention can also be applied to a tunnel type SGT having a source and a drain with different polarities. This also applies to other embodiments of the present invention.
• one SGT is formed on one semiconductor pillar, but the present invention can also be applied to circuit formation in which two or more SGTs are formed.
• the present invention is capable of various embodiments and modifications without departing from the broad spirit and scope of the present invention.
• the embodiment described above is for explaining one example of the present invention, and does not limit the scope of the present invention.
• the above embodiments and modifications can be combined arbitrarily.
• a memory device using SGT with high density and high performance can be obtained.

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• 2022
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