WO2023185951A1 - 基于阻挡层绝缘层融合的可热修复通孔制备方法 - Google Patents

基于阻挡层绝缘层融合的可热修复通孔制备方法 Download PDF

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WO2023185951A1
WO2023185951A1 PCT/CN2023/084825 CN2023084825W WO2023185951A1 WO 2023185951 A1 WO2023185951 A1 WO 2023185951A1 CN 2023084825 W CN2023084825 W CN 2023084825W WO 2023185951 A1 WO2023185951 A1 WO 2023185951A1
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substrate
layer
hole
fusion
fusion layer
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PCT/CN2023/084825
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English (en)
French (fr)
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王琛
邓晓楠
张思勉
武逸飞
王宇祺
柯声贤
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清华大学
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Publication of WO2023185951A1 publication Critical patent/WO2023185951A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Definitions

  • the present disclosure relates to the field of electronic packaging technology, and in particular to a method for preparing thermally repairable vias based on the fusion of barrier layers and insulating layers.
  • the high aspect ratio through-hole manufacturing process has complex processes, high processing temperatures, high costs, and cannot be thermally repaired.
  • the through-hole structure itself has problems such as interface delamination, substrate cracking, electrical performance degradation, and large electrical losses.
  • thermal budget management has become more and more stringent.
  • the cost of the product is also one of the important considerations. How to provide a low-cost, low-processing temperature, and broad technical application scenario?
  • a through-hole preparation method that solves the problems of interface delamination, substrate cracking, electrical performance degradation, large electrical loss, and inability to be thermally repaired in related technologies is an urgent technical problem that needs to be solved.
  • the present disclosure proposes a thermally repairable via preparation method based on barrier layer insulating layer fusion.
  • a through hole preparation method based on barrier layer insulating layer fusion which method includes:
  • the substrate includes a silicon substrate or a glass substrate;
  • Polishing is performed until the first side of the substrate is exposed
  • the second side of the substrate opposite to the first side is thinned until the conductive pillar is exposed, thereby completing the preparation of the through hole in the substrate.
  • the material of the fusion layer includes organic materials, inorganic materials or composite materials with fluidity and insulation properties, and the organic materials include polyimide, wherein spin coating or drop coating is used
  • the method to generate a fusion layer on the surface of the hole includes: spin-coating a fusion layer material precursor on the first side of the substrate and forming a fusion layer after solidification, the speed and time of the spin coating are according to the The preset size is determined.
  • the viscosity of the material of the fusion layer matches the structural characteristics of the holes and the speed of spin coating.
  • the method further includes:
  • etching the substrate to form a hole of a predetermined size on the first surface of the substrate includes:
  • the dielectric layer and the substrate are etched to form a hole of a predetermined size in a direction corresponding to the first surface of the substrate; wherein, when the hole is a blind hole, the hole The bottom surface of is in the substrate.
  • the material of the seed layer includes metal or metal alloy
  • the metal includes metal nickel
  • generating the seed layer on the fusion layer includes:
  • the diameter of the through hole is 10 nanometers to 900 microns, and the aspect ratio of the through hole is greater than or equal to 100:1.
  • the aspect ratio may depend on the preparation process of the through hole.
  • the holes are prepared using any one of the following methods: dry etching, wet etching, Bosch process and 3D printing.
  • the material of the conductive pillar includes metal or metal alloy
  • the metal includes metal copper
  • the conductive pillar is made by using any one of electroplating, metal filling process or metal alloy filling process. prepared.
  • the embodiments of the present disclosure provide a thermally repairable through-hole preparation method based on the fusion of the barrier layer and insulating layer, which can simplify the process steps of the through-hole, has low cost, low processing temperature, high shape retention and can be thermally repaired, and makes relevant In the technology, problems such as complex process of through holes, interface delamination, substrate cracking, electrical performance degradation, large electrical loss, and inability to be thermally repaired can be solved.
  • FIG. 1 shows a flow chart of a thermally repairable via preparation method based on barrier layer insulating layer fusion according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic flowchart of a thermally repairable via preparation method based on barrier layer insulating layer fusion according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic flow chart of fusion layer preparation in a thermally repairable via preparation method based on fusion of barrier layer and insulating layer according to an embodiment of the present disclosure.
  • FIG. 4 shows a schematic flowchart of a thermally repairable via preparation method based on barrier layer insulating layer fusion according to an embodiment of the present disclosure.
  • FIG. 5 shows the I-V curve of a device using a through hole according to an embodiment of the present disclosure during the breakdown process, after breakdown, and after self-healing.
  • Figure 6 shows a schematic diagram of the repair ratio of devices using through holes with different insulation layers.
  • exemplary means "serving as an example, example, or illustrative.” Any embodiment described herein as “exemplary” is not necessarily to be construed as superior or superior to other embodiments.
  • a through silicon via consists of an insulating layer, a barrier layer and a conductive pillar.
  • the through-silicon hole filling technology has a complex process. First, a silicon oxide insulating layer is deposited on the inner wall of the through-silicon hole to isolate the conductive pillars of the through-silicon hole from the surrounding silicon substrate. Then a titanium Ti barrier layer is sputtered and deposited on the inner wall to prevent the diffusion of copper Cu in the silicon oxide insulating layer. The inner wall is then covered with a Cu seed layer by sputtering deposition to facilitate electroplating and filling of the Cu pillars. Finally, the silicon is removed by chemical mechanical polishing. Excess Cu pillars on the substrate surface.
  • the silicon oxide insulating layer is usually deposited using the ion-enhanced chemical vapor deposition (PECVD) method, and the process temperature is 200°C–400°C.
  • PECVD ion-enhanced chemical vapor deposition
  • the silicon oxide insulating layer prepared by PECVD may have a large initial stress.
  • TSVs with silicon oxide insulating layers will cause huge electrical losses due to parasitic capacitance.
  • the silicon oxide insulating layer deposited through the high-temperature process of plasma enhanced chemical vapor deposition (PECVD) will Thermal stress exists, causing problems such as interface delamination, silicon substrate cracking, and electrical performance degradation.
  • the density of the silicon oxide insulating layer prepared by PECVD is relatively low and the insulation performance is relatively poor; while the oxide layer with better insulation performance prepared by thermal oxidation has greater stress and requires a higher growth temperature (1000°C above), is less compatible with processes where temperature-sensitive processes are performed prior to via filling.
  • the Ti barrier layer and Cu seed layer must achieve uniform distribution in depth and high coverage.
  • the atomic layer deposition (Atomic layer deposition, ALD) process is used, and the process temperature is 270°C, the deposition rate is low and the process cost is high.
  • the traditional Physical Vapor Deposition (PVD) process is difficult to achieve the deposition of highly conformal barrier layers and seed layers for high aspect ratio via holes.
  • embodiments of the present disclosure provide a thermally repairable through-hole preparation method based on the fusion of barrier layer insulating layers, which can simplify the process steps of the through-hole, has low cost, low processing temperature, high shape retention, and high performance.
  • the technology that can be applied has a wide range of application scenarios, and can solve the problems in related technologies such as interface delamination of through holes, substrate cracking, electrical performance degradation, large electrical losses, and inability to be thermally repaired.
  • FIG. 1 shows a flow chart of a thermally repairable via preparation method based on barrier layer insulating layer fusion according to an embodiment of the present disclosure.
  • FIG. 2 shows a schematic flowchart of a thermally repairable via preparation method based on barrier layer insulating layer fusion according to an embodiment of the present disclosure.
  • the method includes: step S11-step S16.
  • the substrate 41 is etched or additively manufactured, and a hole 42 of a predetermined size is formed on the first surface of the substrate 41.
  • the substrate 42 can be a silicon substrate, a glass substrate, etc. Substrates of other materials.
  • the preset size of the hole 42 may be set according to the size of the through hole to be manufactured, which is not limited by the present disclosure.
  • the Bosch process dry etching, wet etching, 3D printing and other processes can be used, and this disclosure is not limited thereto.
  • the surface of the holes made by the Bosch process is more conducive to fusion. layer formation.
  • the hole 42 may be a blind hole, a through hole, etc., which is not limited in this application.
  • the substrate may be a 2- to 15-inch silicon wafer substrate.
  • step S12 spin coating or drop coating is used to generate a fusion layer 43 on the surface of the hole 42.
  • the fusion layer 43 serves as a barrier layer and an insulating layer for the through hole that needs to be prepared.
  • the surface of the hole 42 may refer to the inner wall and bottom surface of the hole 42 .
  • the fusion layer can also be formed on part or all of the first surface of the substrate 41 as shown in FIG. 2 , which is not limited by this disclosure.
  • the fusion layer provided by the present disclosure can replace the insulating layer and barrier layer in the through hole in the related art, and because the fusion layer is prepared by spin coating or drop coating, the processing temperature is low, and the fusion layer itself does not have the insulating layer in the related art.
  • the thermal stress and initial stress generated during high-temperature processing can reduce or even avoid the occurrence of interface delamination, substrate cracking, electrical performance degradation, etc., and reduce electrical losses.
  • preparing the fusion layer by spin coating can smooth the side protrusions, which is beneficial to improving the continuity of the subsequent seed layer.
  • a vacuum spin coating process may be used to prepare the fusion layer.
  • the material of the fusion layer can be a material with the following properties:
  • the contact angle between the fusion layer and the surface of the pore structure is less than 70°, so that the fusion layer can be closely combined with the pore surface and avoid unfavorable situations such as interface delamination. .
  • the contact angle between the fusion layer and the surface of the hole structure can be 10° to 60°.
  • the resistivity can be 10 12 ⁇ cm ⁇ 10 16 ⁇ cm, so that the insulation of the fusion layer needs to match the insulation design of the through hole to ensure that the conductive pillar can be connected with the surrounding substrate isolation.
  • the material viscosity that matches the structural characteristics of the through hole (structural characteristics include: depth, sidewall relief, diameter and other characteristics of the three-dimensional structure of the through hole) and the spin coating speed. Because the material viscosity is too high and the rotation speed is too low, the material cannot be spin-coated uniformly on the surface of the hole, and even the material at the bottom of the hole cannot be thrown out, forming a tapered cross-section; the material viscosity is too low, the rotation speed is too high, and the material cannot be continuous Adhesion to the inner walls of the holes makes the prepared fusion layer uneven and even exposes the substrate. In addition, the viscosity of the material is set to ensure the shape retention of the fusion layer.
  • the fusion layer has the function of blocking diffusion.
  • the density can be 1.3g/cm 3 to 1.5g/cm 3 . It is uniformly covered on the hole wall, with a thickness uniformity of more than 50%.
  • the viscosity of the material of the fusion layer can be 1500 cP, and the spin coating speed at this viscosity is 400 r/min.
  • the insulation performance can be a leakage current of ten picoamps at a bias voltage of the order of ten volts.
  • the material of the fusion layer can be organic materials with fluidity and insulation properties such as polyimide (PI), polyethylene glycol terephthalate (PET), etc. , inorganic materials or composite materials, etc. Those skilled in the art can set the material of the fusion layer according to actual needs, and this disclosure does not limit this.
  • PI polyimide
  • PET polyethylene glycol terephthalate
  • inorganic materials or composite materials etc.
  • FIG. 3 shows a schematic flow chart of fusion layer preparation in a through-hole preparation method based on fusion of barrier layers and insulating layers according to an embodiment of the present disclosure.
  • the material of the fusion layer 43 is polyimide.
  • step S12 may include: spin-coating polyimide 43' on the first surface of the substrate 41 and forming the fusion layer 43 after solidification. The speed and time of the spin-coating are determined according to the preset size. of.
  • the fusion layer 43 can be prepared by drop coating, and the present disclosure does not limit this.
  • the polyimide 43 ′ can be coated on the first surface of the substrate 41 first, and then the substrate 41 is rotated according to the determined rotation speed and rotation time, so as to This allows the polyimide 43' to evenly cover the surface of the hole 42 and the first surface of the substrate 41 during the rotation process, and then the polyimide 43' is cured to obtain the fusion layer 43.
  • step S13 a seed layer 44 is generated on the fusion layer 43.
  • the material of the seed layer 44 may include metal or metal alloy, where the metal may be metallic nickel, and step S13 may include: using electroless plating at 70° C. (or other suitable temperature).
  • a metallic nickel seed layer 44 is generated on the fusion layer 43 by a method.
  • the seed layer is prepared through electroless plating, which reduces the process temperature, improves the preparation speed and efficiency of the seed layer, and also reduces the cost of through-hole preparation.
  • the deposition technology used to prepare the seed layer 44 can be selected and set according to the material of the seed layer 44 , which is not limited by the present disclosure.
  • step S14 the hole is filled with the seed layer 44 to form a conductive pillar 45 .
  • the material of the conductive pillar 45 may include metal, metal alloy, metallic nanomaterial or conductive polymer.
  • the metal can be metallic copper, the metallic nanomaterial can be carbon nanotubes, and the conductive polymer can be silver nanoslurry; the conductive pillar 45 can be made by using an electroplating process, a metal filling process, a metal alloy filling process, or a pressurized filling process. Prepared by other processes, this disclosure does not limit this.
  • the execution process of step S14 can be set according to the material of the conductive pillar 45 .
  • the preparation of conductive pillars of different materials is described below.
  • the conductive pillar 45 can be prepared by using an epitaxial growth process, a solution filling process, or other processes, and this disclosure is not limited thereto.
  • the conductive material can be filled in the pores through a metallic nanomaterial solution suspension filling process.
  • the metallic nanomaterial solution may include a metallic carbon nanotube solution with a content of 15% to 25%, and step S14 may be: using a low-speed suspension coating process in a vacuum environment to completely fill the holes with the solution; and then proceeding at room temperature for about 5 hours of solvent evaporation to achieve complete filling of the pores with carbon nanotubes.
  • the filling process using metallic nanomaterials simplifies the seed layer preparation and electroplating processes, further realizes room-temperature through-hole filling, improves the filling preparation speed and efficiency, and also reduces costs.
  • the seed layer may not be prepared, and the conductive material may be directly filled in the hole, thereby reducing the preparation process.
  • step S14 may be: evenly placing indium In particles on the surface of the substrate after the fusion layer 43 is prepared; and then heating the whole body to 170°C in a vacuum. Until the molten indium liquid completely fills the hole. In this way, the filling process using liquid metal does not require seed layer preparation and electroplating processes, further achieving through-hole filling that is compatible with low temperature requirements, and improving the filling preparation speed and efficiency.
  • liquid metal such as indium In
  • step S14 may be: completely immersing the substrate structure in the silver conductor paste (that is, silver nano paste) in the sealed cavity; Fill the cavity with Ar to 0.8atm ⁇ 2atm so that the slurry completely fills the hole structure; then take out the substrate and heat it to 150°C ⁇ 250°C to solidify the silver conductive slurry.
  • the filling process of conductive polymer simplifies the seed layer preparation and electroplating process, further realizes low-temperature through-hole filling, improves the filling preparation speed and efficiency, and also reduces the cost.
  • the seed layer may not be prepared, and the conductive material may be directly filled in the hole, thereby reducing the preparation process.
  • step S15 polishing is performed until the first surface of the substrate 41 is exposed.
  • the fusion layer 43 and the seed layer covering the first surface of the substrate 41 can be removed during the polishing process. 44. Conductive pillars 45 protruding from the first surface of the substrate 41 to facilitate subsequent assembly of the substrate 41 .
  • Chemical Mechanical Polishing (CMP) can be used to remove the fusion layer, seed layer and protruding conductive pillars attached to the first side of the substrate.
  • step S16 the second surface of the substrate 41 opposite to the first surface is thinned until the conductive pillar 45 is exposed, thereby completing the preparation of the through hole in the substrate 41 .
  • the through hole prepared includes the fusion layer 43 , the seed layer 44 and the conductive pillar 45 .
  • FIG. 4 shows a schematic flowchart of a through hole preparation method based on fusion of barrier layers and insulating layers according to an embodiment of the present disclosure.
  • the method may further include: forming a dielectric layer 46 on the first surface of the substrate 41 ; then step S11 may include: combining the dielectric layer 46 and the The substrate 41 is etched to form a hole 42 of a predetermined size in a direction corresponding to the first surface of the substrate 41 , and the bottom surface of the hole 42 is located in the substrate 41 .
  • the dielectric layer may be an ONO layer, that is, a silicon oxide (SiO 2 )/silicon nitride (SiN x )/silicon oxide layer, which can be prepared using a PECVD process.
  • ONO layer that is, a silicon oxide (SiO 2 )/silicon nitride (SiN x )/silicon oxide layer, which can be prepared using a PECVD process.
  • photoresist can be coated on the surface of the dielectric layer 46 first, and the photoresist can be etched to locate the position of the holes. Then, an Inductively Coupled Plasma (ICP) dry etching process can be used to etch the dielectric layer 46, and then the Bosch process is used to etch the substrate 41 to form a layer that passes through the dielectric layer 46 and the bottom surface is on the substrate. 41 internal hole 42.
  • ICP Inductively Coupled Plasma
  • the thickness of the fusion layer 43 of the through hole prepared by this method can be from tens of nanometers to several micrometers, and the breakdown voltage can be from tens of volts to hundreds of volts.
  • the fusion layer prepared by this method can achieve thermal repair.
  • the thermal repair temperature can be 80 degrees Celsius.
  • the material characteristic temperature of the fusion layer can be selected according to the required thermal repair temperature.
  • the present disclosure also provides an application example of the through hole prepared by the above method.
  • TSVs used in high-power devices and systems will face failure problems under high voltage.
  • the dielectric materials used as liners will fail due to breakdown.
  • the main causes of electrical breakdown include impact ionization, trap generation and anode hole injection.
  • the insulation properties will be greatly reduced, leading to device failure.
  • the organic liner layer realized by the through-hole filling process of fusion of the barrier layer and the insulating layer proposed in the embodiment of the present disclosure can achieve self-healing of the insulation performance after electrical breakdown (that is, thermal repair).
  • the self-repairing process of the insulation performance of the organic liner layer realized by the present invention includes the following steps:
  • the results of the self-healing process of the organic liner layer implemented by the present invention are shown in Figure 5.
  • the IV curve measured in the hole is shown in Figure 5.
  • the post-self-healing curve shows that the leakage current changes again by three orders of magnitude at 86V, which demonstrates the insulating performance of the organic liner layer. of recovery.
  • This method can achieve a typical repair ratio of 75% or higher, compared with the same treatment method and filling the via with a traditional silicon oxide insulating layer, as shown in Figure 6. The ratio has increased by more than 6 times.

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Abstract

本公开涉及一种基于阻挡层绝缘层融合的可热修复通孔制备方法，该方法包括：对衬底进行刻蚀或增材制造，在衬底的第一面形成预设尺寸的孔；采用旋涂或者滴涂的方式在孔的表面生成融合层，融合层作为需要制备的通孔的阻挡层和绝缘层；在融合层上生成种子层；利用种子层对孔进行填充，形成导电柱；进行抛光直至暴露出衬底的第一面；对衬底的与第一面相对的第二面进行减薄直至暴露出导电柱，完成衬底中通孔的制备。该方法能够简化通孔的工艺步骤，成本低、加工温度低、保形性高、能够热修复，且使得相关技术中通孔的工艺复杂、界面分层、衬底开裂、电气性能退化、电损耗大、无法热修复等问题得以解决。

Description

基于阻挡层绝缘层融合的可热修复通孔制备方法 技术领域
本公开涉及电子封装技术领域，尤其涉及一种基于阻挡层绝缘层融合的可热修复通孔制备方法。
背景技术
随着AI技术的发展，智能电子产品对更高带宽、更多I/O引脚、更高容量和集成密度的需求不断增加，基于硅通孔(Through Silicon Via，TSV)、玻璃通孔(Through Glass Via,TGV)、或者其他材料的通孔互联的3D集成技术已成为器件小型化的最有潜力的解决方案。另一方面，通孔可实现多功能子系统的垂直堆叠，例如模拟、逻辑、生物传感器、射频(RF)、存储器和MEM芯片，是实现器件多功能化的重要手段。
相关技术中，高深宽比的通孔制造工艺存在工艺复杂、加工温度高、成本高、无法热修复，通孔结构本身存在界面分层、衬底开裂、电气性能退化、电损耗大等问题，随着芯片模组的复杂化和多层集成的要求，对热预算管理越发严格，对产品的成本也是重要考量之一，如何提供一种成本低、加工温度低、具有广阔的技术应用场景，且使得相关技术中通孔的界面分层、衬底开裂、电气性能退化、电损耗大、无法热修复等问题得以解决的通孔制备方法，是亟待解决的技术问题。
发明内容
有鉴于此，本公开提出了一种基于阻挡层绝缘层融合的可热修复通孔制备方法。
根据本公开的一方面，提供了一种基于阻挡层绝缘层融合的通孔制备方法，所述方法包括：
对衬底进行刻蚀或增材制造，在所述衬底的第一面形成预设尺寸的孔，所述衬底包括硅衬底或玻璃衬底；
采用旋涂或者滴涂的方式在所述孔的表面生成融合层，所述融合层作为需要制备的通孔的阻挡层和绝缘层；
在所述融合层上生成种子层；
利用所述种子层对所述孔进行填充，形成导电柱；
进行抛光直至暴露出所述衬底的第一面；
对所述衬底的与所述第一面相对的第二面进行减薄直至暴露出所述导电柱，完成所述衬底中所述通孔的制备。
在一种可能的实现方式中，所述融合层的材料包括具有流动性和绝缘性的有机材料、无机材料或复合材料，所述有机材料包括聚酰亚胺，其中，采用旋涂或者滴涂的方式在所述孔的表面生成融合层，包括：在所述衬底的第一面旋涂融合层材料前体并在固化后形成融合层，所述旋涂的速度和时间是根据所述预设尺寸确定的。
在一种可能的实现方式中，所述融合层的材料的粘度是与所述孔的结构特征以及旋涂的速度匹配的。
在一种可能的实现方式中，所述方法还包括：
在所述衬底的第一面形成介质层；
其中，所述对衬底进行刻蚀，在所述衬底的第一面形成预设尺寸的孔，包括：
对所述介质层和所述衬底进行刻蚀，在对应于所述衬底的第一面的方向形成预设尺寸的孔；其中，在所述孔为盲孔的情况下，所述孔的底面处于所述衬底中。
在一种可能的实现方式中，所述种子层的材料包括金属或金属合金，所述金属包括金属镍，所述在所述融合层上生成种子层，包括：
在70℃或者合适的温度下下采用化学镀等其他沉积技术在所述融合层上生成种子层。
在一种可能的实现方式中，所述通孔的直径为10纳米到900微米，所述通孔的深宽比大于或等于100:1，深宽比可以取决于通孔的制备工艺。
在一种可能的实现方式中，所述孔是利用以下方法中的任意一种制备的：干法刻蚀、湿法刻蚀、Bosch工艺和3D打印。
在一种可能的实现方式中，所述导电柱的材料包括金属或金属合金，所述金属包括金属铜，所述导电柱是利用电镀、金属填充工艺或者金属合金填充工艺中的任意一种工艺制备的。
本公开实施例提供的一种基于阻挡层绝缘层融合的可热修复通孔制备方法，能够简化通孔的工艺步骤，成本低、加工温度低、保形性高且能够热修复，且使得相关技术中通孔的工艺复杂、界面分层、衬底开裂、电气性能退化、电损耗大、无法热修复等问题得以解决。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法的流程图。
图2示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法的流程示意图。
图3示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法中融合层制备的流程示意图。
图4示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法的流程示意图。
图5示出应用本公开一实施例通孔的器件在击穿过程中、击穿后、自修复后的I-V曲线图。
图6示出采用不同绝缘层的通孔的器件的修复比例示意图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除 非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
相关技术中，硅通孔由绝缘层、阻挡层以及导电柱组成。硅通孔填充技术具有复杂的工艺流程，首先在硅通孔的内壁沉积氧化硅绝缘层，将硅通孔的导电柱与周围的硅衬底隔离。然后在内壁溅射沉积钛Ti阻挡层以防止铜Cu在氧化硅绝缘层中的扩散，再通过溅射沉积使内壁覆盖Cu种子层以便于进行Cu柱的电镀填充，最后通过化学机械抛光去除硅衬底表面多余的Cu柱。
相关技术中，氧化硅绝缘层的沉积通常采用离子体增强化学气相沉积(PECVD)法，工艺温度为200℃–400℃。但相关技术中该工艺存在4个主要的缺陷。第一，对于高深宽比的硅通孔来说，PECVD制备的氧化硅绝缘层可能具有较大的大初始应力。第二，随着工作频率增加到射频甚至毫米波范围，具有氧化硅绝缘层的硅通孔会因寄生电容而导致巨大的电损耗。第三，由于铜、硅衬底和氧化硅绝缘层在热膨胀系数上存在巨大的失配，通过等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)高温过程沉积的氧化硅绝缘层会存在热应力，引起界面分层、硅衬底开裂、电气性能退化等问题。第四，PECVD制备的氧化硅绝缘层致密度相对较低，绝缘性能相对较差；而采用热氧化制备的绝缘性能更好的氧化层有较大的应力及需要较高的生长温度(1000℃以上)，与在通孔填充之前进行过温度敏感工艺的工艺流程兼容性较差。相关技术中对于高深宽比硅通孔，Ti阻挡层和Cu种子层须实现深度上的均匀分布以及高覆盖率，一般采用原子层沉积原子层沉积(Atomic layer deposition，ALD)工艺，其工艺温度为270℃，沉积速率低且工艺成本高。而传统的物理气相沉积(Physical Vapor Deposition，PVD)工艺难以实现高深宽比通孔的高保形性阻挡层与种子层沉积。
为解决上述技术问题，本公开实施例提供了一种基于阻挡层绝缘层融合的可热修复通孔制备方法，能够简化通孔的工艺步骤，成本低、加工温度低、保形性高、所能应用的技术应用场景广阔，且使得相关技术中通孔的界面分层、衬底开裂、电气性能退化、电损耗大、无法热修复等问题得以解决。
图1示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法的流程图。图2示出根据本公开一实施例的一种基于阻挡层绝缘层融合的可热修复通孔制备方法的流程示意图。如图1、图2所示，该方法包括：步骤S11-步骤S16。本领域技术人员可以根据实际需要对通孔的直径、深宽比进行设置，本公开对此不作限制。
在步骤S11中，对衬底41进行刻蚀或者增材制造，在所述衬底41的第一面形成预设尺寸的孔42，所述衬底42可以为硅衬底、玻璃衬底等其他材料的衬底。
在本实施例中，孔42的预设尺寸可以是根据所需制造的通孔的尺寸设置出的，本公开对此不作限制。制造孔42的过程中可以采用Bosch工艺、干法刻蚀、湿法刻蚀和3D打印等等工艺，本公开对此不作限制。其中，采用Bosch工艺所制造的孔的表面更有利于融合 层的形成。在一些实施例中，孔42可以是盲孔、通孔等孔，本申请对此不作限制。本领域技术人员可以根据实际需要对衬底的尺寸进行设置，本公开对此不作限制。例如，衬底可以是2～15英寸的硅晶圆基底。
在步骤S12中，采用旋涂或者滴涂的方式在所述孔42的表面生成融合层43，所述融合层43作为需要制备的通孔的阻挡层和绝缘层。
其中，孔42的表面可以是指孔42的内壁以及底面。在旋涂或滴涂中除了在孔42的表面生成融合层43，也可以如图2所示在衬底41的第一面的部分或全部区域也生成融合层，本公开对此不作限制。本公开所提供的融合层可以代替相关技术中通孔中绝缘层和阻挡层的作用，且由于融合层采用旋涂或者滴涂方式制备，加工工艺温度低，融合层本身没有相关技术中绝缘层高温加工中产生的热应力和初始应力，能够减少甚至避免界面分层、衬底开裂、电气性能退化等情况的发生，降低电损耗。并且，由于孔的制造过程会使得孔的内壁产生侧突，旋涂的方式制备融合层能够平滑侧突，有利于后续种子层连续性的提高。在一些实施例中，可以采用真空旋涂的工艺方式进行融合层的制备。
在一种可能的实现方式中，融合层的材料可以是具备以下性能的材料：
具有特定的表面能，表面能可以为20～60mJ/m2，使得融合层与孔结构表面接触角小于70°，以便于融合层可以与孔表面紧密结合、避免界面分层等不利情况的发生。其中，融合层与孔结构表面接触角可以为10°～60°。
与种子层金属亲和力好，以便于种子层能够附着于融合层、且保证二者可以紧密结合、避免界面分层等不利情况的发生。
具有特定的电阻率，在TSV填充共同工艺中电阻率可以为1012Ω·cm～1016Ω·cm，使得融合层的绝缘性与通孔的绝缘设计需要匹配，保证导电柱可以与周围的衬底隔离。
具有与通孔的结构特征(结构特征包括：深度、侧壁起伏度、直径等通孔在三维结构上的特征)以及旋涂转速匹配的粘度。因为材料粘度过高、转速过低会使得材料无法均匀的旋涂到孔表面，甚至孔底部的材料会无法甩出、形成锥形截面；材料粘度过低、转速过高又会使得材料不能连续附着于孔的内壁使得所制备的融合层不均匀甚至暴露出衬底。另外，对材料的粘度进行设置也是为了保证融合层的保形性。
具有特定的密度和结构，使得融合层具备阻挡扩散作用。密度可为1.3g/cm3～1.5g/cm3。均一覆盖在孔壁，厚度均一性达50％以上。
例如，对深宽比为1:5～1:10，直径为10μm～40μm的孔，融合层的材料的粘度可以为1500cP，该粘度下的旋涂的转速为400r/min。绝缘性能可以为在十伏量级偏压下实现十皮安级漏电流。
在一些实施例中，融合层的材料可以是聚酰亚胺(Polyimide，简写为PI)、聚对苯二甲酸乙二醇酯(polyethylene glycol terephthalate，PET)等具有流动性和绝缘性的有机材料、无机材料或者复合材料等。本领域技术人员可以根据实际需要对融合层的材料进行设置，本公开对此不作限制。
图3示出根据本公开一实施例的一种基于阻挡层绝缘层融合的通孔制备方法中融合层制备的流程示意图。在一种可能的实现方式中，如图3所示，若融合层43的材料为聚酰亚胺。其中，步骤S12可以包括：在所述衬底41的第一面旋涂聚酰亚胺43’并在固化后形成融合层43，所述旋涂的速度和时间是根据所述预设尺寸确定的。在一些实施例中，也 可以采用滴涂的方法进行融合层43的制备，本公开对此不作限制。
在该实现方式中，如图3所示，可以先将聚酰亚胺43’涂覆于衬底41的第一面，而后按照确定出的旋转速度和旋转时间对衬底41进行旋转，以使得旋转过程中聚酰亚胺43’可以均匀覆盖在孔42的表面以及覆盖在衬底41的第一面，而后对聚酰亚胺43’进行固化，得到融合层43。
在步骤S13中，在所述融合层43上生成种子层44。
在一种可能的实现方式中，所述种子层44的材料可以包括金属或金属合金，其中金属可以为金属镍，则步骤S13可以包括：在70℃(或者其他合适的温度)下采用化学镀的方式在所述融合层43上生成金属镍种子层44。这样，通过化学镀实现种子层的制备，降低了工艺温度，提高了种子层的制备速度和效率，同时也能降低通孔制备的成本。在一些实施例中，可以根据种子层44的材料对制备种子层44所采用的沉积技术进行选择设置，本公开对此不作限制。
在步骤S14中，利用所述种子层44对所述孔进行填充，形成导电柱45。
在一种可能的实现方式中，所述导电柱45的材料可以包括金属，金属合金，金属性纳米材料或导电聚合物。金属可以是金属铜，金属性纳米材料可以是碳纳米管，导电聚合物可以是银纳米浆料；所述导电柱45可以是利用电镀工艺、金属填充工艺、金属合金填充工艺、加压填充工艺等工艺制备的，本公开对此不作限制。
在一些实施例中，可以根据导电柱45的材料对步骤S14的执行过程进行设置。以下对不同材料的导电柱制备进行说明。
例如，若导电柱的材料为金属性纳米材料(如碳纳米管)，则制备导电柱45可以利用外延生长工艺、溶液填充工艺等工艺制备的，本公开对此不作限制。其中，可以通过金属性纳米材料溶液悬涂填充工艺实现在孔中对导电材料的填充。所述金属性纳米材料溶液可以包括含量15％～25％的金属性碳纳米管溶液，则步骤S14可以为：在真空环境中采用低速悬涂工艺使溶液完全填充孔；之后在室温下进行约5小时的溶剂蒸发以实现碳纳米管对孔的完全填充。这样采用金属性纳米材料的填充工艺简化了种子层制备与电镀过程，进一步实现了常温通孔填充，提高了填充制备速度和效率，同时也降低成本。在该实现方式中，可不制备种子层，在所述孔中直接填充导电材料，从而减少制备工序。
例如，若导电柱的材料为液态金属(如铟In)，则步骤S14可以为：将铟In颗粒均匀放置在融合层43制备完成的衬底表面；之后在真空中将整体加热至170℃，至熔融铟In液体完全填充孔。这样采用液态金属的填充工艺无需种子层制备与电镀过程，进一步实现了低温需求兼容的通孔填充，提高了填充制备速度和效率。
例如，若导电柱的材料为导电聚合物(如银纳米浆料)，则步骤S14可以为：在密封腔中将衬底结构完全浸入银导体浆料(也即银纳米浆料)；在密封腔中充入Ar至0.8atm～2atm，使浆料完全填充孔结构；而后取出衬底，加热至150℃～250℃使银导电浆料固化。这样采用导电聚合物的填充工艺简化了种子层制备与电镀过程，进一步实现了低温通孔填充，提高了填充制备速度和效率，同时也降低成本。在该实现方式中，可不制备种子层，在所述孔中直接填充导电材料，从而减少制备工序。
在步骤S15中，进行抛光直至暴露出所述衬底41的第一面。
在本实施例中，抛光过程之中可以去除衬底41的第一面上覆盖的融合层43、种子层 44、凸出于衬底41的第一面的导电柱45，以便于该衬底41的后续装配。可以采用化学机械抛光(Chemical Mechanical Polishing，CMP)的方式去除衬底第一面附着的融合层、种子层和突出的导电柱。
在步骤S16中，对所述衬底41的与所述第一面相对的第二面进行减薄直至暴露出所述导电柱45，完成所述衬底41中所述通孔的制备。
通过上述步骤，制备出的通孔包括融合层43、种子层44和导电柱45。
图4示出根据本公开一实施例的一种基于阻挡层绝缘层融合的通孔制备方法的流程示意图。在一种可能的实现方式中，如图4所示，该方法还可以包括：在所述衬底41的第一面形成介质层46；则步骤S11可以包括：对所述介质层46和所述衬底41进行刻蚀，在对应于所述衬底41的第一面的方向形成预设尺寸的孔42，所述孔42的底面处于所述衬底41中。
其中，介质层可以是ONO层，也即氧化硅(SiO2)/氮化硅(SiNx)/氧化硅层，可以采用PECVD工艺制备。
在该实现方式中，如图4所示，完成介质层46的制备后，可以先在介质层46表面涂覆光刻胶，并对光刻胶进行刻蚀定位孔的位置。而后可以采用感耦合等离子体(Inductively Coupled Plasma，ICP)干法刻蚀工艺对介质层46进行刻蚀，而后再利用Bosch工艺对衬底41刻蚀，形成穿过介质层46、底面处于衬底41内部的孔42。
本方法制备的通孔的融合层43(也即作为需要制备的通孔的阻挡层绝缘层)的厚度可以为几十纳米到几微米，击穿电压可以为几十伏到几百伏。击穿后，本方法制备的融合层能够实现热修复，例如，热修复温度可以为80摄氏度。其中，可以根据需要的热修复温度对融合层的材料特性温度进行选择。
本公开还提供了上述方法制备的通孔的一种应用示例。应用于高功率器件和系统的TSV是会面临高压下的故障问题的。在较高的电压和电场强度下，用作衬垫的介电材料将因击穿而失效。电击穿的主要原因包括冲击电离、陷阱产生和阳极空穴注入。对于所有电介质衬垫，击穿后，绝缘性能将大大降低，从而导致器件故障。对此，本公开实施例提出的阻挡层绝缘层融合的通孔填充工艺实现的有机衬垫层可实现电击穿后的绝缘性能自修复(也即可热修复)。本发明实现的有机衬垫层绝缘性能自修复工艺包括以下步骤：
(1)将击穿后的通孔样品置于适当温度的加热板上在惰性气体氛围下常压加热(对聚亚酰胺衬垫，该优选温度为80℃)并保温一定时间(对聚亚酰胺，该优选时间为10min)，之后关闭加热板，使样品与加热板一同降至室温，完成退火处理。
(2)对易氧化填充金属(如铜)，如在非惰性气体或在真空氛围下进行处理，需要将退火处理后样品置于0.1mol/L盐酸内浸泡5min，以去除表面金属氧化层。
本发明实现的有机衬垫层自修复工艺结果如图5所示，I-V曲线通过在两个相邻通孔之间施加0V～100V连续变化的电压得到。在击穿过程中，漏电流在V＝76V时发生了3个数量级的变化，标志有机衬垫层的击穿。在击穿后进行的测量中，漏电流在10V内就达到了设备截止电流，表明该通孔衬垫层绝缘性能的严重劣化。在经过如上所述的自修复退火处理后，该孔测量得到I-V曲线如图5所示自修复后曲线，漏电流在86V时再次发生三个数量级的变化，这表明了有机衬垫层绝缘性能的恢复。该方法可实现75％或更高的典型修复比例，与同样处理方法后的采用传统氧化硅绝缘层填充的通孔相比，如图6所示，修复 比例有6倍以上的提高。
需要说明的是，尽管以上述实施例作为示例介绍了基于阻挡层绝缘层融合的可热修复通孔制备方法如上，但本领域技术人员能够理解，本公开应不限于此。事实上，用户完全可根据个人喜好和/或实际应用场景灵活设定各步骤，只要符合本公开的技术方案即可。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (8)

  1. 一种基于阻挡层绝缘层融合的可热修复通孔制备方法，其特征在于，所述方法包括：
    对衬底进行刻蚀或增材制造，在所述衬底的第一面形成预设尺寸的孔，所述衬底包括硅衬底或玻璃衬底；
    采用旋涂或者滴涂的方式在所述孔的表面生成融合层，所述融合层作为需要制备的通孔的阻挡层和绝缘层；
    在所述融合层上生成种子层；
    利用所述种子层对所述孔进行填充，形成导电柱；
    进行抛光直至暴露出所述衬底的第一面；
    对所述衬底的与所述第一面相对的第二面进行减薄直至暴露出所述导电柱，完成所述衬底中所述通孔的制备。
  2. 根据权利要求1所述的方法，其特征在于，所述融合层的材料包括具有流动性和绝缘性的有机材料、无机材料或复合材料，所述有机材料包括聚酰亚胺，
    其中，采用旋涂或者滴涂的方式在所述孔的表面生成融合层，包括：
    在所述衬底的第一面旋涂融合层材料前体并在固化后形成融合层，所述旋涂的速度和时间是根据所述预设尺寸确定的。
  3. 根据权利要求2所述的方法，其特征在于，所述融合层的材料的粘度是与所述孔的结构特征以及旋涂的速度匹配的。
  4. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在所述衬底的第一面形成介质层；
    其中，所述对衬底进行刻蚀，在所述衬底的第一面形成预设尺寸的孔，包括：
    对所述介质层和所述衬底进行刻蚀，在对应于所述衬底的第一面的方向形成预设尺寸的孔；
    其中，在所述孔为盲孔的情况下，所述孔的底面处于所述衬底中。
  5. 根据权利要求1所述的方法，其特征在于，所述种子层的材料包括金属或金属合金，所述金属包括金属镍，所述在所述融合层上生成种子层，包括：
    在70℃下采用化学镀的方式在所述融合层上生成金属镍种子层。
  6. 根据权利要求1所述的方法，其特征在于，所述通孔的直径为10纳米到900微米之间，所述通孔的深宽比大于或等于100:1。
  7. 根据权利要求1所述的方法，其特征在于，所述孔是利用以下方法中的任意一种制备的：干法刻蚀、湿法刻蚀、Bosch工艺和3D打印。
  8. 根据权利要求1所述的方法，其特征在于，所述导电柱的材料包括以下任意一种：金属、金属合金、金属性纳米材料和导电聚合物，所述金属包括金属铜，所述金属性纳米材料包括碳纳米管，所述导电聚合物包括银纳米浆料；所述导电柱是利用电镀工艺、金属填充工艺、金属合金填充工艺和加压填充工艺中的任意一种工艺制备的。
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Publication number Priority date Publication date Assignee Title
CN103311141A (zh) * 2013-07-05 2013-09-18 北京理工大学 一种同轴垂直互连导电体的制作方法
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CN104882432B (zh) * 2015-04-24 2017-12-08 苏州含光微纳科技有限公司 一种具有垂直通孔互连的半导体结构及其制造方法
CN107293515A (zh) * 2017-06-20 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种tsv封装结构的制备方法及其所制备的tsv封装结构
CN107731744A (zh) * 2017-10-12 2018-02-23 北京理工大学 一种空气绝缘低阻硅柱垂直通孔结构及其制造方法
CN110854064A (zh) * 2019-11-27 2020-02-28 西安电子科技大学 一种tsv硅通孔和单层rdl再布线一次性整体成型方法
CN111769095B (zh) * 2020-06-18 2022-06-21 复旦大学 基于高功能密度硅通孔结构的三维电容电感及制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311141A (zh) * 2013-07-05 2013-09-18 北京理工大学 一种同轴垂直互连导电体的制作方法
CN104900585A (zh) * 2015-04-16 2015-09-09 北京理工大学 一种垂直互连侧壁绝缘层的制作方法
CN111816608A (zh) * 2020-07-09 2020-10-23 电子科技大学 玻璃盲孔加工方法
CN114725013A (zh) * 2022-03-30 2022-07-08 清华大学 基于阻挡层绝缘层融合的硅通孔制备方法

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