WO2023184927A1 - 场效应管、存储器及其制备方法、半导体阵列和晶体管 - Google Patents

场效应管、存储器及其制备方法、半导体阵列和晶体管 Download PDF

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WO2023184927A1
WO2023184927A1 PCT/CN2022/124169 CN2022124169W WO2023184927A1 WO 2023184927 A1 WO2023184927 A1 WO 2023184927A1 CN 2022124169 W CN2022124169 W CN 2022124169W WO 2023184927 A1 WO2023184927 A1 WO 2023184927A1
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word line
semiconductor
substrate
drain
source
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PCT/CN2022/124169
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English (en)
French (fr)
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戴瑾
尹晓明
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北京超弦存储器研究院
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Publication of WO2023184927A1 publication Critical patent/WO2023184927A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of semiconductor technology. Specifically, this application relates to a field effect transistor, a memory and a preparation method thereof, a semiconductor array and a transistor.
  • a field effect transistor is an electronic device that uses electric field effects to control current.
  • Field effect transistors generally produce less noise and can be used in noise-sensitive electronic devices such as tuners and for VHF and Low-noise amplifier for satellite receivers; field effect tubes are relatively immune to radiation, show no offset voltage at zero drain current, and can be used as signal choppers.
  • This application proposes a field effect transistor, a memory and a preparation method thereof, a semiconductor array and a transistor to improve the integration of the memory, simplify the device structure, etc.
  • a field effect transistor including:
  • a stacked structure which includes a drain structure, a gate structure, and a source structure that are sequentially stacked above a substrate along a first direction, the first direction being perpendicular to the substrate; the stacked structure It also includes a gate insulation structure wrapped around the periphery of the gate structure;
  • Two semiconductor structures are spaced apart along the second direction, and the gate structure is located between the two semiconductor structures; the gate insulation structure and the drain electrode on the side surfaces of the semiconductor structure and the gate structure
  • the side surface of the structural part is in contact with the side surface of the source structural part, and the second direction is parallel to the substrate.
  • embodiments of the present application provide a memory, including: a substrate and at least two word lines; the memory includes at least two of the field effect transistors arranged in an array, with any phase along the second direction.
  • a semiconductor structure is provided between the stacked structures of two adjacent field effect transistors, and the second direction is parallel to the substrate;
  • the word line extends along a third direction and includes a gate structure of each of the stacked structures located in the same straight line along the third direction.
  • the third direction is parallel to the substrate and is parallel to the second direction. There is a set angle between them.
  • embodiments of the present application provide a memory preparation method, including:
  • a drain structure is prepared on one side of the substrate, and the drain structure is arranged in an array;
  • a word line, a source structure, a gate insulation structure and a semiconductor structure are prepared on the side of the drain structure away from the substrate, and the drain structure, the word line and the source structure are stacked along a first direction.
  • Layer is placed, the gate insulating structure is wrapped around the periphery of the word line, a semiconductor structure is arranged along the second direction between adjacent word lines, the word line extends along the third direction; the semiconductor structure is arranged along the third direction.
  • the second direction is in contact with the side surface of the drain structure part, the side surface of the source structure part and the gate insulation structure respectively, the first direction is perpendicular to the substrate, and the second direction Parallel to the substrate, the third direction is parallel to the substrate and has a set angle with the second direction.
  • embodiments of the present application provide a semiconductor array, including:
  • a plurality of word lines having an upper surface, a lower surface, two opposite side surfaces, and two opposite end surfaces; the plurality of word lines extend along the column direction on the upper surface of the substrate and are spaced apart in the row direction. arrangement;
  • each gate insulating layer corresponding to one of the word lines, the gate insulating layer surrounding the upper surface, lower surface and two opposite surfaces of the corresponding word line lateral surface;
  • a plurality of drain electrodes are spaced apart from each other along the row direction and the column direction and are distributed in an array; the drain electrode in each column is located on the lower surface of one of the word lines and is insulated from the word line through the gate insulating layer. Different columns The drain electrode is located under different word lines;
  • a plurality of source electrodes are spaced apart from each other along the row direction and the column direction and are distributed in an array; the source electrode in each column is located on the upper surface of one of the word lines and is insulated from the word line through the gate insulating layer. Different columns The source electrode is located above different word lines;
  • a plurality of semiconductor film layers arranged spaced apart from each other, wherein two columns of the semiconductor film layers are respectively provided on two side surfaces of each word line, and each of the semiconductor film layers in each column is connected to the corresponding semiconductor film layer in a corresponding column.
  • Each of the source electrodes has a one-to-one correspondence, and the two semiconductor film layers corresponding to one of the source electrodes are spaced apart from the source electrode in the row direction.
  • embodiments of the present application provide a transistor, including:
  • Two semiconductor film layers are spaced apart along the row direction.
  • Each of the semiconductor film layers has two main surfaces perpendicular to the direction of the substrate. Two of the main surfaces of the two semiconductor film layers are adjacent and facing each other. and place;
  • a word line is located between the two semiconductor film layers and extends along the column direction, and the row direction is perpendicular to the column direction; the word line has an upper surface, a lower surface and two side surfaces;
  • An insulating layer is located on the upper surface, lower surface and two side surfaces of the word line.
  • the two adjacent main surfaces of the two semiconductor film layers are respectively in contact with the insulating layer on the side surfaces of the word line.
  • the two semiconductor film layers are distributed on the side surface of the word line and distributed on the insulating layer of the word line;
  • the source electrode and the drain electrode are respectively located on the upper surface and lower surface of the word line, and are insulated from the word line through the insulating layer.
  • the drain structure, the gate structure and the source structure are stacked in a direction perpendicular to the substrate to form a stacked structure, thereby simplifying the structure of the field effect transistor and reducing the manufacturing field.
  • channels are formed on both sides of the gate structure to conduct the drain structure and the source structure, which can increase the sensitivity of the field effect transistor. The direction of this channel is perpendicular to the substrate.
  • the semiconductor structure when no voltage is applied, the semiconductor structure can play the role of insulating the stacked structure of two adjacent field effect transistors, so there is no need to set up an additional insulating structure between the stacked structures of two adjacent field effect transistors. , can reduce the area occupied by the field effect transistor, facilitate the improvement of memory integration, and help reduce the manufacturing cost of the memory.
  • Figure 1 is a schematic cross-sectional view of the film structure of a field effect tube provided by an embodiment of the present application
  • Figure 2 is a schematic cross-sectional view of the film structure of a memory provided by an embodiment of the present application
  • Figure 3 is a schematic cross-sectional view taken at H-H in Figure 2;
  • Figure 4 is a schematic flow chart of a memory preparation method provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a preparation method for preparing word lines, source structures, gate insulation structures and semiconductor structures on the side of the drain structure away from the substrate provided by the embodiment of the present application;
  • Figure 6 is a schematic cross-sectional view of the film structure prepared by preparing a drain structure on one side of the substrate and arranging the drain structure array according to the embodiment of the present application;
  • Figure 7 is a schematic cross-sectional view of the film structure of the first intermediate substrate obtained by covering one side of the substrate exposed to the drain structure with a first dielectric layer according to an embodiment of the present application;
  • Figure 8 is a schematic top view of the structure of the patterned first intermediate substrate provided by the embodiment of the present application.
  • Figure 9 is a cross-sectional view at A-A in Figure 8.
  • Figure 10 is a top view schematic diagram obtained after preparing the first initial gate insulation structure conforming to the inner surface of the first trench according to the embodiment of the present application;
  • Figure 11 is a cross-sectional view at B-B in Figure 10;
  • Figure 12 is a top view schematic diagram obtained after preparing word lines according to the embodiment of the present application.
  • Figure 13 is a cross-sectional view at C-C in Figure 12;
  • Figure 14 is a schematic top view obtained after forming the first gate insulation structure and the third gate insulation structure according to the embodiment of the present application;
  • Figure 15 is a cross-sectional view at D-D in Figure 14;
  • Figure 16 is a schematic top view obtained after patterning the second intermediate substrate covering the second dielectric layer according to the embodiment of the present application.
  • Figure 17 is a cross-sectional view at E-E in Figure 16;
  • Figure 18 is a top view schematic diagram obtained after preparing the semiconductor structure provided by the embodiment of the present application.
  • Figure 19 is a cross-sectional view at F-F in Figure 18;
  • Figure 20 is a schematic cross-sectional view of the film structure obtained after covering the third dielectric layer on the side exposed to the semiconductor structure according to the embodiment of the present application;
  • Figure 21 is a schematic cross-sectional view of the film structure obtained by etching the third dielectric layer according to the embodiment of the present application.
  • Figure 22 is a top view schematic diagram obtained after preparing the source structure provided in the embodiment of the present application.
  • Figure 23 is a cross-sectional view at G-G in Figure 22;
  • Figure 24 is a schematic flow chart of another preparation method of preparing word lines, source structures, gate insulation structures and semiconductor structures on the side of the drain structure away from the substrate provided by the embodiment of the present application;
  • Figure 25 is a three-dimensional schematic diagram of an array-arranged drain structure provided on one side of a substrate according to an embodiment of the present application.
  • Figure 26 is a schematic three-dimensional view obtained after preparing the third intermediate substrate according to the embodiment of the present application.
  • Figure 27 is a schematic three-dimensional view obtained after preparing the fourth intermediate substrate according to the embodiment of the present application.
  • Figure 28 is a three-dimensional schematic diagram obtained after patterning the fourth intermediate substrate provided by the embodiment of the present application.
  • Figure 29 is a three-dimensional schematic diagram obtained after preparing the source structure provided in the embodiment of the present application.
  • Figure 30 is a schematic three-dimensional view obtained after preparing the fifth intermediate substrate according to the embodiment of the present application.
  • Figure 31 is a schematic top view of the patterned fifth intermediate substrate provided by the embodiment of the present application.
  • Figure 32 is a cross-sectional view at J-J in Figure 31;
  • Figure 33 is a schematic cross-sectional view of the film structure obtained after preparing the first gate insulation structure according to the embodiment of the present application.
  • Figure 34 is a schematic cross-sectional view of the film structure obtained after filling the third groove with semiconductor material to form the initial semiconductor structure in the preparation of the semiconductor structure provided by the embodiment of the present application;
  • Figure 35 is a schematic cross-sectional view of the film structure obtained after removing excess semiconductor material through the CMP process in preparing the semiconductor structure provided by the embodiment of the present application, so that the surface of the remaining initial semiconductor structure is flush with the surface of the five-dielectric structure;
  • Figure 36 is a schematic cross-sectional view of the film structure after the semiconductor structure is obtained by etching back the initial semiconductor structure according to the embodiment of the present application;
  • Figure 37 is a schematic cross-sectional view of the film structure obtained after filling the side of the semiconductor structure and the five-dielectric structure away from the substrate with dielectric material to form a sixth dielectric layer according to the embodiment of the present application;
  • Figure 38 is a schematic cross-sectional view of the film structure after the sixth dielectric layer is smoothed through the CMP process until the surface of the source structure is exposed, and the sixth dielectric layer is formed into the sixth dielectric structure according to the embodiment of the present application;
  • Figure 39 is a schematic cross-sectional view of the film structure of a semiconductor array provided by an embodiment of the present application.
  • Figure 40 is a cross-sectional view at KK in Figure 39;
  • Figure 41 is a schematic cross-sectional view of the film structure after removing the semiconductor film layer in a semiconductor array provided by an embodiment of the present application;
  • Figure 42 is a schematic cross-sectional view of the film structure of a transistor provided by an embodiment of the present application.
  • Fig. 43 is a cross-sectional view at LL in Fig. 42.
  • 8-Fourth intermediate substrate 8-Second gate insulating layer; 82-Polysilicon layer; 83-Third gate insulating layer; 84-Source layer;
  • 300-semiconductor array 301-substrate; 302-word line; 303-gate insulating layer; 304-drain electrode; 305-source electrode; 306-semiconductor film layer; 307-trench; 308-dielectric protective layer;
  • This application provides a field effect transistor, a memory and a preparation method thereof, a semiconductor array and a transistor, aiming to solve the above technical problems of the prior art.
  • an embodiment of the present application provides a field effect transistor 100 .
  • a schematic structural diagram of the field effect transistor 100 includes: a stacked structure 1 and two semiconductor structures 2 .
  • the laminated structure 1 is configured to be disposed on one side of the substrate 201 (ie, the upper surface of the substrate 201 ). As shown in FIG. 1 , the laminated structure 1 includes components along a first direction (vertical to the upper surface of the substrate 201 ). The drain structure 11, the gate structure 121 and the source structure 13 are sequentially stacked on the surface of the gate structure 121. The stacked structure 1 also includes an upper surface, a lower surface and two opposite surfaces wrapped around the gate structure 121. side surface) of the gate insulating structure 122.
  • the two semiconductor structures 2 are spaced apart, and the gate structure 121 is located between the two semiconductor structures 2 .
  • the semiconductor structure 2 is in contact with the gate insulation structure 122 of the side surface of the gate electrode 121 , the side surface of the drain structure 11 part and the side surface of the source structure 13 part.
  • the drain structure 11 , the gate structure 121 and the source structure 13 are stacked in a direction perpendicular to the substrate 201 to form a stacked structure 1 , and the drain structure 11 and the source structure 13 are on the substrate 201
  • the orthographic projections at least partially overlap, thereby simplifying the structure of the field effect transistor 100 , reducing the difficulty of manufacturing the field effect transistor 100 , and reducing the cost of manufacturing the field effect transistor 100 .
  • two semiconductor structures 2 are respectively provided on both sides of the stacked structure 1 along the second direction, that is, one semiconductor structure 2 is provided on both sides of the stacked structure 1, and on the opposite gate
  • channels are formed on both sides of the gate structure 121 to conduct the drain structure 11 and the source structure 12, which can increase the sensitivity of the field effect transistor 100.
  • the direction of this channel is perpendicular to the substrate 201 direction; when no voltage is applied, the semiconductor structure 2 can play the role of insulating the stacked structure 1 of two adjacent field effect transistors 100, so there is no need to insulate the stacked structure 1 of two adjacent field effect transistors 100. Setting an additional insulating structure between them can reduce the area occupied by the field effect transistor 100, facilitate the improvement of memory integration, and help reduce the manufacturing cost of the memory.
  • the substrate 201 is introduced as a reference.
  • the substrate 201 may include at least one of a substrate, a source structure, a drain structure, a gate structure and a semiconductor structure. Depending on the actual situation, The specific settings are not limited here.
  • the drain structure 11 and the source structure 13 at least partially overlap in the first direction.
  • the orthographic projections of the drain structure 11 and the source structure 13 on the substrate 201 at least partially overlap, which can greatly save the occupied area of the field effect transistor 100 in the embodiment of the present application, and is beneficial to improving the field effect transistor 100 per unit area. quantity, thereby helping to increase the integration density of the field effect transistor 100.
  • the drain structure 11 and the source structure 13 overlap.
  • the drain structure 11 and the source structure 13 are arranged facing each other up and down, which further reduces the area occupied by the field effect transistor 100 and is conducive to increasing the number of field effect transistors 100 per unit area, thereby conducive to increasing the number of field effect transistors.
  • the integration density of 100 is beneficial to reducing the manufacturing difficulty and cost of the field effect transistor 100.
  • the gate insulation structure 122 includes a first gate insulation structure 1221, a second gate insulation structure 1222, and a third gate insulation structure 1223.
  • the first gate insulation structure 1221 is disposed between the gate structure 121 and the semiconductor structure. 2; the second gate insulation structure 1222 is provided between the gate structure 121 and the drain structure 11; the third gate insulation structure 1223 is provided between the gate structure 121 and the source structure 13.
  • the material of the semiconductor structure 2 is an amorphous semiconductor material, which can serve to conduct the drain structure 11 and the source structure 13 under the control of the gate structure 121 , further reducing the volume of the field effect transistor 100 .
  • the material of the semiconductor structure 2 is a metal oxide semiconductor.
  • the metal in the metal oxide semiconductor may include at least one or more of indium, gallium, zinc, tungsten, tin, rare earth metals, and the like. Such as IGZO, ITO, IWO, etc.
  • the metal oxide semiconductor material in this application is used to distinguish it from single crystal, polycrystalline, amorphous and other semiconductor materials, but the specific composition of the metal oxide semiconductor material is not limited.
  • an embodiment of the present application provides a memory 200, as shown in FIGS. 2 and 3, including: a substrate 201 and at least two word lines 202.
  • the memory 200 includes at least two field effect transistors 100 in the previous embodiment arranged in an array. Along the second direction, a semiconductor structure 2 is disposed between the stacked structures 1 of any two adjacent field effect transistors 100. direction parallel to the substrate.
  • the word line 202 extends along the third direction and includes the gate structures 121 of each stacked structure 1 located on the same straight line along the third direction.
  • the third direction is parallel to the substrate 201 and has a set angle with the second direction.
  • a high-density memory 200 can be prepared, further reducing the volume of the memory 200, and facilitating the implementation of the memory. 200 integration.
  • vertical channels can be formed on both sides of the stacked structure 1 of the field effect transistor 100 of the memory 200, which can enhance the conductive performance of the memory 200.
  • FIG. 4 The schematic flow chart of the preparation method is shown in Figure 4, including step S1 and step S2, as follows:
  • S1 Prepare the drain structure 11 on one side of the substrate 201, and arrange the drain structure 11 in an array.
  • metal is deposited on one side of the substrate 201 to form a metal layer, and the drain structure 11 arranged in an array is obtained through photolithography and etching processes.
  • S2 Prepare the word line 202, the source structure 13, the gate insulation structure 122 and the semiconductor structure 2 on the side of the drain structure 11 away from the substrate 201.
  • the drain structure 11, the word line 202 and the source structure 13 are stacked along the first direction, the gate insulation structure 122 is wrapped around the periphery of the word line 202, and a semiconductor structure is arranged between adjacent word lines 202 along the second direction.
  • the word line 202 extends along the third direction; the semiconductor structure 2 is in structural contact with the side surface of the drain structure 11 part, the side surface of the source structure 13 part and the gate insulation structure 122 part along the second direction.
  • the first direction Perpendicular to the substrate 201, the second direction is parallel to the substrate 201, and the third direction is parallel to the substrate 201 and has a set angle with the second direction.
  • step S2 a preparation method of preparing the word line 202, the source structure 13, the gate insulation structure 122 and the semiconductor structure 2 on the side of the drain structure 11 away from the substrate 201
  • the flow chart is shown in Figure 5, including the following steps S201 to S206:
  • S201 Cover the first dielectric layer 4 on one side of the substrate 201 exposed to the drain structure 11 to obtain the first intermediate substrate 3, pattern the first intermediate substrate 3, and form at least two first intermediate substrates extending in the third direction.
  • the trench 51 has a plurality of drain structures 11 exposed in the first trench 51 .
  • FIG. 6 is a schematic structural diagram of an array of drain structures 11 arranged on one side of the substrate 201.
  • the drain structures 11 are arranged perpendicularly to the substrate 201 along the first direction;
  • FIG. 7 is a schematic diagram of the drain structure 11 exposed on One side of the substrate 201 is covered with the first dielectric layer 4 to obtain the structural schematic diagram of the first intermediate substrate 3.
  • the material of the first dielectric layer 4 can be silicon oxide, silicon nitride, etc., as long as it can play an insulating role. .
  • FIG. 8 a top view is shown after photolithography and etching processes are performed on one side of the first intermediate substrate 3 to form the first trench 51 .
  • FIG. 9 is a cross-sectional view at A-A in FIG. 8 , where the photolithography process may include Coat photoresist on one side of the first intermediate substrate 3, and set a mask above the first intermediate substrate 3 for exposure and development.
  • the mask includes a light-transmitting area and a non-light-transmitting area, and is located in the third direction.
  • the orthographic projection of the same straight line of the drain structure 11 on the substrate 201 falls into the orthographic projection of the light-transmitting area on the substrate 201.
  • Ultraviolet light is used to illuminate the side of the mask away from the first intermediate substrate 3, and then the non-transparent area is illuminated.
  • the photoresist in the developed area is developed, and then etching is performed on the developed photoresist area until the surface of the drain structure 11 is exposed.
  • the patterning process may also include alignment, drying and other processes. The specific process may be based on the actual situation. Choose according to the situation.
  • S202 Prepare a first initial gate insulation structure 52 conforming to the inner surface of the first trench 51, and prepare a word line 202 in the second trench 53 conforming to the first initial gate insulation structure 52.
  • the gate insulation structure 52 includes a second gate insulation structure 1222 between the word line 202 and the drain structure 11 .
  • the first initial gate insulating structure 52 can be conformally prepared on the inner surface of the first trench 51 using atomic layer deposition (ALD).
  • the material of the first initial gate insulating structure 52 can be Silicon oxide or silicon nitride, etc.
  • FIG. 10 The top schematic diagram obtained after the first initial gate insulation structure 52 is conformally prepared on the inner surface of the first trench 51 is shown in FIG. 10 , and FIG. 11 is a cross-sectional view at B-B in FIG. 10 .
  • step S202 the word line 202 is prepared in the second trench 53 conforming to the first initial gate insulation structure 52.
  • a top view of the word line 202 is obtained after preparing the word line 202.
  • FIG. 13 is The cross-sectional view at C-C in Figure 12 includes:
  • a metal layer is deposited on one side of the first initial insulating structure 52 with the second trench 53 .
  • the metallic material may be tungsten.
  • the metal layer is polished through a CMP (Chemical Mechanical Polishing) process until the first initial insulating structure 52 is exposed, that is, the metal layer is flush with the surface of the first initial dielectric structure 41 .
  • CMP Chemical Mechanical Polishing
  • the remaining metal layer in the second trench 53 is etched to obtain a word line 202.
  • the word line 202 includes the gate structure 121; the word line 202 extends along the third direction and includes gates located on the same straight line along the third direction. Structure 121 , the word line 202 and the drain structure 11 are in contact through a second gate insulation structure 1222 .
  • S203 Fill the second trench 53 with the word line 202 with insulating material and smooth it to form the first gate insulation structure 1221 and the third gate insulation structure 1223 to obtain the second intermediate substrate 5, as shown in Figure 14 is a schematic top view of the second intermediate substrate 5 , and FIG. 15 is a cross-sectional view taken along E-E in FIG. 14 .
  • the second trench 53 is filled with insulating material, and the excess insulating material is removed through a CMP process to form the first gate insulation structure 1221 and the third gate insulation structure 1223.
  • S204 Pattern the second intermediate substrate 5 covering the second dielectric layer to form first grooves 61 arranged in an array.
  • the first grooves 61 are located between any two adjacent drain structures 11. Partial side surfaces of the first gate insulation structure 1221 and the drain structure 11 are exposed in the first grooves 61 ; a semiconductor structure 2 is prepared in each first groove 61 .
  • one side of the second intermediate substrate 5 is covered with a second dielectric layer, and processes such as photolithography and etching are performed on one side of the second dielectric layer to form first grooves 61 and second grooves arranged in an array.
  • the dielectric structure 55, photolithography, etching and other processes are existing processes and will not be described in detail here.
  • a top view schematic diagram is obtained after covering one side of the second intermediate substrate 5 with the second dielectric layer.
  • Figure 16 17 is a cross-sectional view at E-E in Figure 16 .
  • step S204 a semiconductor structure 2 is prepared in each first groove 61.
  • Figure 18 is a top view of the semiconductor structure 2 obtained after preparing the semiconductor structure 2.
  • Figure 19 is a cross-sectional view at F-F in Figure 18, including:
  • a semiconductor material is deposited in the first groove 61 to form a semiconductor layer.
  • the semiconductor material may include at least one of indium gallium zinc oxide and tungsten-doped indium oxide, or the semiconductor material may be other amorphous semiconductor materials.
  • the remaining semiconductor layer in the first groove 61 is etched to obtain the semiconductor structure 2.
  • the semiconductor structure 2 is respectively connected with the side surface of the drain structure 11 part, the side surface of the source structure 13 part and the second part along the second direction. Part of the side surface of the initial gate insulation structure 54 is in contact.
  • S205 Cover the third dielectric layer 56 on the side exposed to the semiconductor structure 2, etch the third dielectric layer 56, and form a second groove 62, exposing part of the third gate insulation structure 1223 and Side surface of the semiconductor structure 2 part.
  • the third dielectric layer 56 on the side of the semiconductor structure 2 and the second dielectric structure 55 away from the substrate 201 etch the third dielectric layer 56 to form a third dielectric structure 57, as shown in Figures 20 and 21 .
  • FIG. 22 is a top view schematic diagram obtained after preparing the source structure 13, and FIG. 23 is a cross-sectional view at G-G in FIG. 22.
  • the second groove 62 is filled with metal to form a metal layer, and the metal layer is ground flush with the surface of the third dielectric structure 57 through a CMP process to obtain the source structure 13 .
  • step S2 word lines 202, source structures 13, gate insulation structures 122 and another semiconductor structure 2 are prepared on the side of the drain structure 11 away from the substrate 201.
  • the schematic flow chart of the preparation method is shown in Figure 24, including steps S211 to S216, as follows:
  • S211 Cover the side of the substrate 201 exposed on the drain structure 11 with the fourth dielectric layer to obtain the third intermediate substrate 7 .
  • FIG. 25 is a schematic three-dimensional view of the drain structure 11 arranged in an array on one side of the substrate 201
  • FIG. 26 is a third structure flush with the surface of the drain structure 11 formed on one side of the drain structure 11 .
  • the three-dimensional schematic diagram obtained after four initial dielectric structures 71.
  • One method of preparing the third intermediate substrate 7 is: depositing metal on one side of the substrate 201, and obtaining an array-arranged drain structure 11 through photolithography and etching processes; depositing a dielectric in the area where the metal has been etched away The material forms the dielectric layer, which can be silicon oxide or silicon nitride. The CMP process is then used to make the surface of the dielectric layer flush with the surface of the drain structure 11 to obtain the third intermediate substrate 7 .
  • Another method of preparing the third intermediate substrate 7 is to deposit a dielectric material on one side of the substrate 201 to form a dielectric layer, and obtain an array of grooves and dielectric structures through photolithography and etching processes; Fill the metal to form a metal layer, and then use the CMP process to make the surface of the metal layer flush with the surface of the dielectric structure to form the drain structure 11 to obtain the third intermediate substrate 7 .
  • FIG. 27 is a schematic three-dimensional view obtained after preparing the fourth intermediate substrate 8 .
  • the substrate 201 along the first direction, there are the substrate 201, the fourth initial dielectric structure 71, the second gate insulating layer 81, the polysilicon layer 82, the third gate insulating layer 83 and the source layer 84 in order.
  • S213 Pattern the fourth intermediate substrate 8 to form at least two second trenches 92 extending in the third direction and corresponding first intermediate structure rows 91.
  • the first intermediate structure rows 91 include stacked second gate insulation. Structure 1222, word line 202, third gate insulation structure 1223 and initial source structure 911, the side surface of part of the drain structure 11 is exposed in the second trench 92, as shown in Figure 28, which is the patterned fourth intermediate substrate 8 The resulting three-dimensional diagram.
  • photolithography and etching processes are performed on one side of the fourth intermediate substrate 8 to etch the fourth intermediate substrate 8 until the side surface of part of the drain structure 11 is exposed, and the fourth initial dielectric structure 71 forms the fourth dielectric. Structure72.
  • a first intermediate structure row 91 is provided between two adjacent second trenches 92 .
  • the first intermediate structure row 91 also includes a fourth dielectric structure 72 and a portion of the drain structure 11 .
  • S214 Pattern the initial source structure 911 to form the source structure 13 arranged in an array.
  • the source structure 13 and the drain structure 11 are arranged facing each other.
  • One side of the four-dielectric structure 72 covers the fifth dielectric layer 931 to form a fifth intermediate substrate 93; the fifth intermediate substrate 93 is patterned to form a third groove 94 arranged in an array.
  • the third groove 94 Located between any two adjacent source structures 13 , the third groove 94 exposes part of the side surface of the drain structure 11 , part of the side surface of the word line 202 , and the side surface of the source structure 13 , as shown in FIG. 29
  • photolithography and etching are performed on the side of the initial source structure 911 away from the substrate 201 to obtain the source structure 13 .
  • FIG. 30 is a schematic three-dimensional view obtained after forming the fifth intermediate substrate 93 .
  • Photolithography and etching are performed on one side of the fifth intermediate substrate 93, and the fifth dielectric layer 931 forms a fifth dielectric structure 932, forming a third groove 94 arranged in an array.
  • Figure 31 shows the patterned fifth intermediate substrate 93.
  • Figure 32 is a schematic top view obtained at the end, which is a cross-sectional view at J-J in Figure 31.
  • S215 Prepare the first gate insulation structure 1221 based on part of the side surface of the word line 202.
  • the first gate insulation structure 1221 is prepared based on part of the side surface of the word line 202, including: oxidizing the side surface of the word line 202, such as thermal oxidation, on the side surface of the word line 202.
  • the first gate insulating structure 1221 is formed.
  • FIG. 33 is a schematic cross-sectional view of the film structure obtained after forming the first gate insulating structure 1221.
  • preparing the semiconductor structure 2 in the third groove 94 exposing the first gate insulation structure 1221 includes the following process:
  • semiconductor material is filled in the third groove 94 to form an initial semiconductor structure 95 .
  • the semiconductor material may be at least one of indium gallium zinc oxide and tungsten-doped indium oxide, or other amorphous semiconductor materials.
  • a schematic cross-sectional view of the film structure obtained after filling the third groove 94 with semiconductor material to form the initial semiconductor structure 95 is shown in FIG. 34 .
  • Figure 35 is a schematic cross-sectional view of the film structure obtained after removing the excess semiconductor material through the CMP process. .
  • the semiconductor structure 2 is obtained.
  • the semiconductor structure 2 is in contact with the side surface of the drain structure 11 part, the side surface of the source structure 13 part and the first gate insulation structure 1221 respectively along the second direction, such as Figure 36 shows a schematic cross-sectional view of the film structure obtained after obtaining the semiconductor structure 2.
  • step S216 prepares the semiconductor structure 2 in the third groove 94 exposing the first gate insulation structure 1221, it also includes:
  • the side of the semiconductor structure 2 and the fifth dielectric structure 932 away from the substrate 201 is filled with dielectric material to form a sixth dielectric layer 96.
  • a schematic cross-sectional view of the film structure obtained after forming the sixth dielectric layer 96 is shown.
  • the sixth dielectric layer 96 is polished through the CMP process until the surface of the source structure 13 is exposed.
  • the sixth dielectric layer 96 is formed into the sixth dielectric structure 97 .
  • the sixth dielectric layer 96 is polished through the CMP process. Schematic cross-sectional view of the obtained film structure.
  • the semiconductor array 300 includes: a substrate 301, multiple word lines 302, multiple gate insulating layers 303, multiple A plurality of drain electrodes 304, a plurality of source electrodes 305 and a plurality of semiconductor film layers 306 spaced apart from each other.
  • Substrate 301 has an upper surface.
  • the plurality of word lines 302 have an upper surface, a lower surface, two opposite side surfaces, and two opposite end surfaces; the plurality of word lines 302 extend along the column direction on the upper surface of the substrate 301 and are arranged at intervals in the row direction.
  • Each gate insulating layer 303 corresponds to one word line 302 , and the gate insulating layer 303 surrounds the upper surface, lower surface and two opposite side surfaces of the corresponding word line 302 .
  • a plurality of drain electrodes 304 are spaced apart from each other along the row and column directions in an array distribution; the drain electrodes 304 of each column are located on the lower surface of a word line 302 and are insulated from the word line 302 through the gate insulating layer 303.
  • the drain electrodes 304 of different columns are located on the lower surface of a word line 302. Different word lines 302 below.
  • a plurality of source electrodes 305 are spaced apart from each other along the row direction and the column direction in an array distribution; each column source electrode 305 is located on the upper surface of a word line 302 and is insulated from the word line 302 through the gate insulating layer 303. Different column source electrodes 305 are located on above different word lines 302.
  • Each semiconductor film layer 306 in each column corresponds to each source electrode 305 in the corresponding column, corresponding to one source electrode 305.
  • the two semiconductor film layers 306 and the source electrode 305 are spaced apart in the row direction.
  • two rows of semiconductor film layers 306 are respectively provided on the two side surfaces of each word line 302. Channels are formed on both sides of the word line 302 to conduct the drain electrode 304 and the source electrode 305, which can increase the number of semiconductor films.
  • the semiconductor film layer 306 can play the role of insulating two adjacent semiconductors, so there is no need to set up an additional insulation structure between the two adjacent semiconductors, which can reduce the area occupied by the semiconductor and facilitate the improvement of the memory.
  • the degree of integration is beneficial to reducing the manufacturing cost of memory.
  • trench 307 there is a trench 307 extending along the extension direction of the word line 302 between two adjacent word lines 302 , and the trench 307 exposes the side surfaces of the two adjacent word lines 302 .
  • the gate insulating layer 303 , as well as the side surfaces of the source electrode 305 , and the main surface of the semiconductor film layer 306 are at least located where the gate insulating layer 303 extends in a direction perpendicular to the substrate 301 .
  • the trench 307 extends to the side surface of the drain electrode 304 below the word line 302, and the main surface of the semiconductor film layer 306 simultaneously extends to the side surface of the drain electrode 304 above the word line 302, and extending to the side surface of the source electrode 305 .
  • the trench 307 between two adjacent word lines 302 is provided with a column of semiconductor film layers 306 spaced apart in the column direction.
  • Each semiconductor film layer 306 has two oppositely arranged semiconductor film layers 306. The two side surfaces of the semiconductor film layer 306 face the two adjacent word lines 302 respectively, and are respectively connected to the gate insulating layers 303 on the two side surfaces of the two adjacent word lines 302.
  • a top surface of the semiconductor film layer 306 away from the substrate 301 is no higher than the top surface of the source electrode 305, so that a step is formed between the source electrode 305 and the semiconductor film layer 306.
  • the semiconductor film layer 306, source The electrode 305 and the word line 302 are covered with a dielectric protective layer 308.
  • the dielectric protective layer 308 is provided with an opening in a region corresponding to the source electrode 305, and the opening exposes the source electrode 305.
  • the source electrode 305 and the drain electrode 304 are made of metal respectively
  • the semiconductor film layer 306 is made of a metal oxide semiconductor
  • the word line 302 is made of metal or polysilicon.
  • the transistor 400 includes a substrate 401, two semiconductor film layers 402, a word line 403, an insulating layer 404, a source electrode 405 and a leakage current. Extreme 406.
  • Substrate 401 has an upper surface.
  • Each semiconductor film layer 402 has two main surfaces perpendicular to the direction of the substrate 401. Two of the main surfaces of the two semiconductor film layers 402 are adjacent and facing each other. Set.
  • the word line 403 is located between the two semiconductor film layers 402 and extends along the column direction.
  • the row direction is perpendicular to the column direction.
  • the word line 403 has an upper surface, a lower surface and two side surfaces.
  • the insulating layer 404 is located on the upper surface, lower surface and two side surfaces of the word line 403.
  • the two adjacent main surfaces of the two semiconductor film layers 402 are in contact with the insulating layer 404 on the side surfaces of the word line 403 respectively.
  • the film layer 402 is distributed on the side surface of the word line 403 and is distributed on the insulating layer 404 of the word line 403 .
  • the source electrode 405 and the drain electrode 406 are respectively located on the upper surface and the lower surface of the word line 403, and are insulated from the word line 403 by the insulating layer 404.
  • the word line 403 is located between the two semiconductor film layers 402, and channels are formed on both sides of the word line 403 to conduct the source electrode 405 and the drain electrode 406, which can increase the sensitivity of the transistor 400.
  • the source electrode 405 and the drain electrode 406 are in a block shape, and the side surfaces of the block source electrode 405 and the drain electrode 406 do not exceed the side surfaces of the word line 403; the two semiconductor film layers 402 are in The side surfaces of the word lines 403 are distributed and extend to the side surfaces of the source electrode 405 and the drain electrode 406 .
  • the drain structure, the gate structure and the source structure are stacked in a direction perpendicular to the substrate to form a stacked structure, and the drain structure and the source structure at least partially overlap in the orthographic projection of the substrate. , thereby simplifying the structure of the field effect transistor, reducing the difficulty of preparing the field effect transistor, and reducing the cost of preparing the field effect transistor.
  • channels are formed on both sides of the gate structure to conduct the drain structure and the source structure, which can increase the sensitivity of the field effect transistor.
  • the channel The direction is perpendicular to the substrate; when no voltage is applied, the semiconductor structure can play an insulating role, so there is no need to set up an additional active structure, which can reduce the size of the field effect transistor and facilitate the application of memories with this field effect transistor. Integration further reduces memory manufacturing costs.
  • a semiconductor structure is provided between the stacked structures of any two adjacent field effect transistors, so that a high-density memory can be prepared, further reducing the size of the memory, and facilitating the integration of the memory.
  • vertical channels can be formed on both sides of the stacked structure of the field effect transistor of the memory, which can enhance the conductive performance of the memory.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can be alternated, changed, combined, or deleted.
  • steps, measures, and solutions in the various operations, methods, and processes that have been discussed in this application can also be alternated, changed, rearranged, decomposed, combined, or deleted.
  • steps, measures, and solutions in the prior art with various operations, methods, and processes disclosed in this application can also be replaced, changed, rearranged, decomposed, combined, or deleted.
  • first and second are used for descriptive purposes only and shall not be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more of these features. In the description of this application, unless otherwise stated, “plurality” means two or more.
  • connection should be understood in a broad sense.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.
  • connection or integral connection; it can be directly connected, or indirectly connected through an intermediary, or it can be internal connection between two components.

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Abstract

本申请实施例提供一种场效应管、存储器及其制备方法、半导体阵列和晶体管。该场效应管包括叠层结构和两个半导体结构；叠层结构包括沿第一方向依次叠层设置在基板上方的漏极结构、栅极结构和源极结构，叠层结构还包括包裹在栅极结构外周的栅极绝缘结构。通过将漏极结构、栅极结构和源极结构沿垂直于基板的方向叠层设置为叠层结构，且漏极结构和源极结构在基板的正投影至少部分重叠，从而能够简化场效应管的结构，能够降低制备场效应管的难度，以及降低制备场效应管的成本。

Description

场效应管、存储器及其制备方法、半导体阵列和晶体管 技术领域
本申请涉及半导体技术领域，具体而言，本申请涉及一种场效应管、存储器及其制备方法、半导体阵列和晶体管。
背景技术
场效应管(场效应晶体管)是一种用电场效应来控制电流的电子器件，场效应管通常产生更少的噪声，可应用于噪声敏感电子器件，例如调谐器和用于甚高频和卫星接收机的低噪声放大器；场效应管对辐射相对免疫，在零漏极电流下不显示失调电压，可作为信号斩波器。
但是，目前应用于存储器的场效应管存在结构复杂、制备难度大的问题，导致存储器的集成度较低。
发明内容
本申请提出一种场效应管、存储器及其制备方法、半导体阵列和晶体管，用以提高存储器的集成度，简化器件结构等。
第一个方面，本申请实施例提供了一种场效应管，包括：
叠层结构，所述叠层结构包括沿第一方向依次叠层设置在基板上方的漏极结构、栅极结构和源极结构，所述第一方向垂直于所述基板；所述叠层结构还包括包裹在所述栅极结构外周的栅极绝缘结构；
两个半导体结构，沿第二方向间隔分布，所述栅极结构位于两个所述半导体结构之间；所述半导体结构与所述栅极结构的侧表面的栅极绝缘结构、所述漏极结构部分的侧表面和所述源极结构部分的侧表面接触，所述第二方向平行于所述基板。
第二个方面，本申请实施例提供了一种存储器，包括：基板和至少两 条字线；所述存储器包括至少两个阵列排布的所述的场效应管，沿第二方向，任意相邻两个所述场效应管的叠层结构之间设置有一个半导体结构，所述第二方向平行于所述基板；
所述字线沿第三方向延伸，包括沿所述第三方向位于同一直线的各所述叠层结构的栅极结构，所述第三方向平行于所述基板，且与所述第二方向之间具有设定夹角。
第三个方面，本申请实施例提供了一种存储器的制备方法，包括：
在基板的一侧制备漏极结构，所述漏极结构阵列排布；
在所述漏极结构远离所述基板的一侧制备字线、源极结构、栅极绝缘结构和半导体结构，所述漏极结构、所述字线和所述源极结构沿第一方向叠层放置，所述栅极绝缘结构包裹在所述字线外周，相邻所述字线之间沿第二方向设置一个半导体结构，所述字线沿第三方向延伸；所述半导体结构沿所述第二方向分别与所述漏极结构部分的侧表面、所述源极结构部分的侧表面和所述栅极绝缘结构接触，所述第一方向垂直于所述基板，所述第二方向平行于所述基板，所述第三方向平行于所述基板且与所述第二方向之间具有设定夹角。
第四个方面，本申请实施例提供了一种半导体阵列，包括：
衬底，具有上表面；
多条字线，具有上表面、下表面、两个相对的侧表面、两个相对的端面；所述多条字线在所述衬底的所述上表面沿列方向延伸且在行方向间隔排列；
多个栅极绝缘层，每个所述栅极绝缘层与一条所述字线对应，所述栅极绝缘层围设于对应的所述字线的所述上表面、下表面和两个相对的侧表面；
多个漏电极，沿着行方向和列方向相互间隔呈阵列分布；每一列所述漏电极位于一条所述字线的下表面通过所述栅极绝缘层与所述字线相绝缘，不同列所述漏电极位于不同的所述字线下方；
多个源电极，沿着行方向和列方向相互间隔呈阵列分布；每一列所述 源电极位于一条所述字线的上表面通过所述栅极绝缘层与所述字线相绝缘，不同列所述源电极位于不同的所述字线上方；
多个相互间隔设置的半导体膜层，其中，每一所述字线的两个侧表面分别设置有两列所述半导体膜层，每一列中的各所述半导体膜层分别与对应的一列中的各所述源电极一一对应，对应于一个所述源电极的所述两个半导体膜层与所述源电极在行方向间隔排列。
第五个方面，本申请实施例提供了一种晶体管，包括：
衬底，具有上表面；
两个半导体膜层，沿着行方向间隔分布，每个所述半导体膜层具有两个垂直于衬底的方向的主表面，所述两个半导体膜层的其中两个主表面相邻且相向而置；
字线，位于所述两个半导体膜层之间，沿着列方向延伸，所述行方向与所述列方向垂直；所述字线具有上表面、下表面和两个侧表面；
绝缘层，位于所述字线的上表面、下表面和两个侧表面，所述两个半导体膜层的相邻的两个主表面分别与所述字线的侧表面的所述绝缘层接触，所述两个半导体膜层在所述字线的侧表面分布且与所述字线的所述绝缘层上分布；
源电极和漏电极，分别位于所述字线的所述上表面和下表面，通过所述绝缘层与所述字线绝缘。
本申请实施例提供的技术方案带来的有益技术效果包括：
本申请实施例的场效应管中，通过将漏极结构、栅极结构和源极结构沿垂直于基板的方向叠层设置为叠层结构，从而能够简化场效应管的结构，能够降低制备场效应管的难度，以及降低制备场效应管的成本。而且，在对栅极结构施加电压时，在栅极结构的两侧均形成沟道以导通漏极结构和源极结构，能够增加场效应管的灵敏度，此沟道的方向为垂直于基板的方向；在不施加电压时，半导体结构能够起到绝缘相邻两个场效应管的叠层结构的作用，则不需在相邻两个场效应管的叠层结构之间额外设置绝缘结构，能够减小场效应管所占用的面积，便于提升存储器的集成度，有利于 降低存储器的制造成本。
本申请附加的方面和优点将在下面的描述中部分给出，这些将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为本申请实施例提供的一种场效应管的膜层结构剖面示意图；
图2为本申请实施例提供的一种存储器的膜层结构剖面示意图；
图3为图2中H-H处的剖视示意图；
图4为本申请实施例提供的一种存储器的制备方法的流程示意图；
图5为本申请实施例提供的在漏极结构远离基板的一侧制备字线、源极结构、栅极绝缘结构和半导体结构步骤的一种制备方法的流程示意图；
图6为本申请实施例提供的在基板的一侧制备漏极结构，漏极结构阵列排布制备得到的膜层结构剖面示意图；
图7为本申请实施例提供的在露出于漏极结构的基板的一侧覆盖第一介质层，得到第一中间基板的膜层结构剖面示意图；
图8为本申请实施例提供的图案化第一中间基板得到的俯视结构示意图；
图9为图8中A-A处的剖视图；
图10为本申请实施例提供的制备与第一沟槽内表面随形的第一初始栅极绝缘结构后得到的俯视示意图；
图11为图10中B-B处的剖视图；
图12为本申请实施例提供的制备字线后得到的俯视示意图；
图13为图12中C-C处的剖视图；
图14为本申请实施例提供的形成第一栅极绝缘结构和第三栅极绝缘结构后得到的俯视示意图；
图15为图14中D-D处的剖视图；
图16为本申请实施例提供的图案化覆盖第二介质层的第二中间基板后得到的俯视示意图；
图17为图16中E-E处的剖视图；
图18为本申请实施例提供的制备半导体结构后得到的俯视示意图；
图19为图18中F-F处的剖视图；
图20为本申请实施例提供的在露出于半导体结构的一侧覆盖第三介质层后得到的膜层结构剖面示意图；
图21为本申请实施例提供的刻蚀第三介质层得到的膜层结构剖面示意图；
图22为本申请实施例提供的制备源极结构后得到的俯视示意图；
图23为图22中G-G处的剖视图；
图24为本申请实施例提供的在漏极结构远离基板的一侧制备字线、源极结构、栅极绝缘结构和半导体结构步骤的另一种制备方法的流程示意图；
图25为本申请实施例提供的在基板的一侧设置阵列排布的漏极结构后的立体示意图；
图26为本申请实施例提供的制备第三中间基板后得到的立体示意图；
图27为本申请实施例提供的制备第四中间基板后得到的立体示意图；
图28为本申请实施例提供的图案化第四中间基板后得到的立体示意图；
图29为本申请实施例提供的制备源极结构后得到的立体示意图；
图30为本申请实施例提供的制备第五中间基板后得到的立体示意图；
图31为本申请实施例提供的图案化第五中间基板后得到的俯视示意图；
图32为图31中J-J处的剖视图；
图33为本申请实施例提供的制备第一栅极绝缘结构后得到的膜层结构剖面示意图；
图34为本申请实施例提供的制备半导体结构中在第三凹槽中填充半 导体材料形成初始半导体结构后得到的膜层结构剖面示意图；
图35为本申请实施例提供的制备半导体结构中通过CMP工艺去除多余的半导体材料，使得剩余的初始半导体结构的表面与五介质结构的表面平齐后得到的膜层结构剖面示意图；
图36为本申请实施例提供的通过回刻初始半导体结构，得到半导体结构后的膜层结构剖面示意图；
图37为本申请实施例提供的在半导体结构和五介质结构远离基板的一侧填充介质材料，形成第六介质层后得到的膜层结构剖面示意图；
图38为本申请实施例提供的通过CMP工艺磨平第六介质层，直至露出源极结构的表面，第六介质层形成为第六介质结构后的膜层结构剖面示意图；
图39为本申请实施例提供的一种半导体阵列的膜层结构剖面示意图；
图40为图39中KK处的剖视图；
图41为本申请实施例提供的一种半导体阵列中去除半导体膜层后的膜层结构剖面示意图；
图42为本申请实施例提供的一种晶体管的膜层结构剖面示意图；
图43为为图42中LL处的剖视图。
附图标记：
1-叠层结构；11-漏极结构；121-栅极结构；122-栅极绝缘结构；1221-第一栅极绝缘结构；1222-第二栅极绝缘结构；1223-第三栅极绝缘结构；13-源极结构；
2-半导体结构；
3-第一中间基板；
4-第一介质层；41-第一初始介质结构；42-第一介质结构；
5-第二中间基板；51-第一沟槽；52-第一初始栅极绝缘结构；53-第二沟槽；55-第二介质结构；56-第三介质层；57-第三介质结构；
61-第一凹槽；62-第二凹槽；
7-第三中间基板；71-第四初始介质结构；72-第四介质结构；
8-第四中间基板；81-第二栅极绝缘层；82-多晶硅层；83-第三栅极绝缘层；84-源极层；
91-第一中间结构列；911-初始源极结构；92-第二沟槽；
93-第五中间基板；931-第五介质层；932-第五介质结构；94-第三凹槽；95-初始半导体结构；96-第六介质层；97-第六介质结构；
100-场效应管；
200-存储器；201-基板；202-字线；
300-半导体阵列；301-衬底；302-字线；303-栅极绝缘层；304-漏电极；305-源电极；306-半导体膜层；307-沟槽；308-介质保护层；
400-晶体管；401-衬底；402-半导体膜层；403-字线；404-绝缘层；405-源电极；406-漏电极。
具体实施方式
下面结合本申请中的附图描述本申请的实施例。应理解，下面结合附图所阐述的实施方式，是用于解释本申请实施例的技术方案的示例性描述，对本申请实施例的技术方案不构成限制。
本技术领域技术人员可以理解，除非特意声明，这里使用的单数形式“一”、“一个”、“所述”和“该”也可包括复数形式。应该进一步理解的是，本申请的说明书中使用的措辞“包括”是指存在所述特征、整数、步骤、操作、元件和/或组件，但不排除实现为本技术领域所支持其他特征、信息、数据、步骤、操作、元件、组件和/或它们的组合等。这里使用的术语“和/或”指该术语所限定的项目中的至少一个，例如“A和/或B”可以实现为“A”，或者实现为“B”，或者实现为“A和B”。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请的研发思路包括：目前应用于存储器的场效应管存在结构复杂、制备难度大的问题，导致存储器的集成化低的问题。
本申请提供的一种场效应管、存储器及其制备方法、半导体阵列和晶 体管，旨在解决现有技术的如上技术问题。
下面以具体地实施例对本申请的技术方案以及本申请的技术方案如何解决上述技术问题进行详细说明。需要指出的是，下述实施方式之间可以相互参考、借鉴或结合，对于不同实施方式中相同的术语、相似的特征以及相似的实施步骤等，不再重复描述。
如图1所示，本申请实施例提供了一种场效应管100，该场效应管100的结构示意图，包括：叠层结构1和两个半导体结构2。
如图2所示，叠层结构1被构造为设置在基板201的一侧(即基板201的上表面)，如图1所示，叠层结构1包括沿第一方向(垂直基板201的上表面)依次叠层设置的漏极结构11、栅极结构121和源极结构13，层叠结构1还包括包裹在栅极结构121外周(即栅极结构121的上表面、下表面和两个相对的侧表面)的栅极绝缘结构122。
沿第二方向(平行于基板201的上表面)，两个半导体结构2间隔分布，栅极结构121位于两个半导体结构2之间。半导体结构2与栅极121的侧表面的栅极绝缘结构122、漏极结构11部分的侧表面和源极结构13部分的侧表面接触。
本实施例中，通过将漏极结构11、栅极结构121和源极结构13沿垂直于基板201的方向叠层设置为叠层结构1，且漏极结构11和源极结构13在基板201的正投影至少部分重叠，从而能够简化场效应管100的结构，能够降低制备场效应管100的难度，以及降低制备场效应管100的成本。
以及，沿平行于基板201的方向，两个半导体结构2分别设置于叠层结构1沿第二方向的两侧，即在叠层结构1的两侧分别设置一个半导体结构2，在对栅极结构121施加电压时，在栅极结构121的两侧均形成沟道以导通漏极结构11和源极结构12，能够增加场效应管100的灵敏度，此沟道的方向为垂直于基板201的方向；在不施加电压时，半导体结构2能够起到绝缘相邻两个场效应管100的叠层结构1的作用，则不需在相邻两个场效应管100的叠层结构1之间额外设置绝缘结构，能够减小场效应管 100所占用的面积，便于提升存储器的集成度，有利于降低存储器的制造成本。
需要说明的是，为了便于描述场效应管100的结构，引入了基板201作为参照，基板201可以包括基底、源极结构、漏极结构、栅极结构和半导体结构中至少一个，根据实际情况，具体设定，在此不作任何限定。
可选地，漏极结构11和源极结构13在第一方向上至少部分地交叠。
本实施例中，漏极结构11和源极结构13在基板201的正投影至少部分重叠，可以大大节省本申请实施例的场效应管100的占用面积，有利于提升单位面积的场效应管100数量，从而有利于提升场效应管100的集成密度。
可选地，沿第一方向，漏极结构11和源极结构13重叠。
本实施例中，漏极结构11与源极结构13为上下正对设置，进一步减小场效应管100的占用面积，有利于提升单位面积的场效应管100数量，从而有利于提升场效应管100的集成密度，利于降低场效应管100的制造难度和成本。
可选地，栅极绝缘结构122包括第一栅极绝缘结构1221、第二栅极绝缘结构1222和第三栅极绝缘结构1223，第一栅极绝缘结构1221设置在栅极结构121与半导体结构2之间；第二栅极绝缘结构1222设置在栅极结构121与漏极结构11之间；第三栅极绝缘结构1223设置栅极结构121与源极结构13之间。
可选地，半导体结构2的材料为非晶半导体材料，在栅极结构121的控制下能够起到导通漏极结构11和源极结构13的作用，进一步减小场效应管100的体积。
可选地，半导体结构2的材料为金属氧化物半导体，示例性的，金属氧化物半导体中的金属可以包括铟、镓、锌、钨、锡、稀土金属等中的至少一种或多种。比如IGZO、ITO、IWO等。本申请的金属氧化物半导体材料是用于区别于单晶、多晶、非晶等半导体材料，但是不限制金属氧化物半导体材料的具体成分组成。
基于同一发明构思，本申请实施例提供了一种存储器200，参考图2和图3所示，包括：基板201和至少两条字线202。
存储器200包括至少两个阵列排布的前述实施例中的场效应管100，沿第二方向，任意相邻两个场效应管100的叠层结构1之间设置有一个半导体结构2，第二方向平行于所述基板。
字线202沿第三方向延伸，包括沿第三方向位于同一直线的各叠层结构1的栅极结构121，第三方向平行于基板201，且与第二方向之间具有设定夹角。
本实施例中，通过在任意相邻两个场效应管100的叠层结构1之间设置有一个半导体结构2，能够制备得到高密度的存储器200，进一步减小存储器200的体积，利于实现存储器200的集成化。以及，在存储器200的场效应管100的叠层结构1的两侧均可以形成垂直沟道，能够增强存储器200的导电性能。
基于同一发明构思，本申请实施例提供了一种存储器的制备方法，该制备方法的流程示意图如图4所示，包括步骤S1和步骤S2，具体如下：
S1：在基板201的一侧制备漏极结构11，漏极结构11阵列排布。
本实施例中，在基板201的一侧沉积金属，形成金属层，通过光刻和刻蚀工艺得到阵列排布的漏极结构11。
S2：在漏极结构11远离基板201的一侧制备字线202、源极结构13、栅极绝缘结构122和半导体结构2。
其中，漏极结构11、字线202和源极结构13沿第一方向叠层放置，栅极绝缘结构122包裹在字线202外周，相邻字线202之间沿第二方向设置一个半导体结构2，字线202沿第三方向延伸；半导体结构2沿第二方向分别与漏极结构11部分的侧表面、源极结构13部分的侧表面和栅极绝缘结构122部分结构接触，第一方向垂直于基板201，第二方向平行于基板201，第三方向平行于基板201且与第二方向之间具有设定夹角。
在其中一种可行的实施方式中，上述步骤S2中，在漏极结构11远离基板201的一侧制备字线202、源极结构13、栅极绝缘结构122和半导体结构2的一种制备方法的流程示意图如图5所示，包括如下步骤S201至 S206：
S201：在露出于漏极结构11的基板201的一侧覆盖第一介质层4，得到第一中间基板3，图案化第一中间基板3，形成至少两个延伸方向为第三方向的第一沟槽51，第一沟槽51中露出多个漏极结构11。
本实施例中，图6为漏极结构11阵列排布在基板201的一侧的结构示意图，漏极结构11沿第一方向垂直于基板201设置；图7为在露出于漏极结构11的基板201的一侧覆盖第一介质层4，得到第一中间基板3后的结构示意图，第一介质层4的材料可以为氧化硅、氮化硅等，只要能够起到绝缘作用的材料均可。
如图8所示为在第一中间基板3的一侧进行光刻和刻蚀工艺形成第一沟槽51后的俯视示意图，图9为图8中A-A处的剖视图，其中光刻工艺可包括在第一中间基板3的一侧涂覆光刻胶、在第一中间基板3的上方设置掩膜版进行曝光和显影，掩膜版包括透光区和非透光区，与位于第三方向的同一直线的漏极结构11在基板201的正投影落入在透光区在基板201的正投影，利用紫外线在掩膜版远离第一中间基板3的一侧进行光照，再将非透光区的光刻胶显影掉，随后在显影掉的光刻胶区域进行刻蚀，直至露出漏极结构11的表面，图案化的工艺还可以包括对准、烘干等工艺，具体工艺可根据实际情况进行选择。
S202：制备与第一沟槽51内表面随形的第一初始栅极绝缘结构52，在第一初始栅极绝缘结构52随形的第二沟槽53内制备字线202，第一初始栅极绝缘结构52包括字线202与漏极结构11之间的第二栅极绝缘结构1222。
本实施例中，可利用原子层沉积技术(ALD)在第一沟槽51内表面随形制备第一初始栅极绝缘结构52，可选地，第一初始栅极绝缘结构52的材料可以为氧化硅或者氮化硅等。在第一沟槽51内表面随形制备第一初始栅极绝缘结构52后得到的俯视示意图如图10所示，图11为图10中B-B处的剖视图。
可选地，在步骤S202中在第一初始栅极绝缘结构52随形的第二沟槽53内制备字线202，如图12所示为制备字线202后得到的俯视示意图， 图13为图12中C-C处剖视图，包括：
在具有第二沟槽53的第一初始绝缘结构52的一侧沉积金属层。可选地，金属材料可以为钨。
通过CMP(Chemical Mechanical Polishing，化学机械抛光)工艺将金属层研磨至露出第一初始绝缘结构52，即金属层与第一初始介质结构41的表面平齐。
对第二沟槽53中残留的金属层进行刻蚀，得到字线202，字线202包括栅极结构121；字线202沿第三方向延伸，包括沿第三方向位于同一直线的各栅极结构121，字线202与漏极结构11之间通过第二栅极绝缘结构1222接触。
S203：在具有字线202的第二沟槽53内填充绝缘材料并磨平，形成第一栅极绝缘结构1221和第三栅极绝缘结构1223，得到第二中间基板5，如图14所示为第二中间基板5的俯视示意图，图15为图14中E-E处的剖视图。
本实施例中，在第二沟槽53内填充绝缘材料，通过CMP工艺将多余的绝缘材料去掉，形成第一栅极绝缘结构1221和第三栅极绝缘结构1223。
S204：图案化覆盖第二介质层的第二中间基板5，形成阵列排布的第一凹槽61，沿第二方向，第一凹槽61位于任意相邻两个漏极结构11之间，第一凹槽61中露出第一栅极绝缘结构1221和漏极结构11部分的侧表面；在各第一凹槽61中制备半导体结构2。
本实施例中，在第二中间基板5的一侧覆盖第二介质层，在第二介质层的一侧进行光刻和刻蚀等工艺，形成阵列排布的第一凹槽61和第二介质结构55，光刻和刻蚀等工艺为现有的工艺，在此不再赘述，如图16所示为在第二中间基板5的一侧覆盖第二介质层后得到的俯视示意图，图17为图16中E-E处的剖视图。
可选地，步骤S204中在各第一凹槽61中制备半导体结构2，如图18为制备半导体结构2后得到的俯视示意图，图19为图18中F-F处的剖视图，包括：
在第一凹槽61内沉积半导体材料，形成半导体层，半导体材料可以 包括铟镓锌氧化物和掺钨氧化铟中的至少一种，或者半导体材料为其它非晶半导体材料。
通过CMP工艺将多余的半导体材料去除，剩余的半导体层与第二介质结构55的表面平齐。
对第一凹槽61内的剩余的半导体层进行刻蚀，得到半导体结构2，半导体结构2沿第二方向分别与漏极结构11部分的侧表面、源极结构13部分的侧表面和第二初始栅极绝缘结构54的部分侧表面接触。
S205：在露出于半导体结构2的一侧覆盖第三介质层56，刻蚀第三介质层56,，形成第二凹槽62，第二凹槽62中露出部分第三栅极绝缘结构1223和半导体结构2部分的侧表面。
可选地，在半导体结构2和第二介质结构55远离基板201的一侧填充第三介质层56；刻蚀第三介质层56，形成第三介质结构57，如图20和图21所示。
S206：在第二凹槽62中制备源极结构13，如图22为制备源极结构13后得到的俯视示意图，图23为图22中G-G处的剖视图。
本实施例中，在第二凹槽62中填充金属，形成金属层，通过CMP工艺将金属层研磨至与第三介质结构57的表面平齐，得到源极结构13。
在其中另一种可行的实施方式中，上述步骤S2中，在漏极结构11远离基板201的一侧制备字线202、源极结构13、栅极绝缘结构122和半导体结构2的另一种制备方法的流程示意图如图24所示，包括步骤S211至S216，具体如下：
S211：在露出于漏极结构11的基板201的一侧覆盖第四介质层，得到第三中间基板7。
本实施例中，图25为在基板201的一侧设置阵列排布的漏极结构11的立体示意图，图26为在漏极结构11的一侧形成与漏极结构11的表面平齐的第四初始介质结构71后得到的立体示意图。
其中一种制备第三中间基板7的方法为：在基板201的一侧沉积金属，通过光刻和刻蚀工艺，得到阵列排布的漏极结构11；在被刻蚀掉金属的区域沉积介质材料形成介质层，可以为氧化硅或者氮化硅，再通过CMP 工艺使得介质层的表面与漏极结构11的表面平齐，得到第三中间基板7。
其中另一种制备第三中间基板7的方法为：在基板201的一侧沉积介质材料形成介质层，通过光刻和刻蚀工艺，得到阵列排布的凹槽和介质结构；在凹槽内填充金属形成金属层，再通过CMP工艺使得金属层的表面与介质结构的表面平齐，形成漏极结构11，得到第三中间基板7。
S212：在具有漏极结构11的第三中间基板7一侧依次制备第二栅极绝缘层81、多晶硅层82、第三栅极绝缘层83和源极层84，得到第四中间基板8，如图27所示为制备第四中间基板8后得到的立体示意图。
本实施例中，沿第一方向，依次为基板201、第四初始介质结构71、第二栅极绝缘层81、多晶硅层82、第三栅极绝缘层83和源极层84。
S213：图案化第四中间基板8，形成至少两个延伸方向为第三方向的第二沟槽92和对应的第一中间结构列91，第一中间结构列91包括层叠的第二栅极绝缘结构1222、字线202、第三栅极绝缘结构1223和初始源极结构911，第二沟槽92中露出漏极结构11部分的侧表面，如图28所示为图案化第四中间基板8后得到的立体示意图。
本实施例中，在第四中间基板8的一侧进行光刻和刻蚀工艺，刻蚀第四中间基板8直至露出漏极结构11部分的侧表面，第四初始介质结构71形成第四介质结构72。
相邻两个第二沟槽92之间设置一个第一中间结构列91，第一中间结构列91还包括第四介质结构72和部分的漏极结构11。
S214：图案化初始源极结构911，形成阵列排布的源极结构13，源极结构13与漏极结构11正对设置，在露出于源极结构13的第三栅极绝缘结构1223和第四介质结构72的一侧覆盖第五介质层931，形成第五中间基板93；图案化第五中间基板93，形成阵列排布的第三凹槽94，沿第二方向，第三凹槽94位于任意相邻两个源极结构13之间，第三凹槽94中露出漏极结构11部分的侧表面、字线202的部分侧表面、和源极结构13侧表面，如图29所示为形成阵列排布的源极结构13后得到的立体示意图。
本实施例中，在初始源极结构911远离基板201的一侧进行光刻和刻蚀，得到源极结构13。
在第三栅极绝缘结构1223和第四介质结构72的一侧覆盖第五介质层931，形成第五中间基板93，其中第四介质结构72、第二栅极绝缘结构1222、字线202和第三栅极绝缘结构1223的两端露在外面，如图30所示为形成第五中间基板93后得到的立体示意图。
在第五中间基板93的一侧进行光刻和刻蚀，第五介质层931形成第五介质结构932，形成阵列排布的第三凹槽94，如图31为图案化第五中间基板93后得到的俯视示意图，图32为图31中J-J处的剖视图。
S215：基于字线202的部分侧表面，制备第一栅极绝缘结构1221。
可选地，在步骤S215中基于字线202的部分侧表面，制备第一栅极绝缘结构1221，包括：对露出字线202的侧表面进行氧化，比如热氧化，在字线202的侧表面形成第一栅极绝缘结构1221，如图33所示为形成第一栅极绝缘结构1221后得到的膜层结构剖面示意图。
S216：在露出第一栅极绝缘结构1221的第三凹槽94中制备半导体结构2。
本实施例中，在露出第一栅极绝缘结构1221的第三凹槽94中制备半导体结构2包括如下过程：
在第三凹槽94中填充半导体材料形成初始半导体结构95。可选地，半导体材料可以为铟镓锌氧化物和掺钨氧化铟中的至少一种，或者其他非晶半导体材料。在第三凹槽94中填充半导体材料形成初始半导体结构95后得到的膜层结构剖面示意图如图34所示。
通过CMP工艺去除多余的半导体材料，使得剩余的初始半导体结构95的表面与五介质结构932的表面平齐，如图35所示为通过CMP工艺去除多余的半导体材料后得到的膜层结构剖面示意图。
通过回刻初始半导体结构95，得到半导体结构2，半导体结构2沿第二方向分别与漏极结构11部分的侧表面、源极结构13部分的侧表面和第一栅极绝缘结构1221接触，如图36所示为得到半导体结构2后得到的膜层结构剖面示意图。
可选地，在上述步骤S216在露出第一栅极绝缘结构1221的第三凹槽94中制备半导体结构2之后，还包括：
在半导体结构2和五介质结构932远离基板201的一侧填充介质材料，形成第六介质层96，如图37所示为形成第六介质层96后得到的膜层结构剖面示意图。
通过CMP工艺磨平第六介质层96，直至露出源极结构13的表面，第六介质层96形成为第六介质结构97，如图38所示为通过CMP工艺磨平第六介质层96后得到的膜层结构剖面示意图。
基于同一发明构思，本申请实施例提供了一种半导体阵列300，如图39至图40所示，半导体阵列300包括：衬底301、多条字线302、多个栅极绝缘层303、多个漏电极304、多个源电极305和多个相互间隔设置的半导体膜层306。
衬底301具有上表面。
多条字线302具有上表面、下表面、两个相对的侧表面、两个相对的端面；多条字线302在衬底301的上表面沿列方向延伸且在行方向间隔排列。
每个栅极绝缘层303与一条字线302对应，栅极绝缘层303围设于对应的字线302的上表面、下表面和两个相对的侧表面。
多个漏电极304沿着行方向和列方向相互间隔呈阵列分布；每一列漏电极304位于一条字线302的下表面通过栅极绝缘层303与字线302相绝缘，不同列漏电极304位于不同的字线302下方。
多个源电极305沿着行方向和列方向相互间隔呈阵列分布；每一列源电极305位于一条字线302的上表面通过栅极绝缘层303与字线302相绝缘，不同列源电极305位于不同的字线302上方。
每一字线302的两个侧表面分别设置有两列半导体膜层306，每一列中的各半导体膜层306分别与对应的一列中的各源电极305一一对应，对应于一个源电极305的两个半导体膜层306与源电极305在行方向间隔排列。
本实施例中，每一字线302的两个侧表面分别设置有两列半导体膜层306，在字线302的两侧均形成沟道以导通漏电极304和源电极305，能够增加半导体阵列300的灵敏度。在不施加电压时，半导体膜层306能够 起到绝缘相邻两个半导体的作用，则不需要在相邻两个半导体之间额外设置绝缘结构，能够减小半导体所占用的面积，便于提升存储器的集成度，有利于降低存储器的制造成本。
可选地，参考图41，相邻的两条字线302之间具有沿着字线302的延伸方向延伸的沟槽307，沟槽307露出相邻的两条字线302的侧表面上的栅极绝缘层303，以及源电极305的侧表面，半导体膜层306的主表面至少位于栅极绝缘层303沿垂直衬底301的方向延伸。
可选地，参考图39和图41，沟槽307延伸到字线302下方的漏电极304的侧表面，半导体膜层306的主表面同时延伸到字线302上方的漏电极304的侧表面，以及延伸到源电极305的侧表面。
可选地，参考图39和图41，相邻两条字线302之间的沟槽307设置有一列在列方向间隔设置的半导体膜层306，每个半导体膜层306具有两个相对设置的侧表面，半导体膜层306的两个侧表面分别朝向两条相邻的字线302，且分别与相邻的两条字线302的两个侧表面上的栅极绝缘层303连接。
可选地，参考图39，半导体膜层306远离衬底301的一个顶面不高于源电极305的顶面，使得源电极305与半导体膜层306之间形成台阶，半导体膜层306、源电极305和字线302上覆盖有介质保护层308，介质保护层308对应源电极305的区域设置有开口，开口露出源电极305。
可选地，源电极305和漏电极304分别为金属，半导体膜层306为金属氧化物半导体，字线302为金属或多晶硅。
基于同一发明构思，本申请实施例提供了一种晶体管400，参考图42和图43，晶体管400包括衬底401、两个半导体膜层402、字线403、绝缘层404、源电极405和漏电极406。
衬底401具有上表面。
两个半导体膜层402沿着行方向间隔分布，每个半导体膜层402具有两个垂直于衬底401的方向的主表面，两个半导体膜层402的其中两个主表面相邻且相向而置。
字线403位于两个半导体膜层402之间，沿着列方向延伸，行方向与 列方向垂直；字线403具有上表面、下表面和两个侧表面。
绝缘层404位于字线403的上表面、下表面和两个侧表面，两个半导体膜层402的相邻的两个主表面分别与字线403的侧表面的绝缘层404接触，两个半导体膜层402在字线403的侧表面分布且与字线403的绝缘层404上分布。
源电极405和漏电极406分别位于字线403的上表面和下表面，通过绝缘层404与字线403绝缘。
本实施例中，字线403位于两个半导体膜层402之间，在字线403的两侧均形成沟道以导通源电极405和漏电极406，能够增加晶体管400的灵敏度。
可选地，参考图42和图43，源电极405和漏电极406呈块状，块状源电极405和漏电极406的侧表面不超过字线403的侧表面；两个半导体膜层402在字线403的侧表面分布且延伸到源电极405和漏电极406的侧表面。
应用本申请实施例，至少能够实现如下有益效果：
1.本申请实施例中通过将漏极结构、栅极结构和源极结构沿垂直于基板的方向叠层设置为叠层结构，且漏极结构和源极结构在基板的正投影至少部分重叠，从而能够简化场效应管的结构，能够降低制备场效应管的难度，以及降低制备场效应管的成本。
2.本申请实施例中在对栅极结构施加电压时，在栅极结构的两侧均形成沟道以导通漏极结构和源极结构，能够增加场效应管的灵敏度，此沟道的方向为垂直于基板的方向；在不施加电压时，半导体结构能够起到绝缘作用，则不需额外设置有源结构，能够减小场效应管的体积，便于使得应用有此场效应管的存储器的集成化，进一步降低存储器的制造成本。
3.本申请实施例中通过在任意相邻两个场效应管的叠层结构之间设置有一个半导体结构，能够制备得到高密度的存储器，进一步减小存储器的体积，利于实现存储器的集成化。以及，在存储器的场效应管的叠层结构的两侧均可以形成垂直沟道，能够增强存储器的导电性能。
本技术领域技术人员可以理解，本申请中已经讨论过的各种操作、方 法、流程中的步骤、措施、方案可以被交替、更改、组合或删除。进一步地，具有本申请中已经讨论过的各种操作、方法、流程中的其他步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。进一步地，现有技术中的具有与本申请中公开的各种操作、方法、流程中的步骤、措施、方案也可以被交替、更改、重排、分解、组合或删除。
在本申请的描述中，词语“中心”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方向或位置关系，为基于附图所示的示例性的方向或位置关系，是为了便于描述或简化描述本申请的实施例，而不是指示或暗示所指的装置或部件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
应该理解的是，虽然附图的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤的实施顺序并不受限于箭头所指示的顺序。除非本文中有明确的说明，否则在本申请实施例的一些实施场景中，各流程中的步骤可以按照需求以其他的顺序执行。而且，各流程图中的部分或全部步骤基于实际的实施场景，可以包括多个子步骤或者多个阶段。这些子步骤或者阶段中的部分或全部可以在同一时刻被执行，也可以在不同的时刻被执 行在执行时刻不同的场景下，这些子步骤或者阶段的执行顺序可以根据需求灵活配置，本申请实施例对此不限制。
以上所述仅是本申请的部分实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请的方案技术构思的前提下，采用基于本申请技术思想的其他类似实施手段，同样属于本申请实施例的保护范畴。

Claims (19)

  1. 一种场效应管，其特征在于，包括：
    叠层结构，所述叠层结构包括沿第一方向依次叠层设置在基板上方的漏极结构、栅极结构和源极结构，所述第一方向垂直于所述基板；所述叠层结构还包括包裹在所述栅极结构外周的栅极绝缘结构；
    两个半导体结构，沿第二方向间隔分布，所述栅极结构位于两个所述半导体结构之间；所述半导体结构与所述栅极结构的侧表面的栅极绝缘结构、所述漏极结构部分的侧表面和所述源极结构部分的侧表面接触，所述第二方向平行于所述基板。
  2. 根据权利要求1所述的场效应管，其特征在于，所述漏极结构和所述源极结构在所述第一方向上至少部分地交叠。
  3. 根据权利要求2所述的场效应管，其特征在于，沿所述第一方向，所述漏极结构和所述源极结构重叠。
  4. 根据权利要求1所述的场效应管，其特征在于，所述栅极绝缘结构包括第一栅极绝缘结构、第二栅极绝缘结构和第三栅极绝缘结构，所述第一栅极绝缘结构设置在所述栅极结构与所述半导体结构之间；所述第二栅极绝缘结构设置在所述栅极结构与所述漏极结构之间；所述第三栅极绝缘结构设置在所述栅极结构与所述源极结构之间。
  5. 根据权利要求1所述的场效应管，其特征在于，所述半导体结构的材料包括铟镓锌氧化物和掺钨氧化铟中的至少一种。
  6. 一种存储器，其特征在于，包括：基板和至少两条字线；
    所述存储器包括至少两个阵列排布的如权利要求1-5任一项所述的场效应管，沿第二方向，任意相邻两个所述场效应管的叠层结构之间设置有一个半导体结构，所述第二方向平行于所述基板；
    所述字线沿第三方向延伸，包括沿第三方向位于同一直线的各所述叠层结构的栅极结构，所述第三方向平行于所述基板，且与所述第二方向之间具有设定夹角。
  7. 一种存储器的制备方法，其特征在于，包括：
    在基板的上方制备漏极结构，所述漏极结构阵列排布；
    在所述漏极结构的上方制备字线、源极结构、栅极绝缘结构和半导体结构，所述漏极结构、所述字线和所述源极结构沿第一方向叠层放置，所述栅极绝缘结构包裹在所述字线外周，相邻所述字线之间沿第二方向设置一个半导体结构，所述字线沿第三方向延伸；所述半导体结构沿所述第二方向分别与所述漏极结构部分的侧表面、所述源极结构部分的侧表面和所述栅极绝缘结构接触，所述第一方向垂直于所述基板，所述第二方向平行于所述基板，所述第三方向平行于所述基板且与所述第二方向之间具有设定夹角。
  8. 根据权利要求7所述的制备方法，其特征在于，所述在漏极结构远离所述基板的一侧制备字线、源极结构、栅极绝缘结构和半导体结构，包括：
    在露出于所述漏极结构的所述基板上方覆盖第一介质层，得到第一中间基板，图案化所述第一中间基板，形成至少两个延伸方向为第三方向的第一沟槽，所述第一沟槽中露出多个所述漏极结构；
    制备与所述第一沟槽内表面随形的第一初始栅极绝缘结构，在所述第一初始栅极绝缘结构随形的第二沟槽内制备字线，第一初始栅极绝缘结构包括所述字线与所述漏极结构之间的第二栅极绝缘结构；
    在具有所述字线的第二沟槽内填充绝缘材料并磨平，形成第一栅极绝缘结构和第三栅极绝缘结构，得到第二中间基板；
    图案化覆盖第二介质层的所述第二中间基板，形成阵列排布的第一凹槽，沿所述第二方向，所述第一凹槽位于任意相邻两个所述漏极结构之间，所述第一凹槽中露出第一栅极绝缘结构和所述漏极结构部分的侧表面；在各所述第一凹槽中制备半导体结构；
    在露出于所述半导体结构的上方覆盖第三介质层，刻蚀所述第三介质层，形成第二凹槽，所述第二凹槽中露出部分第三栅极绝缘结构和半导体结构部分的侧表面；
    在所述第二凹槽中制备源极结构。
  9. 根据权利要求8所述的制备方法，其特征在于，在所述第一初始绝缘结构随形的第二沟槽内制备字线，包括：
    在具有所述第二沟槽的第一初始绝缘结构的上方沉积金属层；
    通过CMP工艺将所述金属层研磨至露出所述第一初始绝缘结构；
    对所述第二沟槽中残留的金属层进行刻蚀，得到所述字线，所述字线包括栅极结构。
  10. 根据权利要求7所述的制备方法，其特征在于，所述在漏极结构的上方制备字线、源极结构、栅极绝缘结构和半导体结构，包括：
    在露出于所述漏极结构的所述基板的上方覆盖第四介质层，得到第三中间基板；
    在具有所述漏极结构的第三中间基板上方依次制备第二栅极绝缘层、多晶硅层、第三栅极绝缘层和源极层，得到第四中间基板；
    图案化第四中间基板，形成至少两个延伸方向为第三方向的第二沟槽和对应的第一中间结构列，第一中间结构列包括层叠的第二栅极绝缘结构、字线、第三栅极绝缘结构和初始源极结构，所述第二沟槽中露出所述漏极结构部分的侧表面；
    图案化初始源极结构，形成阵列排布的源极结构，所述源极结构与所述漏极结构正对设置，在露出于所述源极结构的所述第三栅极绝缘结构和第四介质结构的一侧覆盖第五介质层，形成第五中间基板；图案化所述第五中间基板，形成阵列排布的第三凹槽，沿所述第二方向，所述第三凹槽位于任意相邻两个所述源极结构之间，所述第三凹槽中露出所述漏极结构部分的侧表面、所述字线部分的侧表面、和所述源电极的侧表面；
    基于所述字线部分的侧表面，制备第一栅极绝缘结构；
    在露出所述第一栅极绝缘结构的第三凹槽中制备半导体结构。
  11. 根据权利要求10所述的制备方法，其特征在于，所述基于所述字线部分的侧表面，制备第一栅极绝缘结构，包括：对露出所述字线的侧表面进行氧化，在所述字线的侧表面形成第一栅极绝缘结构。
  12. 一种半导体阵列，其特征在于，包括：
    衬底，具有上表面；
    多条字线，具有上表面、下表面、两个相对的侧表面、两个相对的端面；所述多条字线在所述衬底的所述上表面沿列方向延伸且在行方向间隔排列；
    多个栅极绝缘层，每个所述栅极绝缘层与一条所述字线对应，所述栅极绝缘层围设于对应的所述字线的所述上表面、下表面和两个相对的侧表面；
    多个漏电极，沿着行方向和列方向相互间隔呈阵列分布；每一列所述漏电极位于一条所述字线的下表面通过所述栅极绝缘层与所述字线相绝缘，不同列所述漏电极位于不同的所述字线下方；
    多个源电极，沿着行方向和列方向相互间隔呈阵列分布；每一列所述源电极位于一条所述字线的上表面通过所述栅极绝缘层与所述字线相绝缘，不同列所述源电极位于不同的所述字线上方；
    多个相互间隔设置的半导体膜层，其中，每一所述字线的两个侧表面分别设置有两列所述半导体膜层，每一列中的各所述半导体膜层分别与对应的一列中的各所述源电极一一对应，对应于一个所述源电极的所述两个半导体膜层与所述源电极在行方向间隔排列。
  13. 根据权利要求12所述的半导体阵列，其特征在于，相邻的两条所述字线之间具有沿着所述字线的延伸方向延伸的沟槽，所述沟槽露出所述相邻的两条字线的所述侧表面上的栅极绝缘层，以及所述源电极的侧表面，所述半导体膜层的主表面至少位于所述栅极绝缘层沿垂直衬底的方向延伸。
  14. 根据权利要13所述的半导体阵列，其特征在于，所述沟槽延伸到所述字线下方的漏电极的侧表面，所述半导体膜层的主表面同时延伸到所述字线下方的漏电极的侧表面，以及延伸到所述源电极的侧表面。
  15. 根据权利要13或14所述的半导体阵列，其特征在于，相邻两条所述字线之间的所述沟槽设置有一列在列方向间隔设置的所述半导体膜层，每个所述半导体膜层具有两个相对设置的侧表面，所述半导体膜层的两个侧表面分别朝向所述两条相邻的字线，且分别与所述相邻的两条字线的两个侧表面上的栅极绝缘层连接。
  16. 根据权利要15所述的半导体阵列，其特征在于，所述半导体膜层远离衬底的一个顶面不高于所述源电极的顶面，使得所述源电极与所述半导体膜层之间形成台阶，所述半导体膜层、所述源电极和所述字线上覆盖有介质保护层，所述介质保护层对应所述源电极的区域设置有开口，所述开口露出所述源电极。
  17. 根据权利要12所述的半导体阵列，其特征在于，所述源电极和所述漏电极分别为金属，所述半导体膜层为金属氧化物半导体，所述字线为金属或多晶硅。
  18. 一种晶体管，其特征在于，包括：
    衬底，具有上表面；
    两个半导体膜层，沿着行方向间隔分布，每个所述半导体膜层具有两个垂直于衬底的方向的主表面，所述两个半导体膜层的其中两个主表面相邻且相向而置；
    字线，位于所述两个半导体膜层之间，沿着列方向延伸，所述行方向与所述列方向垂直；所述字线具有上表面、下表面和两个侧表面；
    绝缘层，位于所述字线的上表面、下表面和两个侧表面，所述两个半导体膜层的相邻的两个主表面分别与所述字线的侧表面的所述绝缘层接触，所述两个半导体膜层在所述字线的侧表面分布且与所述字线的所述绝缘层上分布；
    源电极和漏电极，分别位于所述字线的所述上表面和下表面，通过所述绝缘层与所述字线绝缘。
  19. 根据权利要求18所述的晶体管，其特征在于，所述源电极和漏电极呈块状，所述块状源电极和漏电极的侧表面不超过所述字线的侧表面；
    所述两个半导体膜层在所述字线的侧表面分布且延伸到所述源电极和所述漏电极的侧表面。
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