WO2023181803A1 - 電子部品及び回路装置 - Google Patents

電子部品及び回路装置 Download PDF

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Publication number
WO2023181803A1
WO2023181803A1 PCT/JP2023/007305 JP2023007305W WO2023181803A1 WO 2023181803 A1 WO2023181803 A1 WO 2023181803A1 JP 2023007305 W JP2023007305 W JP 2023007305W WO 2023181803 A1 WO2023181803 A1 WO 2023181803A1
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Prior art keywords
semiconductor substrate
electronic component
conductor
electrode
capacitor
Prior art date
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Ceased
Application number
PCT/JP2023/007305
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English (en)
French (fr)
Japanese (ja)
Inventor
翔太 安藤
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202380029129.2A priority Critical patent/CN118872056A/zh
Priority to JP2024509886A priority patent/JP7747177B2/ja
Publication of WO2023181803A1 publication Critical patent/WO2023181803A1/ja
Priority to US18/891,564 priority patent/US20250015001A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers

Definitions

  • the present invention relates to an electronic component that includes a semiconductor substrate and is configured by providing a capacitor, an inductor, etc. on the semiconductor substrate.
  • Patent Document 1 discloses a high frequency integrated circuit device in which passive devices such as inductors and capacitors are formed on an insulator layer stacked on a semiconductor substrate. All of the capacitors included in this high-frequency integrated circuit device have a MIM (metal-insulator-metal) structure, and their electrodes are arranged on the surface of the stacked insulator layer with respect to the semiconductor substrate.
  • MIM metal-insulator-metal
  • Patent Document 2 discloses a semiconductor device including a capacitor configured by laminating a dielectric layer and an electrode layer on a semiconductor substrate.
  • One electrode of the capacitor is located on the stacked surface of the insulator layer relative to the semiconductor substrate, and the other electrode is located on the lower surface of the semiconductor substrate. Therefore, if the substrate on which the semiconductor device is mounted is a conductor at ground potential, the capacitor and the ground are directly electrically connected, and no wiring is required to connect them.
  • a capacitor having such a structure is herein referred to as a "vertical capacitor" for convenience.
  • such a high frequency integrated circuit device when configuring a power amplifier for a communication device, it is assumed that the power amplifier is placed on a copper foil surface at ground potential formed on a circuit board. . Further, such a high frequency integrated circuit device includes a capacitor inserted between the signal line and ground. When this capacitor is configured using the above-mentioned MIM, it is necessary to connect one electrode of the capacitor to the ground using a wiring structure such as a wire. In this case, parasitic impedance due to the wiring structure is electrically inserted between the capacitor and the ground, which causes deterioration of electrical characteristics such as the Q value of the capacitor.
  • Patent Document 2 With a vertical capacitor as shown in Patent Document 2, the problem of deterioration of electrical circuit characteristics due to the wiring structure described above does not occur.
  • Patent Document 1 attempts have been made to form a vertical capacitor as well as a passive device such as an inductor (hereinafter referred to as a "pattern inductor") using a conductor pattern on an insulator layer stacked on a semiconductor substrate. Then, as described below, the electrical characteristics such as the Q value of the inductor deteriorate.
  • a passive device such as an inductor (hereinafter referred to as a "pattern inductor")
  • ESR equivalent series resistance
  • the equivalent series resistance of a vertical capacitor is determined by the conductivity of the internal wiring and semiconductor substrate, which are the paths for current flowing through the capacitor.
  • a semiconductor substrate has lower conductivity than internal wiring, and has a longer current path. Therefore, the conductivity of the semiconductor substrate tends to be the main factor that increases the equivalent series resistance of the vertical capacitor.
  • To lower the equivalent series resistance of a vertical capacitor it is necessary to increase the conductivity of the semiconductor substrate.
  • the equivalent series resistance (ESR) of a patterned inductor is also determined by the conductivity of the conductor pattern including internal wiring and the semiconductor substrate. That is, since the conductor pattern is part of the current path of the inductor, the equivalent series resistance of the pattern inductor is directly affected by the conductivity of the conductor pattern.
  • An object of the present invention is to form an inductor using a wiring pattern on an insulator layer laminated on a semiconductor substrate and also to form a vertical capacitor, an electronic component including an inductor with a high Q value and a capacitor with a high Q value. and to provide a circuit device.
  • a pattern inductor When a pattern inductor operates as an inductor, it generates a high-frequency magnetic field around it, and this high-frequency magnetic field induces eddy currents in conductors near the pattern inductor, and these eddy currents generate Joule heat. .
  • This Joule heat is generally called eddy current loss, and increases as the conductivity of the conductor through which the eddy current flows increases. This eddy current loss appears as equivalent series resistance in terms of the electrical characteristics of the inductor.
  • the "semiconductor substrate” refers to the above-mentioned “conductor near the inductor.” Therefore, in order to lower the equivalent series resistance of the patterned inductor, it is necessary to lower the conductivity of the semiconductor substrate.
  • the equivalent series resistance of the vertical capacitor and patterned inductor is affected by the conductivity of the silicon substrate, there is a trade-off relationship between them. For example, if the conductivity of the silicon substrate is increased to improve the Q value of a vertical capacitor, the Q value of the patterned inductor will deteriorate; if the conductivity of the silicon substrate is decreased to improve the Q value of the patterned inductor, The Q value of the vertical capacitor deteriorates.
  • the electronic component as an example of the present disclosure is a semiconductor substrate; an insulator layer formed on the semiconductor substrate; a plurality of conductor layers formed on the insulator layer; a dielectric layer formed on the semiconductor substrate; a lower surface electrode formed on the lower surface of the semiconductor substrate; Equipped with At least one of the plurality of conductor layers is a wiring pattern, At least one of the plurality of conductive layers is a flat electrode that pairs with the semiconductor substrate or the bottom electrode with the dielectric layer in between, A first region of the semiconductor substrate where the dielectric layer and the flat plate electrode are formed has a conductor portion having a higher conductivity than the semiconductor substrate at a higher rate than a second region other than the first region. placed, It is characterized by
  • a circuit device as an example of the present disclosure includes: Comprising the above electronic component and a mounting board on which the electronic component is mounted, A ground pattern of the mounting board and the bottom electrode of the electronic component are connected.
  • an electronic component can be obtained that includes an inductor with a high Q value due to suppression of eddy current flowing through a semiconductor substrate and a capacitor with a high Q value due to a reduction in equivalent series resistance.
  • FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment
  • FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A).
  • FIG. 2 is a circuit diagram of the electronic component 101.
  • FIG. 3 is a block diagram showing the circuit configuration of the transmitter of the communication device. 4(A) is a circuit diagram of an electronic component 101A different from the electronic component 101 shown in FIG. 1(A) and FIG. 1(B)
  • FIG. 4(B) is a circuit diagram of an electronic component 101A different from the electronic component 101 shown in FIG.
  • FIG. 3 is a circuit diagram of another electronic component 101B different from the electronic component 101 shown in FIG. FIG.
  • FIG. 5 is a cross-sectional view of the electronic component 102 according to the second embodiment.
  • FIG. 6 is a cross-sectional view of the electronic component 103 according to the third embodiment.
  • FIG. 7 is a cross-sectional view of the electronic component 104 according to the fourth embodiment.
  • FIG. 8 is a sectional view of an electronic component 105 according to the fifth embodiment.
  • 9(A) is a partial vertical sectional view of an electronic component 106 according to the sixth embodiment
  • FIG. 9(B) is a plan sectional view taken along the line XX in FIG. 9(A).
  • FIG. 10 is a partial plan cross-sectional view of an electronic component 107 according to the seventh embodiment.
  • FIG. 1(A) is a plan view of an electronic component 101 according to the first embodiment
  • FIG. 1(B) is a sectional view taken along the line BB in FIG. 1(A).
  • FIG. 1A is a plan view in a state before formation of a protective film 10, which will be described later.
  • This electronic component 101 includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, and conductor layers 3A, 3B, 3C, 3D, 3E, 3F, and 3G formed on the insulator layer 2. , 3H, a dielectric layer 4 formed on the semiconductor substrate 1, a dielectric layer 5 formed in the insulator layer 2, and a first pad electrode 9A and a dielectric layer 5 formed on the conductor layers 3G and 3H. It includes a second pad electrode 9B, a protective film 10 formed on the upper surface side of the semiconductor substrate 1, and a lower surface electrode 8 formed on the lower surface of the semiconductor substrate 1.
  • the semiconductor substrate 1 is, for example, a substrate made of an impurity semiconductor such as a carrier-doped silicon substrate
  • the insulator layer 2 is, for example, a SiN film
  • the conductor layers 3A, 3B, 3C, 3D, and 3E are, for example, an Al film
  • the conductor layers 3F, 3G, and 3H. is, for example, a Cu film
  • the dielectric layers 4 and 5 are, for example, a SiO 2 film
  • the first pad electrode 9A and the second pad electrode 9B are, for example, a metal film with a Ni base and an Au surface
  • the protective film 10 is, for example, a solder resist.
  • the organic insulating film and the lower electrode 8 are, for example, a metal film having a base of Cu or Ni and a surface of Au.
  • the wiring pattern formed by the conductor layers 3A and 3B constitutes an inductor.
  • the conductor layers 3C and 3D constitute a capacitor electrode formed in the insulator layer 2.
  • the conductor layer 3E constitutes a flat electrode formed on the dielectric layer 4.
  • the conductor layers 3F, 3G, and 3H constitute extraction electrodes.
  • the first pad electrode 9A and the second pad electrode 9B are used, for example, as pads for wire bonding.
  • the lower surface electrode 8 is used, for example, as an electrode for die bonding.
  • An inductor region ZL in the semiconductor substrate 1 is formed by the wiring pattern formed by the conductor layers 3A and 3B. Furthermore, the region in the semiconductor substrate 1 where the conductor layer 3E and the dielectric layer 4 as flat plate electrodes are formed is a capacitor region ZC.
  • This capacitor region ZC is an example of a first region according to the present invention.
  • the area other than the first area of the semiconductor substrate 1 is a second area.
  • a conductor portion 7 is formed in the capacitor region ZC of the semiconductor substrate 1.
  • the conductor portion 7 is arranged below the dielectric layer 4.
  • the inductor region ZL is part of the second region.
  • the conductor portions 7 are arranged in a higher proportion in the capacitor region ZC (first region) of the semiconductor substrate 1 than in the second region of the semiconductor substrate 1 including the inductor region ZL.
  • the conductor portion 7 is made of conductive polysilicon, for example, and has higher conductivity than the semiconductor substrate 1.
  • the conductor portion 7 is formed by, for example, digging a plurality of trenches in the semiconductor substrate 1 and filling the trenches with the conductive polysilicon or the like.
  • the conductor layer 3E is composed of sides extending in the X-axis direction and sides extending in the Y-axis direction, and the plurality of conductor parts 7 extend in parallel to each other in the Y-axis direction.
  • the conductor layers 3A and 3B are spiral conductor layers and constitute an inductor.
  • the conductor layer 3E, the dielectric layer 4, the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8 constitute a capacitor.
  • the conductor layer 3E is the first electrode of the capacitor
  • the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8 are the second electrodes of the capacitor.
  • the conductor portions 7 having higher conductivity than the semiconductor substrate 1 are arranged in the capacitor region ZC in the semiconductor substrate 1 at a higher rate than in the inductor region ZL. This allows the conductivity of the semiconductor substrate 1 to be lowered, thereby suppressing eddy currents induced in the semiconductor substrate 1 due to the high frequency magnetic field generated by the wiring patterns of the conductor layers 3A and 3B, resulting in a high Q value. An inductor is obtained. Further, the conductivity of the capacitor region ZC in which the conductor layer 3E as a flat plate electrode is formed can be increased, and a capacitor with a high Q value can be obtained.
  • the electronic component 101 shown above is mounted on a mounting board for mounting it.
  • This mounting board and electronic component 101 constitute a circuit device.
  • a ground pattern and other electrode patterns are formed on the mounting board.
  • the first pad electrode 9A is electrically connected to the conductor layer 3E, and the second pad electrode 9B is electrically connected to one end of the conductor layer 3A forming the inductor pattern. The other end and the conductor layer 3E are electrically connected.
  • the lower surface electrode 8 of the electronic component 101 is connected to a ground pattern formed on the mounting board, and the first pad electrode 9A and the second pad electrode 9B are wired to an electrode pattern other than the ground pattern formed on the mounting board. Bonded.
  • FIG. 2 is a circuit diagram of the electronic component 101.
  • the ports P1 and P2 shown in FIG. 2 correspond to the first pad electrode 9A and the second pad electrode 9B of the electronic component 101 shown in FIGS. 1(A) and 1(B), respectively, and the ground shown in FIG. 1(A) and the lower surface electrode 8 in FIG. 1(B).
  • the capacitor C1 shown in FIG. 2 is a capacitor that includes a conductor layer 3E, a dielectric layer 4, a conductor portion 7, a semiconductor substrate 1, and a bottom electrode 8.
  • a capacitor C2 shown in FIG. 2 is a capacitor composed of conductor layers 3C and 3D and a dielectric layer 5.
  • the inductor L1 shown in FIG. 2 is an inductor composed of conductor layers 3A and 3B. Such an LC circuit constitutes an impedance matching circuit.
  • the capacitor C1 formed in the capacitor region ZC is connected to the ground pattern of the mounting board through the semiconductor substrate 1 and the conductor part, the equivalent series resistance ESR can be suppressed compared to a path device structured via wiring, and the Q value can be reduced. A high impedance matching circuit can be obtained.
  • FIG. 3 is a block diagram showing the circuit configuration of the transmitter of the communication device.
  • This transmitting section includes a transmitting circuit that inputs a transmitting signal, modulates it, and outputs a high-frequency transmitting signal, a power amplifier PA, and an impedance matching circuit MC that matches impedance between the transmitting circuit and the power amplifier PA.
  • the output signal of power amplifier PA is guided to an antenna.
  • a communication device including the transmitter shown in FIG. 3 is provided in a base station, for example.
  • FIG. 4(A) is a circuit diagram of an electronic component 101A different from the electronic component 101 shown in FIG. 1(A) and FIG. 1(B), and FIG. 4(B) is a circuit diagram of an electronic component 101A different from the electronic component 101 shown in FIG.
  • FIG. 2 is a circuit diagram of another electronic component 101B different from the electronic component 101 shown in FIG.
  • the electronic component 101A is a ⁇ -type impedance matching circuit including capacitors C1, C2 and an inductor L1
  • the electronic component 101B is a T-type impedance matching circuit including inductors L1, L2 and capacitor C1.
  • capacitors C1 and C2 that are shunt-connected between the signal line and the ground are vertical capacitors configured in the capacitor region ZC in FIGS. 1(A) and 1(B).
  • the inductor L1 inserted in series in the signal line is an inductor configured in the inductor region ZL in FIGS. 1(A) and 1(B).
  • the capacitor C1 connected in a shunt manner between the signal line and the ground is a vertical capacitor configured in the capacitor region ZC in FIGS. 1(A) and 1(B). Furthermore, the inductors L1 and L2 inserted in series in the signal line are inductors configured in the inductor region ZL in FIGS. 1(A) and 1(B).
  • an impedance matching circuit composed of a capacitor with a high Q value and an inductor with a high Q value is obtained.
  • the bottom electrode 8 formed on the bottom surface of the semiconductor substrate 1 is connected to the ground of the impedance matching circuit.
  • the first pad electrode 9A and the lower surface electrode 8 are used is not limited to this example.
  • the first pad electrode 9A may be connected to the circuit ground, and the lower surface electrode 8 may be used as a signal line port. That is, the lower surface electrode of the semiconductor substrate 1 may be used as a capacitor electrode.
  • the second embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the capacitor region is different from the example shown in the first embodiment.
  • FIG. 5 is a cross-sectional view of the electronic component 102 according to the second embodiment.
  • the cross-sectional position corresponds to the position shown in FIG. 1(B).
  • the conductor portion 7 is formed on the top of the semiconductor substrate 1, but in the example shown in FIG. 5, the conductor portion 7 is formed on the bottom of the semiconductor substrate 1.
  • the conductor portion 7 is directly electrically connected to, or in contact with, the lower electrode 8 .
  • the conductor part 7 is formed by digging a plurality of trenches in the upper part of the semiconductor substrate 1 and filling the trenches with a conductor.
  • the conductor portion 7 is formed by digging a plurality of trenches in the lower part of the semiconductor substrate 1 and filling the trenches with a conductor.
  • the conductor portion 7 disposed in the capacitor region ZC may be formed at the bottom of the semiconductor substrate 1. Also in the electronic component 102, since the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8, which constitute the second electrode of the vertical capacitor, is high, a capacitor with a high Q value can be constructed.
  • the third embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the capacitor region is different from the examples shown in the previous embodiments.
  • FIG. 6 is a cross-sectional view of the electronic component 103 according to the third embodiment.
  • the cross-sectional position corresponds to the position shown in FIG. 1(B).
  • the conductor portion 7 is formed near the top of the semiconductor substrate 1, but in the example shown in FIG. It is formed.
  • the conductor portion 7 disposed in the capacitor region ZC may be formed from the upper surface to the lower surface of the semiconductor substrate 1. Also in the electronic component 103, since the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8, which constitute the second electrode of the vertical capacitor, is high, a capacitor with a high Q value can be constructed.
  • the fourth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the capacitor region is different from the examples shown in the previous embodiments.
  • FIG. 7 is a cross-sectional view of the electronic component 104 according to the fourth embodiment.
  • the cross-sectional position corresponds to the position shown in FIG. 1(B).
  • the conductor portion 7 is formed near the top of the semiconductor substrate 1, but in the example shown in FIG. ing.
  • the conductor portion 7 disposed in the capacitor region ZC may be formed inside the semiconductor substrate 1. Also in the electronic component 104, since the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8, which constitute the second electrode of the vertical capacitor, is high, a capacitor with a high Q value can be constructed.
  • the fifth embodiment will exemplify an electronic component in which the configuration of the conductor portion disposed in the capacitor region is different from the examples shown in the previous embodiments.
  • FIG. 8 is a cross-sectional view of an electronic component 105 according to the fifth embodiment.
  • the cross-sectional position corresponds to the position shown in FIG. 1(B).
  • the conductor portion 7 is formed on the upper part of the semiconductor substrate 1, and in the electronic component 102 shown in FIG.
  • some of the plurality of conductor parts 7 are formed on the upper part of the semiconductor substrate 1, and some parts are formed on the lower part of the semiconductor substrate 1.
  • the conductor portion 7 disposed in the capacitor region ZC may be formed on both the upper and lower portions of the semiconductor substrate 1. Also in the electronic component 102, since the combined conductivity of the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8, which constitute the second electrode of the vertical capacitor, is high, a capacitor with a high Q value can be constructed.
  • FIG. 9(A) is a partial longitudinal sectional view of the electronic component 106 according to the sixth embodiment
  • FIG. 9(B) is a plan sectional view taken along the line XX in FIG. 9(A).
  • FIGS. 9(A) and 9(B) illustrate the vertical capacitor portion, and the configurations of other portions are the same as the electronic components shown in the previous embodiments.
  • the electronic component 106 of this embodiment includes a semiconductor substrate 1, an insulator layer 2 formed on the semiconductor substrate 1, conductor layers 3E, 3F, and 3G formed on the insulator layer 2, and a semiconductor substrate 1.
  • the dielectric layer 4 formed on the top, the first pad electrode 9A formed on the conductor layer 3G, the protective film 10 formed on the top surface of the semiconductor substrate 1, and the first pad electrode 9A formed on the bottom surface of the semiconductor substrate 1. and a lower surface electrode 8. Examples of materials for each part are as described in the first embodiment.
  • the dielectric layer 4 is formed by digging a plurality of trenches in the upper surface of the semiconductor substrate 1 and coating the inner surfaces of these trenches and the upper surface of the semiconductor substrate 1 with a dielectric material. Further, the dielectric layer 4 is coated with a conductive layer 3E.
  • the conductor portion 7 is formed by digging a plurality of trenches in the lower surface of the semiconductor substrate 1 and filling the trenches with a conductor.
  • the gap between the conductor portion 7 and the dielectric layer 4 can be reduced, so the Q value of the vertical capacitor can be effectively increased. Further, the effective area of the dielectric layer 4 interposed between the conductor layer 3E and the semiconductor substrate 1 can be increased, and the space of the vertical capacitor can be saved.
  • FIG. 10 is a partial plan cross-sectional view of an electronic component 107 according to the seventh embodiment.
  • the cross-sectional position corresponds to the position shown in FIG. 9(B).
  • the lower part of the conductor layer 3E and the conductor portion 7 are formed in a line shape, and the lower part of the dielectric layer 4 is formed in a groove shape.
  • the lower portions of the conductor layer 3E and the conductor portion 7 are formed into a cylindrical shape, and the lower portion of the dielectric layer 4 is formed into a cylindrical shape.
  • the gap between the conductor portion 7 and the dielectric layer 4 can be reduced, so the Q value of the vertical capacitor can be effectively increased. Further, the effective area of the dielectric layer 4 interposed between the conductor layer 3E and the semiconductor substrate 1 can be increased, and the space of the vertical capacitor can be saved.
  • the inductor pattern formed in the inductor region ZL has a spiral shape, but the inductor pattern formed in the inductor region ZL is not limited to the spiral shape.
  • it may be in a loop shape, or it may be in a helical shape in which a plurality of loop-shaped conductor patterns are stacked and connected by an interlayer connecting conductor.
  • FIG. 1 shows a conductor portion extending in the Y-axis direction
  • the shape of the conductor portion is not limited to this.
  • it may have a plurality of cylindrical shapes, a plurality of cross shapes, or a plurality of cylindrical shapes.
  • an electronic component including a capacitor and an inductor is shown as a passive component, but the present invention can be similarly applied to an electronic component including an active component as well as a passive component.
  • the conductor portion 7 when viewed in a direction perpendicular to the plane of the semiconductor substrate 1, the conductor portion 7 is located in the formation region of the dielectric layer 4 in the X-axis direction.
  • the conductor portion 7 fits in and protrudes from the formation region of the dielectric layer 4 in the Y-axis direction, the present invention is not limited to this.
  • the conductor portion 7 may be arranged outside the region where the dielectric layer 4 is formed in the X-axis direction. Even in that case, it is effective for increasing the substantial conductivity of the current path flowing through the second electrode constituted by the semiconductor substrate 1, the conductor portion 7, and the lower surface electrode 8.
  • the conductor portion 7 is arranged only in the capacitor region ZC of the vertical capacitor, but the conductor portion may be arranged outside the capacitor region. Even in that case, it is sufficient that the conductor portions 7 are arranged in a higher proportion in the capacitor region ZC of the semiconductor substrate 1 than in the inductor region ZL.

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PCT/JP2023/007305 2022-03-23 2023-02-28 電子部品及び回路装置 Ceased WO2023181803A1 (ja)

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Application Number Priority Date Filing Date Title
CN202380029129.2A CN118872056A (zh) 2022-03-23 2023-02-28 电子部件及电路装置
JP2024509886A JP7747177B2 (ja) 2022-03-23 2023-02-28 電子部品及び回路装置
US18/891,564 US20250015001A1 (en) 2022-03-23 2024-09-20 Electronic component and circuit device

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JP2022-046259 2022-03-23
JP2022046259 2022-03-23

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JP2009515356A (ja) * 2005-11-08 2009-04-09 エヌエックスピー ビー ヴィ 高周波数動作においてアプリケーションを分離するのに適したトレンチキャパシタ装置

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JP4835082B2 (ja) * 2005-09-28 2011-12-14 株式会社デンソー 半導体装置及びその製造方法
WO2009104132A1 (en) * 2008-02-20 2009-08-27 Nxp B.V. Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate
DE102014200869B4 (de) * 2013-11-22 2018-09-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Integrierter Kondensator und Verfahren zum Herstellen desselben und dessen Verwendung

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US20010019865A1 (en) * 1997-11-05 2001-09-06 Erdeljac John P. Metallization outside protective overcoat for improved capacitors and inductors
JP2009515356A (ja) * 2005-11-08 2009-04-09 エヌエックスピー ビー ヴィ 高周波数動作においてアプリケーションを分離するのに適したトレンチキャパシタ装置

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