JPWO2023181803A1 - - Google Patents
Info
- Publication number
- JPWO2023181803A1 JPWO2023181803A1 JP2024509886A JP2024509886A JPWO2023181803A1 JP WO2023181803 A1 JPWO2023181803 A1 JP WO2023181803A1 JP 2024509886 A JP2024509886 A JP 2024509886A JP 2024509886 A JP2024509886 A JP 2024509886A JP WO2023181803 A1 JPWO2023181803 A1 JP WO2023181803A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/495—Capacitive arrangements or effects of, or between wiring layers
- H10W20/496—Capacitor integral with wiring layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/497—Inductive arrangements or effects of, or between, wiring layers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2022046259 | 2022-03-23 | ||
| JP2022046259 | 2022-03-23 | ||
| PCT/JP2023/007305 WO2023181803A1 (ja) | 2022-03-23 | 2023-02-28 | 電子部品及び回路装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2023181803A1 true JPWO2023181803A1 (https=) | 2023-09-28 |
| JPWO2023181803A5 JPWO2023181803A5 (https=) | 2024-11-28 |
| JP7747177B2 JP7747177B2 (ja) | 2025-10-01 |
Family
ID=88100559
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024509886A Active JP7747177B2 (ja) | 2022-03-23 | 2023-02-28 | 電子部品及び回路装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20250015001A1 (https=) |
| JP (1) | JP7747177B2 (https=) |
| CN (1) | CN118872056A (https=) |
| WO (1) | WO2023181803A1 (https=) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010019865A1 (en) * | 1997-11-05 | 2001-09-06 | Erdeljac John P. | Metallization outside protective overcoat for improved capacitors and inductors |
| JP2007095950A (ja) * | 2005-09-28 | 2007-04-12 | Denso Corp | 半導体装置及びその製造方法 |
| JP2009515356A (ja) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | 高周波数動作においてアプリケーションを分離するのに適したトレンチキャパシタ装置 |
| WO2009104132A1 (en) * | 2008-02-20 | 2009-08-27 | Nxp B.V. | Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate |
| JP2015111671A (ja) * | 2013-11-22 | 2015-06-18 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | 集積キャパシタおよびそれを製造する方法 |
-
2023
- 2023-02-28 WO PCT/JP2023/007305 patent/WO2023181803A1/ja not_active Ceased
- 2023-02-28 JP JP2024509886A patent/JP7747177B2/ja active Active
- 2023-02-28 CN CN202380029129.2A patent/CN118872056A/zh active Pending
-
2024
- 2024-09-20 US US18/891,564 patent/US20250015001A1/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010019865A1 (en) * | 1997-11-05 | 2001-09-06 | Erdeljac John P. | Metallization outside protective overcoat for improved capacitors and inductors |
| JP2007095950A (ja) * | 2005-09-28 | 2007-04-12 | Denso Corp | 半導体装置及びその製造方法 |
| JP2009515356A (ja) * | 2005-11-08 | 2009-04-09 | エヌエックスピー ビー ヴィ | 高周波数動作においてアプリケーションを分離するのに適したトレンチキャパシタ装置 |
| WO2009104132A1 (en) * | 2008-02-20 | 2009-08-27 | Nxp B.V. | Ultra high density capacity comprising pillar-shaped capacitors formed on both sides of a substrate |
| JP2015111671A (ja) * | 2013-11-22 | 2015-06-18 | フラウンホッファー−ゲゼルシャフト ツァ フェルダールング デァ アンゲヴァンテン フォアシュンク エー.ファオ | 集積キャパシタおよびそれを製造する方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US20250015001A1 (en) | 2025-01-09 |
| WO2023181803A1 (ja) | 2023-09-28 |
| JP7747177B2 (ja) | 2025-10-01 |
| CN118872056A (zh) | 2024-10-29 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20240918 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20240918 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20250819 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20250901 |
|
| R150 | Certificate of patent or registration of utility model |
Ref document number: 7747177 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |