WO2023178739A1 - 一种半导体结构及其制作方法 - Google Patents

一种半导体结构及其制作方法 Download PDF

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Publication number
WO2023178739A1
WO2023178739A1 PCT/CN2022/086178 CN2022086178W WO2023178739A1 WO 2023178739 A1 WO2023178739 A1 WO 2023178739A1 CN 2022086178 W CN2022086178 W CN 2022086178W WO 2023178739 A1 WO2023178739 A1 WO 2023178739A1
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layer
gate stack
contact
substrate
semiconductor structure
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PCT/CN2022/086178
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English (en)
French (fr)
Inventor
吴铁将
朱玲欣
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长鑫存储技术有限公司
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Priority to US17/846,011 priority Critical patent/US20230328971A1/en
Publication of WO2023178739A1 publication Critical patent/WO2023178739A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • an electric fuse refers to a connecting line in an integrated circuit whose resistance can change significantly (from a low configuration to a high resistance state) or can be blown.
  • the main uses of electric fuses include: (1) Used to activate redundant circuits to replace defective circuits on the same wafer, thereby effectively improving process yield.
  • the electric fuse connects the redundant circuits in the integrated circuit. Once the integrated circuit is detected to be defective, the electric fuse is used to repair or replace the defective circuit; (2) It is used for the programming function of the integrated circuit.
  • the metal interconnections, device arrays and programmed circuits are first processed on the chip, and then the data is input from the outside, that is, the standard chip is made into a unique chip through the programmed circuit.
  • Various chips are used to activate redundant circuits to replace defective circuits on the same wafer, thereby effectively improving process yield.
  • the electric fuse connects the redundant circuits in the integrated circuit. Once the integrated circuit is detected to be defective, the electric fuse is used to repair or replace the defective circuit; (2) It is used for the programming function of the integrated circuit.
  • Electric fuses can greatly save chip development and production costs in integrated circuit programming functions, so they are widely used in Programmable Read Only Memory (PROM).
  • PROM Programmable Read Only Memory
  • the writing of information "1" is completed by blowing the electric fuse at a higher voltage to create an open circuit, while the undisconnected electric fuse remains connected, which is the state "0".
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method, which can at least reduce the difficulty of blowing an electric fuse.
  • embodiments of the present disclosure provide a semiconductor structure, including: a substrate, and a gate oxide layer located on the surface of the substrate; a gate stack layer, the gate stack layer is located on the gate oxide layer. the surface of the layer; an isolation layer, the isolation layer covering at least the first sidewall of the gate stack layer; a contact structure, the contact structure is at least located on the surface of the substrate; a dielectric layer, the dielectric layer is located at least on the Between the contact structure and the second sidewall of the gate stack layer, the first sidewall and the second sidewall are arranged oppositely, and the thickness of the dielectric layer is smaller than the thickness of the isolation layer.
  • the isolation layer is also located on part of the top surface of the gate stack layer; part of the contact structure is located above the gate stack layer.
  • the contact structure overlaps with the projection of the gate stack layer on the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 ⁇ 0.5 of the width of the gate stack layer.
  • the thickness of the dielectric layer is smaller than the thickness of the gate oxide layer.
  • a portion of the contact structure is located within an active region of the substrate.
  • the contact structure includes: a contact layer, a barrier layer and a conductive layer, the barrier layer is located between the contact layer and the conductive layer, and the contact layer is located in the active area .
  • the thickness of the dielectric layer is less than or equal to 3 nm.
  • another aspect of the present disclosure also provides a method for manufacturing a semiconductor structure, including: providing a substrate, forming a gate oxide layer on the surface of the substrate, and forming a gate stack on the gate oxide layer layer; forming an isolation layer, the isolation layer covering at least the first sidewall of the gate stack layer; forming a dielectric layer, the dielectric layer covering at least the second sidewall of the gate stack layer, the first The side wall is arranged opposite to the second side wall, and the thickness of the dielectric layer is smaller than the thickness of the isolation layer; a contact structure is formed, the contact structure is at least located on the surface of the substrate, and the contact structure is with the surface contact of the dielectric layer.
  • the method of forming the isolation layer includes forming an initial isolation layer covering sidewalls and top surfaces of the gate stack layer and the substrate. the surface; pattern the initial isolation layer, remove the initial isolation layer located on the second sidewall surface of the gate stack layer, and the remainder is located on the first sidewall of the gate stack layer
  • the initial isolation layer on the surface and top surface serves as the isolation layer.
  • patterning the initial isolation layer includes: forming a groove that exposes at least the second sidewall and a portion of the top surface of the gate stack layer, and the groove also exposes the base.
  • forming the dielectric layer includes: depositing dielectric material on the sidewalls and bottom of the groove, removing the dielectric material located at the bottom of the groove, and forming a second side of the gate stack layer covering the wall dielectric layer.
  • the method before removing the dielectric material located at the bottom of the groove, the method further includes: performing ion implantation on the substrate at the bottom of the groove.
  • forming the contact structure includes: forming a contact layer at the bottom of the groove, the contact layer being electrically connected to the substrate; forming a barrier layer, the barrier layer being located on the surface of the dielectric layer and the top surface of the contact layer; forming a conductive layer, and the conductive layer fills the groove.
  • the method of forming the dielectric layer includes: controlling the thickness of the dielectric layer to be smaller than the thickness of the gate oxide layer.
  • the contact structure overlaps with the projection of the gate stack layer on the substrate surface, and the width of the overlapping portion is less than or equal to 0.1 ⁇ 0.5 of the width of the gate stack layer.
  • an electric fuse is formed by a substrate, a gate oxide layer, a gate stack layer, a contact structure and a dielectric layer, and by arranging the contact structure adjacent to the gate stack layer, when the gate stack The voltage on the layer is large enough, and the breakdown path of the electric fuse becomes from the gate stack layer through the dielectric layer to the contact structure, thereby reducing the difficulty of breakdown of the entire semiconductor structure.
  • the thickness of the dielectric layer is smaller than the thickness of the isolation layer
  • the contact path between the breakdown gate stack layer and the contact structure can be reduced, thereby reducing the breakdown difficulty of the entire semiconductor structure.
  • Figure 1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure
  • Figure 2 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure.
  • 3 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure.
  • the implementation of the present disclosure provides a semiconductor structure.
  • the breakdown path of the semiconductor structure is formed by the gate stack layer.
  • the layer passes through the gate oxide layer and the substrate to the contact structure and changes from the gate stack layer through the dielectric layer to the contact structure.
  • FIG. 1 is a cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 2 is a cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a substrate 100 and a gate oxide layer 110 located on the surface of the substrate 100 ; a gate stack layer 120 located on the surface of the gate oxide layer 110 ; an isolation layer 130 , the isolation layer 130 at least covers the first sidewall of the gate stack layer 120; the contact structure 140, the contact structure 140 is at least located on the surface of the substrate 100; the dielectric layer 150, the dielectric layer 150 is at least located between the contact structure 140 and the gate stack layer 120 Between the second side walls, the first side wall and the second side wall are arranged oppositely, and the thickness of the dielectric layer 150 is smaller than the thickness of the isolation layer 130 .
  • the base 100 , the gate oxide layer 110 , the gate stack layer 120 , the contact structure 140 and the dielectric layer 150 form an electric fuse.
  • the connection between the gate stack layer 120 and the contact structure 140 can be made.
  • the dielectric layer 150 in between is broken down, thereby forming a conductive path in the dielectric layer 150, so that the gate stack layer 120 is electrically connected to the contact structure 140, and the signal of the semiconductor structure is derived through the contact structure 140.
  • Setting the breakdown path from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140 can reduce the difficulty of breakdown of the entire semiconductor and structure, and can reduce the transmission path of the entire electrical signal transmission, thereby reducing the risk of electrical signal transmission during the transmission process. electrical signal loss, thereby improving the sensitivity of the semiconductor structure.
  • the material of the substrate 100 can be silicon, germanium or silicon germanium, and the material of the substrate 100 can also be doped. Taking the material of the substrate 100 as silicon as an example, the material of the substrate 100 can be doped. Doping trace amounts of trivalent elements, such as: boron, indium, gallium or aluminum, etc., thereby forming a P-type substrate; similarly, doping trace amounts of pentavalent elements, such as: phosphorus, antimony, arsenic, etc., into the substrate 100, thereby forming a P-type substrate. An N-type substrate can be formed, and the selection of doping elements of the substrate 100 can be considered based on actual needs and product performance. The embodiments of the present disclosure do not limit the materials and doped elements of the substrate 100 .
  • the gate oxide layer 110 is used to prevent the gate stack layer 120 from being in direct contact with the substrate 100.
  • the principle of breakdown of the gate oxide layer 110 is: when a higher voltage is applied between the upper and lower interfaces of the gate oxide layer 110. , the defects in the gate oxide layer 110 will form electron traps, which are randomly distributed in the middle of the gate oxide layer 110 . Under the action of the electric field of the gate oxide layer 110, each electron well has the ability to capture electrons. Under the action of a high electric field, the areas where the electron traps capture electrons may overlap each other, forming a current channel of the gate oxide layer 110. Then this channel It becomes a channel for potential breakdown.
  • the gate oxide layer 110 forms a current channel, and the performance of the gate oxide layer 110 slowly decreases. When the current is further discharged through the current channel, the gate oxide layer 110 is broken down. Since the distribution of electron wells in the gate oxide layer 110 is random, when the gate oxide layer 110 is thinner, the number of electron wells that need to form a path is relatively smaller. Therefore, a thin gate oxide layer 110 is more efficient than a thick gate oxide layer 110 . Breakdown is prone to occur.
  • the gate stack layer 120 may have a four-layer structure, including a first conductive layer 121, an intermediate layer 122, a second conductive layer 123 and a protective layer 124.
  • the first conductive layer 121 is located on the top of the gate oxide layer 110.
  • the intermediate layer 122 is located between the first conductive layer 121 and the second conductive layer 123
  • the protective layer 124 is at least located on the top surface of the second conductive layer 123 .
  • the gate stack layer 120 may also be a single-layer structure.
  • the gate stack layer may also be formed by stacking other layers. In this embodiment of the disclosure, the gate stack layer 120 is not The number of layers is limited.
  • the material of the first conductive layer 121 can be a semiconductor material, such as polysilicon; the material of the middle layer 122 can be titanium nitride or gallium nitride; the material of the second conductive layer 123 can be The material may be a metal material with good electrical conductivity, such as tungsten metal; the material of the protective layer 124 may be a hard insulating material, such as silicon nitride.
  • the electrical signal can be transmitted from the semiconductor material to the substrate 100.
  • Semiconductor materials thereby avoiding the direct transmission of electrical signals from semiconductor materials to other materials, resulting in abnormalities in the process of transmitting electrical signals, thereby improving the stability of signal transmission in the semiconductor structure and improving the reliability of the semiconductor structure.
  • the intermediate layer 122 is provided to isolate the first conductive layer 121 and the second conductive layer 123, thereby preventing metal ions in the second conductive layer 123 from ion diffusion. Metal ions diffuse into the first conductive layer 121, and the intermediate layer 122 prevents ion diffusion from the second conductive layer 123 from contaminating the first conductive layer 121, thereby improving the stability of the first conductive layer 121 and thereby improving the reliability of the semiconductor structure.
  • the conductive performance of tungsten metal is higher than that of semiconductor materials such as polysilicon.
  • the metal material can improve the conductive performance of the gate stack layer 120, increase the transmission speed of electrical signals of the gate stack layer 120, and thereby improve the performance of the semiconductor structure.
  • the protective layer 124 covers the top surface of the second conductive layer 123.
  • the first conductive layer can be shared when the semiconductor structure is subjected to external pressure.
  • the stress on the first conductive layer 121, the middle layer 122 and the second conductive layer 123 is reduced, thereby reducing the stress on the first conductive layer 121, the middle layer 122 and the second conductive layer 123, thereby protecting the first conductive layer 121, the middle layer 122 and the second conductive layer 123.
  • the second conductive layer 123 further improves the reliability of the semiconductor structure.
  • the isolation layer 130 may be a multi-layer structure stacked.
  • the isolation layer 130 may include a first isolation layer 131, a second isolation layer 132 and a third isolation layer 133.
  • the first isolation layer 131 at least covers the gate.
  • the second isolation layer 132 is located between the first isolation layer 131 and the third isolation layer 133; in other embodiments, the isolation layer may also be a single-layer structure. There is no limit on the number of isolation layers.
  • the first isolation layer 131 and the third isolation layer 133 may be made of the same material, which may be silicon nitride, and the second isolation layer 132 may be made of silicon oxide.
  • the isolation layer 130 has a NON (Nitride-Oxide-Nitride) structure, that is, a nitride layer-oxide layer-nitride layer structure.
  • NON Niride-Oxide-Nitride
  • the isolation between the first isolation layer 131 and the third isolation layer can be improved.
  • the insulation performance between the layers 133 is because the material of the second isolation layer 132 is soft and the morphology is poor. Therefore, the first isolation layer 131 and the third isolation layer 133 are formed of a nitride layer to improve the formation of the second isolation layer 133 .
  • the morphology of the second isolation layer 132 is a NON (Nitride-Oxide-Nitride) structure, that is, a nitride layer-oxide layer-nitride layer structure.
  • the substrate 100 is also lightly doped and heavily doped. Since a certain space difference needs to be retained between the light doping and the heavy doping, by forming the first isolation layer 131 can be used as a lightly doped mask, and the formation of the third isolation layer 133 can be used as a mask for a heavily doped process, thereby facilitating the subsequent doping process of the substrate 100 .
  • the contact structure 140 may be formed by a multi-layer structure stack.
  • the contact structure 140 may include: a contact layer 141, a barrier layer 142, and a conductive layer 143.
  • the contact layer 141 is located on the surface of the substrate 100, and the barrier layer 142 is located on the contact layer.
  • the material of the contact layer 141 can be a compound of metal and semiconductor material or the semiconductor material is metal-doped, such as cobalt silicide, and the material of the barrier layer 142 can be titanium nitride or Gallium nitride, etc.
  • the material of the conductive layer 143 may be a metal material, such as tungsten metal.
  • the Schottky barrier between the contact structure 140 and the substrate 100 can be reduced, thereby reducing the contact resistance between the contact structure 140 and the substrate 100, thereby improving the response speed of the semiconductor structure.
  • the lattice of cobalt silicide and the silicon lattice can match each other very well, which can also reduce defects between the contact layer 141 and the substrate 100.
  • Metal is formed on the surface as a contact structure. By first forming the contact layer 141, the contact resistance between the contact structure 140 and the substrate 100 and defects between the two can be reduced, thereby improving the performance of the semiconductor structure.
  • the material of the contact layer 141 may also be metal silicide such as nickel silicide.
  • the metal ions in the conductive layer 143 can be prevented from diffusing into the contact layer 141 when ion diffusion occurs.
  • the barrier layer 142 can prevent the ion diffusion of the conductive layer 143 from contaminating the contact layer 141, thereby improving the resistance of the contact layer 141. stability, thereby improving the reliability of the semiconductor structure.
  • the material of the barrier layer 142 may be at least one of titanium nitride, tantalum nitride, or tantalum silicide.
  • the material of the conductive layer 143 may be tungsten metal.
  • the conductive performance of tungsten metal is higher than that of semiconductor materials such as polysilicon.
  • the conductive layer may also be made of metals such as molybdenum, or semiconductor materials such as polysilicon.
  • the isolation layer 130 is located on a portion of the top surface of the gate stack layer 120 ; and a portion of the contact structure 140 is located above the gate stack layer 120 .
  • the breakdown area between 140 includes the area where the sidewalls of the first conductive layer 121, the middle layer 122 and the second conductive layer 123 face the contact structure 140, and the breakdown area also includes the second conductive layer 121.
  • the area of the top surface of layer 123 facing the contact structure 140 reduces the difficulty of breakdown of the semiconductor structure by increasing the size of the breakdown area, by making the breakdown path of the semiconductor structure from the gate stack layer 120 to the dielectric layer 150 Turning to the contact structure 140, the difficulty of breakdown of the semiconductor structure can be reduced, and arranging the contact structure 140 above the gate stack layer 120 can reduce the volume of the contact structure 140 partially located on the surface of the substrate 100, thereby reducing the entire semiconductor structure. volume of.
  • the contact structure 140 overlaps with the projection of the gate stack layer 120 on the surface of the substrate 100 , and the width of the overlapping portion is less than or equal to 0.1 ⁇ 0.5 of the width of the gate stack layer 120 . It can be understood that the more overlapping parts there are, the larger the breakdown area between the corresponding gate stack layer 120 and the contact structure 140 will be.
  • the width of the overlapping portion is 0.1 to 0.5, which increases the breakdown area between the gate stack layer 120 and the contact structure 140 while providing a certain protection effect.
  • portions of contact structure 140 are located within the active region of substrate 100 . Specifically, part of the contact structure 140 is disposed in the substrate 100 to ensure the electrical connection between the contact structure 140 and the substrate 100 , thereby ensuring that the electrical signals of the substrate 100 and the gate stack layer 120 are exported through the contact structure 140 .
  • contact layer 141 is located within the active area. Specifically, in some embodiments, the top surface of the contact layer 141 may be flush with the top surface of the substrate 100 , or the top surface of the contact layer 141 may be higher than the top surface of the substrate 100 , that is, the bottom surface of the barrier layer 142 is flush with the top surface of the substrate 100 . The top surface of the contact layer 100 is flush or the bottom surface of the barrier layer 142 is higher than the top surface of the substrate 100; in other embodiments, the top surface of the contact layer 141 may be lower than the top surface of the substrate 100, that is, the bottom surface of the barrier layer 142 is lower than the top surface of the substrate 100. on the top surface of the substrate 100 . By disposing the contact layer 141 within the substrate 100, the electrical connection between the contact structure 140 and the substrate 100 is ensured, thereby improving the stability of the semiconductor structure.
  • flushness may mean that the top surface of the contact layer 141 is completely flush with the top surface of the substrate 100 , or it may mean that the height difference between the top surface of the contact layer 141 and the top surface of the substrate 100 is within 1 nm.
  • the height difference between the top surface of the contact layer 141 and the top surface of the substrate 100 is within 1 nm. It can also be considered that the top surface of the contact layer 141 can be flush with the top surface of the substrate 100 .
  • the isolation layer 130 may also cover the entire top surface of the gate stack layer 120. That is to say, the contact structure 140 is disposed opposite to the second sidewall of the gate stack layer 120 , that is, the projection of the gate stack layer 120 on the surface of the substrate 100 is adjacent to the projection of the contact structure 140 on the surface of the substrate 100 .
  • the dielectric layer 150 has opposite sidewalls, wherein one sidewall of the dielectric layer 150 is in contact with the gate stack layer 120 and the other opposite sidewall is in contact with the contact structure 140 .
  • the electric field between the gate stack layer 120 and the contact structure 140 will cause the defects between the dielectric layer 150 to have the ability to capture electrons. Under the action of the high electric field, the electron traps capture The areas of electrons may overlap each other, thus forming a current channel in the dielectric layer 150. As the current in the gate stack layer 120 continues to increase, the current channel on the dielectric layer 150 is turned on, thereby forming a breakdown, thereby causing the gate stack to The electrical signal of the layer 120 is conducted to the contact structure 140 , and then the electrical signal of the semiconductor structure is derived through the contact structure 140 .
  • the dielectric layer 150 is used to isolate the contact structure 140 and the gate stack layer 120 to avoid direct contact between the contact structure 140 and the gate stack layer 120. By breaking down the dielectric layer 150, the gate stack layer 120 and the contact structure 140 are electrically connected. , thereby reducing the breakdown difficulty of the electric fuse. By setting the thickness of the dielectric layer 150 to be smaller than the thickness of the isolation layer 130, the breakdown difficulty of the dielectric layer 150 can be reduced, thereby improving the breakdown sensitivity of the semiconductor structure. It should be noted that breakdown Sensitivity refers to the difficulty of breakdown. The higher the breakdown sensitivity, the lower the breakdown difficulty. The lower the breakdown sensitivity, the higher the breakdown difficulty.
  • the material of the dielectric layer 150 can be the same as the material of the gate oxide layer 110 , which can be silicon oxide. In another embodiment, the material of the dielectric layer 150 can also be different from the material of the gate oxide layer. The material can also be other materials that are more susceptible to breakdown, thereby reducing the difficulty of breakdown of the semiconductor structure.
  • the thickness of the dielectric layer 150 may be smaller than the thickness of the gate oxide layer 110. It can be understood that the thinner the thickness, the lower the corresponding breakdown difficulty, that is, the easier it is for breakdown phenomenon to occur there. Therefore, by setting the thickness of the dielectric layer 150 to be smaller than the thickness of the gate oxide layer 110, the possibility of breakdown on the dielectric layer 150 can be increased, so that the breakdown path of the semiconductor structure is from the gate stack layer 120 through the dielectric layer 150 to the contact. structure 140, thereby reducing the difficulty of breakdown of the semiconductor structure.
  • the thickness of the dielectric layer 150 is the size of the dielectric layer 150 in the direction of the gate stack layer 120 towards the contact structure 140; with reference to Figure 2, the thickness of the dielectric layer 150 is located between the first conductive layer 121, the intermediate layer 122 and The thickness of the dielectric layer 150 on the sidewall of the second conductive layer 123 is the size of the dielectric layer 150 in the direction perpendicular to the first conductive layer 121 toward the middle layer 122; the thickness of the dielectric layer 150 located above the second conductive layer 123 is the size of the first The size of the dielectric layer 150 in the direction of the conductive layer 121 toward the intermediate layer 122 .
  • the thickness of dielectric layer 150 is less than or equal to 3 nm. It can be understood that the smaller the thickness of the dielectric layer 150 , the correspondingly lower difficulty of breakdown in the dielectric layer 150 , and the smaller the thickness of the dielectric layer 150 , the current required to breakdown the dielectric layer is relatively smaller. By setting the thickness of the dielectric layer 150 to less than 3 nm, the possibility of breakdown on the dielectric layer 150 can be increased. By breaking down the dielectric layer 150, the electrical signal of the gate stack layer 120 is transmitted to the contact structure 140, which can reduce the risk of the semiconductor structure. Breakthrough difficulty.
  • the semiconductor structure further includes a filling layer 180.
  • the filling layer 180 is used to fill the semiconductor structure flat.
  • the filling layer 180 can be patterned to form other structures on the semiconductor structure.
  • the material of the filling layer can be an oxide. .
  • the embodiment of the present disclosure provides a method of arranging the contact structure 140 adjacent to the gate stack layer 120 and reducing the thickness of the dielectric layer 150 between the gate stack layer 120 and the contact structure 140, so that the breakdown path of the semiconductor structure is From the gate stack layer 120 through the dielectric layer 150 to the contact structure 140, by controlling the breakdown of the dielectric layer 150 to cause breakdown of the semiconductor structure, the breakdown difficulty of the entire semiconductor structure can be reduced, and the transmission path of the entire electrical signal transmission can be reduced, thereby Reduce the electrical signal loss during the transmission process of electrical signals, thereby improving the performance of the semiconductor structure.
  • Another embodiment of the present disclosure also provides a manufacturing method of a semiconductor structure.
  • the manufacturing method of the semiconductor structure can be used to form the semiconductor structure of the previous embodiment.
  • the same or corresponding parts can be referred to the embodiments described in Figures 1 and 2. No further details will be given below.
  • a method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • 3 to 7 are structural schematic diagrams corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.
  • a substrate 100 is provided, a gate oxide layer 110 is formed on the surface of the substrate 100, and a gate stack layer 120 is formed on the gate oxide layer 110; an isolation layer 130 is formed, and the isolation layer 130 covers at least the gate stack layer 120.
  • First side wall is provided.
  • the gate stack layer 120 may have a four-layer structure, including a first conductive layer 121, an intermediate layer 122, a second conductive layer 123 and a protective layer 124.
  • the first conductive layer 121 is located on the gate oxide layer.
  • the intermediate layer 122 is located between the first conductive layer 121 and the second conductive layer 123, and the protective layer 124 is located on the top surface of the second conductive layer 123.
  • the gate stack layer 120 may also have a single-layer structure. In other embodiments, the gate stack layer 120 may also be formed by stacking other layers.
  • the isolation layer 130 may include a first isolation layer 131, a second isolation layer 132, and a third isolation layer 133.
  • the first isolation layer 131 at least covers the first sidewall of the gate stack layer 120
  • the second isolation layer 133 covers at least the first sidewall of the gate stack layer 120.
  • the isolation layer 132 is located between the first isolation layer 131 and the third isolation layer 133; in other embodiments, the isolation layer may also be a single-layer structure.
  • a method of forming the isolation layer 130 includes: forming an initial isolation layer 160 covering the sidewalls and top surfaces of the gate stack layer 120 and the surface of the substrate 100; patterning the initial isolation layer 160; and removing the isolation layer 160.
  • the initial isolation layer 160 is located on the second sidewall surface of the gate stack layer 120
  • the remaining initial isolation layer 160 is located on the first sidewall surface and the top surface of the gate stack layer 120 as the isolation layer 130 .
  • a method of forming the initial isolation layer 160 includes: forming a first initial isolation layer 161, the first initial isolation layer 161 covering the first sidewall and the second sidewall of the gate stack layer 120; A second initial isolation layer 162 is formed, and the second initial isolation layer 162 covers the sidewalls of the first initial isolation layer 161 and the top surface of the gate stack layer 120; a third initial isolation layer 163 is formed, and the third initial isolation layer 163 covers the first initial isolation layer 161. The top surface of the second initial isolation layer 162.
  • the material of the third initial isolation layer 163 and the first initial isolation layer 161 can be the same, which are nitrides, and the material of the second initial isolation layer 162 can be oxide, thus forming a NON structure.
  • the second initial isolation layer 162 is an oxide layer, which can improve the insulation performance between the first initial isolation layer 162 and the third initial isolation layer 163.
  • the shape of the second initial isolation layer 162 formed The morphology of the second initial isolation layer 162 is improved by forming the first initial isolation layer 161 and the third initial isolation layer 163 made of a nitride layer.
  • the initial isolation layer 160 can also be used as a mask for light doping and heavy doping processes of the substrate 100, thereby controlling the areas of the lightly doped region and the heavily doped region.
  • the initial isolation layer 160 is patterned (refer to FIG. 3 ), the initial isolation layer 160 located on the second sidewall surface of the gate stack layer 120 is removed, and the remaining portion is located on the first sidewall surface of the gate stack layer 120 and The initial isolation layer 160 on the top surface serves as the isolation layer 130 . Patterning the initial isolation layer 160 (see FIG. 3 ) provides process space for subsequent formation of dielectric layers and contact structures.
  • the portion of the patterned initial isolation layer 160 includes a portion of the initial isolation layer 160 (refer to FIG. 3 ) on the top surface of the gate stack layer 120 and the second sidewall of the gate stack layer 120 .
  • the initial isolation layer 160 (refer to FIG. 3); in other embodiments, the portion of the patterned initial isolation layer 160 (refer to FIG. 3) only includes the initial isolation layer 160 (refer to the second sidewall of the gate stack layer 120). Refer to Figure 3).
  • the process of patterning the initial isolation layer 160 also includes patterning a portion of the protective layer 124 to expose a portion of the second conductive layer 123, thereby providing space for the subsequently formed dielectric layer and contact structure portions to be located.
  • a process basis is provided on the second conductive layer.
  • patterning the initial isolation layer includes: forming a groove 170 , the groove 170 exposes at least the second sidewall and part of the top surface of the gate stack layer 120 , and the groove 170 also exposes the substrate. 100.
  • a process basis can be provided for the subsequent formation of the dielectric layer and the contact structure partially on the second conductive layer.
  • By controlling the position of the groove 170 and The area can control the position and area of the subsequently formed dielectric layer and contact structure.
  • the groove may also expose only the second sidewall of the gate stack layer and part of the substrate.
  • a dielectric layer 150 is formed.
  • the dielectric layer 150 at least covers the second sidewall of the gate stack layer 120 .
  • the first sidewall and the second sidewall are arranged oppositely.
  • the thickness of the dielectric layer 150 is smaller than that of the isolation layer 130 . thickness.
  • forming the dielectric layer 150 includes: depositing dielectric material on the sidewalls and bottom of the groove 170 , removing the dielectric material located at the bottom of the groove 170 , and forming a dielectric layer covering the second sidewall of the gate stack layer 120 150.
  • a dielectric material is also deposited on the exposed top surface of the second conductive layer 123, and the dielectric layer 150 is formed on the top surface of the second conductive layer 123 to provide a process for subsequent formation of a contact structure above the gate stack layer 120. basis to avoid direct contact between the contact structure formed on the top surface of the second conductive layer 123 and the second conductive layer 123 .
  • the method of forming the dielectric layer 150 may be to form the dielectric layer 150 on the sidewalls of the groove 170 through atomic layer deposition technology.
  • the atomic layer deposition technology has excellent thickness control performance, and the formed dielectric layer 150 The thickness is relatively uniform.
  • the method before removing the dielectric material at the bottom of the groove 170 , the method further includes: performing ion implantation on the substrate 100 at the bottom of the groove 170 .
  • the source and drain of the MOS transistor are formed by ion implantation into the substrate 100 at the bottom of the groove 170 .
  • the type of ions to be implanted when implanting ions into the substrate 100, can be controlled according to the type of MOS transistor to be formed.
  • the method of forming the dielectric layer 150 may include: controlling the thickness of the dielectric layer 150 to be smaller than the thickness of the gate oxide layer 110. It can be understood that the thinner the thickness, the lower the corresponding breakdown difficulty, that is, the easier it is for breakdown phenomenon to occur there. Therefore, by setting the thickness of the dielectric layer 150 to be smaller than the thickness of the gate oxide layer 110, the efficiency of the dielectric layer can be improved. The possibility of breakdown on the semiconductor structure 150 can reduce the difficulty of breakdown of the semiconductor structure by breaking down the dielectric layer 150 so that the electrical signal of the gate stack layer 120 is transmitted to the contact structure 140 .
  • a contact structure 140 is formed, the contact structure 140 is at least located on the surface of the substrate 100 , and the contact structure 140 is in contact with the surface of the dielectric layer 150 .
  • forming the contact structure 140 may include: forming a contact layer 141 at the bottom of the groove 170 (see FIG. 6 ), the contact layer 141 being electrically connected to the substrate 100 ; forming a barrier layer 142 , the barrier layer 142 being located on the dielectric layer 150 surface and the top surface of the contact layer 141; a conductive layer 143 is formed, and the conductive layer 143 fills the groove 170.
  • the Schottky barrier between the contact structure 140 and the substrate 100 can be reduced, thereby reducing the contact resistance between the contact structure 140 and the substrate 100, thereby improving the response speed of the semiconductor structure, and the contact layer 141
  • the material is metal silicide.
  • the lattice of metal silicide and the silicon lattice can match each other very well, which can also reduce defects between the contact layer 141 and the substrate 100.
  • the contact resistance between the contact structure 140 and the substrate 100 and defects between the two can be reduced, thereby improving the performance of the semiconductor structure.
  • the metal ions in the conductive layer 143 can be prevented from diffusing into the contact layer 141 when ion diffusion occurs.
  • the barrier layer 142 can prevent the ion diffusion of the conductive layer 143 from contaminating the contact layer 141, thereby improving the resistance of the contact layer 141. stability, thereby improving the reliability of the semiconductor structure.
  • the conductive performance of the contact structure 140 can be improved, the transmission speed of electrical signals of the contact structure 140 can be improved, and the performance of the semiconductor structure can be improved.
  • the contact structure 140 overlaps with the projection of the gate stack layer 120 on the surface of the substrate 100 , and the width of the overlapping portion is less than or equal to 0.1 ⁇ 0.5 of the width of the gate stack layer 120 . The more overlapping parts there are, the larger the breakdown area between the corresponding gate stack layer 120 and the contact structure 140 will be.
  • the protective layer 124 and the isolation layer 130 can provide better protection effects to the first conductive layer 121 , the middle layer 122 and the second conductive layer 123 by setting the width of the overlapping portion to be less than or equal to the width of the gate stack layer 120 0.1 to 0.5 can increase the breakdown area between the gate stack layer 120 and the contact structure 140 while providing a certain protection effect.
  • the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure by forming a dielectric layer 150 on the second sidewall of the gate stack layer 120, and the thickness of the dielectric layer 150 is smaller than the thickness of the isolation layer 130, and then forming the dielectric layer 150 with the dielectric layer 130.
  • the contact structure 140 in surface contact with the layer 150 is arranged close to the gate stack layer 120 and the thickness of the dielectric layer 150 between the gate stack layer 120 and the contact structure 140 is reduced, thereby causing breakdown of the semiconductor structure.
  • the path is from the gate stack layer 120 through the dielectric layer 150 to the contact structure 140.
  • the difficulty of breakdown of the entire semiconductor structure can be reduced, and the transmission path of the entire electrical signal transmission can be reduced. , thereby reducing the electrical signal loss during the transmission process of electrical signals, thereby improving the sensitivity of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及制作方法，半导体结构包括：基底(100)，以及位于基底(100)表面的栅氧层(110)；栅极堆叠层(120)，栅极堆叠层(120)位于栅氧层(110)的表面；隔离层(130)，隔离层(130)至少覆盖栅极堆叠层(120)的第一侧壁；接触结构(140)，接触结构(140)至少位于基底(100)的表面；介质层(150)，介质层(150)至少位于接触结构(140)与栅极堆叠层(120)的第二侧壁之间，第一侧壁与第二侧壁相对设置，介质层(150)的厚度小于隔离层(130)的厚度。至少可以降低熔丝结构的击穿难度。

Description

一种半导体结构及其制作方法
交叉引用
本公开要求于2022年03月22日递交的名称为“一种半导体结构及其制作方法”、申请号为202210304778.6的中国专利申请的优先权，其通过引用被全部并入本公开。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及其制作方法。
背景技术
在集成电路制造领域中，电熔丝(efuse)是指在集成电路中，电阻可以发生大幅度改变(由低组态向高阻态改变)或者可以熔断的连接线。
电熔丝的主要用途包括：(1)用于启动冗余电路来代替同晶片上有缺陷的电路，从而有效提高制程良率。所述用途中，电熔丝连接集成电路中的冗余电路，一旦检测发现集成电路具有缺陷，就利用电熔丝修复或者取代有缺陷的电路；(2)用于集成电路程序化功能。实现所述功能时，先将金属互连、器件阵列以及程序化电路(包括电熔丝器件)在芯片上加工好，然后由外部进行数据输入，即通过程序化电路将标准芯片制作成独特的各式芯片。电熔丝在集成电路程序化功能中可以大大节约芯片研发和制作成本，因而大量应用于可编程只读存储器(Programmable Read Only Memory，PROM)上。在集成电路程序化过程中，通过较高电压熔断电熔丝产生断路来完成信息“1”的写入，而未断开的电熔丝保持连接状态，即为状态“0”。
目前，存在电熔丝难以熔断的问题。
发明内容
本公开实施例提供一种半导体结构及制作方法，至少可以降低电熔丝的熔断难度。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：基底，以及位于所述基底表面的栅氧层；栅极堆叠层，所述栅极堆叠层位于所述栅氧层的表面；隔离层，所述隔离层至少覆盖所述栅极堆叠层的第一侧 壁；接触结构，所述接触结构至少位于所述基底的表面；介质层，所述介质层至少位于所述接触结构与所述栅极堆叠层的第二侧壁之间，所述第一侧壁与所述第二侧壁相对设置，所述介质层的厚度小于所述隔离层的厚度。
在一些实施例中，所述隔离层还位于所述栅极堆叠层的部分顶面；部分所述接触结构位于所述栅极堆叠层的上方。
在一些实施例中，所述接触结构与所述栅极堆叠层在所述基底表面的投影相重叠，重叠部分的宽度小于或等于所述栅极堆叠层宽度的0.1～0.5。
在一些实施例中，所述介质层的厚度小于所述栅氧层的厚度。
在一些实施例中，部分所述接触结构位于所述基底的有源区内。
在一些实施例中，所述接触结构包括：接触层、阻挡层及导电层，所述阻挡层位于所述接触层与所述导电层之间，且所述接触层位于所述有源区内。
在一些实施例中，所述介质层的厚度小于或等于3nm。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供基底，在所述基底表面形成栅氧层，在所述栅氧层上形成栅极堆叠层；形成隔离层，所述隔离层至少覆盖所述栅极堆叠层的第一侧壁；形成介质层，所述介质层至少覆盖所述栅极堆叠层的第二侧壁，所述第一侧壁与所述第二侧壁相对设置，所述介质层的厚度小于所述隔离层的厚度；形成接触结构，所述接触结构至少位于所述基底的表面，且所述接触结构与所述介质层的表面接触。
在一些实施例中，形成所述隔离层的方法包括形成所述隔离层的方法包括：形成初始隔离层，所述初始隔离层覆盖所述栅极堆叠层的侧壁和顶面以及所述基底的表面；图形化所述初始隔离层，去除位于所述栅极堆叠层的所述第二侧壁表面的所述初始隔离层，剩余的位于所述栅极堆叠层的所述第一侧壁表面和顶面的所述初始隔离层作为所述隔离层。
在一些实施例中，图形化所述初始隔离层，包括：形成凹槽，所述凹槽至少暴露所述栅极堆叠层的第二侧壁及部分顶面，所述凹槽还暴露所述基底。
在一些实施例中，形成所述介质层，包括：在所述凹槽的侧壁和底部沉积介质材料，去除位于所述凹槽底部的介质材料，形成覆盖所述栅极堆叠层第 二侧壁的介质层。
在一些实施例中，在去除位于所述凹槽底部的介质材料之前，还包括：对所述凹槽底部的所述基底进行离子注入。
在一些实施例中，形成所述接触结构，包括：在所述凹槽底部形成接触层，所述接触层与所述基底电连接；形成阻挡层，所述阻挡层位于所述介质层的表面和所述接触层的顶面；形成导电层，所述导电层填充满所述凹槽。
在一些实施例中，形成所述介质层的方法包括：控制所述介质层的厚度小于所述栅氧层的厚度。
在一些实施例中，所述接触结构与所述栅极堆叠层在所述基底表面的投影相重叠，重叠部分的宽度小于或等于所述栅极堆叠层宽度的0.1～0.5。
本公开实施例提供的技术方案至少具有以下优点：通过基底、栅氧层、栅极堆叠层、接触结构及介质层构成电熔丝，通过将接触结构临近栅极堆叠层设置，当栅极堆叠层上的电压足够大，电熔丝的击穿路径变为从栅极堆叠层经由介质层到接触结构，从而可以降低整个半导体结构的击穿难度，通过设置介质层的厚度小于隔离层的厚度可以降低击穿栅极堆叠层及接触结构之间的接触路径，从而降低整个半导体结构的击穿难度。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一实施例提供的一种半导体结构的剖视图；
图2为本公开一实施例提供的另一种半导体结构的剖视图；
图3至图7为本公开另一实施例提供的一种半导体结构的制作方法各步 骤对应的结构示意图。
具体实施方式
本公开实施提供一种半导体结构，通过将接触结构临近栅极堆叠层设置，并将栅极堆叠层与接触结构之间的介质层的厚度降低，从而使半导体结构的击穿路径由栅极堆叠层经过栅氧层及基底到接触结构变为由栅极堆叠层经过介质层到接触结构，通过将击穿栅氧层导致半导体结构击穿变为击穿介质层导致半导体结构击穿可以降低整个半导体结构的击穿难度，且可以减小整个电信号传递的传递路径，从而降低电信号在传递过程中的电信号损失，进而提高半导体结构的灵敏度。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
参考图1及图2，图1为本公开一实施例提供的一种半导体结构的剖视图，图2为本公开以实施例提供的另一种半导体结构的剖视图。
具体的，参考图1及图2，半导体结构包括：基底100，以及位于基底100表面的栅氧层110；栅极堆叠层120，栅极堆叠层120位于栅氧层110的表面；隔离层130，隔离层130至少覆盖栅极堆叠层120的第一侧壁；接触结构140，接触结构140至少位于基底100的表面；介质层150，介质层150至少位于接触结构140与栅极堆叠层120的第二侧壁之间，第一侧壁与第二侧壁相对设置，介质层150的厚度小于隔离层130的厚度。
通过基底100、栅氧层110、栅极堆叠层120、接触结构140及介质层150构成电熔丝，通过提供给栅极堆叠层120足够的电压可以使栅极堆叠层120与接触结构140之间的介质层150被击穿，从而在介质层150内形成一个导电通路，以使栅极堆叠层120与接触结构140电连接，通过接触结构140将半导体结构的信号导出，通过将半导体结构的击穿路径设置为从栅极堆叠层120经过介质层150到接触结构140可以降低整个半导体及结构的击穿难度，且可以减小整个电信号传递的传递路径，从而降低电信号在传递过程中的电信号损失，进而提高半导体结构的灵敏度。
在一些实施例中，基底100的材料可以是硅、锗或者锗化硅等材料，且还可以在基底100的材料中进行掺杂，以基底100的材料是硅为例，在基底 100中掺杂微量的三价元素，例如：硼、铟、镓或铝等，从而可以形成P型基底；同理，在基底100中掺杂微量的五价元素，例如：磷、锑、砷等，从而可以形成N型基底，基底100掺杂元素的选择可以根据实际的需求及产品性能等方面进行考量，本公开实施例不对基底100的材料及掺杂的元素进行限制。
在一些实施例中，栅氧层110是用于避免栅极堆叠层120与基底100直接接触，栅氧层110击穿的原理为：当栅氧层110上下层界面间被施加较高电压时，栅氧层110中的缺陷就会形成一个个电子阱，随机分布在栅氧层110中间。在栅氧层110电场的作用下每个电子阱都会具备俘获电子的能力，在高电场的作用下电子阱俘获电子的区域可能相互重叠，形成了一条栅氧层110电流通道，那么这条通道就成为一条发生潜在击穿的通道。随着栅极堆叠层120电流的不断增大，栅氧层110通路形成电流通道，栅氧层110性能缓慢下降。当电流通过电流通道进一步放电，栅氧层110被击穿。由于电子阱在栅氧层110的分布是随机的，当栅氧层110越薄，则需要形成通路的电子阱数目就相对越少，因此薄的栅氧层110比厚的栅氧层110更容易发生击穿。
在一些实施例中，栅极堆叠层120可以是四层结构，包括第一导电层121、中间层122、第二导电层123及保护层124，第一导电层121位于栅氧层110的顶面，中间层122位于第一导电层121与第二导电层123之间，保护层124至少位于第二导电层123的顶面。在另一些实施例中，栅极堆叠层120还可以是单层结构，在其他实施例中，栅极堆叠层还可以是其他层数的进行堆叠形成，本公开实施例不对栅极堆叠层120的层数进行限制。
以栅极堆叠层120为四层结构为例，第一导电层121的材料可以是半导体材料，例如多晶硅；中间层122的材料可以是氮化钛或者氮化镓等；第二导电层123的材料可以是导电性能较好的金属材料，例如钨金属；保护层124的材料可以是材质较硬的绝缘材料，例如氮化硅。
以第一导电层121的材料为多晶硅为例，通过设置第一导电层121的材料为多晶硅可以在栅极堆叠层120与基底100出现电信号传递的过程中，使得电信号从半导体材料传递到半导体材料，从而避免电信号从半导体材料直接传递到其他材料导致传递电信号的过程出现异常，进而提高半导体结构信号传递的稳定性，提高半导体结构的可靠性。
以中间层122的材料为氮化钛为例，通过设置中间层122将第一导电层 121与第二导电层123之间隔离，从而避免第二导电层123的金属离子在发生离子扩散的时候金属离子扩散至第一导电层121内，通过中间层122避免第二导电层123的离子扩散污染第一导电层121，从而提高第一导电层121的稳定性，进而提高半导体结构的可靠性。
以第二导电层123的材料为钨金属为例，钨金属的导电性能相较于多晶硅等半导体材料的导电性能而言，钨金属的导电性能较高，通过设置第二导电层123的材料为金属材料可以提高栅极堆叠层120的导电性能，提高栅极堆叠层120的电信号的传递速度，进而提高半导体结构的性能。
以保护层124的材料为氮化硅为例，在一些实施例中，保护层124覆盖第二导电层123的顶面，通过设置保护层124可以在半导体结构受到外界压力的时候分担第一导电层121、中间层122及第二导电层123的应力作用，从而降低第一导电层121、中间层122及第二导电层123上受到的应力，进而保护第一导电层121、中间层122及第二导电层123，进而提高半导体结构的可靠性。
在一些实施例中，隔离层130可以是多层结构堆叠而成，隔离层130可以包括第一隔离层131、第二隔离层132及第三隔离层133，第一隔离层131至少覆盖在栅极堆叠层120的第一侧壁，第二隔离层132位于第一隔离层131与第三隔离层133之间；在另一些实施例中，隔离层还可以是单层结构，本公开实施例不对隔离层的层数进行限制。
以隔离层130为三层结构为例，第一隔离层131与第三隔离层133的材料可以相同，可以都为氮化硅，第二隔离层132的材料可以是氧化硅。
在一些实施例中，隔离层130为NON(Nitride-Oxide-Nitride)结构即氮化层-氧化层-氮化层结构，通过设置第二隔离层132可以提高第一隔离层131与第三隔离层133之间的绝缘性能，由于第二隔离层132的材质较软，形成的形貌较差，故通过形成材质为氮化层的第一隔离层131与第三隔离层133以提高形成第二隔离层132的形貌。
在另一些实施例中，在形成隔离层130后还会对基底100进行轻掺杂及重掺杂，由于轻掺杂与重掺杂之间需要保留一定的空间差，通过形成第一隔离层131可以作为轻掺杂的掩膜，通过形成第三隔离层133可以作为重掺杂工艺的掩膜，从而便于后续对基底100进行掺杂工艺。
在一些实施例中，接触结构140可以是多层结构堆叠形成，接触结构140可以包括：接触层141、阻挡层142及导电层143，接触层141位于基底100 的表面，阻挡层142位于接触层141与导电层143之间；在另一些实施例中，接触结构还可以是单层结构；本公开实施例不对接触结构140的层数进行限制。
以接触结构140的结构为三层结构为例，接触层141的材料可以是金属与半导体材料的化合物或者对半导体材料进行金属掺杂，例如硅化钴，阻挡层142的材料可以是氮化钛或者氮化镓等，导电层143的材料可以是金属材料，例如钨金属。
通过设置接触层141可以降低接触结构140与基底100之间的肖特基势垒，从而降低了接触结构140与基底100之间的接触电阻，从而可以提高半导体结构的响应速度。
以接触层141的材料为硅化钴为例，硅化钴的晶格与硅晶格能很好的相互匹配，从而还可以减少接触层141与基底100之间的缺陷，相较于直接在基底100表面形成金属作为接触结构，通过先形成接触层141可以减少接触结构140与基底100之间的接触电阻及两者之间的缺陷，从而可以提高半导体结构的性能。在另一些实施例中，接触层141的材料还可以是硅化镍等金属硅化物。
通过形成阻挡层142可以避免导电层143的金属离子在发生离子扩散的时候金属离子扩散至接触层141内，通过阻挡层142避免导电层143的离子扩散污染接触层141，从而提高接触层141的稳定性，进而提高半导体结构的可靠性。在一些实施例中阻挡层142的材料可以是氮化钛、氮化钽或硅化钽中的至少一种。
在一些实施例中，导电层143的材料可以为钨金属，钨金属的导电性能相较于多晶硅等半导体材料的导电性能而言，钨金属的导电性能较高，通过设置导电层143的材料为金属材料可以提高接触结构140的导电性能，提高接触结构140的电信号的传递速度，进而提高半导体结构的性能。在另一些实施例中，导电层的材料还可以钼等金属，或者多晶硅等半导体材料。
参考图2，在一些实施例中，隔离层130位于栅极堆叠层120的部分顶面；部分接触结构140位于栅极堆叠层120的上方。通过将隔离层130设置在栅极堆叠层120的部分顶面可以为接触结构140留出空间，从而使得部分接触结构140位于栅极堆叠层120的上方，从而增加栅极堆叠层120与接触结构140之间可击穿的面积，可击穿面积包括第一导电层121、中间层122及第二导电层123的侧壁与接触结构140正对的面积，可击穿面积还包括第二导 电层123的顶面与接触结构140正对的面积，通过增加可击穿面积的大小从而降低半导体结构的击穿难度，通过使得半导体结构的击穿路径为从栅极堆叠层120到介质层150再到接触结构140，可以降低半导体结构的击穿难度，且将接触结构140设置于栅极堆叠层120的上方可以减小部分位于基底100表面的接触结构140的体积，进而可以缩小整个半导体结构的体积。
参考图2，在一些实施例中，接触结构140与栅极堆叠层120在基底100表面的投影相重叠，重叠部分的宽度小于或等于栅极堆叠层120宽度的0.1～0.5。可以理解的是，重叠的部分越多，相应的栅极堆叠层120与接触结构140之间可击穿的面积也就越大，然而重叠的部分越多，相应的位于第二导电层123上的保护层124及隔离层130也就越少，相应的，保护层124及隔离层130可以提供给第一导电层121、中间层122及第二导电层123的保护效果也就越差；重叠的部分越少，保护层124及隔离层130可以提供给第一导电层121、中间层122及第二导电层123的保护效果也就越好，通过将重叠部分的宽度设置为小于或等于栅极堆叠层120宽度的0.1～0.5，在增加栅极堆叠层120与接触结构140之间可击穿的面积的同时提供一定的保护效果。
在一些实施例中，部分接触结构140位于基底100的有源区内。具体的，通过将部分接触结构140设置在基底100内从而确保接触结构140及基底100的电连接，进而确保通过接触结构140将基底100及栅极堆叠层120的电信号导出。
在一些实施例中，接触层141位于有源区内。具体的，在一些实施例中，接触层141的顶面可以与基底100的顶面齐平，或者接触层141的顶面可以高于基底100的顶面，即，阻挡层142的底面与基底100的顶面齐平或者阻挡层142的底面高于基底100的顶面；在另一些实施例中，接触层141的顶面可以低于基底100的顶面，即，阻挡层142的底面低于基底100的顶面。通过设置接触层141位于基底100内从而确保接触结构140及基底100的电连接，进而提高半导体结构的稳定性。
需要说明的是，齐平可以是接触层141的顶面与基底100的顶面完全齐平，也可以是接触层141的顶面与基底100的顶面的高度差在1nm内，当接触层141的顶面与基底100的顶面的高度差在1nm内，也可以视为接触层141的顶面可以与基底100的顶面齐平。
参考图1，在一些实施例中，隔离层130还可以覆盖栅极堆叠层120的整 个顶面。也就是说，接触结构140与栅极堆叠层120的第二侧壁相对设置，即，栅极堆叠层120在基底100表面的投影与接触结构140在基底100表面的投影相邻接。
介质层150具有相对的侧壁，其中介质层150的一侧壁与栅极堆叠层120相接触，相对的另一侧壁与接触结构140相接触。
当提供给栅极堆叠层120足够的电压时，栅极堆叠层120与接触结构140之间的电场会使介质层150之间的缺陷具备俘获电子的能力，在高电场的作用下电子阱俘获电子的区域可能相互重叠，从而形成了一条介质层150电流通道，随着栅极堆叠层120的电流不断增大，介质层150上的电流通道导通，从而形成击穿，从而使栅极堆叠层120的电信号传导给接触结构140，进而通过接触结构140将半导体结构的电信号导出。
介质层150用于隔离接触结构140及栅极堆叠层120，从而避免接触结构140及栅极堆叠层120直接接触，通过将介质层150击穿从而使得栅极堆叠层120与接触结构140导通，从而降低电熔丝的击穿难度，通过设置介质层150的厚度小于隔离层130的厚度可以降低介质层150的击穿难度，从而提高半导体结构的击穿灵敏度，需要说明的是，击穿灵敏度即发生击穿的难度，击穿灵敏度越高击穿难度也就越低，击穿灵敏度越低击穿难度也就越高。
在一些实施例中，介质层150的材料可以与栅氧层110的材料相同，都可以是氧化硅，在另一实施例中，介质层的材料也可以与栅氧层的材料不同，介质层的材料还可以是其他更容易被击穿的材料，从而可以降低半导体结构的击穿难度。
在一些实施例中，介质层150的厚度可以小于栅氧层110的厚度，可以理解的是，厚度越薄，相应的击穿难度也就越低，即越容易在该处发生击穿现象，故通过设置介质层150的厚度小于栅氧层110的厚度可以提高在介质层150上的击穿的可能性，从而使得半导体结构的击穿路径为由栅极堆叠层120经过介质层150到接触结构140，进而降低半导体结构的击穿难度。
需要说明的是，参考图1，介质层150的厚度即在栅极堆叠层120朝向接触结构140的方向上，介质层150的尺寸；参考图2，位于第一导电层121、中间层122及第二导电层123侧壁上的介质层150的厚度为垂直于第一导电层121朝向中间层122方向上介质层150的尺寸；位于第二导电层123上方的介质层150的厚度为第一导电层121朝向中间层122方向上介质层150的尺寸。
在一些实施例中，介质层150的厚度小于或等于3nm。可以理解的是，介质层150的厚度越小，相应的在介质层150上发生击穿的难度也就越低，且介质层150的厚度越小击穿介质层所需的电流相对也减小，通过设置介质层150的厚度小于3nm可以提高在介质层150上的击穿的可能性，通过击穿介质层150使得栅极堆叠层120的电信号传给接触结构140，可以降低半导体结构的击穿难度。在一些实施例中，半导体结构还包括填充层180，填充层180用于将半导体结构填平，且可以通过图形化填充层180以在半导体结构上形成其他结构，填充层的材料可以是氧化物。
本公开实施例通过提供一种将接触结构140临近栅极堆叠层120设置，并将栅极堆叠层120与接触结构140之间的介质层150的厚度降低，从而使半导体结构的击穿路径为由栅极堆叠层120经过介质层150到接触结构140，通过控制击穿介质层150导致半导体结构击穿可以降低整个半导体结构的击穿难度，且可以减小整个电信号传递的传递路径，从而降低电信号在传递过程中的电信号损失，进而提高半导体结构的性能。
本公开另一实施例还提供一种半导体结构的制作方法，该半导体结构的制作方法可用于形成前述实施例的半导体结构，相同或者相应的部分可以参考图1及图2所述的实施例，以下将不再赘述。以下将结合附图对本公开另一实施例提供的半导体结构制作方法进行详细说明。图3至图7为本公开一实施例提供的一种半导体结构的制造方法各步骤对应的结构示意图。
参考图3及图4，提供基底100，在基底100表面形成栅氧层110，在栅氧层110上形成栅极堆叠层120；形成隔离层130，隔离层130至少覆盖栅极堆叠层120的第一侧壁。
具体的，在一些实施例中，栅极堆叠层120可以是四层结构，包括第一导电层121、中间层122、第二导电层123及保护层124，第一导电层121位于栅氧层110的顶面，中间层122位于第一导电层121与第二导电层123之间，保护层124位于第二导电层123的顶面。在另一些实施例中，栅极堆叠层120还可以是单层结构，在其他实施例中，栅极堆叠层还可以是其他层数的进行堆叠形成。
在一些实施例中，隔离层130可以包括第一隔离层131、第二隔离层132及第三隔离层133，第一隔离层131至少覆盖在栅极堆叠层120的第一侧壁，第二隔离层132位于第一隔离层131与第三隔离层133之间；在另一些实施例中，隔离层还可以是单层结构。
在一些实施例中，形成隔离层130的方法包括：形成初始隔离层160，初始隔离层160覆盖栅极堆叠层120的侧壁和顶面以及基底100的表面；图形化初始隔离层160，去除位于栅极堆叠层120的第二侧壁表面的初始隔离层160，剩余的位于栅极堆叠层120的第一侧壁表面和顶面的初始隔离层160作为隔离层130。
参考图3，在一些实施例中，形成初始隔离层160的方法包括：形成第一初始隔离层161，第一初始隔离层161覆盖栅极堆叠层120的第一侧壁及第二侧壁；形成第二初始隔离层162，第二初始隔离层162覆盖第一初始隔离层161的侧壁及栅极堆叠层120的顶面；形成第三初始隔离层163，第三初始隔离层163覆盖第二初始隔离层162的顶面。
在一些实施例中，第三初始隔离层163的材料与第一初始隔离层161的材料可以相同，都为氮化物，第二初始隔离层162的材料可以是氧化物，如此便形成了NON结构，第二初始隔离层162为氧化层可以提高第一初始隔离层162及第三初始隔离层163之间的绝缘性能，然而由于氧化层的材料较软，形成的第二初始隔离层162的形貌较差，故通过形成材质为氮化层的第一初始隔离层161及第三初始隔离层163以提高形成第二初始隔离层162的形貌。
在另一些实施例中，初始隔离层160还可以作为对基底100轻掺杂及重掺杂工艺的掩膜，从而控制轻掺杂区与重掺杂区的面积。
参考图4，图形化初始隔离层160(参考图3)，去除位于栅极堆叠层120的第二侧壁表面的初始隔离层160，剩余的位于栅极堆叠层120的第一侧壁表面和顶面的初始隔离层160作为隔离层130。通过图形化所述初始隔离层160(参考图3)为后续形成介质层及接触结构提供工艺空间。
且通过控制图形化初始隔离层160(参考图3)及保护层124的面积及位置可以控制后续形成的介质层及接触结构的总面积及相应位置。在一些实施例中，图形化初始隔离层160(参考图3)的部分包括栅极堆叠层120的部分顶面的初始隔离层160(参考图3)及位于栅极堆叠层120第二侧壁的初始隔离层160(参考图3)；在另一些实施例中，图形化初始隔离层160(参考图3)的部分仅包括位于栅极堆叠层120第二侧壁上的初始隔离层160(参考图3)。
在一些实施例中，图形化初始隔离层160(参考图3)的过程中还包括图形化部分保护层124，以暴露部分第二导电层123，从而为后续形成的介质 层及接触结构部分位于第二导电层上提供工艺基础。
在一些实施例中，图形化初始隔离层(参考图3)，包括：形成凹槽170，凹槽170至少暴露栅极堆叠层120的第二侧壁及部分顶面，凹槽170还暴露基底100。通过形成暴露栅极堆叠层120的第二侧壁及部分顶面的凹槽170可以为后续形成的介质层及接触结构部分位于第二导电层上提供工艺基础，通过控制凹槽170的位置及面积可以控制后续形成的介质层及接触结构的位置及面积。
在另一些实施例中，凹槽还可以只暴露栅极堆叠层的第二侧壁及部分基底。
参考图5及图6，形成介质层150，介质层150至少覆盖栅极堆叠层120的第二侧壁，第一侧壁与第二侧壁相对设置，介质层150的厚度小于隔离层130的厚度。
在一些实施例中，形成介质层150，包括：在凹槽170的侧壁和底部沉积介质材料，去除位于凹槽170底部的介质材料，形成覆盖栅极堆叠层120第二侧壁的介质层150。通过设置介质层150的厚度小于隔离层130的厚度，且介质层150与栅极堆叠层120相邻设置，可以使得半导体结构的击穿路径为从栅极堆叠层120到介质层150再到接触结构，可以降低介质层150的击穿难度，进而提高半导体结构的性能。
在一些实施例中，还在第二导电层123暴露的顶面沉积介质材料，通过在第二导电层123的顶面形成介质层150为后续在栅极堆叠层120的上方形成接触结构提供工艺基础，避免在第二导电层123顶面形成的接触结构与第二导电层123直接接触。
在一些实施例中，形成介质层150的方法可以是通过原子层沉积技术以在凹槽170的侧壁上形成介质层150，原子层沉积技术具有优异的厚度控制性能，且形成的介质层150的厚度较为均匀。
在一些实施例中，在去除位于凹槽170底部的介质材料之前，还包括：对凹槽170底部的基底100进行离子注入。通过对凹槽170底部的基底100进行离子注入以形成MOS晶体管的源极及漏极。
在一些实施例中向基底100内进行离子注入的时候可以根据想要形成的MOS晶体管的类型，控制注入离子的类型。
在一些实施例中，形成介质层150的方法可以包括：控制介质层150的 厚度小于栅氧层110的厚度。可以理解的是，厚度越薄，相应的击穿难度也就越低，即越容易在该处发生击穿现象，故通过设置介质层150的厚度小于栅氧层110的厚度可以提高在介质层150上的击穿的可能性，通过击穿介质层150使得栅极堆叠层120的电信号传给接触结构140，可以降低半导体结构的击穿难度。
参考图7，形成接触结构140，接触结构140至少位于基底100的表面，且接触结构140与介质层150的表面接触。
在一些实施例中，形成接触结构140，可以包括：在凹槽170(参考图6)底部形成接触层141，接触层141与基底100电连接；形成阻挡层142，阻挡层142位于介质层150的表面和接触层141的顶面；形成导电层143，导电层143填充满凹槽170。
通过形成接触层141可以降低接触结构140与基底100之间的肖特基势垒，从而可以降低接触结构140与基底100之间的接触电阻，从而可以提高半导体结构的响应速度，且接触层141的材料为金属硅化物，金属硅化物的晶格与硅晶格能很好的相互匹配，从而还可以减少接触层141与基底100之间的缺陷，相较于直接在基底100表面形成金属作为接触结构，通过先形成接触层141可以减少接触结构140与基底100之间的接触电阻及两者之间的缺陷，从而可以提高半导体结构的性能。
通过形成阻挡层142可以避免导电层143的金属离子在发生离子扩散的时候金属离子扩散至接触层141内，通过阻挡层142避免导电层143的离子扩散污染接触层141，从而提高接触层141的稳定性，进而提高半导体结构的可靠性。
通过形成导电层143可以提高接触结构140的导电性能，提高接触结构140的电信号的传递速度，进而提高半导体结构的性能。
在一些实施例中接触结构140与栅极堆叠层120在基底100表面的投影相重叠，重叠部分的宽度小于或等于栅极堆叠层120宽度的0.1～0.5。重叠的部分越多，相应的栅极堆叠层120与接触结构140之间可击穿的面积也就越大，然而重叠的部分越多，相应的位于第二导电层123上的保护层124及隔离层130也就越少，相应的，保护层124及隔离层130可以提供给第一导电层121、中间层122及第二导电层123的保护效果也就越差；重叠的部分越少，保护层124及隔离层130可以提供给第一导电层121、中间层122及第二导电层123的保护效果也就越好，通过将重叠部分的宽度设置为小于或等 于栅极堆叠层120宽度的0.1～0.5在增加栅极堆叠层120与接触结构140之间可击穿的面积的同时提供一定的保护效果。
本公开实施例通过提供一种半导体结构的制作方法，通过在栅极堆叠层120的第二侧壁上形成介质层150，且介质层150的厚度小于隔离层130的厚度，然后再形成与介质层150表面接触的接触结构140，通过将接触结构140临近栅极堆叠层120设置，并将栅极堆叠层120与接触结构140之间的介质层150的厚度降低，从而使半导体结构的击穿路径为由栅极堆叠层120经过介质层150到接触结构140，通过控制击穿介质层150导致半导体结构击穿可以降低整个半导体结构的击穿难度，且可以减小整个电信号传递的传递路径，从而降低电信号在传递过程中的电信号损失，进而提高半导体结构的灵敏度。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (15)

  1. 一种半导体结构，包括：
    基底，以及位于所述基底表面的栅氧层；
    栅极堆叠层，所述栅极堆叠层位于所述栅氧层的表面；
    隔离层，所述隔离层至少覆盖所述栅极堆叠层的第一侧壁；
    接触结构，所述接触结构至少位于所述基底的表面；
    介质层，所述介质层至少位于所述接触结构与所述栅极堆叠层的第二侧壁之间，所述第一侧壁与所述第二侧壁相对设置，所述介质层的厚度小于所述隔离层的厚度。
  2. 根据权利要求1所述的半导体结构，其中，所述隔离层还位于所述栅极堆叠层的部分顶面；部分所述接触结构位于所述栅极堆叠层的上方。
  3. 根据权利要求2所述的半导体结构，其中，所述接触结构与所述栅极堆叠层在所述基底表面的投影相重叠，重叠部分的宽度小于或等于所述栅极堆叠层宽度的0.1～0.5。
  4. 根据权利要求1所述的半导体结构，其中，所述介质层的厚度小于所述栅氧层的厚度。
  5. 根据权利要求1所述的半导体结构，其中，部分所述接触结构位于所述基底的有源区内。
  6. 根据权利要求5所述的半导体结构，其中，所述接触结构包括：接触层、阻挡层及导电层，所述阻挡层位于所述接触层与所述导电层之间，且所述接触层位于所述有源区内。
  7. 根据权利要求1所述的半导体结构，其中，所述介质层的厚度小于或等于3nm。
  8. 一种半导体结构的制作方法，包括：
    提供基底，在所述基底表面形成栅氧层，在所述栅氧层上形成栅极堆叠层；
    形成隔离层，所述隔离层至少覆盖所述栅极堆叠层的第一侧壁；
    形成介质层，所述介质层至少覆盖所述栅极堆叠层的第二侧壁，所述第一侧壁与所述第二侧壁相对设置，所述介质层的厚度小于所述隔离层的厚度；
    形成接触结构，所述接触结构至少位于所述基底的表面，且所述接触结构与 所述介质层的表面接触。
  9. 根据权利要求8所述的半导体结构的制作方法，其中，形成所述隔离层的方法包括：
    形成初始隔离层，所述初始隔离层覆盖所述栅极堆叠层的侧壁和顶面以及所述基底的表面；
    图形化所述初始隔离层，去除位于所述栅极堆叠层的所述第二侧壁表面的所述初始隔离层，剩余的位于所述栅极堆叠层的所述第一侧壁表面和顶面的所述初始隔离层作为所述隔离层。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，图形化所述初始隔离层，包括：
    形成凹槽，所述凹槽至少暴露所述栅极堆叠层的第二侧壁及部分顶面，所述凹槽还暴露所述基底。
  11. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述介质层，包括：在所述凹槽的侧壁和底部沉积介质材料，去除位于所述凹槽底部的介质材料，形成覆盖所述栅极堆叠层第二侧壁的介质层。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，在去除位于所述凹槽底部的介质材料之前，还包括：对所述凹槽底部的所述基底进行离子注入。
  13. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述接触结构，包括：
    在所述凹槽底部形成接触层，所述接触层与所述基底电连接；
    形成阻挡层，所述阻挡层位于所述介质层的表面和所述接触层的顶面；
    形成导电层，所述导电层填充满所述凹槽。
  14. 根据权利要求10所述的半导体结构的制作方法，其中，形成所述介质层的方法包括：控制所述介质层的厚度小于所述栅氧层的厚度。
  15. 根据权利要求8所述的半导体结构的制作方法，其中，所述接触结构与所述栅极堆叠层在所述基底表面的投影相重叠，重叠部分的宽度小于或等于所述栅极堆叠层宽度的0.1～0.5。
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