WO2023173375A1 - 显示面板及其制作方法、以及显示装置 - Google Patents

显示面板及其制作方法、以及显示装置 Download PDF

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Publication number
WO2023173375A1
WO2023173375A1 PCT/CN2022/081525 CN2022081525W WO2023173375A1 WO 2023173375 A1 WO2023173375 A1 WO 2023173375A1 CN 2022081525 W CN2022081525 W CN 2022081525W WO 2023173375 A1 WO2023173375 A1 WO 2023173375A1
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sub
pixel
layer
electrode
main surface
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PCT/CN2022/081525
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English (en)
French (fr)
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李云龙
陈小川
卢鹏程
黄冠达
张大成
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京东方科技集团股份有限公司
云南创视界光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 云南创视界光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000486.1A priority Critical patent/CN117242918A/zh
Priority to PCT/CN2022/081525 priority patent/WO2023173375A1/zh
Publication of WO2023173375A1 publication Critical patent/WO2023173375A1/zh

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  • Embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device.
  • organic light-emitting diode (OLED) display panels Compared with traditional liquid crystal display (LCD) panels, organic light-emitting diode (OLED) display panels have the advantages of self-illumination, wide color gamut, high contrast, and thinness, making them widely used in mobile phones and tablet computers. and other fields, and is also widely used in flexible wearable fields such as smart watches.
  • OLED organic light-emitting diode
  • one sub-pixel usually includes multiple light-emitting devices connected in series.
  • At least one embodiment of the present disclosure provides a display panel, which includes a substrate, a plurality of sub-pixels and a pixel defining layer.
  • the substrate has a main surface; each of the plurality of sub-pixels includes a light-emitting device located on the main surface, the light-emitting device including a first electrode stacked in a direction perpendicular to the main surface and a charge generation layer, the charge generation layer is located on a side of the first electrode away from the substrate;
  • the pixel definition layer is located on the main surface and defines a plurality of opening areas, the plurality of opening areas and the A plurality of sub-pixels correspond one to one and expose at least part of the first electrode of the corresponding sub-pixel; the plurality of sub-pixels include adjacent first sub-pixels and second sub-pixels, and the first sub-pixel of the first sub-pixel has a one-to-one correspondence.
  • the pixel defining layer includes a first groove located in the space and recessed toward the main surface, the charge of the first sub-pixel
  • the generation layer and the charge generation layer of the second sub-pixel are spaced apart by the first groove;
  • the pixel definition layer includes a space between two adjacent sub-pixels that are different in the plurality of sub-pixels.
  • the plurality of first grooves in the plurality of first grooves have equal depths in a direction perpendicular to the main surface.
  • the pixel defining layer includes: a spacer part, a first stack part and a second stack part.
  • the spacing part is located in the gap between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel; the first stacking part is stacked on the first electrode in a direction perpendicular to the main surface.
  • a side of the first electrode of the sub-pixel away from the base substrate; a second stack portion is stacked on a side of the first electrode of the second sub-pixel away from the base substrate in a direction perpendicular to the main surface
  • the spacer portion includes the first groove.
  • the main surface has a middle portion located in the interval, the middle portion of the main surface is flat, and the interval portion is located in the middle of the main surface.
  • the first groove has a first bottom surface substantially parallel to the main surface;
  • the display panel also includes a floating charge generation layer, the floating charge generation layer is located in the first groove and located on the On the first bottom surface, the material is the same as the charge generation layer of the first sub-pixel and the charge generation layer of the second sub-pixel; the charge generation layer of the first sub-pixel is located on the first stack portion
  • the charge generation layer of the second sub-pixel is located on a side of the second stack part away from the main surface; the charge generation layer of the first sub-pixel is connected to the floating layer.
  • the charge generation layer is disconnected, and the charge generation layer of the second sub-pixel is disconnected from the floating charge generation layer.
  • the first stack part, the spacer part and the second stack part form a continuous integrated structure;
  • the spacer part of the pixel definition layer covers and directly Contacting the side surface of the first electrode of the first subpixel close to the first electrode of the second subpixel, the flat middle portion of the main surface, and the proximity of the first electrode of the second subpixel
  • the first stack portion covers and directly contacts a portion of the upper surface of the first electrode of the first sub-pixel away from the base substrate, and the first stack portion covers
  • the two stacked parts cover and directly contact a portion of the upper surface of the first electrode of the second sub-pixel away from the base substrate.
  • the edge of the orthographic projection of the charge generation layer of the first sub-pixel on the main surface close to the second sub-pixel is different from the floating charge.
  • the edges of the orthographic projection of the generation layer on the main surface close to the first sub-pixel are connected, and the orthographic projection of the charge generation layer of the second sub-pixel on the main surface is close to the first sub-pixel.
  • An edge of the pixel is connected to an edge of an orthographic projection of the floating charge generation layer on the main surface close to the second sub-pixel.
  • the first electrodes of the plurality of sub-pixels have the same thickness in a direction perpendicular to the main surface, and the first electrode of each of the plurality of sub-pixels has the same thickness.
  • the thickness of the first groove is not less than 450 ⁇ m, and the depth of the first groove in the direction perpendicular to the main surface is not less than 900 ⁇ m.
  • the thickness of the first electrode of the first sub-pixel in a direction perpendicular to the main surface is different from the thickness of the pixel defining layer in a direction perpendicular to the main surface.
  • the ratio of the thickness of the first electrode of the second sub-pixel in the direction perpendicular to the main surface and the thickness of the pixel defining layer in the direction perpendicular to the main surface are not less than 2.
  • the main surface has a middle portion located at the interval, the middle portion of the main surface has a second groove, and the interval portion of the pixel definition layer is at
  • the second groove has a fracture that runs through the partition, and the second groove and the first groove are connected through the fracture; the second groove has a groove that is substantially parallel to the main surface.
  • the display panel further includes a first etching barrier layer, the first etching barrier layer is located in the second groove and on the second bottom surface, and the first etching barrier layer
  • the material of the barrier layer is different from the material of the substrate and the material of the pixel definition layer;
  • the display panel also includes a floating charge generation layer located in the second groove and Located on the side of the first etching barrier layer away from the second bottom surface, the material is the same as the charge generation layer of the first sub-pixel and the charge generation layer of the second sub-pixel;
  • the first sub-pixel The charge generation layer of the pixel is located on a side of the first stack portion away from the main surface, and the charge generation layer of the second sub-pixel is located on a side of the second stack portion away from the main surface;
  • the charge generation layer of the first sub-pixel is disconnected from the floating charge generation layer, and the charge generation layer of the second sub-pixel is disconnected from the floating charge generation layer.
  • the first electrode of each of the plurality of sub-pixels includes a metal electrode layer and a transparent electrode layer stacked in a direction perpendicular to the main surface, and the transparent electrode layer
  • the electrode layer covers the metal electrode layer, and the first etching barrier layer and the transparent electrode layer are made of the same material and are arranged in the same layer.
  • the size of the second groove in a direction parallel to the main surface Gradually become larger, or first gradually increase and then gradually decrease.
  • the shape of the second groove along a cross section perpendicular to the main surface is a trapezoid or an irregular pattern, and the irregular pattern includes the
  • the main surface is substantially parallel to the bottom edge and the first side edge and the second side edge are opposite to each other and both intersect the bottom edge.
  • the first side edge is recessed in a direction away from the second side edge
  • the second side edge is recessed in a direction away from the second side edge.
  • the side is recessed in a direction away from the first side.
  • the display panel further includes a second etching barrier layer, the second etching barrier layer is located on the main surface and in the interval, and is connected with the The first electrode of the first sub-pixel and the first electrode of the second sub-pixel are made of the same material and are spaced in the same layer; the first groove is located in the second etching barrier layer away from the base substrate one side of the second etching barrier layer, and expose at least a portion of the upper surface of the second etching barrier layer away from the base substrate.
  • the size of the first groove in a direction parallel to the main surface gradually changes from a direction away from the main surface to close to the main surface. Large, or first gradually increase and then gradually decrease.
  • the light-emitting device includes a first light-emitting element that emits light of a first color and a second light-emitting element that emits light of a first color, and the first color and The second colors are different, and the charge generation layer is located between the first light-emitting element and the second light-emitting element and connects the first light-emitting element and the second light-emitting element.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display panel provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a display panel.
  • the manufacturing method includes: providing a substrate, wherein the substrate has a main surface; forming a plurality of sub-pixels on the substrate, wherein the Each of the plurality of sub-pixels includes a light-emitting device located on the main surface, the light-emitting device including a first electrode stacked in a direction perpendicular to the main surface and a charge generation layer located on a side of the first electrode away from the substrate; and forming a pixel defining layer, wherein the pixel defining layer is located on the main surface and defines a plurality of opening areas, wherein the plurality of openings The region corresponds to the plurality of sub-pixels one-to-one and exposes at least part of the first electrode of the corresponding sub-pixel; the plurality of sub-pixels include adjacent first sub-pixels and second sub-pixels, and the first There is a space between the first electrode of the sub-pixel and the first electrode of
  • the main surface has a middle portion located in the interval, and the middle portion of the main surface is flat;
  • the first groove is formed including: forming a first electrode of the first sub-pixel and a first electrode of the second sub-pixel on the main surface, wherein the first electrode of the first sub-pixel and the second sub-pixel The first electrode exposes a portion of the main surface located in the interval; and on the side of the first electrode of the first sub-pixel and the first electrode of the second sub-pixel away from the substrate
  • the pixel defining material layer is formed to utilize a thickness of the first electrode of the first sub-pixel in a direction perpendicular to the main surface and a thickness of the first electrode of the second sub-pixel in a direction perpendicular to the main surface.
  • the first groove is formed while forming the pixel-defining material layer, and there is no need to pattern the pixel-defining material layer to form the first groove.
  • the manufacturing method of a display panel includes: performing a patterning process on the pixel defining material layer to form the plurality of opening areas to form the pixel defining layer; and using the same material and the same
  • the channel film layer formation process forms the charge generation layer of the first sub-pixel, the charge generation layer of the second sub-pixel and the floating charge generation layer on the side of the pixel definition layer away from the substrate, wherein , the first groove has a first bottom surface substantially parallel to the main surface, the floating charge generation layer is located in the first groove and on the first bottom surface, and the first sub-pixel
  • the charge generation layer is located on a side of the first stack portion away from the main surface, the charge generation layer of the second sub-pixel is located on a side of the second stack portion away from the main surface, and,
  • the depth of the first groove in the direction perpendicular to the substrate is used to disconnect the charge generation layer of the first sub-pixel from the floating charge generation layer, and the charge generation of the second sub-pixel is layer is disconnected
  • the pixel defining layer includes a spacer portion, a first stacking portion and a second stacking portion.
  • the spacing part is located in the gap between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel; the first stacking part is stacked on the first electrode in a direction perpendicular to the main surface.
  • the first stack portion covers and directly contacts a portion of the upper surface of the first electrode of the first sub-pixel away from the base substrate
  • the second stack portion covers and directly contacts a portion of the first electrode of the second sub-pixel away from the A portion of the upper surface of the base substrate.
  • the main surface has a middle portion located at the interval
  • the manufacturing method includes: forming a second concave portion on the middle portion of the main surface. Groove; forming a first etching barrier layer, wherein the second groove has a second bottom surface substantially parallel to the main surface, the first etching barrier layer is located in the second groove and located at the on the second bottom surface; forming a pixel defining material layer covering the first electrode of the first sub-pixel, the first electrode of the second sub-pixel and the second groove; and forming the pixel defining material layer
  • a patterning process is performed to form the break and the opening area to form the pixel defining layer, wherein the pixel defining layer includes a spacer portion, a first stacked portion and a second stacked portion.
  • the spacing part is located in the gap between the first electrode of the first sub-pixel and the first electrode of the second sub-pixel; a first stacking part is stacked on the first electrode in a direction perpendicular to the main surface.
  • One side of the substrate; the spacer portion includes the first groove; the break is located at the spacer portion of the pixel defining layer at the second groove and runs through the spacer portion, and the second groove is connected to the first groove.
  • the first grooves are connected through the fracture.
  • a method for manufacturing a display panel includes: forming a metal electrode material layer on the main surface, and performing a patterning process on the metal electrode material layer to form a first sub-pixel of the first sub-pixel.
  • a patterning process is performed on the transparent electrode material layer to form a transparent electrode layer covering the metal electrode layer of the first electrode of the first sub-pixel.
  • the transparent electrode layer covering the metal electrode layer of the first electrode of the second sub-pixel, and the first etching barrier layer includes: forming a metal electrode material layer on the main surface, and performing a patterning process on the metal electrode material layer to form a first sub-pixel of the first sub-pixel.
  • the manufacturing method of a display panel further includes: using the same material and the same film layer formation process to form the first sub-pixel on a side of the pixel defining layer away from the substrate.
  • the charge generation layer of the second sub-pixel On one side of the main surface, the charge generation layer of the second sub-pixel is located on a side of the second stack part away from the main surface, and the charge generation layer of the first sub-pixel is connected to the floating charge generation layer. The charge generation layer of the second sub-pixel is disconnected from the floating charge generation layer.
  • the manufacturing method of a display panel provided by at least one embodiment of the present disclosure further includes: etching the second groove after forming the second etching barrier layer, so that the second groove is etched along the line from the main surface to the In the direction of the bottom surface of the second groove, the size of the second groove in the direction parallel to the main surface gradually becomes larger, or first gradually increases and then gradually decreases.
  • a method for manufacturing a display panel includes: forming a second etching barrier layer on the main surface, wherein the second etching barrier layer is located on the first sub-pixel. In the interval between an electrode and the first electrode of the second sub-pixel; forming a first electrode covering the first sub-pixel, the first electrode of the second sub-pixel, and the second etching barrier layer a pixel defining material layer; and performing a patterning process on the pixel defining material layer to form the first groove and the plurality of opening areas, wherein the first groove is located in the second etching barrier layer a side away from the base substrate, and expose at least a portion of the upper surface of the second etching barrier layer away from the base substrate.
  • a method for manufacturing a display panel includes: forming a metal electrode material layer on the main surface, and performing a patterning process on the metal electrode material layer to form a third sub-pixel of the first sub-pixel.
  • Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure
  • Figure 2 is a schematic cross-sectional view along line A-A’ in Figure 1;
  • Figure 3 is a schematic cross-sectional view along line A-A’ in Figure 1 of another display panel provided by an embodiment of the present disclosure
  • Figure 4 is a schematic cross-sectional view of another display panel along line A-A’ in Figure 1 according to an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of another display panel along line A-A’ in FIG. 1 according to an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIGS. 7A-7H are schematic diagrams of a method for manufacturing a display panel according to an embodiment of the present disclosure.
  • FIGS. 8A-8J are schematic diagrams of another method of manufacturing a display panel according to an embodiment of the present disclosure.
  • 9A-9G are schematic diagrams of another method for manufacturing a display panel according to an embodiment of the present disclosure.
  • Tandem organic light-emitting diode (Tandem OLED) devices are prone to crosstalk between adjacent sub-pixels due to the low resistivity of the hole injection layer (Hole Injection Layer, HIL) and charge generation layer (Charge Generated Layer, CGL). problem, which will cause the color gamut of the OLED device to decrease, and thus the display effect of the OLED display panel using the OLED device will decrease. Therefore, preventing crosstalk between adjacent sub-pixels is very important to improve the display effect of OLED display panels. Furthermore, it is important to achieve display uniformity across the entire display panel while ensuring the prevention of crosstalk between adjacent sub-pixels.
  • HIL hole injection Layer
  • CGL Charge Generated Layer
  • At least one embodiment of the present disclosure provides a display panel, which includes a substrate, a plurality of sub-pixels and a pixel defining layer.
  • the substrate has a main surface; each of the plurality of sub-pixels includes a light-emitting device located on the main surface, the light-emitting device including a first electrode stacked in a direction perpendicular to the main surface and a charge generation layer, the charge generation layer is located on a side of the first electrode away from the substrate;
  • the pixel definition layer is located on the main surface and defines a plurality of opening areas, the plurality of opening areas and the A plurality of sub-pixels correspond one to one and expose at least part of the first electrode of the corresponding sub-pixel; the plurality of sub-pixels include adjacent first sub-pixels and second sub-pixels, and the first sub-pixel of the first sub-pixel has a one-to-one correspondence.
  • the pixel defining layer includes a first groove located in the space and recessed toward the main surface, the charge of the first sub-pixel
  • the generation layer and the charge generation layer of the second sub-pixel are spaced apart by the first groove;
  • the pixel definition layer includes a space between two adjacent sub-pixels that are different in the plurality of sub-pixels.
  • the plurality of first grooves in the plurality of first grooves have equal depths in a direction perpendicular to the main surface.
  • FIG. 1 is a schematic plan view of a display panel provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view along line A-A’ in FIG. 1
  • a display panel 10 provided by at least one embodiment of the present disclosure includes: a substrate 1 , a plurality of sub-pixels 100 and a pixel defining layer 4 .
  • the substrate 1 has a main surface 11; each sub-pixel in the plurality of sub-pixels 100 includes a light-emitting device located on the main surface 11, for example, the light-emitting device is a tandem organic light-emitting diode (Tandem OLED) device; the light-emitting device is included perpendicular to the main surface.
  • the first electrode 21 and the charge generation layer 3 (Charge Generated Layer, CGL) are stacked in the direction of the surface 11.
  • the charge generation layer 3 is located on the side of the first electrode 21 away from the substrate 1; the pixel definition layer 4 is located on the main surface 11.
  • the plurality of sub-pixels 100 include adjacent first sub-pixels 100.
  • the pixel defining layer 4 includes a gap SP located in the gap SP and facing the main surface 11
  • the recessed first groove 40, the charge generation layer 3 of the first sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 are separated by the first groove 40; the pixel definition layer 4 includes different components located in the plurality of sub-pixels 100.
  • the plurality of first grooves 40 in the spacing SP between two adjacent sub-pixels 100 have the same depth H in the direction perpendicular to the main surface 11 .
  • grooves are usually formed on the surface of the substrate where the OLED device is provided by etching the silicon oxide layer at the top of the substrate (for example, a silicon-based substrate) (ie, the side closest to the display device).
  • the step difference formed by the groove is used to disconnect the charge generation layers of adjacent sub-pixels (not connected to each other, not in contact, not electrically connected).
  • it is difficult to control the uniformity of etching the silicon oxide layer of the silicon-based substrate. It is impossible to accurately control the depth of the grooves of multiple sub-pixels in the entire display panel in the direction perpendicular to the substrate, resulting in uneven etching depth of the grooves in the entire display area, resulting in Mura defects.
  • the cathode in part of the display area will form a puncture structure in the groove area, resulting in a large leakage of the entire OLED device.
  • the first electrode 21 of the first sub-pixel 101 and the first electrode of the second sub-pixel 102 are The first groove 40 is formed in the space SP between the electrodes 21 through a patterning process (such as a photolithography process), and then the charge generation layer 3 is formed, so that the first groove 40 is used to form the first groove 40 perpendicular to the substrate 1
  • the step difference in the direction of the main surface 11 disconnects the charge generation layer 3 in the OLED device of the first subpixel 101 and the charge generation layer 3 in the OLED device of the second subpixel 102 from each other.
  • the thickness and shape of the pixel defining layer 4 formed by controlling the thickness and shape of the first electrodes 21 of multiple sub-pixels 100 in a direction perpendicular to the main surface 11 of the substrate 1 are also uniform, so that This makes the depth H of the first groove 40 that is naturally formed depending on the shape and thickness of the first electrode 21 uniform in the plurality of sub-pixels 100 , thereby enabling the charge generation layers 3 of the plurality of sub-pixels 100 to be disconnected from each other.
  • the degree of uniformity plays a very important role in improving the display uniformity of the display panel 10 and preventing poor Mura.
  • the substrate 1 is a silicon-based substrate, which includes an insulating layer and a via hole V1 (such as a tungsten hole) penetrating the insulating layer.
  • the first electrode 21 is connected to the connecting electrode 12 through the via hole V1, and the connecting electrode 12 is connected to the connecting electrode 12.
  • the first electrode of the driving transistor of the pixel circuit in the silicon-based substrate is connected.
  • the pixel circuit includes, for example, a thin film transistor and a storage capacitor, and also includes, for example, a data transistor, a compensation transistor, and the like. For example, they are 3T1C, 7T1C, 9T2C and other pixel circuits. This disclosure does not limit the specific type of the pixel circuit.
  • each sub-pixel 100 there are a first light-emitting element 61 and a second light-emitting element 62.
  • the first light-emitting element 61 emits light of a first color
  • the second light-emitting element 62 emits light of a second color.
  • the first color and the second color are different;
  • the charge generation layer 3 is located between the first light-emitting element 61 and the second light-emitting element 62
  • the first light-emitting element 61 and the second light-emitting element 62 are connected in parallel, so that the excitons emit twice the amount of excitons under the action of the electric field, thereby achieving more than twice the photoelectric conversion efficiency.
  • the charge generation layer 3 Since the charge generation layer 3 has stronger conductivity than other functional layers in the OLED device, it will cause pixel crosstalk in the lateral direction, that is, the arrangement direction of the sub-pixels. Therefore, the charge generation layer 3 of adjacent sub-pixels needs to be disconnected. On to prevent crosstalk between adjacent subpixels.
  • each sub-pixel 100 of the display panel also includes a color filter.
  • the color filter is located on the side of the light-emitting device away from the substrate 1 and is emitted by the first light-emitting device.
  • the light emitted by the element 61 and the second light-emitting element 62 is combined into white light.
  • the white light After being filtered by the color filter of the corresponding sub-pixel 100, the white light causes different sub-pixels to emit light of different colors.
  • the first color is yellow and the second color is blue.
  • three consecutive sub-pixels 100 constitute a pixel 10a.
  • the color filters in the three sub-pixels 100 in each pixel 10a are red (R), green (G) and blue ( B); and the first light-emitting elements 61 in the three sub-pixels 100 have the same light-emitting color, and all emit light of the first color; the second light-emitting elements 62 in the three sub-pixels 100 have the same light-emitting color, and all emit light of the third color.
  • the light of the first color and the light of the second color are combined into white light.
  • the white light passes through the red (R) color filter, the green (G) color filter and the blue (B) color filter respectively.
  • red light, green light and blue light are emitted from the three sub-pixels 100 respectively.
  • the first color and the second color are not limited to the above-mentioned types, and the extension of the color filter is not limited to the above-mentioned types, and this disclosure does not limit this.
  • the first electrode 21 includes a metal electrode layer and a transparent electrode layer 21d stacked in a direction perpendicular to the main surface 11, and the transparent electrode layer 21d covers the metal electrode layer.
  • the metal electrode layer has a Ti/Al/Ti/ITO stacked structure. That is, as shown in Figure 2, the metal electrode layer includes a first sub-layer 21a, a second sub-layer 21b and a third sub-layer 21c stacked on the main surface of the substrate 1.
  • the material of the first sub-layer 21a is Metal titanium (Ti)
  • the material of the second sub-layer 21b is metal aluminum (Al)
  • the material of the third sub-layer 21c is metal titanium (Ti), thereby forming the first sub-layer 21a, the second sub-layer 21b and the third
  • the sub-layer 21c forms a Ti/Al/Ti/ITO stack structure.
  • the material of the transparent electrode layer 21 is a transparent conductive material, such as ITO, IZO, etc.
  • the thickness T1 of the first electrode 21 of the plurality of sub-pixels 100 in the direction perpendicular to the main surface 11 is equal, and the thickness of the first electrode 21 of each of the plurality of sub-pixels is not less than 450 ⁇ m to ensure that the thickness T1 depends on the first electrode 21
  • the first groove 40 formed by the thickness has sufficient depth to ensure that the charge generation layer 3 in the OLED device of the first sub-pixel 101 and the second sub-pixel 102 has a better effect of disconnecting from each other, that is, ensuring that the adjacent
  • the reliability of the charge generation layers 3 of the sub-pixels being disconnected from each other improves the yield of the display panel.
  • the depth of the first groove 40 in the direction perpendicular to the main surface 11 is not less than 900 ⁇ m, that is, the first groove 40 has sufficient depth to ensure that the first sub-pixel 101 and the second sub-pixel 102 in the OLED device.
  • the effect of the charge generation layers 3 being disconnected from each other is better, that is, the reliability of the charge generation layers 3 of adjacent sub-pixels being disconnected from each other is ensured, and the yield of the display panel is improved.
  • the multiple sub-pixels 100 of the entire display panel 10 for example, the first electrodes 21 of all the sub-pixels 100 have the same thickness in the direction perpendicular to the main surface 11 of the substrate 1 , so that the plurality of first grooves 40 of the display panel 10
  • the depths H in the direction perpendicular to the main surface 11 of the substrate 1 are equal.
  • the thickness of the first electrode 21 in the direction perpendicular to the main surface 11 of the substrate 1 refers to the sum of the thicknesses of the metal electrode layer and the transparent electrode layer. Therefore, in FIG.
  • the thickness of the first electrode 21 in the direction perpendicular to the main surface 11 of the substrate 1 is a laminate structure composed of the first sub-layer 21a, the second sub-layer 21b and the third sub-layer 21c and is transparent. The sum of the thicknesses of the electrode layers 21d in the direction perpendicular to the main surface 11 of the substrate 1.
  • the pixel definition layer 4 includes a spacer portion 401 , a first stack portion 41 and a second stack portion 42 .
  • the spacer part 401 is located in the space SP between the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102; the first stack part 41 is stacked on the first electrode in a direction perpendicular to the main surface 11.
  • the side of the first electrode 21 of the sub-pixel 101 away from the substrate 1; the second stack portion 42 is stacked on the side of the first electrode 21 of the second sub-pixel 102 away from the substrate 1 in a direction perpendicular to the main surface 11
  • the spacer portion 401 includes a first groove 40 .
  • the main surface 11 of the substrate 1 has a middle portion 1a located at the spacing SP, and the middle portion 1a of the main surface 11 is flat, that is, there is no groove on the main surface 11 at the spacing SP,
  • the spacer portion 401 of the pixel definition layer 4 is located on the middle portion 1a of the main surface 11; for example, the entire main surface 11 is flat.
  • the first groove 40 has a first bottom surface 40a substantially parallel to the main surface 11 to ensure that the spacing portion 401 of the pixel definition layer 4 is formed on the flat surface of the middle portion 1a of the main surface 11, so that the first groove 40 There is also a flat first bottom surface 40a, so that the step difference formed by the depth of the uniform first groove 40 can be used to disconnect the charge generation layer 3 in the OLED device of the first sub-pixel 101 and the second sub-pixel 102 from each other.
  • the entire first bottom surface 40a of the first groove 40 is a continuous surface, that is, there are no grooves, openings, etc. to interrupt the first bottom surface 40a, that is, the first bottom surface 40a is a flat middle portion 1a adapted to the main surface 11 A surface formed by its shape.
  • the display panel 10 further includes a floating charge generation layer 30 .
  • the floating charge generation layer 30 is located in the first groove 40 and on the first bottom surface 40 a and is connected with the charge of the first sub-pixel 101 .
  • the generation layer 3 and the charge generation layer 3 of the second sub-pixel 102 are made of the same material; the charge generation layer 3 of the first sub-pixel 101 is located on a side of the first stack 41 away from the main surface 11, and the charge generation layer of the second sub-pixel 102 is Layer 3 is located on a side of the second stack 42 away from the main surface 11; the charge generation layer 3 of the first sub-pixel 101 is disconnected from the floating charge generation layer 30, and the charge generation layer 3 of the second sub-pixel 102 is disconnected from the floating charge generation layer 30.
  • the charge generation layer 30 is disconnected, that is, the charge generation layer 3 of adjacent sub-pixels is disconnected from each other using the step difference formed by the depth of the first groove 40 .
  • the distance from the floating charge generation layer 30 to the main surface 11 is less than the distance from the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 to the main surface 11 and is smaller than the distance from the upper surface of the first portion 41 of the pixel definition layer 4 to the main surface 11 .
  • the distance from the upper surface of the second portion 42 away from the substrate 1 to the main surface 11 that is, the distance between the upper surface of the floating charge generation layer 30 and the first portion 41 of the pixel definition layer 4 away from the substrate 1 and the second portion 42
  • the first stacking part 41 , the spacing part 401 and the second stacking part 42 form a continuous integrated structure.
  • the spacer portion 401 of the pixel definition layer 4 covers and directly contacts the side surface of the first electrode 21 of the first sub-pixel 101 close to the first electrode 21 of the second sub-pixel 102, the flat middle portion 1a of the main surface 11, And the side surface of the first electrode 21 of the second sub-pixel 102 close to the first electrode 21 of the first sub-pixel 101;
  • the first stack portion 41 covers and directly contacts the side surface of the first electrode 21 of the first sub-pixel 101 away from the substrate.
  • a portion of the upper surface of the substrate 1, the second stack portion 42 covers and directly contacts a portion of the upper surface of the first electrode 21 of the second sub-pixel 102 away from the substrate 1.
  • the front projection of the charge generation layer 3 of the first sub-pixel 101 on the main surface 11 is close to the edge of the second sub-pixel 102 and the front projection of the floating charge generation layer 30 on the main surface 11 is close to the first sub-pixel.
  • the edges of the charge generation layer 3 of the second sub-pixel 102 are connected (for example, coincident with each other), and the orthographic projection of the charge generation layer 3 of the second sub-pixel 102 on the main surface 11 is close to the edge of the first sub-pixel 101 and the edge of the floating charge generation layer 30 on the main surface 11
  • the edges of the orthographic projection close to the second sub-pixel 102 meet (eg coincide with each other).
  • the ratio of the thickness T1 of the first electrode 21 of the first sub-pixel 101 in the direction perpendicular to the main surface 11 to the thickness T3 of the pixel defining layer 4 in the direction perpendicular to the main surface 11, and the The ratio of the thickness T2 of the first electrode 21 of the two sub-pixels 102 in the direction perpendicular to the main surface 11 (for example, T1 T2) to the thickness T3 of the pixel defining layer 4 in the direction perpendicular to the main surface 11 is not less than 2.
  • the first portion 41, the spacer portion 401 and the second portion 42 of the pixel defining layer 4 have the same thickness.
  • the first groove 40 in the pixel defining layer 4 formed by natural deposition due to the thickness and morphology of the electrode 21 has sufficient depth to enable the charge generation layer 3 of the first sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 Disconnected from each other.
  • the light-emitting device also includes a hole injection layer 5 (Hole Injection Layer, HIL).
  • the hole injection layer 5 is located on the side of the first electrode 21 away from the substrate.
  • the hole injection layer 5 is in direct contact with the first electrode 21.
  • the hole injection layer 5 , the first light-emitting element 61 , the charge generation layer 3 and the second light-emitting element 62 are arranged in sequence.
  • the hole injection layer 5 of the first subpixel 101 and the hole injection layer 5 of the second subpixel 102 are disconnected from each other, for example, at the first groove 40 . Since the hole injection layer 5 has stronger conductivity than other functional layers in the OLED device and has a greater impact on the operating performance of the OLED device, it will cause pixel crosstalk in the lateral direction, that is, the arrangement direction of the sub-pixels, so it is required The adjacent sub-hole injection layers 5 are disconnected to prevent crosstalk between adjacent sub-pixels.
  • the step difference formed by the depth of the uniform first groove 40 is used to disconnect the hole injection layer 5 in the OLED device of the first sub-pixel 101 and the second sub-pixel 102 from each other. , making the functional layer structure of multiple sub-pixels uniform.
  • the light-emitting device further includes a floating hole injection layer 50 located in the first groove 40 and on the first bottom surface 40 a, for example, a floating hole injection layer 50 . 50 is in contact with the first bottom surface 40a and has the same material as the hole injection layer 50 of the first sub-pixel 101 and the hole injection layer 50 of the second sub-pixel 102.
  • the distance from the floating hole injection layer 50 to the main surface 11 is smaller than the distance from the first portion 41 of the pixel definition layer 4 to the main surface 11 and smaller than the distance from the second portion 42 of the pixel definition layer 4 to the main surface 11 , that is,
  • the floating hole injection layer 50 exists between the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 and the upper surface of the second portion 42 away from the substrate 1 in the direction perpendicular to the main surface 11
  • the step difference is to continue to utilize the step difference between the floating hole injection layer 50 and the hole injection layer 5 of the first sub-pixel 101, and the step difference between the floating hole injection layer 50 and the hole injection layer 5 of the first sub-pixel 101.
  • the step difference makes the charge generation layer 3 of the first sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 formed on the side of the hole injection layer 5 away from the substrate 1 disconnected, and can ensure that both Reliability of being disconnected from each other.
  • the light-emitting device further includes a floating first light-emitting layer 60.
  • the floating first light-emitting layer 60 is located in the first groove 40 and on the first bottom surface 40a, and is in contact with the first light-emitting layer of the first sub-pixel 101.
  • the element 61 and the first light-emitting element 61 of the second sub-pixel 102 are made of the same material.
  • the distance from the floating first light-emitting layer 60 to the main surface 11 is less than the distance from the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 to the main surface 11 and is less than the distance from the second portion 42 of the pixel definition layer 4
  • the distance from the upper surface away from the substrate 1 to the main surface 11 that is, the upper surface of the first portion 41 of the floating first light-emitting layer 60 and the pixel definition layer 4 away from the substrate 1 and the distance of the second portion 42 away from the substrate 1
  • the step difference between a light-emitting layer 60 and the first light-emitting element 61 of the first sub-pixel 101 is such that the charge generation layer 3 of the first sub-pixel 101 and the second sub-pixel formed on the side of the first light-emitting element 61 away from the substrate 1
  • the charge generation layer 3 of 102 is disconnected, and the reliability of the disconnection between the two can be ensured.
  • the second light emitting element 62 covers the first sub-pixel 101 and the second sub-pixel 101 , fills the first groove 40 and is continuous. Since the second light-emitting element 62 is located on the side of the charge generation layer 3 away from the substrate 1, there is no need for the second light-emitting element 62 to be turned off in the interval SP between the first sub-pixel 101 and the second sub-pixel 102.
  • the surface of the second light emitting element 62 away from the substrate 1 is a flat surface, similar to a flat layer.
  • the second light-emitting element 62 may also be turned off in the interval SP between the first sub-pixel 101 and the second sub-pixel 102.
  • the light emitting device further includes a second electrode 22 .
  • the first electrode is the anode and the second electrode is the cathode.
  • the second electrode 22 is a common cathode covering at least the entire display area of the display panel.
  • the display panel 10 further includes an encapsulation layer 7 .
  • the encapsulation layer 7 may include an inorganic encapsulation layer and/or an organic encapsulation layer.
  • the display area of the display panel 10 includes virtual sub-pixels, that is, floating sub-pixels, which do not perform display functions. There are also gaps between adjacent virtual sub-pixels, but the gaps between adjacent virtual sub-pixels do not need to be
  • the charge generation layer of the adjacent virtual sub-pixel is disconnected, and other functional layers of the series OLED, such as the hole injection layer and the first light-emitting element, are not disconnected.
  • FIG. 3 is a schematic cross-sectional view of another display panel along line A-A’ in FIG. 1 according to an embodiment of the present disclosure.
  • the display panel shown in FIG. 3 has the following differences from the display panel shown in FIG. 2 .
  • the main surface 11 has a middle portion 1 a located at the space SP
  • the middle portion 1 a of the main surface 11 has a second groove 13
  • the spacer portion 401 of the pixel definition layer 4 has a through space at the second groove 13
  • the second groove 13 and the first groove 40 are connected through the fracture 40b of the portion 401
  • the second groove 13 has a second bottom surface 130 substantially parallel to the main surface 11, and the display panel 10 also includes a first etching barrier.
  • the first etch stop layer 81 is located in the second groove 13 and on the second bottom surface 130 , and the material of the first etch stop layer 81 is different from the material of the substrate 1 and is different from the pixel definition layer 4 The materials are different.
  • the first etching barrier layer 81 can be produced first, and then the pixel defining layer 4 can be formed through a patterning process, such as etching, such as wet etching. During the patterning process of the pixel defining layer 4, the first etching process is performed.
  • the barrier layer 81 can block the etching of the second bottom surface 130 of the second groove 13, so that the plurality of second grooves 13 of the entire display panel have equal depths, so that the hole injection layer of each sub-pixel formed subsequently,
  • Each film layer such as the charge generation layer has a uniform structure to prevent Mura display defects and improve the display uniformity of the display panel.
  • the etching liquid will continue to etch the portion of the groove wall of the second groove 13 that is not covered by the first etching barrier layer 81, including the second groove wall.
  • the side surfaces 13a/13b of the second groove 13 that intersect with the second bottom surface 130 continue to be etched, so that the side surfaces 13a/13b of the second groove 13 are recessed in a direction away from the first etching barrier layer 81, which is more conducive to subsequent steps.
  • the film layers of adjacent sub-pixels charge generation layer 3, first light-emitting layer 61, hole injection layer 5) above the pixel definition layer 4 and in the first groove 40 are disconnected.
  • the material of the substrate 1 shown in FIG. 3 is silicon oxide, silicon nitride, etc., for example, the substrate 1 is the uppermost silicon oxide layer of the silicon-based substrate, that is, the second groove 13 is located at the uppermost layer of the silicon-based substrate. in the silicon oxide layer above.
  • the material of the first etching barrier layer 81 is a transparent conductive material, such as ITO, IZO, etc.
  • the display panel 10 further includes a floating charge generation layer 30 located in the second groove 13 and on a side of the first etching barrier layer 81 away from the second bottom surface 130 and connected with the first sub-surface.
  • the charge generation layer 3 of the pixel 101 and the charge generation layer 3 of the second sub-pixel 102 are made of the same material.
  • the charge generation layer 3 of the first sub-pixel 101 is located on a side of the first stack part 41 away from the main surface 11.
  • the second sub-pixel The charge generation layer 3 of 102 is located on the side of the second stack portion 42 away from the main surface 11; the charge generation layer 3 of the first sub-pixel 101 is disconnected from the floating charge generation layer 30, and the charge generation layer of the second sub-pixel 102 3 is disconnected from the floating charge generation layer 30 to disconnect the charge generation layer of the adjacent sub-pixel 100.
  • the floating charge generation layer 30 includes a first part 30 a and a second part 30 b that are spaced apart, thereby further effectively ensuring that the first sub-section
  • the effect is that the charge generation layer 3 of the pixel 101 and the charge generation layer 3 of the second sub-pixel 102 are completely disconnected.
  • the floating charge generation layer 30 further includes a third portion 30c located in the second groove 13.
  • the display panel 10 further includes a floating hole injection layer 50.
  • the floating hole injection layer 50 includes a first part 50a and a second part 50b.
  • the first part 50a and the second part 50b are located in the first recess.
  • the first part 50a and the second part 50b are spaced apart due to the step formed by the communication between the break 40b and the second groove 13.
  • the first portion 50a and the second portion 50b of the floating hole injection layer 50 are located on the bottom surface 40a and respectively located on opposite sides of the break 40b.
  • the first portion 50a of the floating hole injection layer 50 is stacked with the first portion 30a of the floating charge generation layer 30 and is located on a side of the first portion 30a of the floating charge generation layer 30 close to the spacer portion 401 of the pixel definition layer 4;
  • the second portion 50b of the floating hole injection layer 50 is stacked with the second portion 30b of the floating charge generation layer 30, and is located near the spacer portion 401 of the pixel definition layer 4 of the second portion 30b of the floating charge generation layer 30. one side.
  • the floating hole injection layer 50 further includes a third portion 50c.
  • the third portion 50c is located in the second groove 13 and is located between the first etching barrier layer 81 and the third portion 30c of the floating charge generation layer 30. between.
  • the display panel 10 further includes a floating luminescent layer 60.
  • the floating luminescent layer 60 includes a first part 60a and a second part 60b.
  • the first part 60a and the second part 60b are located in the first groove 40, Due to the step difference formed by the communication between the break 40b and the second groove 13, the first part 60a and the second part 60b are spaced apart.
  • the first part 60a and the second part 60b of the floating light-emitting layer 60 are located on the bottom surface 40a and respectively located on opposite sides of the break 40b.
  • the first portion 60a of the floating light-emitting layer 60 is stacked with the first portion 30a of the floating charge generation layer 30 and the first portion 50a of the floating hole injection layer 50, and is located between the first portion 30a of the floating charge generation layer 30 and the floating hole injection layer 50. Between the first portion 50a of the hole injection layer 50; the second portion 60b of the floating light-emitting layer 60, the second portion 30b of the floating charge generation layer 30, and the second portion 50b of the floating hole injection layer 50 are stacked, and are located between the second portion 30b of the floating charge generation layer 30 and the second portion 50b of the floating hole injection layer 50.
  • the floating light-emitting layer 60 further includes a third portion 60c located in the second groove 13 and between the third portion 50c of the floating hole injection layer 50 and the third portion of the floating charge generation layer 30 Between 30c.
  • the first electrode 21 of each of the plurality of sub-pixels includes a metal electrode layer and a transparent electrode layer 21 d stacked in a direction perpendicular to the main surface 11 , and the transparent electrode layer 21 d covers the metal electrode layer.
  • the etching barrier layer 81 and the transparent electrode layer 21d are made of the same material and are arranged in the same layer.
  • the metal electrode layer has a Ti/Al/Ti/ITO stacked structure.
  • the first etching barrier layer 81 and the transparent electrode layer 21d are made of the same material and are arranged in the same layer. Therefore, the first etching barrier layer 81 and the transparent electrode layer 21d can be formed by performing the same patterning process on the same film layer.
  • the specific structure of the first electrode 21 is the same as that in FIG. 2 , and reference may be made to the previous description for details.
  • the size of the second groove 13 in the direction parallel to the main surface 11 first gradually increases and then gradually decreases, so that It is more conducive to subsequently allow the film layers of adjacent sub-pixels (charge generation layer 3, first light-emitting layer 61, hole injection layer 5) in the first groove 40 to pass through the second groove. Slot 13 is disconnected.
  • the side surfaces 13 a / 13 b of the second groove 13 are recessed in a direction away from the first etching barrier layer 81 , which is more conducive to subsequent processing of the pixel definition layer 4
  • the film layers of adjacent sub-pixels (charge generation layer 3, first light-emitting layer 61, hole injection layer 5) in the first groove 40 are disconnected.
  • the shape of the second groove 13 along the cross section perpendicular to the main surface 11 is an irregular figure.
  • the irregular figure includes a bottom edge 130 that is substantially parallel to the main surface 11 and a first side edge 13 a that is opposite to each other and both intersects the bottom edge. and the second side 13b, the first side 13a is recessed in a direction away from the second side 13b, and the second side 13b is recessed in a direction away from the first side 13a.
  • FIG. 3 Other unmentioned features of the embodiment shown in FIG. 3 are the same as those of the embodiment shown in FIG. 2 , and reference may be made to the description of the embodiment shown in FIG. 2 .
  • FIG. 4 is a schematic cross-sectional view of another display panel along line A-A’ in FIG. 1 according to an embodiment of the present disclosure.
  • the display panel shown in FIG. 4 has the following differences from the display panel shown in FIG. 3 .
  • the size of the second groove 13 in the direction parallel to the main surface 11 gradually becomes larger; for example, the second groove 13 gradually becomes larger in size.
  • the shape of 13 along the cross-section perpendicular to the main surface 11 is trapezoidal, so as to be more conducive to subsequent film layers of adjacent sub-pixels (charge generation layer 3, charge generation layer 3, The first light-emitting layer 61 and the hole injection layer 5) are disconnected.
  • the shape of the second groove 13 along the cross section perpendicular to the main surface 11 is not limited to a trapezoid, as long as the second groove 13 is parallel to the main surface in the direction from the main surface 11 to the bottom surface 130 of the second groove 13 .
  • the size in the 11th direction gradually becomes larger.
  • FIG. 4 Other unmentioned features of the embodiment shown in FIG. 4 are the same as those of the embodiment shown in FIG. 3 , and reference may be made to the description of the embodiment shown in FIG. 3 .
  • FIG. 5 is a schematic cross-sectional view of another display panel along line A-A’ in FIG. 1 according to an embodiment of the present disclosure.
  • the display panel shown in FIG. 5 has the following differences from the display panel shown in FIG. 2 .
  • the display panel 10 includes a second etching barrier layer 82 located on the main surface 11 and in the space SP, and is connected to the first electrode 21 of the first sub-pixel 101
  • the material is the same as the first electrode 21 of the second sub-pixel 102 and is set at the same layer spacing SP;
  • the first groove 400 is located on the side of the second etching barrier layer 82 away from the substrate 1 and exposes the second etching barrier At least a portion of the upper surface of layer 82 remote from the base of substrate 1 .
  • the step difference formed by the first groove 400 in the direction perpendicular to the main surface 11 of the substrate 1 can be used to separate the charge generation layer 3 in the OLED device of the first sub-pixel 101 and the OLED device of the second sub-pixel 102.
  • the charge generation layers 3 are disconnected from each other.
  • the second etching barrier layer 82 has a fixed thickness and can prevent the portion of the substrate 1 that is blocked by the second etching barrier layer 82 from being damaged in subsequent etching processes, such as etching to form the pixel defining layer 4 .
  • Etching is performed, so that the first concavity between adjacent sub-pixels 100 can be realized by controlling the thickness of the second etching barrier layer 82 between adjacent sub-pixels 100 to be equal in the direction perpendicular to the main surface 11 .
  • the grooves 400 have the same depth, thereby ensuring uniform functional layer structures of multiple subsequently formed sub-pixels, preventing Mura defects, and improving display uniformity of the display panel.
  • the thickness of the second etching barrier layer 82 in the direction perpendicular to the main surface 11 is equal to the thickness T1/T2 of the first electrode 21 in the direction perpendicular to the main surface 11; for example, the first electrodes 21 of the multiple sub-pixels are in the vertical direction.
  • the thickness in the direction of the main surface 11 is equal, which is beneficial to improving the display uniformity of the display panel.
  • the hole injection layer 5 of the first sub-pixel 101 and the hole injection layer 5 of the second sub-pixel 102 are disconnected from each other, for example, at the first groove 400; the first light emission of the first sub-pixel 101
  • the element 61 and the first light-emitting element 61 of the second sub-pixel 102 are disconnected from each other at, for example, the first groove 400 .
  • the hole injection layer 5 , the first light-emitting element 61 , the charge generation layer 3 and the second light-emitting element 62 are arranged in sequence.
  • the floating hole injection layer 50 , the floating light emitting layer 60 and the floating charge generation layer 30 are located in the first groove 400 and are sequentially stacked on the surface of the second etching barrier layer 82 away from the substrate 1 .
  • the hole injection layers 5 of the first sub-pixel 101 and the second sub-pixel 102 are separated from each other by the first groove 400, and the first light-emitting elements 61 of the first sub-pixel 101 and the second sub-pixel 102 are separated from each other by the first groove. 400 disconnected.
  • the hole injection layer 5, the first light-emitting element 61, the charge generation layer 3 and the second light-emitting element 62 are arranged in order.
  • the second light-emitting element 62 covers the first sub-pixel 101 and the second sub-pixel 101, fills part of the first groove 400, and is continuous.
  • the second light-emitting element 62 may also fill the entire first groove 400 .
  • Other features of the second light emitting element 62 are similar to those in FIG. 2 .
  • the distance from the floating charge generation layer 30 to the main surface 11 is smaller than the distance from the first part 41 of the pixel definition layer 4 to the main surface 11 and smaller than the distance from the second part 42 of the pixel definition layer 4 to the main surface 11 to ensure that the The effect is that the charge generation layer 3 of one sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 are disconnected from each other.
  • the distance from the floating charge generation layer 30 to the main surface 11 may be greater than or equal to the distance from the first part 41 of the pixel definition layer 4 to the main surface 11 and less than the distance from the second part 42 of the pixel definition layer 4 to The distance between the main surfaces 11 is sufficient as long as the charge generation layer 3 of the first subpixel 101 and the charge generation layer 3 of the second subpixel 102 are disconnected from each other.
  • the size of the second etching stop layer 82 in the direction parallel to the main surface 11 is smaller than the size of the first electrode 21 in the same direction parallel to the main surface 11 , and is smaller than the size of the first electrode 21 of the second sub-pixel 102 .
  • the dimensions are parallel to the main surface 11 in the same direction to save space and meet the requirements of high PPI.
  • the size of the first groove 400 in the direction parallel to the main surface 11 first gradually increases and then gradually decreases, so as to be more conducive to making the pixel definition layer 4
  • the film layers of adjacent sub-pixels charge generation layer 3, first light-emitting layer 61, hole injection layer 5) above are disconnected.
  • the size of the first groove 400 in the direction parallel to the main surface 11 gradually becomes larger, so as to be more conducive to the film layer (charge generation) of adjacent sub-pixels above the pixel defining layer 4 Layer 3, first light emitting layer 61, hole injection layer 5) are disconnected.
  • the shape of the first groove along a cross-section perpendicular to the main surface 11 is a trapezoid, but is of course not limited to a trapezoid.
  • FIG. 5 Other unmentioned features of the embodiment shown in FIG. 5 are the same as those of the embodiment shown in FIG. 2 and FIG. 3 , and reference may be made to the description of the embodiment shown in FIG. 2 and FIG. 3 .
  • FIG. 6 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure. As shown in FIG. 6 , at least one embodiment of the present disclosure further provides a display device 1000 .
  • the display device 1000 includes any display panel 10 provided by the embodiments of the present disclosure.
  • the display device 1000 may be, for example, a device with a display function such as a series organic light-emitting diode display device or other types of devices.
  • the embodiments of the present disclosure are not limited to this.
  • the display device 1000 provided by at least one embodiment of the present disclosure can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. No restrictions.
  • At least one embodiment of the present disclosure also provides a method for manufacturing a display panel.
  • the manufacturing method includes: providing a substrate having a main surface; forming a plurality of sub-pixels on the substrate, and among the plurality of sub-pixels
  • Each sub-pixel includes a light-emitting device located on the main surface, the light-emitting device includes a first electrode and a charge generation layer stacked in a direction perpendicular to the main surface, the charge generation layer is located on the first a side of the electrode away from the substrate; and the plurality of sub-pixels include adjacent first sub-pixels and second sub-pixels, the first electrode of the first sub-pixel and the second sub-pixel
  • the pixel defining layer includes a first groove located in the space and recessed toward the main surface, the charge generation layer of the first sub-pixel and the charge generation layer of the second sub-pixel
  • the charge generation layer is spaced apart by the first grooves; the pixel defining layer includes a plurality of the first grooves
  • FIGS. 7A-7H are schematic diagrams of a manufacturing method of the display panel shown in FIG. 2 provided by an embodiment of the present disclosure.
  • the manufacturing method of the display panel will be introduced below with reference to FIGS. 7A-7H.
  • two adjacent sub-pixels of the display panel namely the first sub-pixel 101 and the second sub-pixel 102 are taken as an example for introduction. The same is true for other sub-pixels.
  • a substrate 1 is provided, having a main surface 11 .
  • the material of the substrate 1 is silicon oxide, silicon nitride, etc., and for example, the substrate 1 is the uppermost silicon oxide layer of the silicon-based substrate.
  • the manufacturing method of a display panel includes forming a plurality of sub-pixels on a substrate 1, each of the plurality of sub-pixels including a light-emitting device located on the main surface 11; forming a metal electrode material layer on the main surface 11, such as a metal electrode material layer Including a plurality of stacked metal layers, a patterning process is performed on the metal electrode material layer to form a metal electrode layer of the first electrode 21 of the first sub-pixel 101 and a metal electrode layer of the first electrode 21 of the second sub-pixel 102 .
  • the metal electrode layer has a Ti/Al/Ti/ITO stacked structure.
  • the metal electrode layer includes a first sub-layer 21a, a second sub-layer 21b and a third sub-layer 21c stacked on the main surface of the substrate 1.
  • the material of the first sub-layer 21a is Metal titanium (Ti)
  • the material of the second sub-layer 21b is metal aluminum (Al)
  • the material of the third sub-layer 21c is metal titanium (Ti), thereby forming the first sub-layer 21a, the second sub-layer 21b and the third
  • the sub-layer 21c forms a Ti/Al/Ti/ITO stack structure.
  • the main surface 11 has a middle portion 1a located in the gap SP.
  • the middle portion 1a of the main surface 11 is flat.
  • the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102 expose the portion of the main surface 11 located in the space SP.
  • the transparent electrode layer 21d of the first electrode 21 is formed through the second patterning process, and the transparent electrode layer 21d covers the metal electrode layer.
  • the material of the transparent electrode layer 21 is a transparent conductive material, such as ITO, IZO, etc.
  • a pixel defining layer 4 is formed.
  • the pixel defining layer 4 is located on the main surface 11 .
  • the pixel defining layer 4 includes a first groove 40 located in the interval SP and recessed toward the main surface 11 .
  • the first sub-pixel 101 The charge generation layer 3 and the charge generation layer 3 of the second sub-pixel 102 are spaced SP by the first grooves 40; for example, the pixel definition layer 4 includes a plurality of first grooves 40, and there are a plurality of intervals SP for the plurality of sub-pixels.
  • the first grooves 40 are respectively located in a plurality of intervals SP in a one-to-one correspondence manner, that is, the pixel definition layer 4 includes a plurality of first grooves 40 located in the intervals SP between different adjacent two sub-pixels in the plurality of sub-pixels. Groove 40, the depth H of the plurality of first grooves 40 in the direction perpendicular to the main surface 11 is equal.
  • forming the first groove 40 includes: after forming the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102 on the main surface 11, A pixel-defining material layer is formed on the side of the first electrode 21 of the second sub-pixel 102 away from the substrate 1 to utilize the thickness T1 of the first electrode 21 of the first sub-pixel 101 in the direction perpendicular to the main surface 11 and the second
  • the first groove 40 is formed.
  • a deposition method is used to form the pixel defining material layer. Furthermore, a patterning process is performed on the pixel defining layer 4 to form a plurality of opening areas to form the pixel defining layer 4. The plurality of opening areas correspond to the plurality of sub-pixels 100 and expose at least part of the first electrode 21 of the corresponding sub-pixel 100. .
  • the pixel definition layer 4 includes a spacer part 401, a first stack part 41 and a second stack part 42.
  • the spacer part 401 is located in the space SP between the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102; the first stack part 41 is stacked on the first electrode in a direction perpendicular to the main surface 11.
  • the spacer portion 401 includes the first groove 40; the spacer portion 401 of the pixel definition layer 4 covers and directly contacts the side of the first electrode 21 of the first sub-pixel 101 that is close to the first electrode 21 of the second sub-pixel 102.
  • the first stack portion 41 covers and directly contacts the first
  • the second stack portion 42 covers and directly contacts a portion of the upper surface of the first electrode 21 of the sub-pixel 101 that is away from the substrate of the substrate 1 .
  • the same material and the same film layer formation process are used to form the hole injection of the first sub-pixel 101 on the side of the pixel definition layer 4 away from the substrate 1 Layer 5, the hole injection layer 5 of the second sub-pixel 102 and the floating hole injection layer 50;
  • the first groove 40 has a first bottom surface 40a substantially parallel to the main surface 11, and the floating hole injection layer 50 is located on the second sub-pixel 102.
  • the hole injection layer 5 of the first sub-pixel 101 is located on the side of the first stack portion 41 away from the main surface 11, and the hole injection layer 5 of the second sub-pixel 102 is located on the side of the second stack portion 42 away from the main surface 11 , and the depth H of the first groove 40 in the direction perpendicular to the substrate 1 is used to cause the hole injection layer 5 of the first sub-pixel 101 to be in contact with the floating hole.
  • the hole injection layer 50 is disconnected, and the hole injection layer 5 of the second sub-pixel 102 is disconnected from the floating hole injection layer 50 . Therefore, the step difference formed by the depth of the uniform first groove 40 can be used to make the hole injection layers 5 of adjacent sub-pixels in the plurality of sub-pixels 100 disconnected from each other in a consistent manner.
  • the distance from the floating hole injection layer 50 to the main surface 11 is smaller than the distance from the first portion 41 of the pixel definition layer 4 to the main surface 11 and smaller than the distance from the second portion 42 of the pixel definition layer 4 to the main surface 11 , that is, The floating hole injection layer 50 exists between the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 and the upper surface of the second portion 42 away from the substrate 1 in the direction perpendicular to the main surface 11 Step difference.
  • the same material and the same film layer formation process are used to form the first sub-pixel 101 on the side of the hole injection layer 5 away from the substrate 1 .
  • the first groove 40 is stacked with the floating hole injection layer 50 , and the depth H of the first groove 40 in the direction perpendicular to the substrate 1 is used to cause the first light-emitting element 61 of the first sub-pixel 101 to be connected to the floating hole injection layer 50 .
  • the first light-emitting layer 60 is disconnected, and the first light-emitting element 61 of the second sub-pixel 102 is disconnected from the floating first light-emitting layer 60, that is, the floating hole injection layer 50 and the first sub-pixel 101 are used.
  • the step difference of the hole injection layer 5 and the step difference between the floating hole injection layer 50 and the hole injection layer 5 of the first sub-pixel 101 are such that the first hole injection layer 5 is formed on the side away from the substrate 1
  • the first light-emitting element 61 of the sub-pixel 101 and the first light-emitting element 61 of the second sub-pixel 102 are disconnected.
  • the distance from the floating first light-emitting layer 60 to the main surface 11 is less than the distance from the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 to the main surface 11 and is less than the distance from the second portion 42 of the pixel definition layer 4
  • the distance from the upper surface away from the substrate 1 to the main surface 11 that is, the upper surface of the first portion 41 of the floating first light-emitting layer 60 and the pixel definition layer 4 away from the substrate 1 and the distance of the second portion 42 away from the substrate 1
  • the charge generation layer of the first sub-pixel 101 is formed on the side of the pixel definition layer 4 away from the substrate 1 using the same material and the same layer formation process (for example, the same sputtering process). 3.
  • the charge generation layer 3 and the floating charge generation layer 30 of the second sub-pixel 102; the floating charge generation layer 30 is located in the first groove 40 and is connected with the floating hole injection layer 50 and the floating first light-emitting layer.
  • the charge generation layer 3 of the first sub-pixel 101 is located on the side of the first stack part 41 away from the main surface 11, and the charge generation layer 3 of the second sub-pixel 102 is located on the second stack part 42 on the side away from the main surface 11, and using the depth H of the first groove 40 in the direction perpendicular to the substrate 1 to disconnect the charge generation layer 3 of the first sub-pixel 101 from the floating charge generation layer 30, and
  • the charge generation layer 3 of the second sub-pixel 102 is disconnected from the floating charge generation layer 30, that is, the step difference between the floating first light-emitting layer 60 and the first light-emitting element 61 of the first sub-pixel 101 and the floating
  • the step difference between the first light-emitting layer 60 and the first light-emitting element 61 of the first sub-pixel 101 causes the charge generation layer 3 of the first sub-pixel 101 formed on the side of the first light-emitting element 61 away from the substrate 1 to be different from the second sub-pixel 101 .
  • the second light-emitting element 62 is formed.
  • the second light-emitting element 62 covers the first sub-pixel 101 and the second sub-pixel 101 , fills the first groove 40 and is continuous. Since the second light-emitting element 62 is located on the side of the charge generation layer 3 away from the substrate 1, there is no need for the second light-emitting element 62 to be turned off in the interval SP between the first sub-pixel 101 and the second sub-pixel 102.
  • the surface of the second light emitting element 62 away from the substrate 1 is a flat surface, similar to a flat layer.
  • the second light-emitting element 62 may also be turned off in the interval SP between the first sub-pixel 101 and the second sub-pixel 102.
  • the second electrode 2 and the encapsulation layer 7 of the light-emitting device are sequentially formed, thereby forming the display panel shown in FIG. 2 .
  • FIG. 8A-8J are schematic diagrams of a method for manufacturing the display panel shown in FIG. 5 according to an embodiment of the present disclosure.
  • the manufacturing method of the display panel will be introduced below with reference to Figures 8A-8J.
  • two adjacent sub-pixels of the display panel namely the first sub-pixel 101 and the second sub-pixel 102 are taken as an example for introduction. The same is true for other sub-pixels.
  • a substrate 1 is provided, having a main surface 11 .
  • the material of the substrate 1 is silicon oxide, silicon nitride, etc., and for example, the substrate 1 is the uppermost silicon oxide layer of the silicon-based substrate.
  • the manufacturing method of a display panel includes forming a plurality of sub-pixels on a substrate 1, each of the plurality of sub-pixels including a light-emitting device located on the main surface 11; forming a metal electrode material layer (not shown) on the main surface 11,
  • the metal electrode material layer includes a plurality of stacked metal layers, and a patterning process is performed on the metal electrode material layer to form the metal electrode layer of the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102 metal electrode layer.
  • the specific process is the same as that shown in Figure 7A, please refer to the previous description.
  • the second groove 13 is formed on the middle portion 1 a of the main surface 11 .
  • a first etching barrier layer 81 is formed, the second groove 13 has a second bottom surface 130 substantially parallel to the main surface 11 , and the first etching barrier layer 81 is located in the second groove 13 and on the second groove 13 . On the second bottom surface 130.
  • Forming the first etch stop layer 81 includes: forming a metal electrode layer covering the first electrode 21 of the first sub-pixel 101 , a metal electrode layer covering the first electrode 21 of the second sub-pixel 102 , and a transparent electrode of the second bottom surface 130 Material layer (not shown), perform a patterning process on the transparent electrode material layer to form a transparent electrode layer 21d covering the first electrode 21 of the first sub-pixel 101 and its metal electrode layer, and a first electrode of the second sub-pixel 102 21 covering the metal electrode layer of the transparent electrode layer 21d and the first etching barrier layer 81, so as to make full use of the functional and positional relationship between the transparent electrode layer 21d and the first etching barrier layer 81, and perform the same process on the same film layer.
  • the transparent electrode layer 21d and the first etching barrier layer 8 are formed through a patterning process, which saves process steps and does not require an additional patterning process for setting the first etching barrier layer 81.
  • a pixel defining material layer 40 - 1 covering the first electrode 21 of the first sub-pixel 101 , the first electrode 21 of the second sub-pixel 102 and the second groove 13 is formed.
  • a patterning process is performed on the pixel defining material layer 40 - 1 to form breaks 40 b and opening areas to form the pixel defining layer 4 , which includes a spacer portion 401 , a first stack portion 41 and a second stack portion 42.
  • the spacer part 401 is located in the space SP between the first electrode 21 of the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102; the first stack part 41 is stacked on the first electrode in a direction perpendicular to the main surface 11.
  • the spacer 401 includes the first groove 40; the break 40b is located at the spacer 401 of the pixel definition layer 4 at the second groove 13 and penetrates the spacer 401, and the second groove 13 and the first groove 40 pass through Fracture 40b is connected.
  • etching such as wet etching, is used to pattern the pixel definition layer 4 .
  • the first etching barrier layer 81 can block etching of the second bottom surface 130 of the second groove 13 , thereby making the entire display panel multi-layered.
  • the second grooves 13 have equal depths, so that the hole injection layer, charge generation layer and other film layers of each sub-pixel formed subsequently have a consistent structure, preventing Mura display defects and improving display quality.
  • the etching liquid will continue to etch the portion of the groove wall of the second groove 13 that is not covered by the first etching barrier layer 81, including the second groove wall.
  • the side surfaces 13a/13b of the second groove 13 that intersect with the second bottom surface 130 continue to be etched, so that the side surfaces 13a/13b of the second groove 13 are recessed in a direction away from the first etching barrier layer 81, which is more conducive to subsequent steps.
  • the film layers of adjacent sub-pixels (charge generation layer 3, first light-emitting layer 61, hole injection layer 5) above the pixel definition layer 4 and in the first groove 40 are disconnected. That is, the second groove 13 is etched after the second etching barrier layer 82 is formed.
  • the second etching barrier layer 82 has a fixed thickness and can prevent the formation of a pixel defining layer in subsequent etching processes, such as etching.
  • the portion of the substrate 1 blocked by the second etching barrier layer 82 is etched, so that the second etching barrier layer 82 between adjacent sub-pixels 100 can be etched perpendicular to the main surface 11
  • the thickness in the direction is equal to realize that the first groove 400 between adjacent sub-pixels 100 has the same depth, thereby ensuring a uniform functional layer structure of multiple sub-pixels formed subsequently, preventing Mura failure, and improving the display of the display panel Uniformity.
  • the thickness of the second etching barrier layer 82 in the direction perpendicular to the main surface 11 is equal to the thickness T1/T2 of the first electrode 21 in the direction perpendicular to the main surface 11; for example, the first electrodes 21 of the multiple sub-pixels are in the vertical direction.
  • the thickness in the direction of the main surface 11 is equal, which is beneficial to improving the display uniformity of the display panel.
  • the size of the second groove 13 in the direction parallel to the main surface 11 first gradually increases and then gradually decreases, or such that the second groove 13
  • the size in the direction parallel to the main surface 11 gradually becomes larger, so as to be more conducive to subsequent film layers of adjacent sub-pixels (charge generation layer 3, first groove 40) above the pixel definition layer 4 and in the first groove 40.
  • a light-emitting layer 61 and a hole injection layer 5) are disconnected through the second groove 13.
  • the hole injection layer 5 of the first sub-pixel 101 is formed on the side of the pixel definition layer 4 away from the substrate 1 using the same material and the same layer formation process (for example, including the same sputtering process).
  • the first part 50a and the second part 50b are located in the first groove 40. Due to the step difference formed by the communication between the fracture 40b and the second groove 13, the first part 50a and the second part 50b are spaced apart.
  • the first portion 50a and the second portion 50b of the floating hole injection layer 50 are located on the bottom surface 40a and respectively located on opposite sides of the break 40b.
  • the floating hole injection layer 50 further includes a third portion 50 c located in the second groove 13 and on a side of the first etching barrier layer 81 away from the substrate 1 .
  • the same material and the same film layer formation process are used to form the first light-emitting element of the first sub-pixel 101 on the side of the hole injection layer 5 away from the substrate 1 61.
  • the first part 60a and the second part 60b of the floating light-emitting layer 60 are located on the bottom surface 40a and respectively located on opposite sides of the break 40b.
  • the first portion 60a of the floating light-emitting layer 60 is stacked with the first portion 50a of the floating hole injection layer 50 and is located on a side of the first portion 50a of the floating hole injection layer 50 away from the substrate 1; the floating light-emitting layer 60
  • the second portion 60b is stacked with the second portion 50b of the floating hole injection layer 50 and is located on a side of the second portion 50b of the floating hole injection layer 50 away from the substrate 1 .
  • the floating light-emitting layer 60 further includes a third portion 60c located in the second groove 13 and on a side of the third portion 50c of the floating hole injection layer 50 away from the substrate 1.
  • the charge generation layer 3 and the charge generation layer 3 of the first sub-pixel 101 are formed on the side of the pixel definition layer 4 away from the substrate 1 using the same material and the same film formation process (for example, including the same sputtering process).
  • the charge generation layer 3 and the floating charge generation layer 30 of the second sub-pixel 102 are located in the second groove 13, stacked with the first etching barrier layer 81, the third portion 50c of the floating hole injection layer 50, and the third portion 60c of the floating light emitting layer 60.
  • the side of the third portion 60c of the light-emitting layer 60 away from the second bottom surface 130 is disposed.
  • the charge generation layer 3 of the first sub-pixel 101 is located on the side of the first stack part 41 away from the main surface 11, and the charge generation layer 3 of the second sub-pixel 102 is located on the side of the second stack part 42 away from the main surface 11,
  • the charge generation layer 3 of the first subpixel 101 is disconnected from the floating charge generation layer 30
  • the charge generation layer 3 of the second subpixel 102 is disconnected from the floating charge generation layer 30 .
  • the floating charge generation layer 30 includes a first part 30a and a second part 30b that are spaced apart, thereby further effectively ensuring that the charge generation layer 3 of the first sub-pixel 101 is connected to The effect is that the charge generation layer 3 of the second sub-pixel 102 is completely disconnected.
  • the second light-emitting element 62 , the second electrode 22 and the encapsulation layer 7 are sequentially formed on the side of the charge generation layer 3 away from the substrate 1 , thereby forming the display panel shown in FIG. 3 .
  • FIG. 9A-9G are schematic diagrams of a method for manufacturing the display panel shown in FIG. 5 according to an embodiment of the present disclosure.
  • the manufacturing method of the display panel will be introduced below with reference to Figures 9A-9J.
  • two adjacent sub-pixels of the display panel namely the first sub-pixel 101 and the second sub-pixel 102 are taken as an example for introduction. The same is true for other sub-pixels.
  • a substrate 1 is provided, having a main surface 11 .
  • the material of the substrate 1 is silicon oxide, silicon nitride, etc., and for example, the substrate 1 is the uppermost silicon oxide layer of the silicon-based substrate.
  • the manufacturing method of a display panel includes forming a plurality of sub-pixels on a substrate 1 , each of the plurality of sub-pixels including a light-emitting device located on the main surface 11 .
  • the manufacturing method of the display panel includes: forming a second etching barrier layer 82 on the main surface 11 , the second etching barrier layer 82 is located between the first electrode 21 of the first sub-pixel 101 and the second etching barrier layer 82 . In the interval SP of the first electrode 21 of the sub-pixel 102 .
  • the manufacturing method of the display panel includes: forming a metal electrode material layer on the main surface 11 and performing a patterning process on the metal electrode material layer to form the metal electrode layer of the first electrode 21 of the first sub-pixel 101 and the metal electrode layer of the second sub-pixel 102.
  • the metal electrode layer of the first electrode 21 and the metal electrode layer of the second etching barrier layer 82 are located between the metal electrode layer of the first electrode 21 and the second etching barrier layer 82 of the first sub-pixel 101 . between the metal electrode layers of the first electrode 21 of the sub-pixel 102 . After the metal electrode layer is formed, a transparent electrode material covering the metal electrode layer of the first electrode 21 of the first sub-pixel 101, the first electrode 21 of the second sub-pixel 102, and the second etching barrier layer 82 is formed.
  • a patterning process is performed on the transparent electrode material layer to form a transparent electrode layer 21d covering the metal electrode layer of the first electrode 21 of the first sub-pixel 101, and a transparent electrode layer 21d covering the metal electrode layer of the first electrode 21 of the second sub-pixel 102.
  • the transparent electrode layer 21d of the second etching barrier layer 82 covers the metal electrode layer thereof.
  • the metal electrode layer has a Ti/Al/Ti/ITO stacked structure.
  • the metal electrode layer includes a first sub-layer 21a, a second sub-layer 21b and a third sub-layer 21c stacked on the main surface of the substrate 1.
  • the material of the first sub-layer 21a is titanium metal. (Ti)
  • the material of the second sub-layer 21b is metal aluminum (Al)
  • the material of the third sub-layer 21c is metal titanium (Ti), thereby forming the first sub-layer 21a, the second sub-layer 21b and the third sub-layer 21c constitutes a Ti/Al/Ti/ITO stacked structure.
  • the material of the transparent electrode layer 21 is a transparent conductive material, such as ITO, IZO, etc.
  • the first electrode 21 covering the first sub-pixel 101 and the first electrode 21 of the second sub-pixel 102 are formed on the side away from the substrate 1 .
  • the first electrode 21 of the two sub-pixels 102 and the pixel-defining material layer of the second etching barrier layer 82 perform a first patterning process on the pixel-defining material layer to form a plurality of openings exposing the first electrode 21 of each sub-pixel. district.
  • a second patterning process is performed on the pixel definition material layer to form the first groove 40 .
  • the first groove 40 is located on the side of the second etching barrier layer 82 away from the substrate 1 and is exposed. At least a portion of the upper surface of the second etching barrier layer 82 away from the substrate 1 .
  • the hole injection layer 5 of the first sub-pixel 101 is formed on the side of the pixel definition layer 4 away from the substrate 1 using the same material and the same layer formation process (for example, including the same sputtering process). , the hole injection layer 5 and the floating hole injection layer 50 of the second sub-pixel 102; in the process of forming the hole injection layer 5 by deposition or sputtering, the first groove 400 is used to form the hole injection layer 5 perpendicular to the substrate.
  • the step difference in the direction of the main surface 11 of 1 may disconnect the hole injection layer 5 of the first sub-pixel 101 and the hole injection layer 5 of the second sub-pixel 102 from each other.
  • the hole injection layer 5 is stacked and in contact with the first electrode 21; the floating hole injection layer 50 is located in the first groove 400, stacked with the second etching barrier layer 82, and located in the second etching barrier layer 82.
  • the distance from the floating hole injection layer 50 to the main surface 11 is smaller than the distance from the first portion 41 of the pixel definition layer 4 to the main surface 11 and smaller than the distance from the second portion 42 of the pixel definition layer 4 to the main surface 11 , that is, The floating hole injection layer 50 exists between the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 and the upper surface of the second portion 42 away from the substrate 1 in the direction perpendicular to the main surface 11 Step difference.
  • the same material and the same layer formation process are used to form the first light-emitting element of the first sub-pixel 101 on the side of the hole injection layer 5 away from the substrate 1 61.
  • the step difference existing in each direction can disconnect the first light-emitting element 61 of the first sub-pixel 101 and the first light-emitting element 61 of the second sub-pixel 102 from each other.
  • the first light-emitting element 61 is stacked and in contact with the hole injection layer 5; the floating light-emitting layer 60 is located in the first groove 400, stacked with the floating hole injection layer 50, and located in the floating hole The side of the implant layer 50 away from the substrate 1 .
  • the distance from the floating first light-emitting layer 60 to the main surface 11 is less than the distance from the upper surface of the first portion 41 of the pixel definition layer 4 away from the substrate 1 to the main surface 11 and is less than the distance from the second portion 42 of the pixel definition layer 4
  • the distance from the upper surface away from the substrate 1 to the main surface 11 that is, the upper surface of the first portion 41 of the floating first light-emitting layer 60 and the pixel definition layer 4 away from the substrate 1 and the distance of the second portion 42 away from the substrate 1
  • the charge generation layer 3 of the first sub-pixel 101 is formed on the side of the first light-emitting element 61 away from the substrate 1 using the same material and the same film layer formation process (for example, including the same sputtering process). , the charge generation layer 3 and the floating charge generation layer 30 of the second sub-pixel 102; in the process of forming the charge generation layer 3, the first groove 400 is used to form the first groove 400 in the direction perpendicular to the main surface 11 of the substrate 1.
  • the step difference, and the upper surface of the floating first light-emitting layer 60 and the first part 41 of the pixel definition layer 4 away from the substrate 1 and the upper surface of the second part 42 away from the substrate 1 are in the direction perpendicular to the main surface 11
  • the step difference existing on both can disconnect the charge generation layer 3 of the first sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 from each other.
  • the charge generation layer 3 is stacked with the first light-emitting element 61 and the hole injection layer 5; the floating charge generation layer 30 is located in the first groove 400 and is connected with the floating first light-emitting layer 60 and the hole injection layer 5.
  • the hole injection layer 50 is stacked and located on a side of the floating first light-emitting layer 60 away from the substrate 1 .
  • the distance from the floating charge generation layer 30 to the main surface 11 is smaller than the distance from the first part 41 of the pixel definition layer 4 to the main surface 11 and smaller than the distance from the second part 42 of the pixel definition layer 4 to the main surface 11 to ensure that the The effect is that the charge generation layer 3 of one sub-pixel 101 and the charge generation layer 3 of the second sub-pixel 102 are disconnected from each other.
  • the distance from the floating charge generation layer 30 to the main surface 11 may be greater than or equal to the distance from the first part 41 of the pixel definition layer 4 to the main surface 11 and less than the distance from the second part 42 of the pixel definition layer 4 to The distance between the main surfaces 11 is sufficient as long as the charge generation layer 3 of the first subpixel 101 and the charge generation layer 3 of the second subpixel 102 are disconnected from each other.
  • the second light emitting element 62 , the second electrode 22 and the encapsulation layer 7 are sequentially formed on the side of the charge generation layer 3 away from the substrate 1 , thereby forming the display panel shown in FIG. 5 .

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Abstract

一种显示面板(10)及其制作方法、以及显示装置(1000)，该显示面板(10)包括衬底(1)、多个子像素(100)和像素界定层(4)。衬底(1)具有主表面(11)；每个子像素包括位于主表面(11)上的发光器件，发光器件包括堆叠的第一电极(21)和电荷产生层(3)，电荷产生层(3)位于第一电极的远离衬底(1)的一侧；像素界定层(4)限定出多个开口区，多个开口区与多个子像素(100)一一对应且暴露对应的子像素的第一电极(21)；多个子像素(100)中包括相邻的第一子像素(101)和第二子像素(102)，第一子像素(101)的第一电极(21)和第二子像素(102)的第一电极(21)之间存在间隔，像素界定层(4)包括位于间隔中的第一凹槽(40)，第一子像素(101)的电荷产生层(3)与第二子像素(102)的电荷产生层(3)被第一凹槽(40)间隔开；像素界定层(4)包括位于不同的相邻的两个子像素(100)之间的间隔中的多个第一凹槽(40)，多个第一凹槽(40)的深度相等。

Description

显示面板及其制作方法、以及显示装置 技术领域
本公开实施例提供一种显示面板及其制作方法、以及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板与传统的液晶显示(LCD)面板相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域，另外也广泛应用于智能手表等柔性可穿戴领域。串联型OLED显示面板中，一个子像素通常包括串联的多个发光器件。
发明内容
本公开至少一实施例提供一种显示面板，该显示面板包括衬底、多个子像素和像素界定层。衬底具有主表面；所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；像素界定层位于所述主表面上，且限定出多个开口区，所述多个开口区与所述多个子像素一一对应且暴露对应的所述子像素的第一电极的至少部分；所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
例如，在本公开至少一实施例提供的显示面板中，所述像素界定层包括：间隔部、第一堆叠部和第二堆叠部。间隔部位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；第一堆叠部在垂直于所述主表面的方向上堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；第二堆叠部在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧，所述间隔部包括所述第一凹槽。
例如，在本公开至少一实施例提供的显示面板中，所述主表面具有位于所述间隔的中间部分，所述主表面的中间部分是平坦的，所述间隔部位于所述主表面的中间部分上；所述第一凹槽具有与所述主表面基本平行的第一底面；所述显示面板还包括浮置电荷产生层，浮置电荷产生层位于所述第一凹槽中且位于所述第一底面上，且与所述第一子像素的电荷产生层和所述第二子像素的电荷产生层材料相同；所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆 叠部的远离所述主表面的一侧；所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
例如，在本公开至少一实施例提供的显示面板中，所述第一堆叠部、所述间隔部和所述第二堆叠部构成连续的一体结构；所述像素界定层的间隔部覆盖且直接接触所述第一子像素的第一电极的靠近所述第二子像素的第一电极的侧表面、所述主表面的平坦的中间部分、以及所述第二子像素的第一电极的靠近所述第一子像素的第一电极的侧表面；所述第一堆叠部覆盖且直接接触所述第一子像素的第一电极的远离所述衬底基板的上表面的一部分，所述第二堆叠部覆盖且直接接触所述第二子像素的第一电极的远离所述衬底基板的上表面的一部分。
例如，在本公开至少一实施例提供的显示面板中，所述第一子像素的电荷产生层在所述主表面上的正投影的靠近所述第二子像素的边缘与所述浮置电荷产生层在所述主表面上的正投影的靠近所述第一子像素的边缘相接，所述第二子像素的电荷产生层在所述主表面上的正投影的靠近所述第一子像素的边缘与所述浮置电荷产生层在所述主表面上的正投影的靠近所述第二子像素的边缘相接。
例如，在本公开至少一实施例提供的显示面板中，所述多个子像素的第一电极在垂直于所述主表面方向上的厚度相等，所述多个子像素中的每个的第一电极的厚度不小于450μm，所述第一凹槽在垂直于所述主表面的方向上的深度不小于900μm。
例如，在本公开至少一实施例提供的显示面板中，所述第一子像素的第一电极在垂直于所述主表面方向上的厚度与所述像素界定层在垂直于所述主表面方向上的厚度之比、以及所述第二子像素的第一电极在垂直于所述主表面方向上的厚度与所述像素界定层在垂直于所述主表面方向上的厚度之比均不小于2。
例如，在本公开至少一实施例提供的显示面板中，所述主表面具有位于所述间隔的中间部分，所述主表面的中间部分具有第二凹槽，所述像素界定层的间隔部在所述第二凹槽处具有贯穿所述间隔部的断口，所述第二凹槽与所述第一凹槽通过所述断口连通；所述第二凹槽具有与所述主表面基本平行的第二底面，所述显示面板还包括第一刻蚀阻挡层，所述第一刻蚀阻挡层位于所述第二凹槽中且位于所述第二底面上，并且，所述第一刻蚀阻挡层的材料与所述衬底的材料不同、且与所述像素界定层的材料不同；所述显示面板还包括浮置电荷产生层，浮置电荷产生层位于所述第二凹槽中且位于所述第一刻蚀阻挡层的远离所述第二底面的一侧，与所述第一子像素的电荷产生层和所述第二子像素的电荷产生层材料相同；所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧；所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
例如，在本公开至少一实施例提供的显示面板中，所述多个子像素的每个的第一电极包括在垂直于所述主表面方向上堆叠的金属电极层和透明电极层，所述透明电极层覆盖所 述金属电极层，所述第一刻蚀阻挡层与所述透明电极层材料相同且同层设置。
例如，在本公开至少一实施例提供的显示面板中，沿从所述主表面到所述第二凹槽的底面的方向，所述第二凹槽在平行于所述主表面方向上的尺寸逐渐变大，或者先逐渐增大再逐渐减小。
例如，在本公开至少一实施例提供的显示面板中，所述第二凹槽的沿垂直于所述主表面的截面的形状为梯形或不规则图形，所述不规则图形包括所述与所述主表面基本平行的底边和彼此相对且均与所述底边相交的第一侧边和第二侧边，所述第一侧边朝向远离所述第二侧边的方向凹陷，第二侧边朝向远离所述第一侧边的方向凹陷。
例如，在本公开至少一实施例提供的显示面板中，所述显示面板还包括第二刻蚀阻挡层，第二刻蚀阻挡层位于所述主表面上且位于所述间隔中，并且与所述第一子像素的第一电极和所述第二子像素的第一电极材料相同且同层间隔设置；所述第一凹槽位于所述第二刻蚀阻挡层的远离所述衬底基板的一侧，且暴露所述第二刻蚀阻挡层的远离所述衬底基板的上表面的至少部分。
例如，在本公开至少一实施例提供的显示面板中，沿从远离所述主表面到靠近所述主表面的方向，所述第一凹槽在平行于所述主表面方向上的尺寸逐渐变大，或者先逐渐增大再逐渐减小。
例如，在本公开至少一实施例提供的显示面板中，所述发光器件包括发射第一颜色的光的第一发光元件和发射第一颜色的光的第二发光元件，所述第一颜色和所述第二颜色不同，所述电荷产生层位于所述第一发光元件和所述第二发光元件之间并连接所述第一发光元件和所述第二发光元件。
本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
本公开至少一实施例还提供一种显示面板的制作方法，该制作方法包括：提供衬底，其中，所述衬底具有主表面；在所述衬底上形成多个子像素，其中，所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；以及形成像素界定层，其中，所述像素界定层位于所述主表面上，且限定出多个开口区，其中，所述多个开口区与所述多个子像素一一对应且暴露对应的所述子像素的第一电极的至少部分；所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
例如，在本公开至少一实施例提供的显示面板的制作方法中，所述主表面具有位于所 述间隔中的中间部分，所述主表面的中间部分是平坦的；形成所述第一凹槽包括：在所述主表面上形成所述第一子像素的第一电极和所述第二子像素的第一电极，其中，所述第一子像素的第一电极和所述第二子像素的第一电极暴露所述主表面的位于所述间隔中的部分；以及在所述第一子像素的第一电极和所述第二子像素的第一电极的远离所述衬底的一侧形成像素界定材料层以利用所述第一子像素的第一电极在垂直于所述主表面方向上的厚度与所述第二子像素的第一电极在垂直于所述主表面方向上的厚度而在形成所述像素界定材料层的同时形成所述第一凹槽，其中，不需要对像素界定材料层进行构图而形成第一凹槽。
例如，本公开至少一实施例提供的显示面板的制作方法中包括：对所述像素界定材料层进行构图工艺以形成所述多个开口区从而形成所述像素界定层；以及利用同一材料和同一道膜层形成工艺在所述像素界定层的远离所述衬底的一侧形成所述第一子像素的电荷产生层、所述第二子像素的电荷产生层和浮置电荷产生层，其中，所述第一凹槽具有与所述主表面基本平行的第一底面，所述浮置电荷产生层位于所述第一凹槽中且位于所述第一底面上，所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧，并且，利用所述第一凹槽在垂直于所述衬底方向上的深度使得所述第一子像素的电荷产生层与所述浮置电荷产生层断开、以及所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
例如，在本公开至少一实施例提供的显示面板的制作方法中，所述像素界定层包括间隔部、第一堆叠部和第二堆叠部。间隔部位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；第一堆叠部在垂直于所述主表面的方向上堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；第二堆叠部在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧；所述间隔部包括所述第一凹槽；所述像素界定层的间隔部覆盖且直接接触所述第一子像素的第一电极的靠近所述第二子像素的第一电极的侧表面、所述主表面的位于所述间隔的部分、以及所述第二子像素的第一电极的靠近所述第一子像素的第一电极的侧表面；所述第一堆叠部覆盖且直接接触所述第一子像素的第一电极的远离所述衬底基板的上表面的一部分，所述第二堆叠部覆盖且直接接触所述第二子像素的第一电极的远离所述衬底基板的上表面的一部分。
例如，在本公开至少一实施例提供的显示面板的制作方法中，所述主表面具有位于所述间隔的中间部分，所述制作方法包括：在所述主表面的中间部分上形成第二凹槽；形成第一刻蚀阻挡层，其中，所述第二凹槽具有与所述主表面基本平行的第二底面，所述第一刻蚀阻挡层位于所述第二凹槽中且位于所述第二底面上；形成覆盖所述第一子像素的第一电极、所述第二子像素的第一电极和所述第二凹槽的像素界定材料层；以及对所述像素界定材料层执行构图工艺以形成断口和所述开口区从而形成所述像素界定层，其中，所述像素界定层包括间隔部、第一堆叠部和第二堆叠部。间隔部位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；第一堆叠部，在垂直于所述主表面的方向上 堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；第二堆叠部在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧；所述间隔部包括所述第一凹槽；所述断口位于像素界定层的间隔部在所述第二凹槽处且贯穿所述间隔部，所述第二凹槽与所述第一凹槽通过所述断口连通。
例如，本公开至少一实施例提供的显示面板的制作方法包括：在所述主表面上形成金属电极材料层，对所述金属电极材料层执行构图工艺以形成所述第一子像素的第一电极的金属电极层和所述第二子像素的第一电极的金属电极层；以及形成覆盖所述第一子像素的第一电极的金属电极层、所述第二子像素的第一电极的金属电极层、以及所述第二底面的透明电极材料层，对所述透明电极材料层执行构图工艺以形成所述第一子像素的第一电极的覆盖其金属电极层的透明电极层、所述第二子像素的第一电极的覆盖其金属电极层的透明电极层、以及所述第一刻蚀阻挡层。
例如，本公开至少一实施例提供的显示面板的制作方法还包括：利用同一材料和同一道膜层形成工艺在所述像素界定层的远离所述衬底的一侧形成所述第一子像素的电荷产生层、所述第二子像素的电荷产生层和浮置电荷产生层，其中，所述第二凹槽具有与所述主表面基本平行的第二底面，所述浮置电荷产生层位于所述第二凹槽中且位于所述第一刻蚀阻挡层的远离所述第二底面的一侧，所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧，所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
例如，本公开至少一实施例提供的显示面板的制作方法还包括：在形成所述第二刻蚀阻挡层之后对所述第二凹槽进行刻蚀，以使得沿从所述主表面到所述第二凹槽的底面的方向，所述第二凹槽在平行于所述主表面方向上的尺寸逐渐变大，或者先逐渐增大再逐渐减小。
例如，本公开至少一实施例提供的显示面板的制作方法包括：在所述主表面上形成第二刻蚀阻挡层，其中，所述第二刻蚀阻挡层位于所述第一子像素的第一电极与所述第二子像素的第一电极的间隔中；形成覆盖所述第一子像素的第一电极、所述第二子像素的第一电极、以及所述第二刻蚀阻挡层的像素界定材料层；以及对所述像素界定材料层执行构图工艺以形成所述第一凹槽和所述多个开口区，其中，所述第一凹槽位于所述第二刻蚀阻挡层的远离所述衬底基板的一侧，且暴露所述第二刻蚀阻挡层的远离所述衬底基板的上表面的至少部分。
例如，本公开至少一实施例提供的显示面板的制作方法包括：在所述主表面上形成金属电极材料层，对所述金属电极材料层执行一次构图工艺以形成所述第一子像素的第一电极的金属电极层、所述第二子像素的第一电极的金属电极层和第二刻蚀阻挡层的金属电极层，其中，所述第二刻蚀阻挡层的金属电极层位于所述第一子像素的第一电极的金属电极层与所述第二子像素的第一电极的金属电极层之间；以及形成覆盖所述第一子像素的第一 电极的金属电极层、所述第二子像素的第一电极、以及所述第二刻蚀阻挡层的金属电极层的透明电极材料层，对所述透明电极材料层执行一次构图工艺以形成所述第一子像素的第一电极的覆盖其金属电极层的透明电极层、所述第二子像素的第一电极的覆盖其金属电极层的透明电极层、以及所述第二刻蚀阻挡层的覆盖其金属电极层的透明电极层。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是本公开一实施例提供的一种显示面板的平面示意图；
图2是沿图1中的A-A’线的截面示意图；
图3是本公开一实施例提供的另一种显示面板沿图1中的A-A’线的截面示意图；
图4是本公开一实施例提供的又一种显示面板沿图1中的A-A’线的截面示意图；
图5是本公开一实施例提供的再一种显示面板沿图1中的A-A’线的截面示意图；
图6为本公开至少一实施例提供的一种显示装置的示意图；
图7A-7H为本公开一实施例提供的一种显示面板的制作方法示意图；
图8A-8J为本公开一实施例提供的另一种显示面板的制作方法示意图；
图9A-9G为本公开一实施例提供的另一种显示面板的制作方法示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。以下所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
串联式有机发光二极管(Tandem OLED)器件存在因空穴注入层(Hole Injection Layer，HIL)以及电荷产生层(Charge Generated Layer，CGL)的电阻率较低而容易引起相邻子像素之间的串扰的问题，从而会使得OLED器件色域下降，从而采用OLED器件的OLED显示面板的显示效果下降。因此，防止相邻子像素之间的串扰对提高OLED显示面板的 显示效果非常重要。并且，在保证防止相邻子像素之间的串扰的同时，实现整个显示面板的显示均一性很重要。
本公开至少一实施例提供一种显示面板，该显示面板包括衬底、多个子像素和像素界定层。衬底具有主表面；所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；像素界定层位于所述主表面上，且限定出多个开口区，所述多个开口区与所述多个子像素一一对应且暴露对应的所述子像素的第一电极的至少部分；所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
示例性地，图1是本公开一实施例提供的一种显示面板的平面示意图，图2是沿图1中的A-A’线的截面示意图。参考图1-2，本公开至少一实施例提供的显示面板10包括：衬底1、多个子像素100和像素界定层4。衬底1具有主表面11；多个子像素100中的每个子像素包括位于主表面11上的发光器件，例如该发光器件为串联式有机发光二极管(Tandem OLED)器件；发光器件包括在垂直于主表面11的方向上堆叠的第一电极21和电荷产生层3(Charge Generated Layer，CGL)，电荷产生层3位于第一电极21的远离衬底1的一侧；像素界定层4位于主表面11上，且限定出多个开口区，多个开口区与多个子像素100一一对应且暴露对应的子像素100的第一电极21的至少部分；多个子像素100中包括相邻的第一子像素101和第二子像素102，第一子像素101的第一电极21和第二子像素102的第一电极21之间存在间隔SP，像素界定层4包括位于间隔SP中且朝向主表面11凹陷的第一凹槽40，第一子像素101的电荷产生层3与第二子像素102的电荷产生层3被第一凹槽40间隔开；像素界定层4包括位于多个子像素100中不同的相邻的两个子像素100之间的间隔SP中的多个第一凹槽40，多个第一凹槽40在垂直于主表面11方向上的深度H相等。
例如，通常会通过刻蚀衬底(例如为硅基基板)的最上方(即最靠近显示器件的一侧)的氧化硅层而在衬底的设置有OLED器件的表面形成凹槽，利用该凹槽而形成的段差来将相邻的子像素的电荷产生层断开(彼此不连接、不接触，非电连接)，但是，对硅基基板的氧化硅层刻蚀均一性难以把控，无法精准控制整个显示面板的多个子像素的凹槽在垂直于衬底方向上的深度一致，从而导致整个显示区域凹槽的刻蚀深度不均一，形成Mura不良。这种情况下，微观显示表明显示区域的部分区域的阴极在凹槽区域会形成穿刺结构，从而导致整个OLED器件形成较大漏电。然而，对于本公开实施例提供的显示面板10，在制作显示面板10的过程中，在形成第一电极21之后，在第一子像素101的第一电极 21和第二子像素102的第一电极21之间的间隔SP之间通过构图工艺(例如光刻工艺)形成第一凹槽40，然后再在形成电荷产生层3，从而利用第一凹槽40形成的在垂直于衬底1的主表面11方向上的段差将第一子像素101的OLED器件中的电荷产生层3和第二子像素102的OLED器件中的电荷产生层3彼此断开。在实际过程中，可通过控制多个子像素100的第一电极21在垂直于衬底1的主表面11的方向上的厚度一致，形状而形成的像素界定层4的厚度也是均匀一致的，从而使得在多个子像素100中，依赖于第一电极21的形状和厚度而自然形成的第一凹槽40的深度H均匀一致，由此，可以实现多个子像素100的电荷产生层3彼此断开的程度均匀一致，这对于提高采用显示面板10显示均一性具有非常重要的作用，防止Mura不良。
例如，衬底1为硅基基板，该硅基基板包括绝缘层和贯穿绝缘层的过孔V1(例如钨孔)，第一电极21通过过孔V1与连接电极12连接，连接电极12与制作于硅基基板中的像素电路的驱动晶体管的第一极连接。该像素电路该像素电路例如包括薄膜晶体管和存储电容，例如还包括数据晶体管、补偿晶体管等。例如为3T1C、7T1C、9T2C等像素电路，本公开对像素电路的具体类型不作限定。
例如，如图2所示，在每个子像素100中，第一发光元件61和第二发光元件62。第一发光元件61发射第一颜色的光，第二发光元件62发射第二颜色的光，第一颜色和第二颜色不同；电荷产生层3位于第一发光元件61和第二发光元件62之间并连接第一发光元件61和第二发光元件62，以使得激子在电场作用下发出两倍的激子量，实现两倍以上的光电转换效率。由于电荷产生层3相比于OLED器件中其他功能层的导电能力较强，因此，会在横向方向即子像素的排列方向引起像素串扰，故而需要将相邻的子像素的电荷产生层3断开，以防止相邻子像素之间的串扰。
例如，发光器件发出的光复合为白光；例如，显示面板的每个子像素100还包括彩膜，在每个子像素100中，彩膜位于发光器件的远离衬底1的一侧，由第一发光元件61和第二发光元件62所发的光复合为白光，该白光在经相应子像素100的彩膜滤光后使得不同子像素出射不同颜色的光。例如，第一颜色为黄色，第二颜色为蓝色。例如，如图1所示，三个连续的子像素100构成一个像素10a，每一个像素10a中的三个子像素100中的彩膜颜色分别为红色(R)、绿色(G)和蓝色(B)；并且三个子像素100中的第一发光元件61的发光颜色相同，均发出第一颜色的光；三个子像素100中的第二发光元件62的发光颜色的发光颜色相同，均发出第二颜色的光。在一个像素的三个子像素100中，第一颜色的光与第二颜色的光复合为白光，该白光分别经红色(R)彩膜、绿色(G)彩膜和蓝色(B)彩膜后，从三个子像素100分别出射红光、绿光和蓝光。当然，第一颜色和第二颜色不限于上述列举种类，彩膜的延伸也不限于上述列举种类，本公开对此不作限定。
例如，对于每个子像素100，第一电极21包括在垂直于主表面11方向上堆叠的金属电极层和透明电极层21d，透明电极层21d覆盖金属电极层。例如，金属电极层为Ti/Al/Ti/ITO叠层结构。即，如图2所示，金属电极层包括在衬底1的主表面上堆叠设置 的第一子层21a、第二子层21b和第三子层21c，例如第一子层21a的材料是金属钛(Ti)，第二子层21b的材料是金属铝(Al)，第三子层21c的材料是金属钛(Ti)，从而形成第一子层21a、第二子层21b和第三子层21c构成Ti/Al/Ti/ITO叠层结构。例如透明电极层21的材料为透明导电材料，例如为ITO、IZO等。
例如，多个子像素100的第一电极21在垂直于主表面11方向上的厚度T1相等，多个子像素中的每个的第一电极21的厚度不小于450μm，以保证依赖于第一电极21的厚度而形成的第一凹槽40具有足够的深度，从而保证第一子像素101和第二子像素102的OLED器件中的电荷产生层3彼此断开的效果较好，即保证相邻的子像素的电荷产生层3彼此断开的可靠性，提高显示面板的良率。
例如，第一凹槽40在垂直于主表面11的方向上的深度不小于900μm，即第一凹槽40具有足够的深度来保证第一子像素101和第二子像素102的OLED器件中的电荷产生层3彼此断开的效果较好，即保证相邻的子像素的电荷产生层3彼此断开的可靠性，提高显示面板的良率。
例如整个显示面板10的多个子像素100例如全部子像素100的第一电极21在垂直于衬底1的主表面11方向上的厚度相等，从而使得显示面板10的对多个第一凹槽40在垂直于衬底1的主表面11方向上的深度H相等。例如，在图2所示的实施例中，第一电极21在垂直于衬底1的主表面11方向上的厚度是指由金属电极层和透明电极层的厚度之和，因此，在图2所示的实施例中，第一电极21在垂直于衬底1的主表面11方向上的厚度是第一子层21a、第二子层21b和第三子层21c构成的叠层结构和透明电极层21d的在垂直于衬底1的主表面11方向上的厚度之和。
例如，如图2所示，像素界定层4包括间隔部401、第一堆叠部41和第二堆叠部42。间隔部401位于第一子像素101的第一电极21与第二子像素102的第一电极21之间的间隔SP中；第一堆叠部41在垂直于主表面11的方向上堆叠于第一子像素101的第一电极21的远离衬底1基板的一侧；第二堆叠部42在垂直于主表面11的方向上堆叠于第二子像素102的第一电极21的远离衬底1基板的一侧，间隔部401包括第一凹槽40。
例如，如图2所示，衬底1的主表面11具有位于间隔SP的中间部分1a，主表面11的中间部分1a是平坦的，即，在主表面11在间隔SP处不存在凹槽，像素界定层4的间隔部401位于主表面11的中间部分1a上；例如，整个主表面11都是平坦的。第一凹槽40具有与主表面11基本平行的第一底面40a，以保证像素界定层4的间隔部401形成于的主表面11的中间部分1a的平坦的表面上，使得第一凹槽40也具有平坦的第一底面40a，从而能够利用均一的第一凹槽40的深度形成的段差来使得第一子像素101和第二子像素102的OLED器件中的电荷产生层3彼此断开。
例如，第一凹槽40整个第一底面40a是连续的面，即不存在凹槽、开口等将第一底面40a断开，即第一底面40a是适应于主表面11的平坦的中间部分1a的形貌而形成的面。
例如，如图2所示，显示面板10还包括浮置电荷产生层30，浮置电荷产生层30位 于第一凹槽40中且位于第一底面40a上，且与第一子像素101的电荷产生层3和第二子像素102的电荷产生层3材料相同；第一子像素101的电荷产生层3位于第一堆叠部41的远离主表面11的一侧，第二子像素102的电荷产生层3位于第二堆叠部42的远离主表面11的一侧；第一子像素101的电荷产生层3与浮置电荷产生层30断开，第二子像素102的电荷产生层3与浮置电荷产生层30断开，即，利用第一凹槽40的深度形成的段差使相邻的子像素的电荷产生层3彼此断开。
例如，如图2所示，浮置电荷产生层30到主表面11的距离小于像素界定层4的第一部分41的远离衬底1的上表面到主表面11的距离且小于像素界定层4的第二部分42的远离衬底1的上表面到主表面11的距离，即，浮置电荷产生层30与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差，以保证第一子像素101的电荷产生层3与第二子像素102的电荷产生层3之间断开的效果的可靠性。
例如，如图2所示，第一堆叠部41、间隔部401和第二堆叠部42构成连续的一体结构。例如，像素界定层4的间隔部401覆盖且直接接触第一子像素101的第一电极21的靠近第二子像素102的第一电极21的侧表面、主表面11的平坦的中间部分1a、以及第二子像素102的第一电极21的靠近第一子像素101的第一电极21的侧表面；第一堆叠部41覆盖且直接接触第一子像素101的第一电极21的远离衬底1基板的上表面的一部分，第二堆叠部42覆盖且直接接触第二子像素102的第一电极21的远离衬底1基板的上表面的一部分。
例如，第一子像素101的电荷产生层3在主表面11上的正投影的靠近第二子像素102的边缘与浮置电荷产生层30在主表面11上的正投影的靠近第一子像素101的边缘相接(例如重合)，第二子像素102的电荷产生层3在主表面11上的正投影的靠近第一子像素101的边缘与浮置电荷产生层30在主表面11上的正投影的靠近第二子像素102的边缘相接(例如重合)。
例如，如图2所示，第一子像素101的第一电极21在垂直于主表面11方向上的厚度T1与像素界定层4在垂直于主表面11方向上的厚度T3之比、以及第二子像素102的第一电极21在垂直于主表面11方向上的厚度T2(例如T1＝T2)与像素界定层4在垂直于主表面11方向上的厚度T3之比均不小于2。例如，像素界定层4的第一部分41、间隔部401和第二部分42具有相同的厚度。如此，以保证在形成第一子像素101的第一电极21和第二子像素102的第一电极21之后，依赖于第一子像素101的第一电极21和第二子像素102的第一电极21的厚度和形貌而自然沉积形成的像素界定层4中的第一凹槽40具有足够的深度以使得第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开。
例如，如图2所示，发光器件还包括空穴注入层5(Hole Injection Layer，HIL)。空穴注入层5位于第一电极21的远离衬底的一侧，例如空穴注入层5与第一电极21直接接 触。沿从靠近衬底1到远离衬底1的方向，空穴注入层5、第一发光元件61、电荷产生层3和第二发光元件62依次排列。
例如，如图2所示，第一子像素101的空穴注入层5与第二子像素102的空穴注入层5彼此断开，例如在第一凹槽40处彼此间断开。由于空穴注入层5比于OLED器件中其他功能层的导电能力较强，且对OLED器件的工作性能的影响较大，因此，会在横向方向即子像素的排列方向引起像素串扰，故而需要将相邻的子空穴注入层5断开，以防止相邻子像素之间的串扰。在制作空穴注入层5的过程中，利用均一的第一凹槽40的深度形成的段差来使得第一子像素101和第二子像素102的OLED器件中的空穴注入层5彼此断开，使得多个子像素的功能层结构均一。并且，如图2所示，发光器件还包括浮置空穴注入层50，浮置空穴注入层50位于第一凹槽40中且位于第一底面40a上，例如，浮置空穴注入层50与第一底面40a接触，且与第一子像素101的空穴注入层50和第二子像素102的空穴注入层50材料相同。例如，浮置空穴注入层50到主表面11的距离小于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，即，浮置空穴注入层50与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差，以为了后续继续利用该浮置空穴注入层50与第一子像素101的空穴注入层5的段差、和浮置空穴注入层50与第一子像素101的空穴注入层5的段差使得形成于空穴注入层5的远离衬底1的一侧的第一子像素101的电荷产生层3与第二子像素102的电荷产生层3之间断开，且能够保证这两者彼此断开的可靠性。
例如，同理，发光器件还包括浮置第一发光层60，浮置第一发光层60位于第一凹槽40中且位于第一底面40a上，且与第一子像素101的第一发光元件61和第二子像素102的第一发光元件61材料相同。例如，浮置第一发光层60到主表面11的距离小于像素界定层4的第一部分41的远离衬底1的上表面到主表面11的距离且小于像素界定层4的第二部分42的远离衬底1的上表面到主表面11的距离，即，浮置第一发光层60与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差，以保证后续继续利用该浮置第一发光层60与第一子像素101的第一发光元件61的段差、和浮置第一发光层60与第一子像素101的第一发光元件61的段差使得形成于第一发光元件61的远离衬底1的一侧的第一子像素101的电荷产生层3与第二子像素102的电荷产生层3之间断开，且能够保证这两者彼此断开的可靠性。
例如，如图2所示，例如，第二发光元件62覆盖第一子像素101和第二子像素101，填充第一凹槽40且是连续的。由于第二发光元件62位于电荷产生层3的远离衬底1的一侧，因此不需要第二发光元件62在第一子像素101和第二子像素102之间的间隔SP中断开。例如，第二发光元件62的远离衬底1的表面是平坦表面，类似于平坦层。当然，在其他实施例中，第二发光元件62也可以在第一子像素101和第二子像素102之间的间 隔SP中断开。
例如，如图2所示，发光器件还包括第二电极22。例如第一电极为阳极，第二电极为阴极。例如第二电极22是至少覆盖显示面板的整个显示区的公共阴极。
例如，如图2所示，显示面板10还包括封装层7，例如封装层7可以包括无机封装层和/或有机封装层。
显示面板10的显示区域包括虚拟子像素，即浮置子像素，不执行显示功能，相邻的虚拟子像素之间也存在间隔，但是相邻的虚拟子像素之间的间隔中可以不将相邻的虚拟子像素的电荷产生层断开，也不将串联OLED的其他功能层，例如空穴注入层、第一发光元件，断开。
图3是本公开一实施例提供的另一种显示面板沿图1中的A-A’线的截面示意图。图3所示的显示面板与图2所示的显示面板具有以下区别。如图3所示，主表面11具有位于间隔SP的中间部分1a，主表面11的中间部分1a具有第二凹槽13，像素界定层4的间隔部401在第二凹槽13处具有贯穿间隔部401的断口40b，第二凹槽13与第一凹槽40通过断口40b连通；第二凹槽13具有与主表面11基本平行的第二底面130，显示面板10还包括第一刻蚀阻挡层81，第一刻蚀阻挡层81位于第二凹槽13中且位于第二底面130上，并且，第一刻蚀阻挡层81的材料与衬底1的材料不同、且与像素界定层4的材料不同。如此，可先制作得到第一刻蚀阻挡层81，然后再通过构图工艺形成像素界定层4，例如采用刻蚀例如湿刻法对在对像素界定层4进行构图的过程中，第一刻蚀阻挡层81可以阻挡刻蚀第二凹槽13的第二底面130，从而使得整个显示面板的多个第二凹槽13具有相等的深度，从而使后续形成的各个子像素的空穴注入层、电荷产生层等各个膜层具有均与一致的结构，防止Mura显示不良，提高显示面板的显示均一性。刻蚀液除了刻蚀掉用于形成像素界定层4的材料层之外会将第二凹槽13的槽壁的没有被第一刻蚀阻挡层81覆盖的部分继续进行刻蚀，包括将第二凹槽13的与其第二底面130相交的侧面13a/13b继续进行刻蚀，从而使第二凹槽13的侧面13a/13b朝向远离第一刻蚀阻挡层81的方向凹陷，更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。
例如，图3所示的衬底1的材料为氧化硅、氮化硅等，例如该衬底1为硅基基板的最上方的氧化硅层，即第二凹槽13位于硅基基板的最上方的氧化硅层中。例如，第一刻蚀阻挡层81的材料为透明导电材料，例如为ITO、IZO等。
例如，如图3所示，显示面板10还包括浮置电荷产生层30，位于第二凹槽13中且位于第一刻蚀阻挡层81的远离第二底面130的一侧，与第一子像素101的电荷产生层3和第二子像素102的电荷产生层3材料相同，第一子像素101的电荷产生层3位于第一堆叠部41的远离主表面11的一侧，第二子像素102的电荷产生层3位于第二堆叠部42的远离主表面11的一侧；第一子像素101的电荷产生层3与浮置电荷产生层30断开，第二子像素102的电荷产生层3与浮置电荷产生层30断开，以将相邻的子像素100的电荷产 生层断开。
例如，如图3所示，由于断口40b和第二凹槽13连通而形成的段差，浮置电荷产生层30包括被间隔开的第一部分30a和第二部分30b，从而进一步有效保证第一子像素101的电荷产生层3与第二子像素102的电荷产生层3彻底断开地效果。例如，浮置电荷产生层30还包括位于第二凹槽13中的第三部分30c。
例如，如图3所示，显示面板10还包括浮置空穴注入层50，浮置空穴注入层50包括第一部分50a和第二部分50b，第一部分50a和第二部分50b位于第一凹槽40中，由于断口40b和第二凹槽13连通而形成的段差，第一部分50a与第二部分50b被间隔开。浮置空穴注入层50的第一部分50a和第二部分50b位于底面40a上且分别位于断口40b的相对的两侧。浮置空穴注入层50的第一部分50a与浮置电荷产生层30的第一部分30a堆叠，且位于浮置电荷产生层30的第一部分30a的靠近像素界定层4的间隔部401的一侧；浮置空穴注入层50的第二部分50b与浮置电荷产生层30的第二部分30b堆叠，且位于浮置电荷产生层30的第二部分30b的靠近像素界定层4的间隔部401的一侧。例如，浮置空穴注入层50还包括第三部分50c，第三部分50c位于第二凹槽13中，且位于第一刻蚀阻挡层81与浮置电荷产生层30的第三部分30c之间。
例如，如图3所示，显示面板10还包括浮置发光层60，浮置发光层60包括第一部分60a和第二部分60b，第一部分60a和第二部分60b位于第一凹槽40中，由于断口40b和第二凹槽13连通而形成的段差，第一部分60a与第二部分60b被间隔开。浮置发光层60的第一部分60a和第二部分60b位于底面40a上且分别位于断口40b的相对的两侧。浮置发光层60的第一部分60a与浮置电荷产生层30的第一部分30a、浮置空穴注入层50的第一部分50a堆叠，且位于浮置电荷产生层30的第一部分30a与浮置空穴注入层50的第一部分50a之间；浮置发光层60的第二部分60b与浮置电荷产生层30的第二部分30b、浮置空穴注入层50的第二部分50b堆叠，且位于浮置电荷产生层30的第二部分30b与浮置空穴注入层50的第二部分50b之间。例如，浮置发光层60还包括第三部分60c，第三部分60c位于第二凹槽13中且位于浮置空穴注入层50的第三部分50c与浮置电荷产生层30的第三部分30c之间。
例如，如图3所示，多个子像素的每个的第一电极21包括在垂直于主表面11方向上堆叠的金属电极层和透明电极层21d，透明电极层21d覆盖金属电极层，第一刻蚀阻挡层81与透明电极层21d材料相同且同层设置。例如，金属电极层为Ti/Al/Ti/ITO叠层结构。第一刻蚀阻挡层81与透明电极层21d材料相同且同层设置，从而，可通过对同一膜层执行同一次构图工艺以形成第一刻蚀阻挡层81与透明电极层21d。第一电极21的具体结构与图2中的相同，具体可参考之前的描述。
例如，如图3所示，沿从主表面11到第二凹槽13的底面130的方向，第二凹槽13在平行于主表面11方向上的尺寸先逐渐增大再逐渐减小，以更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、 空穴注入层5)通过第二凹槽13断开。
例如，如上所述，在图3所示的显示面板10中，第二凹槽13的侧面13a/13b朝向远离第一刻蚀阻挡层81的方向凹陷，更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。第二凹槽13的沿垂直于主表面11的截面的形状为不规则图形，不规则图形包括与主表面11基本平行的底边130和彼此相对且均与底边相交的第一侧边13a和第二侧边13b，第一侧边13a朝向远离第二侧边13b的方向凹陷，第二侧边13b朝向远离第一侧边13a的方向凹陷。
图3所示的实施例的其他未提及的特征均与图2所示的实施例相同，可参考对图2所示的实施例的描述。
图4是本公开一实施例提供的又一种显示面板沿图1中的A-A’线的截面示意图。图4所示的显示面板与图3所示的显示面板具有以下区别。如图4所示，例如，沿从主表面11到第二凹槽13的底面130的方向，第二凹槽13在平行于主表面11方向上的尺寸逐渐变大；例如，第二凹槽13的沿垂直于主表面11的截面的形状为梯形，以更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。当然，第二凹槽13的沿垂直于主表面11的截面的形状不限于梯形，只要沿从主表面11到第二凹槽13的底面130的方向，第二凹槽13在平行于主表面11方向上的尺寸逐渐变大即可。
图4所示的实施例的其他未提及的特征均与图3所示的实施例相同，可参考对图3所示的实施例的描述。
图5是本公开一实施例提供的再一种显示面板沿图1中的A-A’线的截面示意图。图5所示的显示面板与图2所示的显示面板具有以下区别。如图5所示，例如，显示面板10包括第二刻蚀阻挡层82，第二刻蚀阻挡层82位于主表面11上且位于间隔SP中，并且与第一子像素101的第一电极21和第二子像素102的第一电极21材料相同且同层间隔SP设置；第一凹槽400位于第二刻蚀阻挡层82的远离衬底1基板的一侧，且暴露第二刻蚀阻挡层82的远离衬底1基板的上表面的至少部分。从而，可利用第一凹槽400形成的在垂直于衬底1的主表面11方向上的段差将第一子像素101的OLED器件中的电荷产生层3和第二子像素102的OLED器件中的电荷产生层3彼此断开。并且，第二刻蚀阻挡层82具有固定的厚度，且可阻止在后续刻蚀工艺中例如刻蚀形成像素界定层4的过程中对衬底1的被第二刻蚀阻挡层82遮挡的部分进行刻蚀，从而可通过控制相邻的子像素100之间的第二刻蚀阻挡层82在垂直于主表面11方向上的厚度相等，来实现相邻的子像素100之间的第一凹槽400具有相同的深度，从而保证后续形成的多个子像素的功能层结构均一，防止Mura不良，提高显示面板的显示均一性。
例如，第二刻蚀阻挡层82在垂直于主表面11方向上的厚度与第一电极21在垂直于主表面11方向上的厚度T1/T2相等；例如多个子像素的第一电极21在垂直于主表面11 方向上的厚度相等，有利于提高显示面板的显示均一性。
例如，第一子像素101的空穴注入层5与第二子像素102的空穴注入层5彼此断开，例如在第一凹槽400处彼此间断开；第一子像素101的第一发光元件61与第二子像素102的第一发光元件61在例如第一凹槽400处彼此间断开。沿从靠近衬底1到远离衬底1的方向，空穴注入层5、第一发光元件61、电荷产生层3和第二发光元件62依次排列。浮置空穴注入层50、浮置发光层60和浮置电荷产生层30位于第一凹槽400中，且依次堆叠于第二刻蚀阻挡层82的远离衬底1的表面上。第一子像素101和第二子像素102的空穴注入层5彼此被第一凹槽400断开、第一子像素101和第二子像素102的第一发光元件61彼此被第一凹槽400断开。空穴注入层5、第一发光元件61、电荷产生层3和第二发光元件62依次排列。例如，第二发光元件62覆盖第一子像素101和第二子像素101，填充部分第一凹槽400且是连续的。例如，在其他实施例中，第二发光元件62也可以填充整个第一凹槽400。第二发光元件62的其他特征与图2中的类似。
例如，浮置电荷产生层30到主表面11的距离小于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，以保证第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开的效果。当然，在其他实施例中，浮置电荷产生层30到主表面11的距离可以大于或等于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，只要第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开即可。
例如，第二刻蚀阻挡层82在平行于主表面11方向上的尺寸小于的第一电极21在平行于主表面11同一方向上的尺寸，且小于第二子像素102的第一电极21在平行于主表面11同一方向上的尺寸，以节省空间，满足高PPI的要求。
例如，沿从远离主表面11到靠近主表面11的方向，第一凹槽400在平行于主表面11方向上的尺寸先逐渐增大再逐渐减小，以更加有利于使得在像素界定层4之上的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。
或者，在其他实施例中，第一凹槽400在平行于主表面11方向上的尺寸逐渐变大，以更加有利于使得在像素界定层4之上的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。例如第一凹槽的沿垂直于主表面11的截面的形状为梯形，当然不限于是梯形。
图5所示的实施例的其他未提及的特征均图2与图3所示的实施例相同，可参考对图2和图3所示的实施例的描述。
图6是本公开至少一实施例提供的显示装置示意图。如图6所示，本公开至少一实施例还提供一种显示装置1000，该显示装置1000包括本公开实施例提供的任意一种显示面板10。该显示装置1000例如可以为串联式有机发光二极管显示装置等具有显示功能的装置或其他类型的装置。本公开的实施例对此不作限制。
本公开实施例提供的显示装置的结构、功能及技术效果等可以参考上述本公开实施例 提供的显示面板10中的相应描述，在此不再赘述。
例如，本公开至少一实施例提供的显示装置1000可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开的实施例对此不作限制。
本公开至少一实施例还提供一种显示面板的制作方法，该制作方法包括：提供衬底，所述衬底具有主表面；在所述衬底上形成多个子像素，所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；以及所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
例如，图7A-7H为本公开一实施例提供的图2所示的显示面板的制作方法示意图，下面结合图7A-7H对该显示面板的制作方法进行介绍。这里以显示面板的两个相邻的子像素，即第一子像素101和第二子像素102为例进行介绍，对于其他的子像素也是如此。
如图7A所示，提供衬底1，衬底1具有主表面11。例如衬底1的材料为氧化硅、氮化硅等，例如该衬底1为硅基基板的最上方的氧化硅层。显示面板的制作方法包括在衬底1上形成多个子像素，多个子像素中的每个子像素包括位于主表面11上的发光器件；在主表面11上形成金属电极材料层，例如金属电极材料层包括多个堆叠的多个金属层，对金属电极材料层执行构图工艺以形成第一子像素101的第一电极21的金属电极层和第二子像素102的第一电极21的金属电极层。例如，金属电极层为Ti/Al/Ti/ITO叠层结构。即，如图7A所示，金属电极层包括在衬底1的主表面上堆叠设置的第一子层21a、第二子层21b和第三子层21c，例如第一子层21a的材料是金属钛(Ti)，第二子层21b的材料是金属铝(Al)，第三子层21c的材料是金属钛(Ti)，从而形成第一子层21a、第二子层21b和第三子层21c构成Ti/Al/Ti/ITO叠层结构。第一子像素101的第一电极21和第二子像素102的第一电极21之间存在间隔SP，主表面11具有位于间隔SP中的中间部分1a，主表面11的中间部分1a是平坦的，第一子像素101的第一电极21和第二子像素102的第一电极21暴露主表面11的位于间隔SP中的部分。
如图7B所示，通过第二次构图工艺形成第一电极21的透明电极层21d，透明电极层21d覆盖金属电极层。例如透明电极层21的材料为透明导电材料，例如为ITO、IZO等。
如图7C所示，形成像素界定层4，像素界定层4位于主表面11上，像素界定层4包括位于间隔SP中且朝向主表面11凹陷的第一凹槽40，第一子像素101的电荷产生层3与第二子像素102的电荷产生层3被第一凹槽40间隔SP开；例如，像素界定层4包括 多个第一凹槽40，多个子像素存在多个间隔SP，多个第一凹槽40分别一一一对应的方式位于多个间隔SP中，即像素界定层4包括位于多个子像素中不同的相邻的两个子像素之间的间隔SP中的多个第一凹槽40，多个第一凹槽40在垂直于主表面11方向上的深度H相等。例如，形成第一凹槽40包括：在主表面11上形成第一子像素101的第一电极21和第二子像素102的第一电极21之后，在第一子像素101的第一电极21和第二子像素102的第一电极21的远离衬底1的一侧形成像素界定材料层以利用第一子像素101的第一电极21在垂直于主表面11方向上的厚度T1与第二子像素102的第一电极21在垂直于主表面11方向上的厚度T2(例如T1＝T2)而在形成像素界定材料层的同时形成第一凹槽40，不需要对像素界定材料层进行构图而形成第一凹槽40。例如采用沉积的方法形成像素界定材料层。并且，对像素界定层4进行构图工艺以形成多个开口区从而形成像素界定层4，多个开口区与多个子像素100一一对应且暴露对应的子像素100的第一电极21的至少部分。
例如，像素界定层4包括间隔部401、第一堆叠部41和第二堆叠部42。间隔部401位于第一子像素101的第一电极21与第二子像素102的第一电极21之间的间隔SP中；第一堆叠部41在垂直于主表面11的方向上堆叠于第一子像素101的第一电极21的远离衬底1基板的一侧；第二堆叠部42在垂直于主表面11的方向上堆叠于第二子像素102的第一电极21的远离衬底1基板的一侧，间隔部401包括第一凹槽40；像素界定层4的间隔部401覆盖且直接接触第一子像素101的第一电极21的靠近第二子像素102的第一电极21的侧表面、主表面11的位于间隔SP的部分、以及第二子像素102的第一电极21的靠近第一子像素101的第一电极21的侧表面；第一堆叠部41覆盖且直接接触第一子像素101的第一电极21的远离衬底1基板的上表面的一部分，第二堆叠部42覆盖且直接接触第二子像素102的第一电极21的远离衬底1基板的上表面的一部分。
接着，如图7D所示，利用同一材料和同一道膜层形成工艺(例如为同一道溅射工艺)在像素界定层4的远离衬底1的一侧形成第一子像素101的空穴注入层5、第二子像素102的空穴注入层5和浮置空穴注入层50；第一凹槽40具有与主表面11基本平行的第一底面40a，浮置空穴注入层50位于第一凹槽40中且位于第一底面40a上，第一子像素101的空穴注入层5位于第一堆叠部41的远离主表面11的一侧，第二子像素102的空穴注入层5位于第二堆叠部42的远离主表面11的一侧，并且，利用第一凹槽40在垂直于衬底1方向上的深度H使得第一子像素101的空穴注入层5与浮置空穴注入层50断开、以及第二子像素102的空穴注入层5与浮置空穴注入层50断开。从而能够利用均一的第一凹槽40的深度形成的段差来使得多个子像素100中相邻的子像素的空穴注入层5彼此断开得情况一致。
例如，浮置空穴注入层50到主表面11的距离小于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，即，浮置空穴注入层50与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底 1的上表面之间在垂直于主表面11的方向上均存在段差。
接着，如图7E所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺等)在空穴注入层5的远离衬底1的一侧形成第一子像素101的第一发光元件61、第二子像素102的第一发光元件61和浮置第一发光层60；第一凹槽40具有与主表面11基本平行的第一底面40a，浮置第一发光层60位于第一凹槽40中与浮置空穴注入层50堆叠，并且，利用第一凹槽40在垂直于衬底1方向上的深度H使得第一子像素101的第一发光元件61与浮置第一发光层60断开、以及第二子像素102的第一发光元件61与浮置第一发光层60断开，也即，利用该浮置空穴注入层50与第一子像素101的空穴注入层5的段差、和浮置空穴注入层50与第一子像素101的空穴注入层5的段差使得形成于空穴注入层5的远离衬底1的一侧的第一子像素101的第一发光元件61与第二子像素102的第一发光元件61之间断开。例如，浮置第一发光层60到主表面11的距离小于像素界定层4的第一部分41的远离衬底1的上表面到主表面11的距离且小于像素界定层4的第二部分42的远离衬底1的上表面到主表面11的距离，即，浮置第一发光层60与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差。
接着，如图7F所示，利用同一材料和同一道膜层形成工艺(例如为同一道溅射工艺)在像素界定层4的远离衬底1的一侧形成第一子像素101的电荷产生层3、第二子像素102的电荷产生层3和浮置电荷产生层30；第浮置电荷产生层30位于第一凹槽40中且与浮置空穴注入层50和浮置第一发光层60堆叠于第一底面40a上；第一子像素101的电荷产生层3位于第一堆叠部41的远离主表面11的一侧，第二子像素102的电荷产生层3位于第二堆叠部42的远离主表面11的一侧，并且，利用第一凹槽40在垂直于衬底1方向上的深度H使得第一子像素101的电荷产生层3与浮置电荷产生层30断开、以及第二子像素102的电荷产生层3与浮置电荷产生层30断开，也即，利用该浮置第一发光层60与第一子像素101的第一发光元件61的段差、和浮置第一发光层60与第一子像素101的第一发光元件61的段差使得形成于第一发光元件61的远离衬底1的一侧的第一子像素101的电荷产生层3与第二子像素102的电荷产生层3之间断开，且能够保证这两者彼此断开的可靠性。
如图7G所示，形成第二发光元件62，例如，第二发光元件62覆盖第一子像素101和第二子像素101，填充第一凹槽40且是连续的。由于第二发光元件62位于电荷产生层3的远离衬底1的一侧，因此不需要第二发光元件62在第一子像素101和第二子像素102之间的间隔SP中断开。例如，第二发光元件62的远离衬底1的表面是平坦表面，类似于平坦层。当然，在其他实施例中，第二发光元件62也可以在第一子像素101和第二子像素102之间的间隔SP中断开。
如图7G所示，依次形成发光器件的第二电极2和封装层7，从而形成图2所示的显示面板。
图8A-8J为本公开一实施例提供的图5所示的显示面板的制作方法示意图。下面结合图8A-8J对该显示面板的制作方法进行介绍。这里以显示面板的两个相邻的子像素，即第一子像素101和第二子像素102为例进行介绍，对于其他的子像素也是如此。
如图8A所示，提供衬底1，衬底1具有主表面11。例如衬底1的材料为氧化硅、氮化硅等，例如该衬底1为硅基基板的最上方的氧化硅层。显示面板的制作方法包括在衬底1上形成多个子像素，多个子像素中的每个子像素包括位于主表面11上的发光器件；在主表面11上形成金属电极材料层(未示出)，例如金属电极材料层包括多个堆叠的多个金属层，对金属电极材料层执行构图工艺以形成第一子像素101的第一电极21的金属电极层和第二子像素102的第一电极21的金属电极层。具体与图7A所示的工序相同，请参考之前的描述。
如图8B所示，在主表面11的中间部分1a上形成第二凹槽13。
如图8C所示，形成第一刻蚀阻挡层81，第二凹槽13具有与主表面11基本平行的第二底面130，第一刻蚀阻挡层81位于第二凹槽13中且位于第二底面130上。形成第一刻蚀阻挡层81包括：形成覆盖第一子像素101的第一电极21的金属电极层、第二子像素102的第一电极21的金属电极层、以及第二底面130的透明电极材料层(未示出)，对透明电极材料层执行一道构图工艺以形成第一子像素101的第一电极21的覆盖其金属电极层的透明电极层21d、第二子像素102的第一电极21的覆盖其金属电极层的透明电极层21d、以及第一刻蚀阻挡层81，以充分利用透明电极层21d与第一刻蚀阻挡层81的功能和位置关系，利用对同一膜层执行同一道构图工艺形成透明电极层21d与第一刻蚀阻挡层8，节省了工艺步骤，无需为了设置第一刻蚀阻挡层81而额外增添构图工艺。
如图8D所示，形成覆盖第一子像素101的第一电极21、第二子像素102的第一电极21和第二凹槽13的像素界定材料层40-1。
如图8E所示，对像素界定材料层40-1执行构图工艺以形成断口40b和开口区从而形成像素界定层4，像素界定层4包括间隔部401、第一堆叠部41和第二堆叠部42。间隔部401位于第一子像素101的第一电极21与第二子像素102的第一电极21之间的间隔SP中；第一堆叠部41在垂直于主表面11的方向上堆叠于第一子像素101的第一电极21的远离衬底1基板的一侧；第二堆叠部42在垂直于主表面11的方向上堆叠于第二子像素102的第一电极21的远离衬底1基板的一侧，间隔部401包括第一凹槽40；断口40b位于像素界定层4的间隔部401在第二凹槽13处且贯穿间隔部401，第二凹槽13与第一凹槽40通过断口40b连通。例如采用刻蚀例如湿刻法对在对像素界定层4进行构图的过程中，第一刻蚀阻挡层81可以阻挡刻蚀第二凹槽13的第二底面130，从而使得整个显示面板的多个第二凹槽13具有相等的深度，从而使后续形成的各个子像素的空穴注入层、电荷产生层等各个膜层具有均与一致的结构，防止Mura显示不良，提高显示质量。刻蚀液除了刻蚀掉用于形成像素界定层4的材料层之外会将第二凹槽13的槽壁的没有被第一刻蚀阻挡层81覆盖的部分继续进行刻蚀，包括将第二凹槽13的与其第二底面130相交的侧 面13a/13b继续进行刻蚀，从而使第二凹槽13的侧面13a/13b朝向远离第一刻蚀阻挡层81的方向凹陷，更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)断开。即，在形成第二刻蚀阻挡层82之后对第二凹槽13进行刻蚀，第二刻蚀阻挡层82具有固定的厚度，且可阻止在后续刻蚀工艺中例如刻蚀形成像素界定层4的过程中对衬底1的被第二刻蚀阻挡层82遮挡的部分进行刻蚀，从而可通过控制相邻的子像素100之间的第二刻蚀阻挡层82在垂直于主表面11方向上的厚度相等，来实现相邻的子像素100之间的第一凹槽400具有相同的深度，从而保证后续形成的多个子像素的功能层结构均一，防止Mura不良，提高显示面板的显示均一性。
例如，第二刻蚀阻挡层82在垂直于主表面11方向上的厚度与第一电极21在垂直于主表面11方向上的厚度T1/T2相等；例如多个子像素的第一电极21在垂直于主表面11方向上的厚度相等，有利于提高显示面板的显示均一性。
例如，使得沿从主表面11到第二凹槽13的底面的方向，第二凹槽13在平行于主表面11方向上的尺寸先逐渐增大再逐渐减小，或者使得第二凹槽13在平行于主表面11方向上的尺寸逐渐变大，以更加有利于后续使得在像素界定层4之上、第一凹槽40之中的相邻子像素的膜层(电荷产生层3、第一发光层61、空穴注入层5)通过第二凹槽13断开。
如图8F所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在像素界定层4的远离衬底1的一侧形成第一子像素101的空穴注入层5、第二子像素102的空穴注入层5和浮置空穴注入层50；第二凹槽13具有与主表面11基本平行的第二底面130，浮置空穴注入层50包括第一部分50a和第二部分50b，第一部分50a和第二部分50b位于第一凹槽40中，由于断口40b和第二凹槽13连通而形成的段差，第一部分50a与第二部分50b被间隔开。浮置空穴注入层50的第一部分50a和第二部分50b位于底面40a上且分别位于断口40b的相对的两侧。例如，浮置空穴注入层50还包括第三部分50c，第三部分50c位于第二凹槽13中，且位于第一刻蚀阻挡层81的远离衬底1的一侧。
如图8G所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在空穴注入层5的远离衬底1的一侧形成第一子像素101的第一发光元件61、第二子像素102的第一发光元件61和浮置发光层60；浮置发光层60包括第一部分60a和第二部分60b，第一部分60a和第二部分60b位于第二凹槽13中，由于断口40b和第二凹槽13连通而形成的段差，第一部分60a与第二部分60b被间隔开。浮置发光层60的第一部分60a和第二部分60b位于底面40a上且分别位于断口40b的相对的两侧。浮置发光层60的第一部分60a与浮置空穴注入层50的第一部分50a堆叠，且位于浮置空穴注入层50的第一部分50a的远离衬底1的一侧；浮置发光层60的第二部分60b与浮置空穴注入层50的第二部分50b堆叠，且位于浮置空穴注入层50的第二部分50b的远离衬底1的一侧。例如，浮置发光层60还包括第三部分60c，第三部分60c位于第二凹槽13中且位于浮置空穴注 入层50的第三部分50c的远离衬底1的一侧。
如图8H所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在像素界定层4的远离衬底1的一侧形成第一子像素101的电荷产生层3、第二子像素102的电荷产生层3和浮置电荷产生层30。浮置电荷产生层30位于第二凹槽13中，与第一刻蚀阻挡层81、浮置空穴注入层50的第三部分50c、浮置发光层60的第三部分60c堆叠，位于浮置发光层60的第三部分60c的远离第二底面130的一侧。第一子像素101的电荷产生层3位于第一堆叠部41的远离主表面11的一侧，第二子像素102的电荷产生层3位于第二堆叠部42的远离主表面11的一侧，第一子像素101的电荷产生层3与浮置电荷产生层30断开，第二子像素102的电荷产生层3与浮置电荷产生层30断开。由于断口40b和第二凹槽13连通而形成的段差，浮置电荷产生层30包括被间隔开的第一部分30a和第二部分30b，从而进一步有效保证第一子像素101的电荷产生层3与第二子像素102的电荷产生层3彻底断开地效果。
如图8I-8J所示，依次在电荷产生层3的远离衬底1的一侧形成第二发光元件62、第二电极22和封装层7，从而形成图3所示的显示面板。
图9A-9G为本公开一实施例提供的图5所示的显示面板的制作方法示意图。下面结合图9A-9J对该显示面板的制作方法进行介绍。这里以显示面板的两个相邻的子像素，即第一子像素101和第二子像素102为例进行介绍，对于其他的子像素也是如此。
如图9A所示，提供衬底1，衬底1具有主表面11。例如衬底1的材料为氧化硅、氮化硅等，例如该衬底1为硅基基板的最上方的氧化硅层。显示面板的制作方法包括在衬底1上形成多个子像素，多个子像素中的每个子像素包括位于主表面11上的发光器件。
例如，如图9A所示，显示面板的制作方法包括：在主表面11上形成第二刻蚀阻挡层82，第二刻蚀阻挡层82位于第一子像素101的第一电极21与第二子像素102的第一电极21的间隔SP中。显示面板的制作方法包括：在主表面11上形成金属电极材料层，对金属电极材料层执行一次构图工艺以形成第一子像素101的第一电极21的金属电极层、第二子像素102的第一电极21的金属电极层和第二刻蚀阻挡层82的金属电极层，第二刻蚀阻挡层82的金属电极层位于第一子像素101的第一电极21的金属电极层与第二子像素102的第一电极21的金属电极层之间。形成金属电极层后，形成覆盖第一子像素101的第一电极21的金属电极层、第二子像素102的第一电极21、以及第二刻蚀阻挡层82的金属电极层的透明电极材料层，对透明电极材料层执行一次构图工艺以形成第一子像素101的第一电极21的覆盖其金属电极层的透明电极层21d、第二子像素102的第一电极21的覆盖其金属电极层的透明电极层21d、以及第二刻蚀阻挡层82的覆盖其金属电极层的透明电极层21d。该设计充分利用了原有的第一电极的位置和结构，对用于制作第一电极的材料层执行同一次构图工艺形成第二刻蚀阻挡层82，因此，不需要为设置第二刻蚀阻挡层82而单独增加构图工艺，简化了显示面板的制作工艺。
例如，金属电极层为Ti/Al/Ti/ITO叠层结构。如图9A所示，金属电极层包括在衬底 1的主表面上堆叠设置的第一子层21a、第二子层21b和第三子层21c，例如第一子层21a的材料是金属钛(Ti)，第二子层21b的材料是金属铝(Al)，第三子层21c的材料是金属钛(Ti)，从而形成第一子层21a、第二子层21b和第三子层21c构成Ti/Al/Ti/ITO叠层结构。例如透明电极层21的材料为透明导电材料，例如为ITO、IZO等。
如图9B所示，在第一子像素101的第一电极21和第二子像素102的第一电极21的远离衬底1的一侧形成覆盖第一子像素101的第一电极21、第二子像素102的第一电极21、以及第二刻蚀阻挡层82的像素界定材料层，对像素界定材料层执行第一次构图工艺以形成暴露各个子像素的第一电极21的多个开口区。
如图9C所示，对像素界定材料层执行第二次构图工艺以形成第一凹槽40，第一凹槽40位于第二刻蚀阻挡层82的远离衬底1基板的一侧，且暴露第二刻蚀阻挡层82的远离衬底1基板的上表面的至少部分。
如图9D所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在像素界定层4的远离衬底1的一侧形成第一子像素101的空穴注入层5、第二子像素102的空穴注入层5和浮置空穴注入层50；在通过沉积或溅射形成空穴注入层5的过程中，利用第一凹槽400形成的在垂直于衬底1的主表面11方向上的段差可将第一子像素101的空穴注入层5和第二子像素102的空穴注入层5彼此断开。在每个子像素中，空穴注入层5与第一电极21堆叠且接触；浮置空穴注入层50位于第一凹槽400中，与第二刻蚀阻挡层82堆叠，且位于第二刻蚀阻挡层82的远离衬底1的一侧。例如，浮置空穴注入层50到主表面11的距离小于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，即，浮置空穴注入层50与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差。
如图9E所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在空穴注入层5的远离衬底1的一侧形成第一子像素101的第一发光元件61、第二子像素102的第一发光元件61和浮置发光层60；在形成第一发光元件61的过程中，利用第一凹槽400形成的在垂直于衬底1的主表面11方向上的段差、以及浮置空穴注入层50与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在的段差，可将第一子像素101的第一发光元件61和第二子像素102的第一发光元件61彼此断开。在每个子像素中，第一发光元件61与空穴注入层5堆叠且接触；浮置发光层60位于第一凹槽400中，与浮置空穴注入层50堆叠，且位于浮置空穴注入层50的远离衬底1的一侧。例如，浮置第一发光层60到主表面11的距离小于像素界定层4的第一部分41的远离衬底1的上表面到主表面11的距离且小于像素界定层4的第二部分42的远离衬底1的上表面到主表面11的距离，即，浮置第一发光层60与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在段差。
如图9F所示，利用同一材料和同一道膜层形成工艺(例如包括同一道溅射工艺)在第一发光元件61的远离衬底1的一侧形成第一子像素101的电荷产生层3、第二子像素102的电荷产生层3和浮置电荷产生层30；在形成电荷产生层3的过程中，利用第一凹槽400形成的在垂直于衬底1的主表面11方向上的段差、以及浮置第一发光层60与像素界定层4的第一部分41的远离衬底1的上表面和第二部分42的远离衬底1的上表面之间在垂直于主表面11的方向上均存在的段差，可将第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开。在每个子像素中，电荷产生层3与、第一发光元件61和空穴注入层5堆叠；浮置电荷产生层30位于第一凹槽400中，与浮置第一发光层60和浮置空穴注入层50堆叠，且位于浮置第一发光层60的远离衬底1的一侧。例如，浮置电荷产生层30到主表面11的距离小于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，以保证第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开的效果。当然，在其他实施例中，浮置电荷产生层30到主表面11的距离可以大于或等于像素界定层4的第一部分41到主表面11的距离且小于像素界定层4的第二部分42到主表面11的距离，只要第一子像素101的电荷产生层3和第二子像素102的电荷产生层3彼此断开即可。
如图9G所示，依次在电荷产生层3的远离衬底1的一侧形成第二发光元件62、第二电极22和封装层7，从而形成图5所示的显示面板。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围根据权利要求书所界定的范围确定。

Claims (25)

  1. 一种显示面板，包括：
    衬底，具有主表面；
    多个子像素，其中，所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；以及
    像素界定层，位于所述主表面上，且限定出多个开口区，其中，所述多个开口区与所述多个子像素一一对应且暴露对应的所述子像素的第一电极的至少部分；
    所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；
    所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
  2. 根据权利要求1所述的显示面板，其中，所述像素界定层包括：
    间隔部，位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；
    第一堆叠部，在垂直于所述主表面的方向上堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；以及
    第二堆叠部，在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧，其中，所述间隔部包括所述第一凹槽。
  3. 根据权利要求2所述的显示面板，其中，所述主表面具有位于所述间隔的中间部分，所述主表面的中间部分是平坦的，所述间隔部位于所述主表面的中间部分上；所述第一凹槽具有与所述主表面基本平行的第一底面；
    所述显示面板还包括：
    浮置电荷产生层，位于所述第一凹槽中且位于所述第一底面上，且与所述第一子像素的电荷产生层和所述第二子像素的电荷产生层材料相同，其中，
    所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧；
    所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
  4. 根据权利要求3所述的显示面板，其中，所述第一堆叠部、所述间隔部和所述第二堆叠部构成连续的一体结构；
    所述像素界定层的间隔部覆盖且直接接触所述第一子像素的第一电极的靠近所述第 二子像素的第一电极的侧表面、所述主表面的平坦的中间部分、以及所述第二子像素的第一电极的靠近所述第一子像素的第一电极的侧表面；
    所述第一堆叠部覆盖且直接接触所述第一子像素的第一电极的远离所述衬底基板的上表面的一部分，所述第二堆叠部覆盖且直接接触所述第二子像素的第一电极的远离所述衬底基板的上表面的一部分。
  5. 根据权利要求3或4所述的显示面板，其中，所述第一子像素的电荷产生层在所述主表面上的正投影的靠近所述第二子像素的边缘与所述浮置电荷产生层在所述主表面上的正投影的靠近所述第一子像素的边缘相接，所述第二子像素的电荷产生层在所述主表面上的正投影的靠近所述第一子像素的边缘与所述浮置电荷产生层在所述主表面上的正投影的靠近所述第二子像素的边缘相接。
  6. 根据权利要求3-5任一所述的显示面板，其中，所述多个子像素的第一电极在垂直于所述主表面方向上的厚度相等，所述多个子像素中的每个的第一电极的厚度不小于450μm，所述第一凹槽在垂直于所述主表面的方向上的深度不小于900μm。
  7. 根据权利要求3-6任一所述的显示面板，其中，所述第一子像素的第一电极在垂直于所述主表面方向上的厚度与所述像素界定层在垂直于所述主表面方向上的厚度之比、以及所述第二子像素的第一电极在垂直于所述主表面方向上的厚度与所述像素界定层在垂直于所述主表面方向上的厚度之比均不小于2。
  8. 根据权利要求2所述的显示面板，其中，所述主表面具有位于所述间隔的中间部分，所述主表面的中间部分具有第二凹槽，所述像素界定层的间隔部在所述第二凹槽处具有贯穿所述间隔部的断口，所述第二凹槽与所述第一凹槽通过所述断口连通；
    所述第二凹槽具有与所述主表面基本平行的第二底面，所述显示面板还包括第一刻蚀阻挡层，所述第一刻蚀阻挡层位于所述第二凹槽中且位于所述第二底面上，并且，所述第一刻蚀阻挡层的材料与所述衬底的材料不同、且与所述像素界定层的材料不同；
    所述显示面板还包括：
    浮置电荷产生层，位于所述第二凹槽中且位于所述第一刻蚀阻挡层的远离所述第二底面的一侧，与所述第一子像素的电荷产生层和所述第二子像素的电荷产生层材料相同，其中，
    所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧；
    所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
  9. 根据权利要求8所述的显示面板，其中，所述多个子像素的每个的第一电极包括在垂直于所述主表面方向上堆叠的金属电极层和透明电极层，所述透明电极层覆盖所述金属电极层，所述第一刻蚀阻挡层与所述透明电极层材料相同且同层设置。
  10. 根据权利要求8所述的显示面板，其中，沿从所述主表面到所述第二凹槽的底面 的方向，所述第二凹槽在平行于所述主表面方向上的尺寸逐渐变大，或者先逐渐增大再逐渐减小。
  11. 根据权利要求10所述的显示面板，其中，所述第二凹槽的沿垂直于所述主表面的截面的形状为梯形或不规则图形，所述不规则图形包括所述与所述主表面基本平行的底边和彼此相对且均与所述底边相交的第一侧边和第二侧边，所述第一侧边朝向远离所述第二侧边的方向凹陷，第二侧边朝向远离所述第一侧边的方向凹陷。
  12. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    第二刻蚀阻挡层，位于所述主表面上且位于所述间隔中，并且与所述第一子像素的第一电极和所述第二子像素的第一电极材料相同且同层间隔设置；
    所述第一凹槽位于所述第二刻蚀阻挡层的远离所述衬底基板的一侧，且暴露所述第二刻蚀阻挡层的远离所述衬底基板的上表面的至少部分。
  13. 根据权利要求12所述的显示面板，其中，沿从远离所述主表面到靠近所述主表面的方向，所述第一凹槽在平行于所述主表面方向上的尺寸逐渐变大，或者先逐渐增大再逐渐减小。
  14. 根据权利要求1-13任一所述的显示面板，其中，所述发光器件包括发射第一颜色的光的第一发光元件和发射第一颜色的光的第二发光元件，所述第一颜色和所述第二颜色不同，所述电荷产生层位于所述第一发光元件和所述第二发光元件之间并连接所述第一发光元件和所述第二发光元件。
  15. 一种显示装置，包括权利要求1-14任一所述的显示面板。
  16. 一种显示面板的制作方法，包括：
    提供衬底，其中，所述衬底具有主表面；
    在所述衬底上形成多个子像素，其中，所述多个子像素中的每个子像素包括位于所述主表面上的发光器件，所述发光器件包括在垂直于所述主表面的方向上堆叠的第一电极和电荷产生层，所述电荷产生层位于所述第一电极的远离所述衬底的一侧；以及
    形成像素界定层，其中，所述像素界定层位于所述主表面上，且限定出多个开口区，其中，所述多个开口区与所述多个子像素一一对应且暴露对应的所述子像素的第一电极的至少部分；
    所述多个子像素中包括相邻的第一子像素和第二子像素，所述第一子像素的第一电极和所述第二子像素的第一电极之间存在间隔，所述像素界定层包括位于所述间隔中且朝向所述主表面凹陷的第一凹槽，所述第一子像素的电荷产生层与所述第二子像素的电荷产生层被所述第一凹槽间隔开；
    所述像素界定层包括位于所述多个子像素中不同的所述相邻的两个子像素之间的间隔中的多个所述第一凹槽，所述多个第一凹槽在垂直于所述主表面方向上的深度相等。
  17. 根据权利要求16所述的显示面板的制作方法，其中，所述主表面具有位于所述间隔中的中间部分，所述主表面的中间部分是平坦的；
    形成所述第一凹槽包括：
    在所述主表面上形成所述第一子像素的第一电极和所述第二子像素的第一电极，其中，所述第一子像素的第一电极和所述第二子像素的第一电极暴露所述主表面的位于所述间隔中的部分；以及
    在所述第一子像素的第一电极和所述第二子像素的第一电极的远离所述衬底的一侧形成像素界定材料层以利用所述第一子像素的第一电极在垂直于所述主表面方向上的厚度与所述第二子像素的第一电极在垂直于所述主表面方向上的厚度而在形成所述像素界定材料层的同时形成所述第一凹槽，其中，不需要对像素界定材料层进行构图而形成第一凹槽。
  18. 根据权利要求17所述的显示面板的制作方法，包括：
    对所述像素界定材料层进行构图工艺以形成所述多个开口区从而形成所述像素界定层；以及
    利用同一材料和同一道膜层形成工艺在所述像素界定层的远离所述衬底的一侧形成所述第一子像素的电荷产生层、所述第二子像素的电荷产生层和浮置电荷产生层，其中，
    所述第一凹槽具有与所述主表面基本平行的第一底面，所述浮置电荷产生层位于所述第一凹槽中且位于所述第一底面上，
    所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧，并且，
    利用所述第一凹槽在垂直于所述衬底方向上的深度使得所述第一子像素的电荷产生层与所述浮置电荷产生层断开、以及所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
  19. 根据权利要求18所述的显示面板的制作方法，其中，所述像素界定层包括：
    间隔部，位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；
    第一堆叠部，在垂直于所述主表面的方向上堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；以及
    第二堆叠部，在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧，其中，所述间隔部包括所述第一凹槽；
    所述像素界定层的间隔部覆盖且直接接触所述第一子像素的第一电极的靠近所述第二子像素的第一电极的侧表面、所述主表面的位于所述间隔的部分、以及所述第二子像素的第一电极的靠近所述第一子像素的第一电极的侧表面；
    所述第一堆叠部覆盖且直接接触所述第一子像素的第一电极的远离所述衬底基板的上表面的一部分，所述第二堆叠部覆盖且直接接触所述第二子像素的第一电极的远离所述衬底基板的上表面的一部分。
  20. 根据权利要求16所述的显示面板的制作方法，其中，所述主表面具有位于所述 间隔的中间部分，所述制作方法包括：
    在所述主表面的中间部分上形成第二凹槽；
    形成第一刻蚀阻挡层，其中，所述第二凹槽具有与所述主表面基本平行的第二底面，所述第一刻蚀阻挡层位于所述第二凹槽中且位于所述第二底面上；以及
    形成覆盖所述第一子像素的第一电极、所述第二子像素的第一电极和所述第二凹槽的像素界定材料层；
    对所述像素界定材料层执行构图工艺以形成断口和所述开口区从而形成所述像素界定层，其中，所述像素界定层包括：
    间隔部，位于所述第一子像素的第一电极与所述第二子像素的第一电极之间的间隔中；
    第一堆叠部，在垂直于所述主表面的方向上堆叠于所述第一子像素的第一电极的远离所述衬底基板的一侧；以及
    第二堆叠部，在垂直于所述主表面的方向上堆叠于所述第二子像素的第一电极的远离所述衬底基板的一侧，其中，所述间隔部包括所述第一凹槽；
    所述断口位于像素界定层的间隔部在所述第二凹槽处且贯穿所述间隔部，所述第二凹槽与所述第一凹槽通过所述断口连通。
  21. 根据权利要求20所述的显示面板的制作方法，包括：
    在所述主表面上形成金属电极材料层，对所述金属电极材料层执行构图工艺以形成所述第一子像素的第一电极的金属电极层和所述第二子像素的第一电极的金属电极层；以及
    形成覆盖所述第一子像素的第一电极的金属电极层、所述第二子像素的第一电极的金属电极层、以及所述第二底面的透明电极材料层，对所述透明电极材料层执行构图工艺以形成所述第一子像素的第一电极的覆盖其金属电极层的透明电极层、所述第二子像素的第一电极的覆盖其金属电极层的透明电极层、以及所述第一刻蚀阻挡层。
  22. 根据权利要求20所述的显示面板的制作方法，还包括：
    利用同一材料和同一道膜层形成工艺在所述像素界定层的远离所述衬底的一侧形成所述第一子像素的电荷产生层、所述第二子像素的电荷产生层和浮置电荷产生层，其中，
    所述第二凹槽具有与所述主表面基本平行的第二底面，所述浮置电荷产生层位于所述第二凹槽中且位于所述第一刻蚀阻挡层的远离所述第二底面的一侧，
    所述第一子像素的电荷产生层位于所述第一堆叠部的远离所述主表面的一侧，所述第二子像素的电荷产生层位于所述第二堆叠部的远离所述主表面的一侧，
    所述第一子像素的电荷产生层与所述浮置电荷产生层断开，所述第二子像素的电荷产生层与所述浮置电荷产生层断开。
  23. 根据权利要求22所述的显示面板的制作方法，还包括：
    在形成所述第二刻蚀阻挡层之后对所述第二凹槽进行刻蚀，以使得沿从所述主表面到所述第二凹槽的底面的方向，所述第二凹槽在平行于所述主表面方向上的尺寸逐渐变大， 或者先逐渐增大再逐渐减小。
  24. 根据权利要求16所述的显示面板的制作方法，包括：
    在所述主表面上形成第二刻蚀阻挡层，其中，所述第二刻蚀阻挡层位于所述第一子像素的第一电极与所述第二子像素的第一电极的间隔中；
    形成覆盖所述第一子像素的第一电极、所述第二子像素的第一电极、以及所述第二刻蚀阻挡层的像素界定材料层；以及
    对所述像素界定材料层执行构图工艺以形成所述第一凹槽和所述多个开口区，其中，所述第一凹槽位于所述第二刻蚀阻挡层的远离所述衬底基板的一侧，且暴露所述第二刻蚀阻挡层的远离所述衬底基板的上表面的至少部分。
  25. 根据权利要求24所述的显示面板的制作方法，包括：
    在所述主表面上形成金属电极材料层，对所述金属电极材料层执行一次构图工艺以形成所述第一子像素的第一电极的金属电极层、所述第二子像素的第一电极的金属电极层和第二刻蚀阻挡层的金属电极层，其中，所述第二刻蚀阻挡层的金属电极层位于所述第一子像素的第一电极的金属电极层与所述第二子像素的第一电极的金属电极层之间；以及
    形成覆盖所述第一子像素的第一电极的金属电极层、所述第二子像素的第一电极、以及所述第二刻蚀阻挡层的金属电极层的透明电极材料层，对所述透明电极材料层执行一次构图工艺以形成所述第一子像素的第一电极的覆盖其金属电极层的透明电极层、所述第二子像素的第一电极的覆盖其金属电极层的透明电极层、以及所述第二刻蚀阻挡层的覆盖其金属电极层的透明电极层。
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US20200152717A1 (en) * 2018-11-13 2020-05-14 Samsung Display Co., Ltd. Display device and method of fabricating the same
CN113921573A (zh) * 2021-09-30 2022-01-11 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20200152717A1 (en) * 2018-11-13 2020-05-14 Samsung Display Co., Ltd. Display device and method of fabricating the same
CN113921573A (zh) * 2021-09-30 2022-01-11 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

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