Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
  • H10B12/48—Data lines or contacts therefor
  • H10B12/482—Bit lines
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
  • H10B12/48—Data lines or contacts therefor
  • H10B12/488—Word lines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
  • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies

Definitions

• the present invention relates to a semiconductor memory device.
• the channel In a typical planar MOS transistor, the channel extends in the horizontal direction along the upper surface of the semiconductor substrate. In contrast, the channel of the SGT extends in a direction perpendicular to the upper surface of the semiconductor substrate (see, for example, Non-Patent Document 1). Therefore, the SGT allows higher density semiconductor devices than planar MOS transistors.
• DRAM Dynamic Random Access Memory
• PCM Phase Change Memory
• Non-Patent Document 3 Phase Change Memory
• Non-Patent Document 4 RRAM (Resistive Random Access Memory, see, for example, Non-Patent Document 4), MRAM (Magneto-resistive Random Access Memory, for example, non-patent See Patent Document 5 ) etc.
• DRAM memory cells configured with one MOS transistor without a capacitor see, for example, Non-Patent Documents 6 and 9
• DRAM memory cells with two gate electrodes and a trench for storing carriers for example, non-patent documents 6 and 9
• Patent Document 8 a DRAM without a capacitor has a problem in that it is largely affected by the coupling of the gate electrode from the word line of the floating body and cannot provide a sufficient voltage margin. Further, when the substrate becomes completely depleted, the adverse effects become greater.
• the present application relates to a memory device using a semiconductor element that does not have a variable resistance element or a capacitor and can be configured only with a MOS transistor.
• This application uses a single transistor-type DRAM that eliminates capacitors to solve the problems of noise caused by capacitive coupling between the word line and the body, erroneous reading due to memory instability, and erroneous rewriting of stored data. provide a memory device; Furthermore, by introducing a structure in which memory cells are vertically stacked using GAA (Gate All Around) technology (for example, see Non-Patent Document 10), a semiconductor memory device that realizes a high-density and high-speed MOS circuit I will provide a.
• GAA Gate All Around
• a semiconductor memory device includes: a first insulating layer on the substrate; a plurality of first impurity layers spaced apart from the first insulating layer, extending horizontally with respect to the substrate, and spaced apart from each other in the vertical direction; a plurality of semiconductor layers that are in contact with each of the plurality of first impurity layers in an extension direction and extend in a horizontal direction with respect to the substrate; a plurality of second impurity layers connected to each of the plurality of first semiconductor layers in the extension direction and extending in the horizontal direction; a plurality of gate insulating layers each covering the plurality of semiconductor layers, a portion of the plurality of first impurity layers, and a portion of the plurality of second impurity layers; a first gate conductor layer in contact with the plurality of gate insulating layers and close to the plurality of first impurity layers; a plurality of second gate conductor layers that are in contact with each of the plurality of gate insulating layers and close
• a current flowing between the plurality of first impurity layers and the plurality of second impurity layers causes an impact ionization phenomenon or a gate-induced drain leakage current to generate electron groups and hole groups in the plurality of semiconductor layers. out of the generated electron group and the hole group, some or all of the electron group or the hole group, which are majority carriers in the plurality of semiconductor layers, are transferred to the plurality of semiconductor layers.
• the plurality of first impurities are controlled by controlling voltages applied to the first conductor layer, the second conductor layer, the first gate conductor layer, and the plurality of second gate conductor layers.
• a memory erasing operation is performed by extracting either the electron group or the hole group, which are majority carriers in the remaining first semiconductor layer, from at least one location of the second impurity layer and the plurality of second impurity layers.
• the first conductor layer connected to the plurality of first impurity layers is connected to a source line
• the second conductor layer connected to the plurality of second impurity layers is connected to a bit
• the first gate conductor layer is connected to a plate line
• the plurality of second gate conductor layers are connected to a word line
• a predetermined line is connected to each of the source line, bit line, plate line, and word line. It is characterized in that the memory is written and erased by applying a voltage (third invention).
• the first impurity layer, the second impurity layer, the semiconductor layer, the gate insulating layer, the first gate conductor layer and the second gate conductor layer are formed.
• a semiconductor device is a memory cell
• a maximum depletion extending from directly below the first gate conductor layer or the plurality of second gate conductor layers in a cross section of the semiconductor of the memory cell in a direction perpendicular to the substrate;
• the semiconductor layer is characterized in that the cross-sectional area of the semiconductor layer is thicker than the total area of the layer widths (fourth invention).
• the fourth invention is characterized in that an interval between adjacent memory cells in a direction perpendicular to the substrate is wider than an interval between adjacent memory cells in a horizontal direction of the substrate. 5 inventions).
• the second gate conductor layer is shared by a plurality of the memory cells adjacent in the horizontal direction of the substrate (sixth invention).
• the plurality of first gate conductor layers are shared by a plurality of cells adjacent to the substrate in a horizontal direction or a vertical direction (seventh invention). ).
• the area of the contact surface between the first conductor layer and the plurality of first impurity layers is equal to the cross-sectional area of the plurality of first semiconductor layers connected to the first impurity layer. (eighth invention).
• the area of the contact surface between the second conductor layer and the plurality of second impurity layers is the cross-sectional area of the plurality of first semiconductor layers connected to the plurality of second impurity layers.
• both or one of the plurality of first impurity layers and the plurality of second impurity layers are shared by adjacent cells in a horizontal direction with respect to the substrate. (10th invention).
• a first metal electrode is in contact with the first conductor layer and connected to the source line at a terminal end of the cell array, and a second metal electrode is in contact with the first gate conductor layer; and a third metal electrode connected to the plate line and in contact with the second conductor layer, and a plurality of fourth metal electrodes connected to the bit line and in contact with each of the plurality of second gate conductor layers.
• a word line is connected to each (eleventh invention).
• all or a part of the metal wiring serving as the plate line, the source line, the word line, and the bit line are formed of metal wiring in the same layer. (12th invention).
• FIG. 1 is a diagram showing a cross-sectional structure of a memory device using a semiconductor element according to a first embodiment
• FIG. 3 is a diagram illustrating an additional example of a cross-sectional structure of a memory device using the semiconductor element according to the first embodiment.
• FIG. 3 is a diagram for explaining a write operation, carrier accumulation immediately after the operation, and cell current of the memory device using the semiconductor element according to the first embodiment.
• FIG. 3 is a diagram for explaining the accumulation of hole carries, the erase operation, and the cell current immediately after the write operation of the memory device using the semiconductor element according to the first embodiment.
• FIG. 3 is a diagram for explaining a cell arrangement of a memory device using a semiconductor element according to a first embodiment.
• FIG. 2 is a diagram for explaining the final end of a cell array of a memory device using a semiconductor element according to a first embodiment.
• FIG. 1 shows an application of the memory of FIG.
• FIG. 3 shows an application of the memory of FIG.
• the write mechanism and carrier behavior of a memory using a semiconductor element will be described with reference to FIG. 3, and the data erase mechanism will be described with reference to FIG.
• FIG. 5 shows an example of the arrangement of memory cells of the semiconductor device according to the present embodiment. 5, and a wiring structure at the final end of the memory cell according to the present embodiment will be described using FIG.
• FIG. 1 shows the structure of a memory using a semiconductor element according to a first embodiment of the present invention.
• FIG. 1 shows the structure of a memory using a semiconductor element according to a first embodiment of the present invention.
• (a) is a plan view
• (b) is a cross-sectional view taken along line XX'
• (c) is a cross-sectional view taken along line Y1-Y1'
• (d) is a cross-sectional view taken along line Y2-Y2'.
• a cross-sectional view along each line is shown.
• n+ layer 2aa (which is an example of the "first impurity layer” in the claims) (hereinafter, a semiconductor region containing a high concentration of donor impurity will be referred to as "n+ layer”).
• p layer a semiconductor region containing a high concentration of donor impurity
• n+ layer 3aa an example of a "second impurity layer” in the claims
• gate insulating layer 4aa an example of a "gate insulating layer” in the claims
• a first gate conductor layer 5 is located close to the n+ layer 2aa, surrounding a part of the gate insulating layer 4aa.
• the gate conductor layer 6a (which is an example of a "second gate conductor layer” in the claims) is in contact with the gate insulating layer 4aa and in close proximity to the n+ layer 3aa without being in contact with the gate conductor layer 5.
• the p layer 1aa, the n+ layer 2aa, the n+ layer 3aa, the gate insulating layer 4aa, the gate conductor layer 5, and the gate conductor layer 6a form one dynamic flash memory cell 8 (indicated by a dotted line in FIG. 1(a)). (which is an example of a "memory cell" in the claims) is formed.
• the above-mentioned dynamic flash memory cells 8 are arranged vertically (hereinafter referred to as "column direction” or “column”) on the substrate 20 and the insulating layer 21 to be separated from each other. , which are further arranged in the horizontal direction (hereinafter referred to as “row direction” or “row”).
• FIGS. 1A to 1D show an example in which memory cells 8 are arranged in three rows and three columns. Note that in FIG. 1, the horizontal direction refers to the direction from the bottom to the top in FIG. 1(a).
• FIG. 1(b) shows a cross-sectional view of three cells arranged in the first row.
• the memory cell in the first row and first column is composed of the p layer 1aa, the n+ layer 2aa, the n+ layer 3aa, the gate insulating layer 4aa, the gate conductor layer 5, and the gate conductor layer 6a.
• the first row and second column are p layer 1ba, n+ layer 2ba, n+ layer 3ba, gate insulating layer 4ba, gate conductor layer 5, and gate conductor layer 6b
• the first row and third column are p layer 1ca
• the n+ layer 2ca, the n+ layer 3ca, the gate insulating layer 4ca, the gate conductor layer 5, and the gate conductor layer 6c each constitute a memory cell.
• the n+ layers 2aa, 2ba, and 2ca are connected to a first conductor layer 12 (which is an example of a "first conductor layer" in the claims).
• n+ layers 3aa, 3ba, and 3ca are connected to a second conductor layer 13a (which is an example of a "second conductor layer" in the claims) to constitute a first row memory cell array.
• a second conductor layer 13a which is an example of a "second conductor layer” in the claims.
• an insulating layer 22 (which is an example of a "second insulating layer” in the claims) in contact with the gate conductor layer 5, the conductor layer 12, and the insulating layer 21;
• An insulating layer 23 (which is an example of a "third insulating layer” in the claims) is in contact with the conductor layers 13a, 13b, 13c and the insulating layer 21.
• FIG. 1(c) shows a cross-sectional structure of nine cell arrays along the line Y1-Y1' in FIG. 1(a) in the p-layer portion.
• the drawing numbers are shown in each cell in the form of p layer 1xy and gate insulating layer 4xy, but the x after each number indicates the row and the y indicates the column.
• b indicates the 1st row or column
• b indicates the 2nd row or column
• c indicates the 3rd row or column.
• p-layer 1aa to p-layer 1cc may be comprehensively expressed as p-layer 1).
• Gate conductor layer 6x is shared by cells in each row direction, and for example, gate conductor layer 6a is shared by cells including p-layers 1aa, 1ab, and 1ac. Similarly, cells including p-layers 1ba, 1bb, and 1bc share gate conductor layer 6b, and cells including p-layers 1ca, 1cb, and 1cc share gate conductor layer 6c.
• FIG. 1(d) shows a cross-sectional structure of nine cell arrays along the line Y2-Y2' in FIG. 1(a) at the gate conductor layer 5.
• Gate conductor layer 5 is shared by gate insulating layers 4aa to 4cc of nine cells.
• the conductor layer 12 is connected to the source line SL (which is an example of a "source line” in the claims), and the gate conductor layer 5 is connected to the plate line PL (which is an example of a "plate line” in the claims). It is connected.
• the conductor layer 13a is connected to the bit line BL1 (which is an example of the "bit line” in the claims), the conductor layer 13b is similarly connected to the bit line BL2, and the conductor layer 13c is connected to the bit line BL3. There is.
• the gate conductor layer 6a is connected to a word line WL1 (which is an example of a "word line” in the claims), similarly the gate conductor layer 6b is connected to WL2, and the gate conductor layer 6c is connected to WL3. .
• the memory operates by individually manipulating the potentials of the source line, bit line, plate line, and word line. This memory device is hereinafter referred to as dynamic flash memory.
• the p layers 1aa to 1cc are p-type semiconductors, but there may be a profile in the impurity concentration. Further, there may be a profile in the impurity concentration of the n+ layers 2aa to 2cc and the n+ layers 3aa to 3cc.
• n+ layers 2aa to 2cc and the n+ layers 3aa to 3cc are formed of a p+ layer in which holes are majority carriers (hereinafter, a semiconductor region containing a high concentration of acceptor impurities is referred to as a "p+ layer")
• p+ layer a semiconductor region containing a high concentration of acceptor impurities
• the substrate 20 in FIG. 1 may be an insulator, a semiconductor, or a conductor, and any material can be used as long as the insulating layer 21 is formed thereon and the memory cell can be supported.
• the gate conductor layer 5 and the gate conductor layers 6a to 6c can be formed of, for example, W, Pd, Ru, Al, TiN, etc. It may be a metal such as TaN or WN, a metal nitride, or an alloy thereof (including silicide), a laminated structure such as TiN/W/TaN, or a highly doped semiconductor. It's okay.
• the conductor layer 12 and the conductor layers 13a to 13c may be made of any material as long as they can be electrically connected to the n+ layers 2aa to 2cc and the n+ layers 3aa to 3cc, respectively.
• any insulating film used in a normal MOS process can be used for the gate insulating layers 4aa to 4cc, such as a SiO2 film, a SiON film, a HfSiON film, or a stacked film of SiO2/SiN.
• FIG. 1 has been described as having a rectangular vertical cross section, it may have a trapezoidal, polygonal, or cylindrical shape.
• gate conductor layer 5 is shown as being integrated in each memory cell 8 in FIG. 1, it may be divided horizontally or vertically with respect to the substrate 20.
• the insulating layer 22 and the insulating layer 23 are illustrated as being separated, but they may be formed as an integral body using the same material or a multilayer combination of multiple materials.
• FIG. 2 shows a modification of the structure of the memory shown in FIG. 1 according to the first embodiment of the present invention.
• FIG. 2(a) is a plan view
• FIG. 2(b) is a sectional view taken along line XX' in (a)
• FIG. 2(c) is a sectional view taken along line Y1-Y1' in (a). , respectively.
• the n+ layers 2aa to 2cc and the conductor layer 12 are shown as being in contact with each other on one surface, but as shown in FIGS. 2(a) and 2(b),
• the contact surface between 2cc and the conductor layer 12 can be made larger than the cross-sectional area of each of the n+ layers 2aa to 2cc.
• the n+ layers 3aa to 3cc and the conductor layers 13a to 13c are shown as being in contact with each other on one surface, but as shown in FIGS.
• the gate conductor layer 6a if the gate conductor layer 6a is in contact with a part of the gate insulating layers 4aa to 4ac, the gate conductor layer 6a can insulate the gate as shown in FIG. A dynamic flash memory can operate even if the layers 4aa to 4ac are not completely covered.
• carrier behavior, storage, and cell current during a write operation of the dynamic flash memory according to the first embodiment of the present invention will be explained.
• the principle of operation will be explained by focusing on the memory cell in the first row and first column in FIG. 1(a).
• the majority carriers in the n+ layer 2aa and the n+ layer 3aa are electrons, and for example, the gate conductor layer 6a connected to the WL and the gate conductor layer 5 connected to the PL are coated with n+ poly (hereinafter, donor impurity).
• donor impurity hereinafter, donor impurity
• 0V is input to the n+ layer 2aa through the conductor layer 12 connected to the source line SL
• 3V for example, is input to the n+ layer 3aa through the conductor layer 13a connected to the bit line BL
• the plate line PL is connected.
• the applied gate conductor layer 5 is set to 3V, for example, and 1.5V, for example, is input to the gate conductor layer 6a connected to the word line WL.
• FIG. 3(b) shows the hole group 17 in the p layer 1aa when all biases are set to 0V immediately after writing.
• the generated hole group 17 is the majority carrier in the p layer 1aa, and is temporarily accumulated in the p layer 1aa surrounded by the depletion layer 16, and in a non-equilibrium state, it is substantially absorbed by the gate conductor layer 5 and the gate conductor layer.
• the p layer 1aa which is the substrate of the MOSFET 6a, is charged to a positive bias.
• the threshold voltage of the MOSFET having the gate conductor layer 6a is lowered due to the positive substrate bias effect caused by the holes temporarily accumulated in the p layer 1aa.
• FIG. 3(c) the threshold voltage of the MOSFET having the gate conductor layer 6a connected to the word line WL becomes lower than that in the neutral state.
• This write state is assigned to logical storage data "1".
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are an example for performing a write operation, and other operating voltage conditions that allow a write operation may be used.
• the position of the pinch-off point 16 shifts toward the gate conductor layer 5. A similar phenomenon can occur.
• a gate induced drain leak (GIDL) current may be passed to generate a hole group (see, for example, Non-Patent Document 8).
• the erase operation mechanism of the dynamic flash memory of the first embodiment shown in FIG. 1 will be explained using FIG. 4.
• the voltage applied to the bit line BL is 0.6 V
• the source line SL is 0 V
• the plate line PL is 2 V
• the word line WL is 0 V.
• the concentration of holes 17 accumulated in the p layer 1aa is sufficiently higher than the hole concentration in the n+ layer 2aa
• holes flow into the n+ layer 2aa by diffusion due to the concentration gradient.
• the electron concentration in the n+ layer 2aa is higher than the electron concentration in the p layer 1aa
• electrons 18 flow into the p layer 1aa by diffusion due to the concentration gradient.
• the voltage applied to the bit line may be higher or lower than 0.6V, but as long as the voltage causes electron drift within the depletion layer 16, it can be adjusted.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL are 0.6V (BL) / 0V (SL) / 0V (PL) / 2V(WL), 0V(BL)/0.6V(SL)/1V(PL)/0V(WL), 0.6V(BL)/0V(SL)/1V(PL)/0V(WL) Combinations such as 1.5V (BL)/0V (SL)/0V (PL)/2.5V (WL) are also possible.
• the voltage conditions applied to the bit line BL, source line SL, word line WL, and plate line PL described above are an example for performing the erase operation, and other operating conditions that allow the erase operation may be used.
• FIGS. 5(a) to 5(d) An example of the arrangement of memory cells that realizes a higher density memory device according to the first embodiment of the present invention is shown using FIGS. 5(a) to 5(d).
• FIGS. 5(a) to 5(d) components that are the same or similar to those in FIG. 1 are designated by the same reference numerals.
• FIG. 5(a) shows a plan view of a plurality of cells with the substrate 20 and insulating layer 21 removed from FIG. 1(a).
• the p layers 1aa to 1cc in FIG. 4cc is collectively referred to as gate insulating layer 4
• gate conductor layers 6a to 6c are collectively referred to as gate conductor layer 6
• wiring conductor layers 13a to 13c are collectively referred to as wiring conductor layer 13.
• FIG. 5(b) shows a cross-sectional view taken along line XX' in FIG. 5(a).
• the component included between the center of the conductor layer 12 and the center of the conductor layer 13 in FIG. 5(a) is defined as an LCE.
• the component included between the center of the conductor layer 12 and the center of the conductor layer 13 in FIG. 5(b) is defined as VCE.
• the unit VCEs of FIG. 5(b) are arranged from the left in FIG. A side-by-side cross-sectional view is shown.
• FIG. 5 shows an example in which the memory cells are expanded to the right, it is also possible to expand the memory cells upward in FIG. 5(a), or vertically from the substrate 20 in FIG. It can also be expanded in any direction.
• FIG. 5 is based on the memory cell in FIG. 1, if you expand the cell using the cell in FIG. It may be coated with 12. Similarly, the n+ layers 3 of adjacent cells may be connected and a portion thereof may be covered with the conductor layer 13.
• FIG. 6 shows the electrode arrangement and wiring structure at the final end of the dynamic flash memory cell array according to the first embodiment of the present invention.
• FIG. 6(a) shows a bird's-eye view of the x-th memory cell and its terminal electrode when the memory cells 8 are arranged in three columns vertically and in x rows horizontally with respect to a substrate (not shown). show.
• N+ layers 2ax to 2cx, n+ layers 3ax to 3cx, gate insulating layers 4ax to 4cx, gate conductor layer 5, gate conductor layers 6a to 6c, conductor layer 12, and conductor layer 13x are the constituent elements of the cell.
• the conductor layer 12 is connected to the source line SL through the electrode 32 (which is an example of the "first metal electrode” in the claims), and the gate conductor layer 5 is connected to the electrode 35 (which is an example of the "second metal electrode” in the claims).
• the conductor layer 13x is connected to the plate line PL through the electrode 33 (which is an example of the "third metal electrode” in the claims), and to the bit line BL through the electrode 33 (which is an example of the "third metal electrode” in the claims).
• the gate conductor layer 6a is connected to the word line WL1 through the electrode 36a (which is an example of the "fourth metal electrode” in the claims), and similarly the gate conductor layer 6b is connected to the word line WL2 through the electrode 36b, and the gate conductor layer 6c is connected to WL3 through electrode 36c.
• the electrodes 32, 33, 35, 36a, 36b, and 36c are electrically connected to the conductor layer 12, the conductor layer 13x, the gate conductor layer 5, and the gate conductor layer 6a, 6b, and 6c, respectively, and Any material may be used as long as it is electrically bonded to the material wired above it.
• FIG. 6(b) shows an example of a plan view in which metal wiring is connected to each electrode shown in FIG. 6(a).
• the electrode 33 is connected to a metal wiring layer 43 which is a bit line
• the electrode 32 is connected to a metal wiring layer 42 which is a source line
• the electrode 35 is connected to a metal wiring layer 45 which is a plate line
• the electrode 36a is connected to a metal wiring layer which is a word line 1.
• the electrode 36b is electrically connected to the metal wiring layer 46b which is the word line 2
• the electrode 36c is electrically connected to the metal wiring layer 46c which is the word line 3.
• the cell array is expanded downward (x direction) in FIG. 6(b).
• the electrodes 33, 32, 35, 36a, 36b, and 36c are arranged in this order as shown in FIG. You can see that the layout can be done with
• FIG. 6(a) the heights of the electrodes 36a, 36b, and 36c are changed so that the upper surfaces of the electrodes 32, 33, 35, 36a, 36b, and 36c are all at the same height
• FIG. 6(b) we showed an example of wiring using metal wiring layers in the same layer, but it is also possible to use multiple layers of electrodes for connecting plate lines, bit lines, and source lines, varying their heights, and using metal wiring in different layers. You may. Furthermore, using a multilayer wiring technique, connections may be made using metal wiring layers of different layers.
• the cross sections may be polygonal, such as square.
• This embodiment has the following features.
• Feature 1 In the dynamic flash memory according to the first embodiment of the present invention, a plurality of memory cells are stacked vertically to the substrate, and adjacent cells are electrically shielded from each other by the gate conductor layer 6. In conventional memory cell placement, electrical interaction between memory cells becomes large when memory cells are arranged at high density with a minimum line width.On the other hand, to prevent this interaction, cell word line spacing is If you open it up, the memory density will be lower. According to the first embodiment of the present invention, the memory cells can be arranged with little interaction without changing the planar area, so that the memory cells can be arranged with high density and with a margin.
• the vertical thickness of the semiconductor layer 1 of the memory cell can be freely adjusted without sacrificing the memory density in plan view.
• the number can be increased, and the margin of memory operation can be expanded.
• the spacing between memory cells in the vertical direction with respect to the substrate can be increased without sacrificing memory density, so that the spacing between the word lines 6 in the vertical direction of each memory can be increased. Since the parasitic capacitance can be made smaller than in the conventional example, and the film thickness of the word line 6 in the vertical direction can be substantially increased, the parasitic resistance can be reduced, contributing to high-speed operation of the memory.
• the metal wiring layers of word lines and bit lines connected to memory cells can be laid out with minimum dimensions, so a high-density memory device can be provided. can.
• the semiconductor element according to the present invention it is possible to provide a semiconductor memory device with higher density, higher speed, and higher operating margin than conventional devices.

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