WO2023159425A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2023159425A1
WO2023159425A1 PCT/CN2022/077687 CN2022077687W WO2023159425A1 WO 2023159425 A1 WO2023159425 A1 WO 2023159425A1 CN 2022077687 W CN2022077687 W CN 2022077687W WO 2023159425 A1 WO2023159425 A1 WO 2023159425A1
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Prior art keywords
line
detection
twenty
control
transistor
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PCT/CN2022/077687
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English (en)
French (fr)
Inventor
黄耀
李诗琪
张静
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202280000278.1A priority Critical patent/CN116941041A/zh
Priority to PCT/CN2022/077687 priority patent/WO2023159425A1/zh
Publication of WO2023159425A1 publication Critical patent/WO2023159425A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission

Definitions

  • the present disclosure relates to but not limited to the field of display technology, especially a display substrate and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum-dot Light Emitting Diodes
  • TFT Thin Film Transistor
  • an exemplary embodiment of the present disclosure provides a display substrate, including a display area and a binding area located on one side of the display area, the display area includes a first display area and a second display area, and the second display area includes a first display area and a second display area.
  • a display area at least partially surrounds the second display area, the first display area is configured to display images, and the second display area is configured to display images and transmit light;
  • the first display area includes A plurality of first sub-pixels and at least one first data line connected to the first sub-pixels
  • the second display area includes a plurality of second sub-pixels and at least one second data line connected to the second sub-pixels data line
  • the binding area includes a detection circuit, and the detection circuit includes a control line, a first signal line, a second signal line, at least one first detection subunit and at least one second detection subunit;
  • the first The control terminal of the detection subunit is connected to the control line, the input terminal of the first detection subunit is connected to the first signal line, and the output terminal of the first detection subunit is connected to the first data line , the first detection subunit is configured to output the signal transmitted by the first signal line to the first data line;
  • the control terminal of the second detection subunit is connected to the control line, and the first detection subunit is
  • the control line includes a first control line, a second control line, and a third control line
  • the first signal line includes a first detection line, a third detection line, and a fifth detection line
  • the second signal line includes a second detection line, a fourth detection line, and a sixth detection line
  • the first detection subunit includes an eleventh switch unit, a twelfth switch unit, and a thirteenth switch unit
  • the first The second detection subunit includes a twenty-first switch unit, a twenty-second switch unit, and a twenty-third switch unit
  • the eleventh switch unit is configured to, under the control of the first control line, switch the The signal transmitted by the first detection line is sent to the first data line connected to the first color sub-pixel in the first display area
  • the twelfth switch unit is configured to, under the control of the second control line, switch
  • the signal transmitted by the third detection line is sent to the first data line connected to the second color sub-pixel in the first display area
  • the thirteenth switch unit is configured to be controlled by
  • control terminal of the eleventh switch unit is connected to the first control line
  • the input terminal of the eleventh switch unit is connected to the first detection line
  • the eleventh switch unit The output end of the switch unit is connected to the first data line connected to the first color sub-pixel in the first display area
  • the control end of the twenty-first switch unit is connected to the first control line
  • the second The input terminal of the eleventh switch unit is connected to the second detection line
  • the output terminal of the twenty-first switch unit is connected to the second data line connected to the first color sub-pixel in the second display area.
  • the eleventh switch unit includes at least one eleventh transistor, the control electrode of the eleventh transistor is connected to the first control line, and the first electrode of the eleventh transistor connected to the first detection line, the second pole of the eleventh transistor is connected to the first data line connected to the first color sub-pixel in the first display area;
  • the twenty-first switch unit includes at least A twenty-first transistor, the control pole of the twenty-first transistor is connected to the first control line, the first pole of the twenty-first transistor is connected to the second detection line, and the second The second poles of the eleven transistors are connected to the second data lines connected to the sub-pixels of the first color in the second display area.
  • the control terminal of the twelfth switch unit is connected to the second control line
  • the input terminal of the twelfth switch unit is connected to the third detection line
  • the twelfth switch unit The output end of the switch unit is connected to the first data line connected to the second color sub-pixel in the first display area
  • the control end of the twenty-second switch unit is connected to the second control line
  • the second The input end of the twelve switch unit is connected to the fourth detection line
  • the output end of the twenty-second switch unit is connected to the second data line connected to the second color sub-pixel in the second display area.
  • the twelfth switch unit includes at least one twelfth transistor and at least one thirteenth transistor, and the control electrodes of the twelfth transistor and the thirteenth transistor are connected to the second control line connected, the first poles of the twelfth transistor and the thirteenth transistor are connected to the third detection line, and the second poles of the twelfth transistor and the thirteenth transistor are connected to the first display area
  • the first data line of the second color sub-pixel is connected;
  • the twenty-second switch unit includes at least one twenty-second transistor and at least one twenty-third transistor, and the twenty-second transistor and the twenty-third transistor
  • the control pole of the transistor is connected to the second control line, the first poles of the twenty-second transistor and the twenty-third transistor are connected to the fourth detection line, and the twenty-second transistor and the twenty-third
  • the second pole of the transistor is connected to the second data line connected to the second color sub-pixel in the second display area.
  • control terminal of the thirteenth switch unit is connected to the third control line
  • the input terminal of the thirteenth switch unit is connected to the fifth detection line
  • the thirteenth switch unit The output terminal of the switch unit is connected to the first data line connected to the sub-pixel of the third color in the first display area
  • the control terminal of the twenty-third switch unit is connected to the third control line
  • the second The input terminal of the thirteenth switch unit is connected to the sixth detection line
  • the output terminal of the twenty-third switch unit is connected to the second data line connected to the sub-pixel of the third color in the second display area.
  • the thirteenth switch unit includes at least one fourteenth transistor and at least one fifteenth transistor, and the control electrodes of the fourteenth transistor and the fifteenth transistor are connected to the third control line
  • the first poles of the fourteenth transistor and the fifteenth transistor are connected to the fifth detection line, and the second poles of the fourteenth transistor and the fifteenth transistor are connected to the first display area.
  • the first data line of the third color sub-pixel is connected;
  • the twenty-third switch unit includes at least one twenty-fourth transistor and at least one twenty-fifth transistor, and the twenty-fourth transistor and the twenty-fifth transistor
  • the control pole of the transistor is connected to the third control line, the first poles of the twenty-fourth transistor and the twenty-fifth transistor are connected to the sixth detection line, the twenty-fourth transistor and the twenty-fifth
  • the second electrode of the transistor is connected to the second data line connected to the sub-pixel of the third color in the second display area.
  • the detection circuit further includes a switching control line and a switching unit, the control pole of the switching unit is connected to the switching control line, and the first pole of the switching unit is connected to the first signal line connected, the second pole of the switching unit is connected to the second signal line, and the switching unit is configured to isolate the first signal line from the second signal line under the control of the switching control line or conduction.
  • the switching unit includes a first switching subunit, a second switching subunit, and a third switching subunit;
  • the first signal line includes a first detection line, a third detection line, and a fifth detection line line;
  • the second signal line includes a second detection line, a fourth detection line and a sixth detection line;
  • the control pole of the first switching subunit is connected to the switching control line, and the control pole of the first switching subunit
  • the first pole is connected to the first detection line, the second pole of the first switching subunit is connected to the second detection line;
  • the control pole of the second switching subunit is connected to the switching control line,
  • the first pole of the second switching subunit is connected to the third detection line, the second pole of the second switching subunit is connected to the fourth detection line;
  • the control pole of the third switching subunit connected to the switching control line, the first pole of the third switching subunit is connected to the fifth detection line, and the second pole of the third switching subunit is connected to the sixth detection line.
  • the first switching subunit includes two first transistors connected in series, the control poles of the two first transistors are connected to the switching control line, and the first pole of one first transistor is connected to the The first detection line is connected, the second pole of the other first transistor is connected to the second detection line, and the second pole of the one first transistor is connected to the first pole of the other first transistor.
  • the second switching subunit includes two second transistors connected in series, the control poles of the two second transistors are connected to the switching control line, and the first pole of one second transistor is connected to the The third detection line is connected, the second pole of the other second transistor is connected to the fourth detection line, and the second pole of the one second transistor is connected to the first pole of the other second transistor.
  • the third switching subunit includes two third transistors connected in series, the control poles of the two third transistors are connected to the switching control line, and the first pole of one third transistor is connected to the The fifth detection line is connected, the second pole of another third transistor is connected to the sixth detection line, and the second pole of the one third transistor is connected to the first pole of the other third transistor.
  • the detection circuit further includes a switch control line, a switch unit, and a signal lead, the control pole of the switch unit is connected to the switch control line, and the first pole of the switch unit is connected to the signal lead.
  • the second pole of the switch unit is connected to the second signal line, and the switch unit is configured to isolate or lead the signal lead line from the second signal line under the control of the switch control line. connected; when the signal lead wire and the second signal wire are turned on, the first signal wire and the second signal wire are isolated, and the first signal wire and the second signal wire output different aging voltage signals; When the signal lead wire is isolated from the second signal wire, the first signal wire and the second signal wire are conducted, and the first signal wire and the second signal wire output the same lighting voltage signal.
  • the display substrate on a plane perpendicular to the display substrate, includes a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer sequentially arranged on a base, and the semiconductor
  • the layers include an active layer of a plurality of transistors in a switching unit, an active layer of a plurality of transistors in a first detection subunit, and an active layer of a plurality of transistors in a second detection subunit, the first conductive layer comprising a switching unit Gate electrodes of multiple transistors in the first detection subunit, gate electrodes of multiple transistors in the first detection subunit, and gate electrodes of multiple transistors in the second detection subunit, the third conductive layer includes the control line, the first signal line and the second signal line.
  • control lines include a first control line, a second control line and a third control line, at least one of the first control line, the second control line and the third control line includes a control lead line and a control extension line, the control lead-out line and the control extension line are connected by a signal connection line, the signal connection line is arranged in the first conductive layer, the control lead-out line and the control extension line are arranged in the second in three conductive layers.
  • the first signal line includes a first detection line, a third detection line, and a fifth detection line
  • the second signal line includes a second detection line, a fourth detection line, and a sixth detection line
  • at least one of the first detection line, the second signal line, the third detection line, the fourth detection line, the fifth detection line and the sixth detection line includes a detection lead-out line and a detection extension line
  • the detection lead-out line is connected with the detection extension line through the signal connection line
  • the signal connection line is arranged in the first conductive layer
  • the detection lead-out line and the detection extension line are arranged in the third conductive layer.
  • the first conductive layer further includes a switch connection line
  • the third conductive layer further includes a switch control line
  • the switch connection line is connected to the switch control line through a via hole
  • the switch The connecting wire and the gate electrodes of the plurality of transistors in the switching unit are connected to each other as an integral structure.
  • the first detection subunit includes a first transmission line and a second transmission line, and the first transmission line is connected to a first data line connected to a first color sub-pixel in the first display area, so The second transmission line is connected to the first data line connecting the second color sub-pixel and the third color sub-pixel in the first display area; the first transmission line is arranged in the first conductive layer, and the second A transmission line is disposed in the second conductive layer.
  • the second transmission line is provided with a twenty-first connection block and a twenty-second connection block;
  • the twenty-first connection block is connected to the first detector through the twelfth connection electrode
  • the twelfth active layer and the thirteenth active layer in the unit are connected, and the twenty-first connection block is arranged between the twelfth active layer and the thirteenth active layer;
  • the second The twelfth connection block is connected to the fourteenth active layer and the fifteenth active layer in the first detection subunit through the thirteenth connection electrode, and the twenty-second connection block is arranged on the fourteenth active layer. between the active layer and the fifteenth active layer.
  • the twelfth connection electrode and the thirteenth connection electrode are disposed in the third conductive layer.
  • the second detection subunit includes a third transmission line and a fourth transmission line
  • the third transmission line is connected to the second data line connected to the first color sub-pixel in the second display area
  • the fourth transmission line is connected to the second data line connecting the second color sub-pixel and the third color sub-pixel in the second display area;
  • the third transmission line is arranged in the first conductive layer, and the fourth A transmission line is disposed in the second conductive layer.
  • the fourth transmission line is provided with a forty-first connection block, a forty-second connection block, a forty-third connection block, and a forty-fourth connection block;
  • the forty-first connection The block is connected to the twenty-second active layer in the second detection subunit through the twenty-second connection electrode, and the forty-first connection block is arranged in the first direction of the twenty-second active layer One side;
  • the forty-second connection block is connected to the twenty-third active layer in the second detection subunit through the twenty-third connection electrode, and the forty-second connection block is arranged on the first The side of the twenty-third active layer opposite to the first direction;
  • the forty-third connection block is connected to the twenty-fourth active layer in the second detection subunit through the twenty-fourth connection electrode,
  • the forty-third connection block is arranged on one side of the twenty-fourth active layer in the first direction;
  • the forty-fourth connection block is connected to the second detection subunit through the twenty-fifth connection electrode The twenty-fifth active layer connection, the forty
  • the twenty-second connection electrode, the twenty-third connection electrode, the twenty-fourth connection electrode, and the twenty-fifth connection electrode are disposed in the third conductive layer.
  • an exemplary embodiment of the present disclosure further provides a display device, including the display substrate described in any one of the foregoing.
  • 1 is a schematic structural view of a display device
  • FIG. 2 is a schematic plan view of a display substrate
  • Fig. 3 is a schematic plan view of a first display area
  • Fig. 4 is a schematic cross-sectional structure diagram of a first display area
  • FIG. 6 is a working timing diagram of a pixel driving circuit
  • FIG. 7 is a schematic plan view showing a binding region in a substrate
  • FIG. 8 is a schematic diagram of an equivalent circuit of a detection circuit
  • 9a and 9b are schematic diagrams of an equivalent circuit of a detection circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • FIG. 11 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • 12a to 12c are schematic diagrams of semiconductor layer patterns formed in an exemplary embodiment of the present disclosure.
  • FIGS. 13a to 13c are schematic diagrams of an exemplary embodiment of the present disclosure after forming a first conductive layer pattern
  • Fig. 14a and Fig. 14b are schematic diagrams of forming the second conductive layer pattern according to the exemplary embodiment of the present disclosure
  • 15a to 15c are schematic diagrams of an exemplary embodiment of the present disclosure after forming a fourth insulating layer pattern
  • 16a to 16c are schematic diagrams of an exemplary embodiment of the present disclosure after forming a third conductive layer pattern
  • FIG. 17 is a schematic structural diagram of a detection circuit connected to pins according to an exemplary embodiment of the present disclosure.
  • FIG. 18 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figure.
  • the figures described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the accompanying drawings. The shape or value shown in the figure, etc.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or a connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • connection includes the case where constituent elements are connected together through an element having some kind of electrical effect.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to the state where the angle formed by two straight lines is -10° to 10°, and therefore includes the state where the angle is -5° to 5°.
  • perpendicular means a state in which the angle formed by two straight lines is 80° to 100°, and therefore also includes an angle of 85° to 95°.
  • film and “layer” are interchangeable.
  • conductive layer may sometimes be replaced with “conductive film”.
  • insulating film may sometimes be replaced with “insulating layer”.
  • triangle, rectangle, trapezoid, pentagon, or hexagon in this specification are not strictly defined, and may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, etc., and there may be some small deformations caused by tolerances. There can be chamfers, arc edges, deformations, etc.
  • FIG. 1 is a schematic structural diagram of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scanning driver and the light emitting driver, and the data driver is respectively connected to a plurality of data lines ( D1 to Dn), the scan drivers are respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light emitting drivers are respectively connected to a plurality of light emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scanning signal line, at least one data line, at least one A light emitting signal line and a pixel driving circuit.
  • the timing controller may supply a gray value and a control signal suitable for the specification of the data driver to the data driver, and may supply a clock signal, a scan start signal, etc. suitable for the specification of the scan driver to the scan driver.
  • the driver can supply a clock signal, an emission stop signal, etc.
  • the data driver may generate data voltages to be supplied to the data lines D1, D2, D3, . . . and Dn using gray values and control signals received from the timing controller. For example, the data driver may sample grayscale values using a clock signal, and apply data voltages corresponding to the grayscale values to the data lines D1 to Dn in units of pixel rows, where n may be a natural number.
  • the scan driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, . . . and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller.
  • the scan driver may sequentially supply scan signals having turn-on level pulses to the scan signal lines S1 to Sm.
  • the scan driver can be configured in the form of a shift register, and can generate scan signals in such a manner as to sequentially transmit scan start signals supplied in the form of on-level pulses to the next-stage circuit under the control of a clock signal , m can be a natural number.
  • the light emitting driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, . . . and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller.
  • the light emission driver may sequentially supply emission signals having off-level pulses to the light emission signal lines E1 to Eo.
  • the light emitting driver can be configured in the form of a shift register, and can generate emission signals in a manner of sequentially transmitting emission stop signals provided in the form of off-level pulses to the next-stage circuit under the control of a clock signal, o Can be a natural number.
  • FIG. 2 is a schematic plan view of a display substrate.
  • the display substrate may include a display area AA, a binding area BD on one side of the display area AA, and a frame area BK on the other side of the display area AA.
  • the display area AA may include a plurality of sub-pixels configured to display dynamic pictures or still images
  • the bonding area BD may include data fan-out lines connecting a plurality of data lines to the integrated circuit
  • the frame area BK may include at least power lines for transmitting voltage signals
  • the binding area BD and the frame area BK may include an isolation dam in a ring structure, which is not limited in this disclosure.
  • the display area AA may include a first display area A1 and a second display area A2, and the first display area A1 may at least partially surround the second display area A2.
  • the first display area A1 is configured to display images
  • the position of the second display area A2 may correspond to the position of the optical device
  • the second display area A2 is configured to display images and transmit light , the transmitted light is received by the optical device.
  • the first display area may be called a normal display area
  • the second display area may be called a camera display area.
  • the position of the second display area A2 in the first display area A1 is not limited, and may be located above or below the first display area A1, or may be located at an edge of the first display area A1.
  • the shape of the second display area A2 can be any one or more of the following: rectangle, polygon, circle and ellipse, and the optical device can be a fingerprint recognition device, a camera or 3D imaging, etc. optical sensor.
  • the resolutions of the first display area A1 and the second display area A2 may be the same, or the resolution of the second display area A2 may be smaller than that of the first display area A1.
  • the resolution of the second display area A2 may be about 50% to 70% of the resolution of the first display area 200 .
  • Resolution Pixels Per Inch, PPI for short refers to the number of pixels per unit area, which can be called pixel density. The higher the PPI value, the higher the density of the display substrate, the richer the details of the picture.
  • Fig. 3 is a schematic plan view of a first display area.
  • the first display area may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P may include a first sub-pixel P1 that emits light of the first color, and a first sub-pixel P1 that emits light of the second color.
  • the second sub-pixel P2 for the light and the third sub-pixel P3 for emitting light of the third color, each of the three sub-pixels includes a pixel driving circuit and a light emitting device, and the pixel driving circuits in the three sub-pixels are respectively connected to the scanning signal line, the data line and the light emitting device.
  • the signal line is connected, and the pixel driving circuit is configured to receive the data voltage transmitted by the data line and output a corresponding current to the light emitting device under the control of the scanning signal line and the light emitting signal line.
  • the light-emitting devices in the three sub-pixels are respectively connected to the pixel driving circuits of the sub-pixels, and the light-emitting devices are configured to respond to the current output by the pixel driving circuits of the sub-pixels to emit light with corresponding brightness.
  • the first sub-pixel P1 may be a red sub-pixel that emits red (R) light
  • the second sub-pixel P2 may be a blue sub-pixel that emits blue (B) light
  • the third sub-pixel P3 It can be a green sub-pixel that emits green (G) light
  • the shape of the sub-pixel can be rectangular, rhombus, pentagon, or hexagon, etc., and can be arranged horizontally, vertically, or in characters.
  • a pixel unit may include four sub-pixels, which may be arranged in a horizontal arrangement, a vertical arrangement, a square, a diamond shape, etc., which are not limited in the present disclosure.
  • FIG. 4 is a schematic cross-sectional structure diagram of a first display area, illustrating the structure of three sub-pixels in the first display area.
  • the first display area may include a driving circuit layer 100B disposed on a base 100A, a light emitting structure layer 100C disposed on a side of the driving circuit layer 100B away from the base, and a light emitting structure layer 100C disposed on the base 100A.
  • the light emitting structure layer 100C is away from the encapsulation structure layer 100D on the side of the substrate.
  • the display substrate may include other film layers, such as spacer pillars, etc., which are not limited in this disclosure.
  • the substrate 100A may be a flexible substrate, or may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be poly Materials such as imide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, the material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., are used to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • PI imide
  • PET polyethylene terephthalate
  • SiNx silicon nitride
  • SiOx silicon oxide
  • the driving circuit layer 100B of each sub-pixel may include a pixel driving circuit composed of multiple transistors and storage capacitors.
  • the driving circuit layer 100B of each sub-pixel may include: a first insulating layer disposed on the substrate; an active layer disposed on the first insulating layer; a second insulating layer covering the active layer ; The gate electrode and the first capacitor electrode arranged on the second insulating layer; The third insulating layer covering the gate electrode and the first capacitor electrode; The second capacitor electrode arranged on the third insulating layer;
  • via holes are opened on the second insulating layer, the third insulating layer and the fourth insulating layer, and the active layer is exposed through the via holes; the source electrode and the drain electrode arranged on the fourth insulating layer, the source electrode and the The drain electrodes are respectively connected to the active layer through via holes; the planar layer covering
  • the light emitting structure layer 100C of each sub-pixel may include a light emitting device composed of multiple film layers, and the multiple film layers may at least include an anode, a pixel definition layer, an organic light emitting layer, and a cathode.
  • the anode can be arranged on the flat layer, and connected to the drain electrode of the driving transistor through the via hole opened on the flat layer.
  • the pixel definition layer is arranged on the anode and the flat layer, and a pixel opening is arranged on the pixel definition layer, and the pixel opening exposes the anode.
  • the organic light emitting layer is at least partly disposed in the pixel opening, and the organic light emitting layer is connected to the anode.
  • the cathode is arranged on the organic light-emitting layer, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode.
  • the encapsulation structure layer 100D may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer may use inorganic materials, and the second encapsulation layer may Organic materials are used, and the second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer, which can ensure that external water vapor cannot enter the light-emitting structure layer 100C.
  • the organic light-emitting layer may include an light-emitting layer (EML) and any one or more layers of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), Hole Blocking Layer (HBL), Electron Transport Layer (ETL) and Electron Injection Layer (EIL).
  • HIL hole injection layer
  • HTL hole transport layer
  • EBL electron blocking layer
  • HBL Hole Blocking Layer
  • ETL Electron Transport Layer
  • EIL Electron Injection Layer
  • the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected together, and adjacent sub-pixels
  • the light-emitting layers can have a small amount of overlap, or can be isolated from each other.
  • FIG. 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit.
  • the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure.
  • the pixel driving circuit may include 7 transistors (the first transistor T1 to the seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is connected with 7 signal lines (data line D, first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, the first power line VDD, the initial signal line INIT and the second power line VSS).
  • the pixel driving circuit may include a first node N1, a second node N2 and a third node N3.
  • the first node N1 is respectively connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4 and the second pole of the fifth transistor T5, and the second node N2 is respectively connected to the second pole of the first transistor
  • the first pole of the second transistor T2, the control pole of the third transistor T3 are connected to the second end of the storage capacitor C
  • the third node N3 is respectively connected to the second pole of the second transistor T2, the second pole of the third transistor T3 and the second terminal of the storage capacitor C.
  • the first pole of the sixth transistor T6 is connected.
  • the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the third transistor T3. Control pole connection.
  • the control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2.
  • the first transistor T1 transmits the first initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3.
  • the control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3.
  • the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.
  • the control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the third transistor T3
  • the second pole of T3 is connected to the third node N3.
  • the third transistor T3 may be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.
  • the control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data line D, and the second electrode of the fourth transistor T4 is connected to the first node N1.
  • the fourth transistor T4 may be referred to as a switching transistor, a scanning transistor, etc., and when a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 enables the data voltage of the data line D to be input to the pixel driving circuit.
  • the control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1.
  • the control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device.
  • the fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors.
  • the fifth transistor T5 and the sixth transistor T6 make the light emitting device emit light by forming a driving current path between the first power line VDD and the second power line VSS.
  • the control electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device.
  • the seventh transistor T7 transmits the second initial voltage to the first pole of the light emitting device, so that the amount of charge accumulated in the first pole of the light emitting device is initialized or The amount of charges accumulated in the first pole of the light emitting device is released.
  • the light emitting device may be an OLED comprising a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode), or may be a QLED comprising a stacked first pole (anode) , a quantum dot light-emitting layer and a second pole (cathode).
  • the second pole of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously high level signal.
  • the first scanning signal line S1 is the scanning signal line in the pixel driving circuit of this display row
  • the second scanning signal line S2 is the scanning signal line in the previous display row pixel driving circuit, that is, for the nth display row, the first scanning signal
  • the line S1 is S(n)
  • the second scanning signal line S2 is S(n-1)
  • the second scanning signal line S2 of this display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row
  • the signal lines can reduce the signal lines of the display panel and realize the narrow frame of the display panel.
  • the first to seventh transistors T1 to T7 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the seventh transistor T7 may use low temperature polysilicon thin film transistors, or may use oxide thin film transistors, or may use low temperature polysilicon thin film transistors and oxide thin film transistors.
  • the active layer of the low temperature polysilicon thin film transistor is made of low temperature polysilicon (Low Temperature Poly-Silicon, LTPS for short), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide).
  • Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current.
  • the low-temperature polysilicon thin-film transistors and oxide thin-film transistors are integrated on a display substrate to form low-temperature polycrystalline oxide (Low Temperature Polycrystalline Oxide (LTPO for short) display substrate can take advantage of the advantages of both to realize low-frequency drive, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline Oxide
  • FIG. 6 is a working timing diagram of a pixel driving circuit. The following describes an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in FIG. 5 .
  • the pixel driving circuit in FIG. 5 includes seven transistors (the first transistor T1 to the seventh transistor T7) and one storage capacitor C, All transistors are P-type transistors.
  • the working process of the pixel driving circuit may include:
  • the first phase t1 is called the reset phase
  • the signal of the second scanning signal line S2 is a low-level signal
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals.
  • the signal of the second scanning signal line S2 is a low-level signal to turn on the first transistor T1
  • the signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor.
  • the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, so that the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off. At this stage, the OLED Does not shine.
  • the signal of the first scanning signal line S1 is a low-level signal
  • the signals of the second scanning signal line S2 and the light-emitting signal line E are high-level signals
  • the data Line D outputs a data voltage.
  • the third transistor T3 is turned on.
  • the signal of the first scanning signal line S1 is a low level signal to turn on the second transistor T2 , the fourth transistor T4 and the seventh transistor T7 .
  • the second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data line D is provided to the second node through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. N2, and charge the difference between the data voltage output by the data line D and the threshold voltage of the third transistor T3 into the storage capacitor C, and the voltage at the second terminal (second node N2) of the storage capacitor C is Vd-
  • the seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), and the internal pre-stored voltage is cleared to complete the initialization and ensure that the OLED does not emit light.
  • the signal of the second scanning signal line S2 is a high level signal, which turns off the first transistor T1.
  • the signal of the light-emitting signal line E is a high-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned off.
  • the third stage t3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals.
  • the signal of the light-emitting signal line E is a low-level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power line VDD passes through the turned-on fifth transistor T5, third transistor T3 and sixth transistor T5.
  • the transistor T6 provides a driving voltage to the first electrode of the OLED to drive the OLED to emit light.
  • the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-
  • I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED
  • K is a constant
  • Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3
  • Vth is the third transistor T3
  • Vd is the data voltage output from the data line D
  • Vdd is the power supply voltage output from the first power line VDD.
  • FIG. 7 is a schematic plan view showing a binding region in a substrate.
  • the binding area BD in a plane parallel to the display substrate, the binding area BD may be located on one side of the display area AA, and along the direction away from the display area AA, the binding area BD may include The fan-out area B1, the bending area B2, the detection circuit area B3, the driver chip area B4 and the binding pin area B5 are arranged in sequence.
  • the first fan-out area B1 may at least include a first power line VDD, a second power line VSS, and a plurality of data transmission lines, and the plurality of data transmission lines are configured to connect the data lines of the display area AA in a fan-out (Fanout) routing manner,
  • the first power line VDD is configured as a high-level power line connected to the display area AA
  • the second power line VSS is configured as a low-level power line connected to the edge area.
  • the bending area B2 may include a composite insulating layer provided with grooves configured to bend the binding area BD to the back of the display area AA.
  • the detection circuit area B3 may be provided with detection circuits CT for detecting the display substrate, and these detection circuits CT may be connected to corresponding signal lines in the display area.
  • the driving chip area B4 can be provided with an integrated circuit IC, the integrated circuit IC is connected to the data signal line of the display area through the data transmission line in the first fan-out area B1, and the integrated circuit IC is configured to generate the driving signal required for driving the sub-pixel , and provide the driving signal to the data line of the display area.
  • the driving signal may be a data signal for driving the luminance of sub-pixels.
  • the binding pin area B5 can be provided with multiple pins (PIN), and the multiple pins are configured to be bound and connected to an external flexible printed circuit (FPC for short).
  • the binding area may include other circuits and signal lines, such as anti-static circuits, multiplexing circuits (MUX), etc., which are not limited in the present disclosure.
  • the detection circuit area B3 may include a detection circuit (Cell Test, CT for short), and the detection circuit may implement an aging (Aging) program of the display substrate and ET lighting detection.
  • the display substrate preparation process requires multiple tests, one of which is the Cell Test (ET for short) lighting (Light-on), ET light for short.
  • ET lighting inspection is to display the display substrate before binding the driver chip (IC) and the flexible circuit board (FPC) that inputs the display signal.
  • the pixels are colored, and the defect detection device is used to check whether each pixel is in good condition. , to confirm whether the display substrate is defective.
  • the aging program is a necessary process before the display device is shipped.
  • the interface can be Unstable aging, reducing the brightness attenuation of the light-emitting device, and increasing the life of the light-emitting device.
  • FIG. 8 is a schematic diagram of an equivalent circuit of a detection circuit.
  • the detection circuit may at least include a plurality of detection subunits 10 , control lines 20 and signal lines 30 , and each detection subunit 10 may include a control terminal, an input terminal and an output terminal.
  • One end of the control line 20 is correspondingly connected to the pins of the binding pin area, the other end of the control line 20 can be connected to the control ends of a plurality of detection subunits 10, and one end of the signal line 30 is connected to the pins of the binding pin area.
  • the pins are correspondingly connected, the other end of the signal line 30 can be connected correspondingly to the input terminals of multiple detection subunits 10, the output terminals of multiple detection subunits 10 can be connected correspondingly to multiple data lines in the display area, and the detection subunit 10 is It is configured to output the signal output by the signal line 30 to the data line in the display area under the control of the control line 20, so as to realize the burn-in procedure and lighting detection of the display substrate.
  • the aging process of the detection circuit is as follows: before the display substrate is bound to the driver chip (IC) and the flexible circuit board (FPC), the external device is connected to the pins of the binding area, and the external device passes through The pin outputs a control signal and an aging voltage signal to the signal line, the control signal controls multiple detection sub-units to conduct, and multiple detection sub-units output the aging voltage signal to multiple data lines in the display area, respectively for the red sub-pixel, blue The color sub-pixel and the green sub-pixel undergo an aging process.
  • IC driver chip
  • FPC flexible circuit board
  • a vertical line ripple (Mura) defect occurs on the display substrate.
  • the first display area and the second display area use the same aging voltage, the brightness characteristics of the light-emitting device in the first display area after aging are different from the brightness characteristics of the light-emitting device in the second display area after aging, so when the lighting is detected, There is a difference in brightness between the first display area and the second display area, so that the first display area presents a vertical line ripple defect.
  • FIG. 9a and 9b are schematic diagrams of an equivalent circuit of a detection circuit according to an exemplary embodiment of the present disclosure.
  • the second display area A2 is provided with a pixel driving circuit and a light emitting device (with built-in pixel driving circuit).
  • the display substrate shown in FIG. 9b only light-emitting devices are provided in the second display area A2 (the pixel driving circuit is externally installed).
  • the display substrate may include a display area AA and a binding area BD located on one side of the display area AA, the display area AA may include a first display area A1 and a second display area A2, and the first display area A1 may be At least partially surrounding the second display area A2, the first display area A1 is configured to display images, and the second display area A2 is configured to display images and transmit light.
  • the first display area A1 may include a plurality of first sub-pixels
  • the first sub-pixels may include a first pixel driving circuit and a first light-emitting device
  • the second display area A2 may include It includes a plurality of second sub-pixels
  • the second sub-pixel may include a second pixel driving circuit and a second light emitting device, and both the second pixel driving circuit and the second light emitting device are arranged in the second display area A2.
  • a plurality of first sub-pixels in the first display area A1 are regularly arranged to form a plurality of first pixel rows and a plurality of first pixel columns, and a plurality of second sub-pixels in the second display area A2 may be regularly arranged, A plurality of second pixel rows and a plurality of second pixel columns are formed.
  • the display area further includes a plurality of data lines D, and the plurality of data lines D may include a plurality of first data lines D1 and a plurality of second data lines D2.
  • a plurality of first data lines D1 and a plurality of second data lines D2 may extend along the first direction X and be sequentially arranged at set intervals along the second direction Y, each first data line D1 is connected to the first display
  • the first pixel driving circuits of a plurality of first sub-pixels in a pixel column in the area A1 are electrically connected
  • each second data line D2 is connected to the second pixel of a plurality of second sub-pixels in a pixel column in the second display area A2.
  • the driving circuit is electrically connected and connected to the first pixel driving circuit of some of the first sub-pixels.
  • the first direction X may be a column direction of the display substrate
  • the second direction Y may be a row direction of the display substrate
  • the first direction X and the second direction Y may be perpendicular to each other.
  • the first display area A1 may include a plurality of first sub-pixels
  • the first sub-pixels may include a first pixel driving circuit and a first light-emitting device
  • the second display area A2 may include It includes a plurality of second sub-pixels
  • the second sub-pixel includes a second light-emitting device and a second pixel driving circuit
  • the second light-emitting device of the second sub-pixel is arranged in the second display area A2
  • the second pixel of the second sub-pixel drives The circuit is arranged in the first display area A1, and the second light emitting device is connected to the second pixel driving circuit through the anode connection line.
  • the display area further includes a plurality of data lines D, and the plurality of data lines D may include a plurality of first data lines D1 and a plurality of second data lines D2.
  • the plurality of first data lines D1 and the plurality of second data lines D2 may extend along the first direction X and be sequentially arranged at set intervals along the second direction Y.
  • Each first data line D1 is connected to the first pixel driving circuits of a plurality of first sub-pixels in a pixel column
  • each second data line D2 is connected to the second pixel driving circuits of a plurality of second sub-pixels in a pixel column connected, and connected to the first pixel driving circuit of some of the first sub-pixels.
  • the detection circuit may be arranged in the binding area BD, and the detection circuit may at least include a plurality of first detection subunits 11, a plurality of second detection subunits 12, at least one control line 20, at least one first signal line 31 and at least one second signal line 32 .
  • the plurality of first detection subunits 11 and the plurality of second detection subunits 12 may each include a control terminal, an input terminal, and an output terminal, and the plurality of first detection subunits 11 and the plurality of second detection subunits
  • the subunits 12 can be arranged in sequence along the second direction Y at set intervals, the positions of the multiple first detection subunits 11 can correspond to the positions of the multiple first data lines D1 in the display area, and the multiple first detection subunits 11 can correspond to the positions of the multiple first data lines D1 in the display area.
  • the positions of the two detection sub-units 12 may be in one-to-one correspondence with the positions of the multiple second data lines D2 in the display area.
  • one end of the control line 20 is correspondingly connected to the control pins in the binding pin area, and the other end of the control line 20 is simultaneously connected to multiple first detection subunits 11 and multiple second detection subunits 12
  • the control line 20 is configured to control the turn-on or turn-off of the plurality of first detection sub-units 11 and the plurality of second detection sub-units 12 .
  • one end of the first signal line 31 is correspondingly connected to the first signal pin in the binding pin area, and the other end of the first signal line 31 is connected to the input ends of the plurality of first detection subunits 11 , the output terminals of the plurality of first detection subunits 11 are correspondingly connected to the plurality of first data lines D1 in the display area, the first signal line 31 is configured to receive a first signal from an external device through a first signal pin, and the first The detection sub-unit 11 is configured to output a first signal to the first data line D1 in the display area, and perform aging treatment or lighting detection on the first sub-pixel in the first display area.
  • one end of the second signal line 32 is correspondingly connected to the second signal pin in the binding pin area, and the other end of the second signal line 32 is connected to the input ends of a plurality of second detection subunits 12 , the output terminals of the plurality of second detection subunits 12 are correspondingly connected to the plurality of second data lines D2 in the display area, and the second signal line 32 is configured to receive a second signal from an external device through a second signal pin, and the second The detection sub-unit 12 is configured to output a second signal to the second data line D2 in the display area to perform aging treatment or lighting detection on the second sub-pixels in the second display area.
  • the working process of the detection circuit in this exemplary embodiment for aging treatment is: connect the external device to the control pin, the first signal pin and the second signal pin of the binding area, and the external device
  • the control signal is output through the control pin
  • the first aging voltage signal is output through the first signal pin
  • the second aging voltage signal is output through the second signal pin.
  • the first aging voltage and the second aging voltage are different.
  • the control signal transmitted by the control line 20 controls the plurality of first detection subunits 11 and the plurality of second detection subunits 12 to be turned on, and the turned on plurality of first detection subunits 11 ages the first signal transmitted by the first signal line 31
  • the voltage signals are respectively output to the multiple first data lines D1 in the display area, and the first aging voltage signals are used to perform aging treatment on the first sub-pixels in the first display area, and the multiple second detection sub-units 12 that are turned on turn on the first sub-pixels in the first display area.
  • the second aging voltage signal transmitted by the second signal line 32 is respectively output to a plurality of second data lines D2 in the display area, and the second aging voltage signal is used to perform aging treatment on the second sub-pixels in the second display area.
  • An exemplary embodiment of the present disclosure proposes a technical solution for partition aging, in which a first aging voltage is used for aging treatment on the first sub-pixels in the first display area, and a second aging voltage is applied to the second sub-pixels in the second display area. Aging treatment is performed, and the first aging voltage and the second aging voltage are different. Since the first display area and the second display area use different aging voltages, it can be ensured that the brightness characteristics of the aged light-emitting device in the first display area are basically the same as those of the aged light-emitting device in the second display area, which can eliminate The difference in brightness between the first display area and the second display area effectively avoids vertical line ripple defects in the display area.
  • FIG. 10 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • the detection circuit may include a plurality of first detection subunits 11, a plurality of second detection subunits 12, at least one control line 20, at least one first signal line 31, at least one second signal line 32, At least one switching control line 41 and at least one switching unit 42 .
  • the connection structure of the control line 20 , the first signal line 31 and the second signal line 32 and the plurality of first detection subunits 11 and the plurality of second detection subunits 12 is basically the same as that shown in FIG. 9 .
  • the switching unit 42 may include a switching control terminal, a switching first terminal and a switching second terminal.
  • One end of the switching control line 41 is correspondingly connected to the switching pin in the binding pin area, the other end of the switching control line 41 is connected to the switching control end of the switching unit 42, and the switching first end of the switching unit 42 is connected to the first signal line 31 connected, the switching second end of the switching unit 42 is connected to the second signal line 32, the switching control line 41 is configured to receive an external switching signal through the switching pin, and the switching unit 42 is configured to be under the control of the switching control line 41,
  • the first signal line 31 and the second signal line 32 are isolated or connected.
  • the first signal line 31 and the second signal line 32 When the first signal line 31 and the second signal line 32 are isolated, the first signal line 31 and the second signal line 32 output different aging voltage signals; when the first signal line 31 and the second signal line 32 are turned on, the second The first signal line 31 and the second signal line 32 output the same lighting voltage signal.
  • the switching unit 42 may include a switching transistor, the control pole of the switching transistor is connected to the switching control line 41, the first pole of the switching transistor is connected to the first signal line 31, and the second pole of the switching transistor is connected to the second The signal line 32 is connected.
  • the working process of the detection circuit in this exemplary embodiment performing the burn-in program is as follows: the external device outputs a control signal through a control pin, outputs a disconnection signal through a switching pin, and outputs a first signal through a first signal pin.
  • the aging voltage signal is used to output the second aging voltage signal through the second signal pin.
  • the control signal transmitted by the control line 20 controls the plurality of first detection subunits 11 and the plurality of second detection subunits 12 to be turned on, and the disconnection signal transmitted by the switching control line 41 controls the switching unit 42 to be turned off, so that the first signal line 31 It is isolated from the second signal line 32.
  • the plurality of first detection sub-units 11 that are turned on output the first aging voltage signal transmitted by the first signal line 31 to the plurality of first data lines D1 in the display area respectively, and use the first aging voltage signal to The first sub-pixel is subjected to aging processing.
  • the plurality of second detection subunits 12 that are turned on output the second aging voltage signal transmitted by the second signal line 32 to the plurality of second data lines D2 in the display area respectively, and use the second aging voltage signal to The second sub-pixel is subjected to aging treatment, and the aging voltages of the first display area and the second display area are different.
  • the working process of the detection circuit in this exemplary embodiment for lighting detection is as follows: the external device outputs a control signal through the control pin, outputs a conduction signal through the switching pin, and outputs the lighting voltage through the first signal pin signal or output the lighting voltage signal through the second signal pin.
  • the control signal transmitted by the control line 20 controls the multiple first detection subunits 11 and the multiple second detection subunits 12 to conduct, and the conduction signal transmitted by the switch control line 41 controls the switch unit 42 to conduct, so that the first signal line 31 In communication with the second signal line 32, the first signal line 31 and the second signal line 32 transmit the same lighting voltage signal.
  • the plurality of first detection subunits 11 and the plurality of second detection subunits 12 that are turned on output the lighting voltage signals to the plurality of first data lines D1 and the plurality of second data lines D2 in the display area respectively, using the same lighting
  • the voltage signal performs lighting detection on the sub-pixels in the first display area and the second display area.
  • the exemplary embodiment of the present disclosure proposes a technical solution for partition burn-in and overall lighting.
  • the first signal line and the second signal line are cut off by the set switching unit, and the first sub-line of the first display area
  • the pixels are subjected to aging treatment using the first aging voltage
  • the second sub-pixels in the second display area are subjected to aging treatment using the second aging voltage.
  • the aging voltages of the first display area and the second display area are different.
  • the provided switching unit conducts the first signal line and the second signal line, and uses the same lighting voltage to perform lighting detection for the first sub-pixel in the first display area and the second sub-pixel in the second display area.
  • the first display area and the second display area use different aging voltages, it can be ensured that the brightness characteristics of the aged light-emitting device in the first display area are basically the same as those of the aged light-emitting device in the second display area, which can eliminate The difference in brightness between the first display area and the second display area effectively avoids the occurrence of vertical line ripple defects. Since the first display area and the second display area use the same lighting voltage, picture uniformity can be ensured.
  • FIG. 11 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • the display area AA may include a plurality of first data lines D1 and a plurality of second data lines D2, the first data lines D1 are correspondingly connected to the first sub-pixels in the first display area, and the second data lines D2 is correspondingly connected to the second sub-pixel in the second display area, and the binding area BD may include a detection circuit.
  • the detection circuit may include a first detection unit E1, a second detection unit E2, a switching unit F and a plurality of signal lines, the first detection unit E1 may be located on one side of the switching unit F in the second direction Y, The second detection unit E2 may be located on one side of the first detection unit E1 in the second direction Y, and the first detection unit E1 may also be disposed on one side of the second detection unit E2 in the second direction Y.
  • the plurality of signal lines may at least include a switch control line 100, a first control line 110, a second control line 120, a third control line 130, a first detection line 210, a second detection line 220, a The third detection line 230, the fourth detection line 240, the fifth detection line 250, and the sixth detection line 260, the first end of the above-mentioned signal line is correspondingly connected to the pin in the binding pin area, and the second end extends to where the detection circuit is located.
  • the detection circuit area is connected with the first detection unit E1, the second detection unit E2 and the switching unit F correspondingly.
  • the first detection unit E1 may include a plurality of first detection subunits EY1 sequentially arranged at set intervals along the second direction Y, and the positions of the plurality of first detection subunits EY1 may be consistent with those displayed The positions of the multiple first data lines D1 in the area correspond to each other.
  • Each first detection subunit EY1 may include an eleventh switch unit EK11, a twelfth switch unit EK12, and a thirteenth switch unit EK13 arranged sequentially at a set interval along the first direction X, and each switch unit may Both include a control terminal, an input terminal and an output terminal.
  • the control terminal of the eleventh switch unit EK11 is connected to the first control line 110, the input terminal of the eleventh switch unit EK11 is connected to the first detection line 210, and the output terminal of the eleventh switch unit EK11 It is connected to the first data line D1 connected to the G sub-pixel in the display area through the first transmission line 91 .
  • the eleventh switch unit EK11 is configured to send the first signal transmitted by the first detection line 210 to the first data line D1 connected to the G sub-pixel under the control of the first control line 110 .
  • the control terminal of the twelfth switch unit EK12 is connected to the second control line 120
  • the input terminal of the twelfth switch unit EK12 is connected to the third detection line 230
  • the output terminal of the twelfth switch unit EK12 It is connected to the first data line D1 connected to the B sub-pixel in the display area through the second transmission line 92 .
  • the twelfth switch unit EK12 is configured to send the third signal transmitted by the third detection line 230 to the first data line D1 connected to the B sub-pixel under the control of the second control line 120 .
  • control terminal of the thirteenth switch unit EK13 is connected to the third control line 130
  • the input terminal of the thirteenth switch unit EK13 is connected to the fifth detection line 250
  • the output terminal of the thirteenth switch unit EK13 It is connected to the first data line D1 connected to the R sub-pixel in the display area through the second transmission line 92 .
  • the thirteenth switch unit EK13 is configured to send the fifth signal transmitted by the fifth detection line 250 to the first data line D1 connected to the R sub-pixel under the control of the third control line 130 .
  • the second detection unit E2 may include a plurality of second detection subunits EY2 sequentially arranged at set intervals along the second direction Y, and the positions of the plurality of second detection subunits EY2 may be consistent with the displayed The positions of the multiple second data lines D2 in the region correspond to each other.
  • Each second detection subunit EY2 may include a twenty-first switch unit EK21, a twenty-second switch unit EK22, and a twenty-third switch unit EK23 arranged sequentially at a set interval along the first direction X, each The switch units may each include a control terminal, an input terminal and an output terminal.
  • control terminal of the twenty-first switch unit EK21 is connected to the first control line 110
  • the input terminal of the twenty-first switch unit EK21 is connected to the second detection line 220
  • the twenty-first switch unit EK21 The output terminal of is connected to the second data line D2 connected to the G sub-pixel in the display area through the third transmission line 93 .
  • the twenty-first switch unit EK21 is configured to send the second signal transmitted by the second detection line 220 to the second data line D2 connected to the G sub-pixel under the control of the first control line 110 .
  • control terminal of the twenty-second switch unit EK22 is connected to the second control line 120
  • the input terminal of the twenty-second switch unit EK22 is connected to the fourth detection line 240
  • the twenty-second switch unit EK22 The output terminal of is connected to the second data line D2 connected to the B sub-pixel in the display area through the fourth transmission line 94 .
  • the twenty-second switching unit EK22 is configured to send the fourth signal transmitted by the fourth detection line 240 to the second data line D2 connected to the B sub-pixel under the control of the second control line 120 .
  • control terminal of the twenty-third switch unit EK23 is connected to the third control line 130
  • the input terminal of the twenty-third switch unit EK23 is connected to the sixth detection line 260
  • the twenty-third switch unit EK23 The output terminal of is connected to the second data line D2 connected to the R sub-pixel in the display area through the fourth transmission line 94 .
  • the twenty-third switch unit EK23 is configured to send the sixth signal transmitted by the sixth detection line 260 to the second data line D2 connected to the R sub-pixel under the control of the third control line 130 .
  • the switching unit F may include a first switching subunit FK1, a second switching subunit FK2, and a third switching subunit FK3, and each switching unit may include a control pole, a first pole, and a second pole. .
  • the control pole of the first switching subunit FK1 is connected to the switching control line 100
  • the first pole of the first switching subunit FK1 is connected to the first detection line 210
  • the second pole of the first switching subunit FK1 The pole is connected to the second detection line 220 .
  • the first switching subunit FK1 is configured to isolate or conduct the first detection line 210 and the second detection line 220 under the control of the switching control line 100. When the first detection line 210 and the second detection line 220 are isolated, The first detection line 210 and the second detection line 220 output different aging voltage signals, and when the first detection line 210 and the second detection line 220 are turned on, the first detection line 210 and the second detection line 220 output the same lighting voltage Signal.
  • the control pole of the second switching subunit FK2 is connected to the switching control line 100
  • the first pole of the second switching subunit FK2 is connected to the third detection line 230
  • the second pole of the second switching subunit FK2 The pole is connected to the fourth detection line 240 .
  • the second switching subunit FK2 is configured to isolate or conduct the third detection line 230 and the fourth detection line 240 under the control of the switching control line 100.
  • the third detection line 230 and the fourth detection line 240 output different aging voltage signals
  • the third detection line 230 and the fourth detection line 240 are turned on, the third detection line 230 and the fourth detection line 240 output the same lighting voltage Signal.
  • the control pole of the third switching subunit FK3 is connected to the switching control line 100
  • the first pole of the third switching subunit FK3 is connected to the fifth detection line 250
  • the second pole of the third switching subunit FK3 The pole is connected to the sixth detection line 260 .
  • the third switching subunit FK3 is configured to isolate or conduct the fifth detection line 250 and the sixth detection line 260 under the control of the switching control line 100.
  • the fifth detection line 250 and the sixth detection line 260 output different aging voltage signals
  • the fifth detection line 250 and the sixth detection line 260 are turned on, the fifth detection line 250 and the sixth detection line 260 output the same lighting voltage Signal.
  • the working process of the detection circuit of this exemplary embodiment performing the burn-in program is as follows:
  • the external device makes the switch control line 100 output the switch control signal, the first control line 110 output the first control signal, and the first detection line 210 output the first burn-in voltage through multiple pins.
  • signal, and the second detection line 220 outputs a second aging voltage signal
  • the switching control signal is an off signal
  • the first control signal is an on signal
  • the first aging voltage signal is different from the second aging voltage signal.
  • the disconnection signal output by the switching control line 100 disconnects the first switching sub-unit FK1 , and the first detection line 210 is isolated from the second detection line 220 .
  • the turn-on signal output by the first control line 110 respectively makes the eleventh switch unit EK11 and the twenty-first switch unit EK21 turn on, and the first aging voltage signal output by the first detection line 210 passes through the turned-on eleventh switch unit EK11 is output to the first data line D1 connected to the G sub-pixel in the display area to perform aging treatment on the G sub-pixel in the first display area, and the second aging voltage signal output by the second detection line 220 passes through the turned-on twentieth
  • a switch unit EK21 outputs to the second data line D2 connected to the G sub-pixel in the display area, and performs aging treatment on the G sub-pixel in the second display area.
  • the aging voltages of the first display area and the second display area are different.
  • the external device makes the switch control line 100 output a switch control signal, the second control line 120 outputs a second control signal, and the third detection line 230 outputs a third burn-in voltage through multiple pins.
  • signal, and the fourth detection line 240 outputs a fourth aging voltage signal
  • the switching control signal is an off signal
  • the second control signal is an on signal
  • the third aging voltage signal is different from the fourth aging voltage signal.
  • the disconnection signal output by the switching control line 100 disconnects the second switching sub-unit FK2 , and isolates the third detection line 230 from the fourth detection line 240 .
  • the turn-on signal output by the second control line 120 makes the twelfth switch unit EK12 and the twenty-second switch unit EK22 turn on respectively, and the third aging voltage signal output by the third detection line 230 passes through the turned-on twelfth switch unit EK12 outputs to the first data line D1 connected to the B sub-pixel in the display area to perform aging treatment on the B sub-pixel in the first display area, and the fourth aging voltage signal output by the fourth detection line 240 passes through the turned-on twentieth
  • the second switch unit EK22 outputs to the second data line D2 connected to the B sub-pixel in the display area to perform aging treatment on the B sub-pixel in the second display area.
  • the aging voltages of the first display area and the second display area are different.
  • the external device When performing the burn-in program on the R sub-pixels in the display area, the external device makes the switching control line 100 output a switching control signal, the third control line 130 outputs a third control signal, and the fifth detection line 250 outputs a fifth aging voltage through multiple pins. signal, and the sixth detection line 260 outputs a sixth aging voltage signal, the switching control signal is an off signal, the third control signal is an on signal, and the fifth aging voltage signal is different from the sixth aging voltage signal.
  • the disconnection signal output by the switching control line 100 disconnects the third switching sub-unit FK3 , and isolates the fifth detection line 250 from the sixth detection line 260 .
  • the turn-on signal output by the third control line 130 respectively makes the thirteenth switch unit EK13 and the twenty-third switch unit EK23 turn on, and the fifth aging voltage signal output by the fifth detection line 250 passes through the turned-on thirteenth switch unit EK13 outputs to the first data line D1 connected to the R sub-pixel in the display area to perform aging treatment on the R sub-pixel in the first display area, and the sixth aging voltage signal output by the sixth detection line 260 passes through the turned-on twentieth
  • the three-switch unit EK23 outputs to the second data line D2 connected to the R sub-pixel in the display area to perform aging treatment on the R sub-pixel in the second display area.
  • the aging voltages of the first display area and the second display area are different.
  • the working process of the detection circuit in this exemplary embodiment for lighting detection is as follows:
  • the external device When performing lighting detection on the G sub-pixels in the display area, the external device makes the switching control line 100 output the switching control signal, the first control line 110 outputs the first control signal, and the first detection line 210 or the second detection line through multiple pins.
  • the line 220 outputs the first lighting voltage signal
  • the switch control signal is the conduction signal
  • the first control signal is the conduction signal.
  • the conduction signal output by the switching control line 100 turns on the first switching subunit FK1, and the first detection line 210 and the second detection line 220 are connected to each other, so the first detection line 210 and the second detection line 220 output the same first Lighting voltage signal.
  • the turn-on signal output by the first control line 110 makes the eleventh switch unit EK11 and the twenty-first switch unit EK21 turn on respectively, and the first lighting voltage signal output by the first detection line 210 and the second detection line 220 is turned on.
  • the eleventh switch unit EK11 and the twenty-first switch unit EK21 output to the first data line D1 connected to the G sub-pixel and the second data line D2 connected to the G sub-pixel in the display area respectively, using the same lighting voltage for the first The G sub-pixels in the first display area and the second display area are turned on.
  • the external device When performing lighting detection on the B sub-pixel in the display area, the external device makes the switching control line 100 output the switching control signal, the second control line 120 outputs the second control signal, and the third detection line 230 or the fourth detection line through multiple pins.
  • the line 240 outputs the second lighting voltage signal, the switching control signal is the conduction signal, and the second control signal is the conduction signal.
  • the conduction signal output by the switching control line 100 turns on the second switching subunit FK2, and the third detection line 230 and the fourth detection line 240 are connected to each other, so the third detection line 230 and the fourth detection line 240 output the same second Lighting voltage signal.
  • the turn-on signal output by the second control line 120 makes the twelfth switch unit EK12 and the twenty-second switch unit EK22 turn on respectively, and the second lighting voltage signal output by the third detection line 230 and the fourth detection line 240 is turned on.
  • the twelfth switch unit EK12 and the twenty-second switch unit EK22 output to the first data line D1 connected to the B subpixel and the second data line D2 connected to the B subpixel in the display area respectively, and the same lighting voltage is used for the first data line D2 connected to the B subpixel.
  • the B sub-pixels in the first display area and the second display area are turned on.
  • the external device When performing lighting detection on the R sub-pixels in the display area, the external device makes the switching control line 100 output a switching control signal, the third control line 130 outputs a third control signal, and the fifth detection line 250 or the sixth detection line through multiple pins.
  • the line 260 outputs the third lighting voltage signal, the switching control signal is the conduction signal, and the third control signal is the conduction signal.
  • the conduction signal output by the switching control line 100 turns on the third switching subunit FK3, and the fifth detection line 250 and the sixth detection line 260 are connected to each other, so the fifth detection line 250 and the sixth detection line 260 output the same third Lighting voltage signal.
  • the turn-on signal output by the third control line 130 makes the thirteenth switch unit EK13 and the twenty-third switch unit EK23 turn on respectively, and the third lighting voltage signal output by the fifth detection line 250 and the sixth detection line 260 is turned on.
  • the thirteenth switch unit EK13 and the twenty-third switch unit EK23 respectively output to the first data line D1 connected to the R sub-pixel and the second data line D2 connected to the R sub-pixel in the display area.
  • the R sub-pixels in the first display area and the second display area are turned on.
  • the first switching subunit FK1 may include two first transistors connected in series, the control poles of the two first transistors are connected to the switching control line, and the first pole of one first transistor is connected to the first detection line connected, the second pole of the other first transistor is connected to the second detection line, and the second pole of one first transistor is connected to the first pole of the other first transistor.
  • the second switching subunit FK2 may include two second transistors connected in series, the control poles of the two second transistors are connected to the switching control line, and the first pole of one second transistor is connected to the third detection line connected, the second pole of the other second transistor is connected to the fourth detection line, and the second pole of one second transistor is connected to the first pole of the other second transistor.
  • the third switching subunit FK3 may include two third transistors connected in series, the control poles of the two third transistors are connected to the switching control line, and the first pole of one third transistor is connected to the fifth detection line connected, the second pole of the other third transistor is connected to the sixth detection line, and the second pole of one third transistor is connected to the first pole of the other third transistor.
  • the eleventh switch unit EK11 may include at least one eleventh transistor, the control electrode of the eleventh transistor is connected to the first control line, and the first electrode of the eleventh transistor is connected to the first detection line , the second pole of the eleventh transistor is connected to the first data line connected to the G sub-pixel in the first display region.
  • the twelfth switch unit EK12 may include at least one twelfth transistor and at least one thirteenth transistor, the control electrodes of the twelfth transistor and the thirteenth transistor are connected to the second control line, and the tenth transistor The first poles of the second transistor and the thirteenth transistor are connected to the third detection line, and the second poles of the twelfth transistor and the thirteenth transistor are connected to the first data line connected to the B sub-pixel in the first display area.
  • the thirteenth switching unit EK13 may include at least one fourteenth transistor and at least one fifteenth transistor, the control electrodes of the fourteenth transistor and the fifteenth transistor are connected to the third control line, and the tenth transistor The first poles of the fourth transistor and the fifteenth transistor are connected to the fifth detection line, and the second poles of the fourteenth transistor and the fifteenth transistor are connected to the first data line connected to the R sub-pixel in the first display area.
  • the twenty-first switch unit EK21 may include at least one twenty-first transistor, the control electrode of the twenty-first transistor is connected to the first control line, and the first electrode of the twenty-first transistor is connected to the first control line.
  • the two detection lines are connected, and the second electrode of the twenty-first transistor is connected to the second data line connected to the G sub-pixel in the second display area.
  • the twenty-second switching unit EK22 may include at least one twenty-second transistor and at least one twenty-third transistor, the control electrodes of the twenty-second transistor and the twenty-third transistor are connected to the second control line connection, the first poles of the twenty-second transistor and the twenty-third transistor are connected to the fourth detection line, and the second poles of the twenty-second transistor and the twenty-third transistor are connected to the B sub-pixel in the second display area The second data line connection.
  • the twenty-third switch unit EK23 may include at least one twenty-fourth transistor and at least one twenty-fifth transistor, the control electrodes of the twenty-fourth transistor and the twenty-fifth transistor are connected to the third control line connection, the first poles of the twenty-fourth transistor and the twenty-fifth transistor are connected to the sixth detection line, and the second poles of the twenty-fourth transistor and the twenty-fifth transistor are connected to the R sub-pixel in the second display area The second data line connection.
  • the detection circuit in a plane perpendicular to the display substrate, the detection circuit may include:
  • a semiconductor layer disposed on the first insulating layer, the semiconductor layer may include an active layer of a plurality of transistors in the switching unit, an active layer of a plurality of transistors in the first detection subunit, and an active layer of a plurality of transistors in the second detection subunit active layer;
  • a second insulating layer covering the semiconductor layer, and a first conductive layer disposed on the second insulating layer, the first conductive layer may include gate electrodes of multiple transistors in the switching unit, gate electrodes of multiple transistors in the first detection sub-unit electrodes and gate electrodes of multiple transistors in the second detection subunit;
  • a fourth insulating layer covering the second conductive layer, and a plurality of via holes are arranged on the fourth insulating layer;
  • a third conductive layer disposed on the fourth insulating layer, the third conductive layer may include the control line, the first signal line and the second signal line.
  • control lines include a first control line, a second control line and a third control line, at least one of the first control line, the second control line and the third control line includes a control lead line and a control extension line, the control lead-out line and the control extension line are connected by a signal connection line, the signal connection line is arranged in the first conductive layer, the control lead-out line and the control extension line are arranged in the second in three conductive layers.
  • the first signal line includes a first detection line, a third detection line, and a fifth detection line
  • the second signal line includes a second detection line, a fourth detection line, and a sixth detection line
  • at least one of the first detection line, the second signal line, the third detection line, the fourth detection line, the fifth detection line and the sixth detection line includes a detection lead-out line and a detection extension line
  • the detection lead-out line is connected with the detection extension line through the signal connection line
  • the signal connection line is arranged in the first conductive layer
  • the detection lead-out line and the detection extension line are arranged in the third conductive layer.
  • the first conductive layer further includes a switch connection line
  • the third conductive layer further includes a switch control line
  • the switch connection line is connected to the switch control line through a via hole
  • the switch The connecting wire and the gate electrodes of the plurality of transistors in the switching unit are connected to each other as an integral structure.
  • the first detection subunit includes a first transmission line and a second transmission line, and the first transmission line is connected to a first data line connected to a first color sub-pixel in the first display area, so The second transmission line is connected to the first data line connecting the second color sub-pixel and the third color sub-pixel in the first display area; the first transmission line is arranged in the first conductive layer, and the second A transmission line is disposed in the second conductive layer.
  • the second transmission line is provided with a twenty-first connection block and a twenty-second connection block;
  • the twenty-first connection block is connected to the first detector through the twelfth connection electrode
  • the twelfth active layer and the thirteenth active layer in the unit are connected, and the twenty-first connection block is arranged between the twelfth active layer and the thirteenth active layer;
  • the second The twelfth connection block is connected to the fourteenth active layer and the fifteenth active layer in the first detection subunit through the thirteenth connection electrode, and the twenty-second connection block is arranged on the fourteenth active layer. between the active layer and the fifteenth active layer.
  • the twelfth connection electrode and the thirteenth connection electrode are disposed in the third conductive layer.
  • the second detection subunit includes a third transmission line and a fourth transmission line
  • the third transmission line is connected to the second data line connected to the first color sub-pixel in the second display area
  • the fourth transmission line is connected to the second data line connecting the second color sub-pixel and the third color sub-pixel in the second display area;
  • the third transmission line is arranged in the first conductive layer, and the fourth A transmission line is disposed in the second conductive layer.
  • the fourth transmission line is provided with a forty-first connection block, a forty-second connection block, a forty-third connection block, and a forty-fourth connection block;
  • the forty-first connection The block is connected to the twenty-second active layer in the second detection subunit through the twenty-second connection electrode, and the forty-first connection block is arranged in the first direction of the twenty-second active layer One side;
  • the forty-second connection block is connected to the twenty-third active layer in the second detection subunit through the twenty-third connection electrode, and the forty-second connection block is arranged on the first The side of the twenty-third active layer opposite to the first direction;
  • the forty-third connection block is connected to the twenty-fourth active layer in the second detection subunit through the twenty-fourth connection electrode,
  • the forty-third connection block is arranged on one side of the twenty-fourth active layer in the first direction;
  • the forty-fourth connection block is connected to the second detection subunit through the twenty-fifth connection electrode The twenty-fifth active layer connection, the forty
  • the twenty-second connection electrode, the twenty-third connection electrode, the twenty-fourth connection electrode, and the twenty-fifth connection electrode are disposed in the third conductive layer.
  • the following is an exemplary description through the preparation process of the detection circuit.
  • the "patterning process” mentioned in this disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and other treatments for metal materials, inorganic materials or transparent conductive materials, and for organic materials, including Coating of organic materials, mask exposure and development, etc.
  • Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition
  • coating can use any one or more of spray coating, spin coating and inkjet printing
  • etching can use dry etching and wet Any one or more of the engravings is not limited in the present disclosure.
  • “Thin film” refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes.
  • the "thin film” does not require a patterning process during the entire manufacturing process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “film” before the patterning process, and it is called a “layer” after the patterning process.
  • the “layer” after the patterning process includes at least one "pattern”.
  • “A and B are arranged in the same layer” in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate.
  • the orthographic projection of A includes the orthographic projection of B
  • the orthographic projection of B is within the range of the orthographic projection of A
  • the boundary of the orthographic projection of B falls within the orthographic projection of A , or the boundary of A's orthographic projection overlaps the boundary of B's orthographic projection.
  • the manufacturing process of the detection circuit may include the following operations.
  • Forming a semiconductor layer pattern on a substrate may include: sequentially depositing a first insulating film and a semiconductor film on the substrate, patterning the semiconductor film through a patterning process, and forming a first insulating layer covering the entire substrate.
  • the semiconductor layer pattern at least includes a plurality of active layers of the switching unit, a plurality of active layers of the first detection subunit and a plurality of active layers of the second detection subunit Layer, as shown in Figure 12a, Figure 12b and Figure 12c,
  • Figure 12a is the structure of the A region in Figure 11
  • Figure 12b is the structure of the B region in Figure 11, showing four first detection subunits
  • Figure 12c is a diagram The structure of region C in 11 shows four second detection subunits.
  • the plurality of active layers of the switching unit may include sequentially disposing a first active layer 101, a second active layer 102, and a third active layer along the first direction X 103.
  • Each active layer may be in the shape of a strip extending along the second direction Y.
  • the first active layer 101 may serve as an active layer of two first transistors T1
  • the second active layer 102 may serve as an active layer of two second transistors T2
  • the third active layer 103 may serve as the active layer of the two third transistors T3.
  • a plurality of first detection subunits may be sequentially arranged along the second direction Y, and a plurality of active layers of each first detection subunit may include X arranges the eleventh active layer 111, the twelfth active layer 112, the thirteenth active layer 113, the fourteenth active layer 114 and the fifteenth active layer 115 in sequence, and each active layer can be A bar shape extending along the first direction X.
  • the eleventh active layer 111 may serve as the active layer of the eleventh transistor T11
  • the twelfth active layer 112 may serve as the active layer of the twelfth transistor T12
  • the thirteenth active layer 112 may serve as the active layer of the twelfth transistor T12.
  • the layer 113 can be used as the active layer of the thirteenth transistor T13
  • the fourteenth active layer 114 can be used as the active layer of the fourteenth transistor T14
  • the fifteenth active layer 115 can be used as the active layer of the fifteenth transistor T15. layer.
  • a plurality of second detection subunits can be arranged in sequence along the second direction Y, and multiple active layers of each second detection subunit can include X sequentially arranges the twenty-first active layer 121, the twenty-second active layer 122, the twenty-third active layer 123, the twenty-fourth active layer 124 and the twenty-fifth active layer 125, each The active layer may be in a stripe shape extending along the first direction X.
  • the twenty-first active layer 121 may serve as the active layer of the twenty-first transistor T21
  • the twenty-second active layer 122 may serve as the active layer of the twenty-second transistor T22
  • the twenty-second active layer 122 may serve as the active layer of the twenty-second transistor T22.
  • the twenty-third active layer 123 can be used as the active layer of the twenty-third transistor T23
  • the twenty-fourth active layer 124 can be used as the active layer of the twenty-fourth transistor T24
  • the twenty-fifth active layer 125 can be used as the active layer of the twenty-third transistor T23.
  • the shapes of the plurality of active layers in the switching unit may be substantially the same, the semiconductor patterns of the plurality of first detection subunits may be substantially the same, and the semiconductor patterns of the plurality of second detection subunits may be substantially the same. same.
  • the substrate may be a flexible substrate, or a rigid substrate, which is not limited by the present disclosure.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate forming the aforementioned pattern, and patterning the first conductive film through a patterning process to form a covering The second insulating layer of the semiconductor layer pattern, and the first conductive layer pattern disposed on the second insulating layer, the first conductive layer pattern at least includes: a switching connection line of the switching unit, a plurality of signal connection lines and a plurality of gate electrodes, A plurality of gate connection lines, a plurality of gate electrodes and the first transmission line of the first detection subunit, and a plurality of gate connection lines, a plurality of gate electrodes and the third transmission line of the second detection subunit, as shown in Fig.
  • FIG. 13a is the structure of region A in FIG. 11
  • FIG. 13b is the structure of region B in FIG. 11
  • FIG. 13c is the structure of region C in FIG.
  • the first conductive layer may be referred to as a first gate metal layer (GATE1).
  • the plurality of gate electrodes of the switching unit may include sequentially disposing a first gate electrode 201, a second gate electrode 202, and a third gate electrode 203 along the first direction X, each The gate electrode may be in the shape of a rectangular ring, and the orthographic projection of the two sides extending along the first direction X in the rectangular ring on the substrate at least partially overlaps the orthographic projection of the corresponding active layer on the substrate to form two transistors the gate electrode.
  • the orthographic projection of the two sides extending along the first direction X on the substrate of the first gate electrode 201 at least partially overlaps the orthographic projection of the first active layer 101 on the substrate, serving as the gates of the two first transistors T1 electrode.
  • the orthographic projection of the two sides extending along the first direction X on the substrate of the second gate electrode 202 at least partially overlaps the orthographic projection of the second active layer 102 on the substrate, serving as the gates of the two second transistors T2 electrode.
  • the orthographic projection of the two sides extending along the first direction X on the substrate of the third gate electrode 203 at least partially overlaps the orthographic projection of the third active layer 103 on the substrate, serving as the gates of the two third transistors T3 electrode.
  • the switching connection line 56 of the switching unit may be in the shape of a line extending along the first direction X, and is respectively connected to the first gate electrode 201, the second gate electrode 202, and the third gate electrode 203, and the switching The connection line 56 is configured to be connected to a subsequently formed switching control line.
  • the first gate electrode 201 , the second gate electrode 202 , the third gate electrode 203 and the switching connection line 56 may be an integral structure connected to each other.
  • the plurality of signal connection lines of the switching unit may include a first signal connection line 51 , a second signal connection line 52 , a third signal connection line 53 , a fourth signal connection line arranged in sequence along the first direction X.
  • the connection line 54 and the fifth signal connection line 55 , five signal connection lines are all located on one side of the switch connection line 56 in the second direction Y.
  • the first signal connection line 51 is configured as a connection line for a subsequently formed second detection line
  • the second signal connection line 52 is configured as a connection line for a subsequently formed first detection line
  • the third signal connection line 53 is configured as a connection line for the subsequently formed third detection line
  • the fourth signal connection line 54 is configured as a connection line for the subsequently formed third control line
  • the fifth signal connection line 55 is configured as As the connection line of the fifth detection line formed subsequently.
  • the first signal connection line 51 to the fifth signal connection line 55 are used as connection lines of the subsequently formed signal lines, which can avoid crossing of the signal lines and facilitate the layout of the subsequently formed signal lines.
  • the plurality of gate electrodes of the first detection subunit may include an eleventh gate electrode 211, a twelfth gate electrode 212, a thirteenth The gate electrode 213, the fourteenth gate electrode 214, and the fifteenth gate electrode 215, each gate electrode may be in the shape of a strip extending along the second direction Y, and may be located in the middle region of the corresponding active layer in the first direction X,
  • the orthographic projection of the bar shape on the substrate at least partially overlaps the orthographic projection of the corresponding active layer on the substrate.
  • the eleventh gate electrode 211 may serve as the gate electrode of the eleventh transistor T11
  • the twelfth gate electrode 212 may serve as the gate electrode of the twelfth transistor T12
  • the thirteenth gate electrode 213 may serve as the gate electrode of the thirteenth transistor T13
  • the fourteenth gate electrode 214 may serve as the gate electrode of the fourteenth transistor T14
  • the fifteenth gate electrode 215 may serve as the gate electrode of the fifteenth transistor T15.
  • the gate connection lines of the first detection subunit may include an eleventh gate connection line 61 , a twelfth gate connection line 62 and a thirteenth gate connection line 63 .
  • the eleventh gate connection line 61 may be in the shape of a line whose main body extends along the first direction X, and the end of the eleventh gate connection line 61 in the direction opposite to the first direction X is connected to The eleventh gate electrode 211 is connected, and the eleventh gate connection line 61 is configured to be connected to the subsequently formed first control line.
  • the twelfth gate connection line 62 may be in the shape of a line whose main body extends along the first direction X, and the end of the twelfth gate connection line 62 in the direction opposite to the first direction X is simultaneously Connected to the twelfth gate electrode 212 and the thirteenth gate electrode 213 , the twelfth gate connection line 62 is configured to be connected to a second control line formed subsequently.
  • the thirteenth gate connection line 63 may be in the shape of a line whose main body extends along the first direction X, and the end of the thirteenth gate connection line 63 in the first direction X is simultaneously connected to the tenth gate connection line.
  • the four gate electrodes 214 are connected to the fifteenth gate electrode 215 , and the thirteenth gate connection line 63 is configured to be connected to a third control line formed later.
  • the first transmission line 91 of the first detection subunit may be in the shape of a line whose main part extends along the first direction X, and may be located on one side of the second direction Y of the plurality of active layers.
  • the first transmission line 91 is configured to be connected to the first data line connecting the G sub-pixels in the display area.
  • the first transmission line 91 is provided with an eleventh connection block 91-1, and the eleventh connection block 91-1 is located on the side of the eleventh active layer 111 opposite to the first direction X,
  • the eleventh connection block 91 - 1 is configured to be connected to the eleventh active layer 111 through a subsequently formed eleventh connection electrode.
  • the first conductive layer patterns of odd-numbered first detection subunits may be substantially the same, and the first conductive layer patterns of even-numbered first detection subunits may be substantially the same , but the first conductive layer patterns of odd-numbered first detection subunits and even-numbered first detection subunits may be different.
  • the shapes and positions of the eleventh gate electrode 211 to the fifteenth gate electrode 215, the eleventh gate connection line 61 and the first transmission line 91 are substantially the same , the shapes of the twelfth gate connection line 62 and the thirteenth gate connection line 63 in the odd-numbered first detection subunits and the even-numbered first detection subunits are different.
  • the plurality of gate electrodes of the second detection subunit may include sequentially disposing the twenty-first gate electrode 221, the twenty-second gate electrode 222, the The twenty-third gate electrode 223, the twenty-fourth gate electrode 224, and the twenty-fifth gate electrode 225, each gate electrode may be in the shape of a strip extending along the second direction Y, and may be located in the first direction of the corresponding active layer.
  • the orthographic projection of the bar shape on the substrate at least partially overlaps with the orthographic projection of the corresponding active layer on the substrate.
  • the twenty-first gate electrode 221 can be used as the gate electrode of the twenty-first transistor T21
  • the twenty-second gate electrode 222 can be used as the gate electrode of the twenty-second transistor T22
  • the twenty-third gate electrode 223 can be used as the twenty-first transistor T22.
  • the gate electrode of the third transistor T23, the twenty-fourth gate electrode 224 may serve as the gate electrode of the twenty-fourth transistor T24, and the twenty-fifth gate electrode 225 may serve as the gate electrode of the twenty-fifth transistor T25.
  • the gate connection lines of the second detection subunit may include a twenty-first gate connection line 71 , a twenty-second gate connection line 72 , and a twenty-third gate connection line 73 .
  • the twenty-first gate connection line 71 may be in the shape of a line whose main part extends along the first direction X, and the end of the twenty-first gate connection line 71 in the direction opposite to the first direction X part is connected to the twenty-first gate electrode 221, and the twenty-first gate connection line 71 is configured to be connected to the first control line formed subsequently.
  • the twenty-second gate connection line 72 may be in the shape of a line whose main body extends along the first direction X, and the end of the twenty-second gate connection line 72 in the direction opposite to the first direction X The portion is connected to the twenty-second gate electrode 222 and the twenty-third gate electrode 223 at the same time, and the twenty-second gate connection line 72 is configured to be connected to the second control line formed subsequently.
  • the twenty-third gate connection line 73 may be in the shape of a line whose main part extends along the first direction X, and the end of the twenty-third gate connection line 73 in the first direction X is simultaneously connected to the The twenty-fourth gate electrode 224 is connected to the twenty-fifth gate electrode 225 , and the twenty-third gate connection line 73 is configured to be connected to a third control line formed subsequently.
  • the third transmission line 93 of the second detection subunit may be in the shape of a line whose main part extends along the first direction X, and may be located on one side of the second direction Y of the plurality of active layers.
  • the third transmission line 93 is configured to be connected to the second data line connecting the G sub-pixels in the display area.
  • the third transmission line 93 is provided with a thirty-first connection block 93-1, and the thirty-first connection block 93-1 is located in the direction opposite to the first direction X of the twenty-first active layer 121.
  • the thirty-first connection block 93 - 1 is configured to be connected to the twenty-first active layer 121 through a subsequently formed twenty-first connection electrode.
  • the first conductive layer patterns of odd-numbered second detection subunits may be substantially the same, and the first conductive layer patterns of even-numbered second detection subunits may be substantially the same , but the patterns of the first conductive layer of the odd-numbered second detection subunits and the even-numbered second detection subunits may be different.
  • the shapes and positions of the twenty-first to twenty-fifth gate electrodes 221 to 225, the twenty-first gate connection line 71, and the third transmission line 93 Basically the same, the shape of the twenty-second gate connection line 72 and the twenty-third gate connection line 73 in the odd-numbered second detection subunits and the even-numbered second detection subunits are different.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate forming the aforementioned pattern, and patterning the second conductive film through a patterning process to form a covering
  • the third insulating layer of the first conductive layer pattern, and the second conductive layer pattern disposed on the third insulating layer, the second conductive layer pattern at least includes: the second transmission line of the first detection subunit and the second detection subunit
  • the fourth transmission line is shown in FIG. 14a and FIG. 14b , FIG. 14a is the structure of area B in FIG. 11 , and FIG. 14b is the structure of area C in FIG. 11 .
  • the second conductive layer may be referred to as a second gate metal layer (GATE2).
  • the second transmission line 92 of the first detection subunit can be in the shape of a line whose main part extends along the first direction X, and can be located in the second direction Y of multiple active layers.
  • the second transmission line 92 is configured to be connected to the first data line connecting the B sub-pixel and the R sub-pixel in the display area.
  • a twenty-first connection block 92 - 1 and a twenty-second connection block 92 - 2 may be disposed on the second transmission line 92 .
  • the twenty-first connection block 92-1 may be located between the twelfth active layer 112 and the thirteenth active layer 113, and the twenty-first connection block 92-1 is configured to pass through a subsequently formed twelfth connection electrode. It is connected to the twelfth active layer 112 and the thirteenth active layer 113 at the same time.
  • the twenty-second connection block 92-2 may be located between the fourteenth active layer 114 and the fifteenth active layer 115, and the twenty-second connection block 92-2 is configured to pass through the subsequently formed thirteenth connection electrode. It is connected to the fourteenth active layer 114 and the fifteenth active layer 115 at the same time.
  • the second conductive layer patterns of the plurality of first detection subunits may be substantially the same.
  • the fourth transmission line 94 of the second detection subunit can be in the shape of a line whose main part extends along the first direction X, and can be located in the second direction Y of multiple active layers.
  • the fourth transmission line 94 is configured to be connected to the second data line connecting the B sub-pixel and the R sub-pixel in the display area.
  • the fourth transmission line 94 may be provided with a forty-first connection block 94-1, a forty-second connection block 94-2, a forty-third connection block 94-3, and a forty-fourth connection block.
  • the forty-first connection block 94-1 may be located on one side of the twenty-second active layer 122 in the first direction X, and the forty-first connection block 94-1 is configured to communicate with the twenty-second connection electrode formed subsequently.
  • the twenty-second active layer 122 is connected.
  • the forty-second connection block 94-2 may be located on the opposite side of the first direction X of the twenty-third active layer 123, and the forty-second connection block 94-2 is configured to pass through the subsequently formed twenty-third The connection electrodes are connected to the twenty-third active layer 123 .
  • the forty-third connection block 94-3 may be located on one side of the twenty-fourth active layer 124 in the first direction X, and the forty-third connection block 94-3 is configured to communicate with the twenty-fourth connection electrode formed subsequently.
  • the twenty-fourth active layer 124 is connected.
  • the forty-fourth connection block 94-4 may be located on the opposite side of the first direction X of the twenty-fifth active layer 125, and the forty-fourth connection block 94-4 is configured to pass through the subsequently formed twenty-fifth The connection electrode is connected to the twenty-fifth active layer 125 .
  • the second conductive layer patterns of the plurality of second detection subunits may be substantially the same.
  • forming the pattern of the fourth insulating layer may include: depositing a fourth insulating film on the substrate forming the aforementioned pattern, patterning the fourth insulating film through a patterning process, and forming a fourth insulating film covering the second conductive layer.
  • Four insulating layer patterns, a plurality of via holes are formed on the fourth insulating layer, as shown in Figure 15a, Figure 15b and Figure 15c, Figure 15a is the structure of the A region in Figure 11, and Figure 15b is the structure of the B region in Figure 11 , Fig. 15c is the structure of region C in Fig. 11 .
  • a plurality of switching units may include a first via hole K1, a second via hole K2, a third via hole K3, a fourth via hole K4, and a fifth via hole K5.
  • the orthographic projection of the first via hole K1 on the substrate may be within the range of the orthographic projection of the first region of the first active layer 101 on the substrate, and the second via hole K1
  • the insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the first region of the first active layer 101, and the first via hole K1 is configured to allow the subsequently formed first detection line to pass through it.
  • the via hole is connected with the first region of the first active layer 101 .
  • the orthographic projection of the second via hole K2 on the substrate may be within the range of the orthographic projection of the second region of the first active layer 101 on the substrate, and the second via hole K2
  • the insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the second region of the first active layer 101, and the second via hole K2 is configured to allow the subsequently formed second detection line to pass through the surface.
  • the via hole is connected with the second region of the first active layer 101 .
  • the orthographic projections of at least two third via holes K3 on the substrate may be within the range of the orthographic projection of the third region of the first active layer 101 on the substrate, and the two third via holes K3 K3 is located between the first via hole K1 and the second via hole K2, the second insulating layer, the third insulating layer and the fourth insulating layer in the third via hole K3 are etched away, exposing the first active layer 101 On the surface of the third area of the first active layer 101 , the two third via holes K3 are configured to connect the subsequently formed first connection electrode to the third area of the first active layer 101 through the via holes.
  • the orthographic projection of the fourth via hole K4 on the substrate may be within the range of the orthographic projection of the first region of the second active layer 102 on the substrate, and the second The insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the first region of the second active layer 102, and the fourth via hole K4 is configured to allow the subsequently formed third detection line to pass through it.
  • the via hole is connected with the first region of the second active layer 102 .
  • the orthographic projection of the fifth via hole K5 on the substrate may be within the range of the orthographic projection of the second region of the second active layer 102 on the substrate, and the second The insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the second region of the second active layer 102, and the fifth via hole K5 is configured to allow the subsequently formed fourth detection line to pass through it.
  • the via hole is connected with the second region of the second active layer 102 .
  • the orthographic projections of at least two sixth via holes K6 on the substrate may be within the range of the orthographic projection of the third region of the second active layer 102 on the substrate, and the two sixth via holes K6 K6 is located between the fourth via hole K4 and the fifth via hole K5, the second insulating layer, the third insulating layer and the fourth insulating layer in the sixth via hole K6 are etched away, exposing the second active layer 102 On the surface of the third region of the second active layer 102 , the two sixth via holes K6 are configured to connect the subsequently formed second connection electrode to the third region of the second active layer 102 through the via holes.
  • the orthographic projection of the seventh via hole K7 on the substrate may be within the range of the orthographic projection of the first region of the third active layer 103 on the substrate, and the second The insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the first region of the third active layer 103, and the seventh via hole K7 is configured to allow the subsequently formed fifth detection line to pass through this The via hole is connected with the first region of the third active layer 103 .
  • the orthographic projection of the eighth via hole K8 on the substrate may be within the range of the orthographic projection of the second region of the third active layer 103 on the substrate, and the second The insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the second region of the third active layer 103, and the eighth via hole K8 is configured to allow the subsequently formed sixth detection line to pass through the second region.
  • the via hole is connected with the second region of the third active layer 103 .
  • the orthographic projections of at least two ninth via holes K9 on the substrate may be within the range of the orthographic projection of the third region of the third active layer 103 on the substrate, and the two ninth via holes K9 K9 is located between the seventh via hole K7 and the eighth via hole K8, the second insulating layer, the third insulating layer and the fourth insulating layer in the ninth via hole K9 are etched away, exposing the third active layer 103
  • the two ninth via holes K9 are configured to connect the subsequently formed third connection electrode to the third region of the third active layer 103 through the via holes.
  • the orthographic projection of the tenth via hole K10 on the substrate may be within the range of the orthographic projection of the switching connection line 56 on the substrate, and the third insulating layer and the fourth insulating layer in the tenth via hole K10 The layer is etched away, exposing the surface of the switching connection line 56 , and the tenth via hole K10 is configured to allow a subsequently formed switching control line to be connected to the switching connection line 56 through the via hole.
  • the orthographic projections of at least two eleventh via holes K11 on the substrate may be within the range of the orthographic projections of the two ends of the first signal connection line 51 on the substrate, and the eleventh via holes K11
  • the third insulating layer and the fourth insulating layer inside are etched away, exposing the surfaces at both ends of the first signal connection line 51, and the eleventh via hole K11 is configured so that the subsequently formed second detection line passes through the via hole and
  • the first signal connection line 51 is connected so that the first signal connection line 51 serves as a bridging line for the subsequently formed second detection line.
  • the orthographic projections of at least two twelfth via holes K12 on the substrate may be within the range of the orthographic projections of the two ends of the second signal connection line 52 on the substrate, and the twelfth via holes K12
  • the third insulating layer and the fourth insulating layer inside are etched away, exposing the surfaces at both ends of the second signal connection line 52, and the twelfth via hole K12 is configured so that the subsequently formed first detection line passes through the via hole and
  • the second signal connection line 52 is connected so that the second signal connection line 52 serves as a bridge line for the subsequently formed first detection line.
  • the orthographic projections of at least two thirteenth vias K13 on the substrate may be within the range of the orthographic projections of the two ends of the third signal connection line 53 on the substrate, and the thirteenth vias K13
  • the third insulating layer and the fourth insulating layer inside are etched away, exposing the surfaces at both ends of the third signal connection line 53, and the thirteenth via hole K13 is configured to allow the subsequently formed third detection line to pass through the via hole and
  • the third signal connection line 53 is connected so that the third signal connection line 53 serves as a bridging line for the subsequently formed third detection line.
  • the orthographic projections of at least two fourteenth via holes K14 on the substrate may be within the range of the orthographic projections of the two ends of the fourth signal connection line 54 on the substrate, and the fourteenth via holes K14
  • the third insulating layer and the fourth insulating layer inside are etched away, exposing the surfaces at both ends of the fourth signal connection line 54, and the fourteenth via hole K14 is configured to allow the subsequently formed third control line to pass through the via hole and
  • the fourth signal connection line 54 is connected so that the fourth signal connection line 54 serves as a bridge line for the subsequently formed third control line.
  • the orthographic projections of at least two fifteenth via holes K15 on the substrate may be within the range of the orthographic projections of the two ends of the third signal connection line 53 on the substrate, and the fifteenth via holes K15
  • the third insulating layer and the fourth insulating layer inside are etched away, exposing the surfaces at both ends of the third signal connection line 53, and the fifteenth via hole K15 is configured to allow the subsequently formed fifth detection line to pass through the via hole and
  • the third signal connection line 53 is connected so that the third signal connection line 53 serves as a bridge line for the fifth detection line formed subsequently.
  • a plurality of the first detection subunits may include the twenty-first via K21, the twenty-second via K22, the twenty-third via K23, the second The fourteenth via K24, the twenty-fifth via K25, the twenty-sixth via K26, the twenty-seventh via K27, the twenty-eighth via K28, the twenty-ninth via K29, the thirtieth via Hole K30, thirty-first via K31, thirty-second via K32, thirty-third via K33, thirty-fourth via K34, thirty-fifth via K35, and thirty-sixth via K36 .
  • the orthographic projection of the twenty-first via hole K21 on the substrate may be within the range of the orthographic projection of the first region of the eleventh active layer 111 on the substrate, and the twenty-first via hole K21
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K21 are etched away, exposing the surface of the first region of the eleventh active layer 111, and the twenty-first via hole K21 is configured to enable subsequent
  • the formed first detection line is connected to the first region of the eleventh active layer 111 through the via hole.
  • the orthographic projection of the twenty-second via hole K22 on the substrate may be within the range of the orthographic projection of the second region of the eleventh active layer 111 on the substrate, and the twenty-second via hole K22
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K22 are etched away, exposing the surface of the second region of the eleventh active layer 111, and the twenty-second via hole K22 is configured to enable subsequent
  • the formed eleventh connection electrode is connected to the second region of the eleventh active layer 111 through the via hole.
  • the orthographic projection of the twenty-third via hole K23 on the substrate may be within the range of the orthographic projection of the first region of the twelfth active layer 112 on the substrate, and the twenty-third via hole K23
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K23 are etched away, exposing the surface of the first region of the twelfth active layer 112, and the twenty-third via hole K23 is configured to enable subsequent
  • the formed third detection line is connected to the first region of the twelfth active layer 112 through the via hole.
  • the orthographic projection of the twenty-fourth via hole K24 on the substrate may be within the range of the orthographic projection of the second region of the twelfth active layer 112 on the substrate, and the twenty-fourth via hole K24
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K24 are etched away, exposing the surface of the second region of the twelfth active layer 112, and the twenty-fourth via hole K24 is configured to enable subsequent
  • the formed twelfth connection electrode is connected to the second region of the twelfth active layer 112 through the via hole.
  • the orthographic projection of the twenty-fifth via hole K25 on the substrate may be within the range of the orthographic projection of the first region of the thirteenth active layer 113 on the substrate, and the twenty-fifth via hole K25
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K25 are etched away, exposing the surface of the first region of the thirteenth active layer 113, and the twenty-fifth via hole K25 is configured to enable subsequent
  • the formed third detection line is connected to the first region of the thirteenth active layer 113 through the via hole.
  • the orthographic projection of the twenty-sixth via hole K26 on the substrate may be within the range of the orthographic projection of the second region of the thirteenth active layer 113 on the substrate, and the twenty-sixth via hole K26
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K26 are etched away, exposing the surface of the second region of the thirteenth active layer 113, and the twenty-sixth via hole K26 is configured to enable subsequent
  • the formed twelfth connection electrode is connected to the second region of the thirteenth active layer 113 through the via hole.
  • the orthographic projection of the twenty-seventh via hole K27 on the substrate may be within the range of the orthographic projection of the first region of the fourteenth active layer 114 on the substrate, and the twenty-seventh via hole K27
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K27 are etched away, exposing the surface of the first region of the fourteenth active layer 114, and the twenty-seventh via hole K27 is configured to enable subsequent
  • the formed fifth detection line is connected to the first region of the fourteenth active layer 114 through the via hole.
  • the orthographic projection of the twenty-eighth via hole K28 on the substrate may be within the range of the orthographic projection of the second region of the fourteenth active layer 114 on the substrate, and the twenty-eighth via hole K28
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K28 are etched away, exposing the surface of the second region of the fourteenth active layer 114, and the twenty-eighth via hole K28 is configured to enable subsequent
  • the formed thirteenth connection electrode is connected to the second region of the fourteenth active layer 114 through the via hole.
  • the orthographic projection of the twenty-ninth via hole K29 on the substrate may be within the range of the orthographic projection of the first region of the fifteenth active layer 115 on the substrate, and the twenty-ninth via hole K29
  • the second insulating layer, the third insulating layer and the fourth insulating layer in K29 are etched away, exposing the surface of the first region of the fifteenth active layer 115, and the twenty-ninth via hole K29 is configured to enable subsequent
  • the formed fifth detection line is connected to the first region of the fifteenth active layer 115 through the via hole.
  • the orthographic projection of the thirtieth via hole K30 on the substrate may be within the range of the orthographic projection of the second region of the fifteenth active layer 115 on the substrate, within the thirtieth via hole K30
  • the second insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the second region of the fifteenth active layer 115, and the thirtieth via hole K30 is configured so that the subsequently formed
  • the thirteenth connection electrode is connected to the second region of the fifteenth active layer 115 through the via hole.
  • the orthographic projection of the thirty-first via hole K31 on the substrate may be within the range of the orthographic projection of the eleventh connection block 91-1 of the first transmission line 91 on the substrate, the thirty-first The third insulating layer and the fourth insulating layer in the via hole K31 are etched away, exposing the surface of the eleventh connection block 91-1, and the thirty-first via hole K31 is configured to make the eleventh connection formed subsequently The electrodes are connected to the eleventh connection block 91-1 through the via hole.
  • the orthographic projection of the thirty-second via hole K32 on the substrate may be within the range of the orthographic projection of the twenty-first connection block 92-1 of the second transmission line 92 on the substrate.
  • the fourth insulating layer in the second via hole K32 is etched away, exposing the surface of the twenty-first connection block 92-1, and the thirty-second via hole K32 is configured to allow the subsequently formed twelfth connection electrode to pass through the second via hole K32.
  • the via holes are connected to the twenty-first connection block 92-1.
  • the orthographic projection of the thirty-third via hole K33 on the substrate may be within the range of the orthographic projection of the twenty-second connection block 92-2 of the second transmission line 92 on the substrate.
  • the fourth insulating layer in the third via hole K33 is etched away, exposing the surface of the twenty-second connection block 92-2, and the thirty-third via hole K33 is configured to allow the subsequently formed thirteenth connection electrode to pass through the third via hole K33.
  • the via holes are connected to the twenty-second connection block 92-2.
  • the orthographic projection of the thirty-fourth via hole K34 on the substrate may be within the range of the orthographic projection of the eleventh gate connection line 61 on the substrate, and the orthographic projection of the thirty-fourth via hole K34
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the eleventh gate connecting line 61, and the thirty-fourth via hole K34 is configured so that the subsequently formed first control line passes through the via hole and The eleventh gate connection line 61 is connected.
  • the orthographic projection of the thirty-fifth via hole K35 on the substrate may be within the range of the orthographic projection of the twelfth gate connection line 62 on the substrate, and the orthographic projection of the thirty-fifth via hole K35
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the twelfth gate connection line 62, and the thirty-fifth via hole K35 in the odd-numbered first detecting subunit is configured to make the subsequently formed
  • the third control line is connected to the twelfth gate connection line 62 through the via hole, and the thirty-fifth via hole K35 in the even-numbered first detection subunit is configured to allow the second control line formed subsequently to pass through the via hole It is connected to the twelfth gate connection line 62 .
  • the orthographic projection of the thirty-sixth via hole K36 on the substrate may be within the range of the orthographic projection of the thirteenth gate connection line 63 on the substrate, and the orthographic projection of the thirty-sixth via hole K36
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the thirteenth gate connection line 63, and the thirty-sixth via hole K36 in the odd-numbered first detection subunit is configured to make the subsequently formed
  • the second control line is connected to the thirteenth gate connection line 63 through the via hole, and the thirty-sixth via hole K36 in the even-numbered first detection subunit is configured to allow the subsequently formed third control line to pass through the via hole It is connected to the thirteenth gate connection line 63 .
  • a plurality of the second detection subunits may include the forty-first via K41, the forty-second via K42, the forty-third via K43, the fourth The fourteenth via K44, the forty-fifth via K45, the forty-sixth via K46, the forty-seventh via K47, the forty-eighth via K48, the forty-ninth via K49, the fiftieth via Hole K50, fifty-first via K51, fifty-second via K52, fifty-third via K53, fifty-fourth via K54, fifty-fifth via K55, fifty-sixth via K56 , the fifty-seventh via hole K57 and the fifty-eighth via hole K58.
  • the orthographic projection of the forty-first via hole K41 on the substrate may be within the range of the orthographic projection of the first region of the twenty-first active layer 121 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K41 are etched away, exposing the surface of the first region of the twenty-first active layer 121, and the forty-first via hole K41 is configured as The subsequently formed second detection line is connected to the first region of the twenty-first active layer 121 through the via hole.
  • the orthographic projection of the forty-second via hole K42 on the substrate may be within the range of the orthographic projection of the second region of the twenty-first active layer 121 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K42 are etched away, exposing the surface of the second region of the twenty-first active layer 121, and the forty-second via hole K42 is configured as The subsequently formed twenty-first connection electrode is connected to the second region of the twenty-first active layer 121 through the via hole.
  • the orthographic projection of the forty-third via hole K43 on the substrate may be within the range of the orthographic projection of the first region of the twenty-second active layer 122 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K43 are etched away, exposing the surface of the first region of the twenty-second active layer 122, and the forty-third via hole K43 is configured as The subsequently formed fourth detection line is connected to the first region of the twenty-second active layer 122 through the via hole.
  • the orthographic projection of the forty-fourth via hole K44 on the substrate may be within the range of the orthographic projection of the second region of the twenty-second active layer 122 on the substrate, and the forty-fourth via hole K44
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K44 are etched away, exposing the surface of the second region of the twenty-second active layer 122, and the forty-fourth via hole K44 is configured as
  • the subsequently formed twenty-second connection electrode is connected to the second region of the twenty-second active layer 122 through the via hole.
  • the orthographic projection of the forty-fifth via hole K45 on the substrate may be within the range of the orthographic projection of the first region of the twenty-third active layer 123 on the substrate, and the forty-fifth via hole K45
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K45 are etched away, exposing the surface of the first region of the twenty-third active layer 123, and the forty-fifth via hole K45 is configured as
  • the subsequently formed fourth detection line is connected to the first region of the twenty-third active layer 123 through the via hole.
  • the orthographic projection of the forty-sixth via hole K46 on the substrate may be within the range of the orthographic projection of the second region of the twenty-third active layer 123 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K46 are etched away, exposing the surface of the second region of the twenty-third active layer 123, and the forty-sixth via hole K46 is configured as The subsequently formed twenty-third connection electrode is connected to the second region of the twenty-third active layer 123 through the via hole.
  • the orthographic projection of the forty-seventh via hole K47 on the substrate may be within the range of the orthographic projection of the first region of the twenty-fourth active layer 124 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K47 are etched away, exposing the surface of the first region of the twenty-fourth active layer 124, and the forty-seventh via hole K47 is configured as The subsequently formed sixth detection line is connected to the first region of the twenty-fourth active layer 124 through the via hole.
  • the orthographic projection of the forty-eighth via hole K48 on the substrate may be within the range of the orthographic projection of the second region of the twenty-fourth active layer 124 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K48 are etched away, exposing the surface of the second region of the twenty-fourth active layer 124, and the forty-eighth via hole K48 is configured as
  • the subsequently formed twenty-fourth connection electrode is connected to the second region of the twenty-fourth active layer 124 through the via hole.
  • the orthographic projection of the forty-ninth via hole K49 on the substrate may be within the range of the orthographic projection of the first region of the twenty-fifth active layer 125 on the substrate.
  • the second insulating layer, the third insulating layer and the fourth insulating layer in the hole K49 are etched away, exposing the surface of the first region of the twenty-fifth active layer 125, and the forty-ninth via hole K49 is configured as The sixth detection line formed later is connected to the first region of the twenty-fifth active layer 125 through the via hole.
  • the orthographic projection of the fiftieth via hole K50 on the substrate may be within the range of the orthographic projection of the second region of the twenty-fifth active layer 125 on the substrate, and the fiftieth via hole K50
  • the inner second insulating layer, the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the second region of the twenty-fifth active layer 125, and the fiftieth via hole K50 is configured so that subsequent formation
  • the twenty-fifth connection electrode is connected to the second region of the twenty-fifth active layer 125 through the via hole.
  • the orthographic projection of the fifty-first via hole K51 on the substrate may be within the range of the orthographic projection of the thirty-first connection block 93-1 of the third transmission line 93 on the substrate, the fiftieth
  • the third insulating layer and the fourth insulating layer in a via hole K51 are etched away, exposing the surface of the thirty-first connection block 93-1, and the fifty-first via hole K51 is configured so that the second via hole K51 formed subsequently
  • the eleventh connection electrode is connected to the thirty-first connection block 93-1 through the via hole.
  • the orthographic projection of the fifty-second via hole K52 on the substrate may be within the range of the orthographic projection of the forty-first connection block 94-1 of the fourth transmission line 94 on the substrate.
  • the fourth insulating layer in the second via hole K52 is etched away, exposing the surface of the forty-first connection block 94-1, and the fifty-second via hole K52 is configured to allow the subsequently formed twenty-second connection electrode to pass through This via hole is connected to the forty-first connection block 94-1.
  • the orthographic projection of the fifty-third via hole K53 on the substrate may be within the range of the orthographic projection of the forty-second connection block 94-2 of the fourth transmission line 94 on the substrate.
  • the fourth insulating layer in the third via hole K53 is etched away, exposing the surface of the forty-second connection block 94-2, and the fifty-third via hole K53 is configured to allow the subsequently formed twenty-third connection electrode to pass through This via is connected to the forty-second connection block 94-2.
  • the orthographic projection of the fifty-fourth via hole K54 on the substrate may be within the range of the orthographic projection of the forty-third connection block 94-3 of the fourth transmission line 94 on the substrate.
  • the fourth insulating layer in the four via holes K54 is etched away, exposing the surface of the forty-third connection block 94-3, and the fifty-fourth via hole K54 is configured to allow the subsequently formed twenty-fourth connection electrode to pass through This via is connected to the forty-third connection block 94-3.
  • the orthographic projection of the fifty-fifth via hole K55 on the substrate may be within the range of the orthographic projection of the forty-fourth connection block 94-4 of the fourth transmission line 94 on the substrate, the fiftieth
  • the fourth insulating layer in the fifth via hole K55 is etched away, exposing the surface of the forty-fourth connection block 94-4, and the fifty-fifth via hole K55 is configured to allow the subsequently formed twenty-fifth connection electrode to pass through This via is connected to the forty-fourth connection block 94-4.
  • the orthographic projection of the fifty-sixth via hole K56 on the substrate may be within the range of the orthographic projection of the thirty-first gate connection line 71 on the substrate, and within the fifty-sixth via hole K56
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the thirty-first gate connection line 71, and the fifty-sixth via hole K56 is configured to allow the first control line formed subsequently to pass through the via The hole is connected to the thirty-first grid connection line 71 .
  • the orthographic projection of the fifty-seventh via hole K57 on the substrate may be within the range of the orthographic projection of the thirty-second gate connection line 72 on the substrate, and within the fifty-seventh via hole K57
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the thirty-second gate connection line 72, and the fifty-seventh via hole K57 in the odd-numbered second detection subunit is configured to enable subsequent
  • the formed second control line is connected to the thirty-second gate connection line 72 through the via hole, and the fifty-seventh via hole K57 in the even-numbered second detection subunit is configured to allow the subsequently formed third control line to pass through
  • the via hole is connected to the thirty-second gate connection line 72 .
  • the orthographic projection of the fifty-eighth via hole K58 on the substrate may be within the range of the orthographic projection of the thirty-third gate connection line 73 on the substrate, and the fifty-eighth via hole K58
  • the third insulating layer and the fourth insulating layer are etched away, exposing the surface of the thirty-third gate connection line 73, and the fifty-eighth via hole K58 in the odd-numbered second detection subunit is configured to enable subsequent
  • the formed third control line is connected to the thirty-third gate connection line 73 through the via hole, and the fifty-eighth via hole K58 in the even-numbered second detection subunit is configured to allow the subsequently formed second control line to pass through
  • the via hole is connected to the thirty-third gate connection line 73 .
  • forming the third conductive layer pattern may include: depositing a third conductive film on the substrate forming the aforementioned pattern, patterning the third conductive film through a patterning process, and forming a third conductive film on the fourth insulating layer.
  • the third conductive layer may be referred to as a first source-drain metal layer ( SD1 ).
  • the third conductive layer pattern may include switching control lines 100, first control lines 110, second control lines 120, third control lines 130, first detection lines 210, second Detection line 220, third detection line 230, fourth detection line 240, fifth detection line 250, sixth detection line 260, first connection electrode 301, second connection electrode 302, third connection electrode 303, eleventh connection The electrode 311, the twelfth connection electrode 312, the thirteenth connection electrode 313, the twenty-first connection electrode 321, the twenty-second connection electrode 322, the twenty-third connection electrode 323, the twenty-fourth connection electrode 324, and the twenty-fourth connection electrode 324. Twenty-five connection electrodes 325 .
  • the first end of the switching control line 100 is connected to the switching control pin in the binding pin area, and the second end extends to the detection circuit area, and is connected to the switching connection line 56 through the tenth via hole K10 . Since the switch connection line 56 is connected to the first gate electrode 201, the second gate electrode 202, and the third gate electrode 203, the switching control signal transmitted by the switch control line 100 can be transmitted to the first gate electrode 201, the second gate electrode 201, and the second gate electrode 203 through the switch connection line 56.
  • the second gate electrode 202 and the third gate electrode 203 control the turn-on and turn-off of the first transistor T1 , the second transistor T2 and the third transistor T3 .
  • the first end of the first control line 110 is connected to the first control pin in the binding pin area, and the second end extends to the detection circuit area.
  • the first control line 110 passes through the thirtieth
  • the four vias K34 are connected to the eleventh gate connection line 61 in each first detection subunit, and on the other hand, are connected to the thirty-first gate connection line in each second detection subunit through the fifty-sixth via K56.
  • Pole connection line 71 is connected.
  • the first control signal transmitted by the first control line 110 can be The eleventh gate electrode 211 and the twenty-first gate electrode 221 are respectively transmitted to the eleventh gate electrode 211 and the twenty-first gate electrode 221 through the eleventh gate connection line 61 and the thirty-first gate connection line 71, to control the eleventh transistor T11 and the twenty-first transistor T21 on and off.
  • the first end of the second control line 120 is connected to the second control pin in the binding pin area, and the second end extends to the detection circuit area.
  • the second control line 120 is connected to the thirteenth gate connection line 63 through the thirty-sixth via hole K36 in the odd-numbered first detection subunit, and on the other hand, through the even-numbered first detection sub-unit.
  • the thirty-fifth via hole K35 in the subunit is connected to the twelfth gate connection line 62 .
  • the second control line 120 is connected to the thirty-second gate connection line 72 through the fifty-seventh via hole K57 in the odd-numbered second detection sub-unit, and on the other hand, through the even-numbered second
  • the fifty-eighth via hole K58 in the detection subunit is connected to the thirty-third gate connection line 73 .
  • the second control signal transmitted by the second control line 120 can control the tenth gate electrode in the even-numbered first detection subunits.
  • the second transistor T12 and the thirteenth transistor T13 are turned on and off.
  • the thirteenth gate connection line 63 is connected to the fourteenth gate electrode 214 and the fifteenth gate electrode 215, the second control signal transmitted by the second control line 120 can control the tenth of the odd-numbered first detection subunits. Turning on and off of the fourth transistor T14 and the fifteenth transistor T15.
  • the thirty-second gate connection line 72 is connected to the twenty-second gate electrode 222 and the twenty-third gate electrode 223, the second control signal transmitted by the second control line 120 can control the odd-numbered second detection subunits.
  • the twenty-second transistor T22 and the twenty-third transistor T23 are turned on and off.
  • the thirty-third gate connection line 73 is connected to the twenty-fourth gate electrode 224 and the twenty-fifth gate electrode 225, the second control signal transmitted by the second control line 120 can control the even-numbered second detection subunits.
  • the twenty-fourth transistor T24 and the twenty-fifth transistor T25 are turned on and off.
  • the third control line 130 may include a third control lead-out line 130-1 and a third control extension line 130-2.
  • the first end of the third control lead-out line 130-1 is connected to the third control pin in the binding pin area, the second end extends to the detection circuit area, and connects to the fourth signal connection line 54 through the fourteenth via hole K14
  • the first end of the third control extension line 130-2 is connected to the second end of the fourth signal connection line 54 through the fourteenth via hole K14, and the second end extends along the second direction Y, so that
  • the third control lead-out line 130 - 1 and the third control extension line 130 - 2 constitute the third control line 130 through the fourth signal connection line 54 .
  • the third control line 130 is connected to the twelfth gate connection line 62 through the thirty-fifth via hole K35 in the odd-numbered first detection subunit, and on the other hand, through the even-numbered first detection sub-unit.
  • the thirty-sixth via hole K36 in the subunit is connected to the thirteenth gate connection line 63 .
  • the third control line 130 is connected to the thirty-third gate connection line 73 through the fifty-eighth via hole K58 in the odd-numbered second detection sub-unit, and on the other hand, through the even-numbered second
  • the fifty-seventh via hole K57 in the detection subunit is connected to the thirty-second gate connection line 72 .
  • the third control signal transmitted by the third control line 130 can control the tenth of the odd-numbered first detection subunits.
  • the second transistor T12 and the thirteenth transistor T13 are turned on and off.
  • the thirteenth gate connection line 63 is connected to the fourteenth gate electrode 214 and the fifteenth gate electrode 215, the third control signal transmitted by the third control line 130 can control the tenth gate electrode in the even-numbered first detection subunits. Turning on and off of the fourth transistor T14 and the fifteenth transistor T15.
  • the third control signal transmitted by the third control line 130 can control The twenty-second transistor T22 and the twenty-third transistor T23 are turned on and off. Since the thirty-third gate connection line 73 is connected to the twenty-fourth gate electrode 224 and the twenty-fifth gate electrode 225, the third control signal transmitted by the third control line 130 can control the odd-numbered second detection subunits. The twenty-fourth transistor T24 and the twenty-fifth transistor T25 are turned on and off.
  • the first detection line 210 may include a first detection lead-out line 210-1 and a first detection extension line 210-2.
  • the first end of the first detection lead-out line 210-1 is connected to the first detection pin in the binding pin area, the second end extends to the detection circuit area, and connects to the second signal connection line 52 through the twelfth via hole K12
  • the first end of the first detection extension line 210-2 is connected to the second end of the second signal connection line 52 through the twelfth via hole K12, and the second end extends along the second direction Y, so that
  • the first detection lead-out line 210 - 1 and the first detection extension line 210 - 2 constitute the first detection line 210 through the second signal connection line 52 .
  • the first detection line 210 is connected to the first region of the first active layer 101 through the first via hole K1 on the one hand, and connected to the first detection subunit through the twenty-first via hole K21 on the other hand.
  • the first region of the eleventh active layer 111 is connected.
  • the second detection line 220 may include a second detection lead-out line 220-1 and a second detection extension line 220-2.
  • the first end of the second detection lead-out line 220-1 is connected to the second detection pin in the binding pin area, the second end extends to the detection circuit area, and connects to the first signal connection line 51 through the eleventh via hole K11
  • the first end of the second detection extension line 220-2 is connected to the second end of the first signal connection line 51 through the eleventh via hole K11, and the second end extends along the second direction Y, so that The second detection lead-out line 220 - 1 and the second detection extension line 220 - 2 constitute the second detection line 220 through the first signal connection line 51 .
  • the second detection line 220 is connected to the second region of the first active layer 101 through the second via hole K2 on the one hand, and connected to the second detection subunit through the forty-first via hole K41 on the other hand.
  • the first region of the twenty-first active layer 121 is connected.
  • the third detection line 230 may include a third detection lead-out line 230-1 and a third detection extension line 230-2.
  • the first end of the third detection lead-out line 230-1 is connected to the third detection pin in the binding pin area, the second end extends to the detection circuit area, and connects to the third signal connection line 53 through the thirteenth via hole K13
  • the first end of the third detection extension line 230-2 is connected to the second end of the third signal connection line 53 through the thirteenth via hole K13, and the second end extends along the second direction Y, so that
  • the third detection lead-out line 230 - 1 and the third detection extension line 230 - 2 constitute the third detection line 230 through the third signal connection line 53 .
  • the third detection line 230 is connected to the first region of the second active layer 102 through the fourth via hole K4, and on the other hand, it is expanded into two third detection lines 230, one third detection line
  • the line 230 is connected to the first region of the twelfth active layer 112 in the first detection subunit through the twenty-third via hole K23, and the other third detection line 230 is connected to the first detection subunit through the twenty-fifth via hole K25.
  • the first regions of the thirteenth active layer 113 in the subunits are connected.
  • the first end of the fourth detection line 240 is connected to the fourth detection pin in the binding pin area, and the second end extends to the detection circuit area, and on the one hand, connects to the fourth through the fifth via hole K5.
  • the second area of the two active layers 102 is connected, and on the other hand, it is expanded into two fourth detection lines 240, and one fourth detection line 240 passes through the forty-third via hole K43 and the first of the twenty-second active layer 122. region, and another fourth detection line 240 is connected to the first region of the twenty-third active layer 123 through the forty-fifth via hole K45.
  • the fifth detection line 250 may include a fifth detection lead-out line 250-1 and a fifth detection extension line 250-2.
  • the first end of the fifth detection lead-out line 250-1 is connected to the fifth detection pin in the binding pin area, the second end extends to the detection circuit area, and connects to the fifth signal connection line 55 through the fifteenth via hole K15
  • the first end of the fifth detection extension line 250-2 is connected to the second end of the fifth signal connection line 55 through the fifteenth via hole K15, and the second end extends along the second direction Y, so that The fifth detection lead-out line 250 - 1 and the fifth detection extension line 250 - 2 constitute the fifth detection line 250 through the fifth signal connection line 55 .
  • the fifth detection line 250 is connected to the first region of the third active layer 103 through the seventh via hole K7;
  • the line 250 is connected to the first region of the fourteenth active layer 114 through the twenty-seventh via hole K27, and the other fifth detection line 250 is connected to the first region of the fifteenth active layer 115 through the twenty-ninth via hole K29. area connection.
  • the first end of the sixth detection line 260 is connected to the sixth detection pin in the binding pin area, and the second end extends to the detection circuit area, and on the one hand, connects to the sixth through hole K8 through the eighth via hole K8.
  • the second area of the three active layers 103 is connected, and on the other hand, it is expanded into two sixth detection lines 260, and one sixth detection line 260 passes through the forty-seventh via hole K47 and the first of the twenty-fourth active layer 124. region, and another sixth detection line 260 is connected to the first region of the twenty-fifth active layer 125 through the forty-ninth via hole K49.
  • the first connection electrode 301 is disposed between the first detection line 210 and the second detection line 220, and is connected to the third region of the first active layer 101 through two third via holes K3, the second A connection electrode 301 can be used as a connection electrode of two first transistors T1, not only as the first pole of one first transistor T1, but also as the second pole of another first transistor T1, realizing the series connection of two first transistors T1 structure.
  • the second connection electrode 302 is disposed between the third detection line 230 and the fourth detection line 240, and is connected to the third region of the second active layer 102 through two sixth via holes K6, the second The two connecting electrodes 302 can be used as connecting electrodes of two second transistors T2, not only as the first pole of one second transistor T2, but also as the second pole of another second transistor T2, realizing the series connection of two second transistors T2 structure.
  • the third connection electrode 303 is disposed between the fifth detection line 250 and the sixth detection line 260, and is connected to the third region of the third active layer 103 through two ninth via holes K9.
  • the three-connection electrode 303 can be used as the connection electrode of two third transistors T3, not only as the first pole of one third transistor T3, but also as the second pole of another third transistor T3, realizing the series connection of two third transistors T3 structure.
  • the eleventh connection electrode 311 may be arranged on the side opposite to the first direction X of the eleventh gate electrode 211 in the first detection subunit, and the eleventh connection electrode 311 passes through the second
  • the twelve vias K22 are connected to the second area of the eleventh active layer 111, and on the other hand, are connected to the eleventh connection block 91-1 of the first transmission line 91 through the thirty-first via K31, realizing the eleventh
  • the transistor T11 controls on and off between the first detection line 210 and the first transmission line 91 .
  • the eleventh transistor T11 When the eleventh transistor T11 is turned on, the first signal transmitted by the first detection line 210 is transmitted to the first transmission line 91, and the first transmission line 91 transmits the first signal to the first data line connected to the G sub-pixel in the display area.
  • the twelfth connection electrode 312 may be disposed between the twelfth gate electrode 212 and the thirteenth gate electrode 213 in the first detection subunit, and the twelfth connection electrode 312 passes through the twentieth gate electrode on the one hand.
  • the four vias K24 are connected to the second area of the twelfth active layer 112, on the other hand are connected to the second area of the thirteenth active layer 113 through the twenty-sixth via K26, and on the other hand are connected through the thirteenth active layer 113
  • the second via hole K32 is connected to the twenty-first connection block 92-1 of the second transmission line 92 to realize the conduction and connection between the third detection line 230 and the second transmission line 92 controlled by the twelfth transistor T12 and the thirteenth transistor T13. disconnect.
  • the third signal transmitted by the third detection line 230 is transmitted to the second transmission line 92, and the second transmission line 92 transmits the third signal to the sub-pixel connected to B in the display area and the first data line of the R sub-pixel.
  • the thirteenth connection electrode 313 may be disposed between the fourteenth gate electrode 214 and the fifteenth gate electrode 215 in the first detection subunit, and the thirteenth connection electrode 313 passes through the twentieth gate electrode on the one hand.
  • the eight vias K28 are connected to the second area of the fourteenth active layer 114, on the other hand are connected to the second area of the fifteenth active layer 115 through the thirtieth via K30, and on the other hand are connected to the second area of the fifteenth active layer 115 through the thirty-third via K30.
  • the via hole K33 is connected to the twenty-second connection block 92-2 of the second transmission line 92, and realizes that the fourteenth transistor T14 and the fifteenth transistor T15 control the conduction and disconnection between the fifth detection line 250 and the second transmission line 92. open.
  • the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, the fifth signal transmitted by the fifth detection line 250 is transmitted to the second transmission line 92, and the second transmission line 92 transmits the fifth signal to the sub-pixel connected to B in the display area and the first data line of the R sub-pixel.
  • the twenty-first connection electrode 321 may be arranged on the opposite side of the first direction X of the twenty-first gate electrode 221 in the second detection subunit, and the twenty-first connection electrode 321 on the one hand Connect to the second region of the twenty-first active layer 121 through the forty-second via hole K42, and connect to the thirty-first connection block 93-1 of the third transmission line 93 through the fifty-first via hole K51 on the other hand , realizing that the twenty-first transistor T21 controls the conduction and disconnection between the second detection line 220 and the third transmission line 93 .
  • the twenty-first transistor T21 When the twenty-first transistor T21 is turned on, the second signal transmitted by the second detection line 220 is transmitted to the third transmission line 93, and the third transmission line 93 transmits the third signal to the second data line connected to the G sub-pixel in the display area .
  • the twenty-second connection electrode 322 may be arranged on one side of the first direction X of the twenty-second gate electrode 222 in the second detection subunit, and the twenty-second connection electrode 322 passes through the fourth Fourteen vias K44 are connected to the second region of the twenty-second active layer 122, and on the other hand, are connected to the forty-first connection block 94-1 of the fourth transmission line 94 through fifty-two vias K52, realizing the second The twelve transistors T22 control on and off between the fourth detection line 240 and the fourth transmission line 94 .
  • the fourth signal transmitted by the fourth detection line 240 is transmitted to the fourth transmission line 94, and the fourth transmission line 94 transmits the fourth signal to the connection between the B sub-pixel and the R sub-pixel in the display area. second data line.
  • the twenty-third connection electrode 323 may be disposed on the opposite side of the first direction X of the twenty-third gate electrode 223 in the second detection subunit.
  • the twenty-third connection electrode 323 Connect to the second region of the twenty-third active layer 123 through the forty-sixth via hole K46, and connect to the forty-second connection block 94-2 of the fourth transmission line 94 through the fifty-third via hole K53 on the other hand , realizing that the twenty-third transistor T23 controls the conduction and disconnection between the fourth detection line 240 and the fourth transmission line 94 .
  • the fourth signal transmitted by the fourth detection line 240 is transmitted to the fourth transmission line 94, and the fourth transmission line 94 transmits the fourth signal to the connection between the B sub-pixel and the R sub-pixel in the display area. second data line.
  • the twenty-fourth connection electrode 324 may be arranged on one side of the first direction X of the twenty-fourth gate electrode 224 in the second detection subunit, and the twenty-fourth connection electrode 324 passes through the fourth
  • the eighteenth via hole K48 is connected to the second region of the twenty-fourth active layer 124, and on the other hand is connected to the forty-third connection block 94-3 of the fourth transmission line 94 through the fifty-fourth via hole K54, realizing the first
  • the twenty-four transistor T24 controls on and off between the sixth detection line 260 and the fourth transmission line 94 .
  • the sixth signal transmitted by the sixth detection line 260 is transmitted to the fourth transmission line 94, and the fourth transmission line 94 transmits the sixth signal to the connection between the B sub-pixel and the R sub-pixel in the display area. second data line.
  • the twenty-fifth connection electrode 325 may be arranged on the side opposite to the first direction X of the twenty-fifth gate electrode 225 in the second detection subunit, and the twenty-fifth connection electrode 325 on the one hand Connect to the second region of the twenty-fifth active layer 125 through the fiftieth via hole K50, and connect to the forty-fourth connection block 94-4 of the fourth transmission line 94 through the fifty-fifth via hole K55 on the other hand,
  • the twenty-fifth transistor T25 is implemented to control the turn-on and turn-off between the sixth detection line 260 and the fourth transmission line 94 .
  • the sixth signal transmitted by the sixth detection line 260 is transmitted to the fourth transmission line 94, and the fourth transmission line 94 transmits the sixth signal to the connection between the B sub-pixel and the R sub-pixel in the display area. second data line.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may use silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Any one or more can be single layer, multilayer or composite layer.
  • the first insulating layer can be called a buffer (Buffer) layer, which is used to improve the water and oxygen resistance of the substrate
  • the second insulating layer and the third insulating layer can be called a gate insulating (GI) layer
  • the fourth insulating layer can be called a It is the interlayer insulation (ILD) layer.
  • the first conductive film, the second conductive film and the third conductive film can be metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Multiple or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), can have a single-layer structure, or a multi-layer composite structure, such as Ti/Al/Ti and the like.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo) or Multiple or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb)
  • AlNd aluminum-neodymium alloy
  • MoNb molybdenum-niobium alloy
  • the active layer film can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si) , hexathiophene or polythiophene materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polycrystalline silicon
  • hexathiophene or polythiophene materials that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.
  • FIG. 17 is a schematic structural diagram of a detection circuit connected to pins according to an exemplary embodiment of the present disclosure.
  • the binding pin area of the binding area can at least include switching control pin PN-A, first control pin PN-B, second control pin PN-C, third control pin PN -D, the first detection pin PN-E, the second detection pin PN-F, the third detection pin PN-G, the fourth detection pin PN-H, the fifth detection pin PN-I and the sixth detection pin Sense pin PN-J.
  • the switching control pin PN-A may be connected to the switching control line 100
  • the first control pin PN-B may be connected to the first control line 110
  • the second control pin PN-C may be connected to the second control line 110.
  • Two control lines 120 are connected
  • the third control pin PN-D can be connected with the third control line 130
  • the first detection pin PN-E can be connected with the first detection line 210
  • the second detection pin PN-F can be connected with the first detection line 210.
  • the second detection line 220 is connected, the third detection pin PN-G can be connected with the third detection line 230, the fourth detection pin PN-H can be connected with the fourth detection line 240, and the fifth detection pin PN-I can be connected Connected to the fifth detection line 250 , the sixth detection pin PN-J may be connected to the sixth detection line 260 .
  • the multiple signal lines of the detection circuit may extend from the binding pin area to the detection circuit area in a zigzag manner, which is not limited in this disclosure.
  • the structure and preparation process of the detection circuit shown in the present disclosure is only an exemplary description. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be added or reduced according to actual needs.
  • the detection circuit can also be provided with other electrodes,
  • the lead wire or the film layer is not limited in the present disclosure.
  • FIG. 18 is a schematic diagram of an equivalent circuit of another detection circuit according to an exemplary embodiment of the present disclosure.
  • the detection circuit may include a plurality of first detection subunits 11, a plurality of second detection subunits 12, at least one control line 20, at least one first signal line 31, at least one second signal line 32, At least one switching control line 41 , at least one switching unit 42 , at least one switching control line 43 and at least one switching unit 44 .
  • the plurality of first detection subunits 11 and the plurality of second detection subunits 12 may each include a control terminal, an input terminal, and an output terminal, and the plurality of first detection subunits 11 and the plurality of second detection subunits
  • the subunits 12 can be arranged in sequence along the second direction Y at set intervals, the positions of the multiple first detection subunits 11 can correspond to the positions of the multiple first data lines D1 in the display area, and the multiple first detection subunits 11 can correspond to the positions of the multiple first data lines D1 in the display area.
  • the positions of the two detection sub-units 12 may be in one-to-one correspondence with the positions of the multiple second data lines D2 in the display area.
  • one end of the control line 20 is correspondingly connected to the control pins in the binding pin area, and the other end of the control line 20 is simultaneously connected to multiple first detection subunits 11 and multiple second detection subunits 12
  • the control line 20 is configured to control the turn-on or turn-off of the plurality of first detection sub-units 11 and the plurality of second detection sub-units 12 .
  • one end of the first signal line 31 is correspondingly connected to the first signal pin in the binding pin area, and the other end of the first signal line 31 is connected to the input ends of the plurality of first detection subunits 11
  • the output terminals of the multiple first detection subunits 11 are correspondingly connected to the multiple first data lines D1 in the display area.
  • one end of the second signal line 32 is connected to the switch second end of the switch unit 44, the other end of the second signal line 32 is connected to the input ends of the plurality of second detection subunits 12, and the plurality of second detection subunits 12 are connected to each other.
  • the output terminals of the two detection sub-units 12 are correspondingly connected to a plurality of second data lines D2 in the display area.
  • one end of the switching control line 41 is correspondingly connected to the switching pins in the binding pin area, and the other end of the switching control line 41 is connected to the switching control end of the switching unit 42, and the switching first of the switching unit 42 terminal is connected to the first signal line 31, the switching second end of the switching unit 42 is connected to the second signal line 32, the switching unit 42 is configured to make the first signal line 31 and the second signal line under the control of the switching control line 41 Line 32 is either isolated or conductive.
  • the first signal line 31 and the second signal line 32 When the first signal line 31 and the second signal line 32 are isolated, the first signal line 31 and the second signal line 32 output different aging voltage signals; when the first signal line 31 and the second signal line 32 are turned on, the second The first signal line 31 and the second signal line 32 output the same lighting voltage signal.
  • one end of the switch control line 43 is correspondingly connected to the switch pins in the binding pin area, and the other end of the switch control line 43 is connected to the switch control terminal of the switch unit 44, and the switch of the switch unit 44 is first end is connected with one end of the signal lead 45, the switch second end of the switch unit 44 is connected with the second signal line 32, the other end of the signal lead 45 is correspondingly connected with the second signal pin of the binding pin area, and the switch unit 44 is connected It is configured to isolate or conduct the signal lead 45 and the second signal line 32 under the control of the switch control line 43 .
  • the signal lead wire 45 When the signal lead wire 45 is isolated from the second signal wire 32 , the first signal wire 31 and the second signal wire 32 are conducted, and the first signal wire 31 and the second signal wire 32 output the same lighting voltage signal.
  • the signal lead wire 45 and the second signal wire 32 are conducted, the first signal wire 31 and the second signal wire 32 are isolated, and the first signal wire 31 and the second signal wire 32 output different aging voltage signals.
  • the switch unit 44 may include a switch transistor, the control pole of the switch transistor is connected to the switch control line 43, the first pole of the switch transistor is connected to the signal lead 45, and the second pole of the switch transistor is connected to the second signal line 32 connections.
  • the working process of the detection circuit in this exemplary embodiment performing the burn-in program is as follows: the external device outputs a control signal through the control pin, outputs a disconnection signal through the switch pin, and outputs a conduction signal through the switch pin, The first aging voltage signal is output through the first signal pin, and the second aging voltage signal is output through the second signal pin.
  • the control signal transmitted by the control line 20 controls the plurality of first detection subunits 11 and the plurality of second detection subunits 12 to be turned on, and the disconnection signal transmitted by the switching control line 41 controls the switching unit 42 to be turned off, so that the first signal line 31 Isolated from the second signal line 32 , the conduction signal transmitted by the switch control line 43 controls the switch unit 44 to conduct, so that the signal lead 45 and the second signal line 32 conduct.
  • the plurality of first detection sub-units 11 that are turned on output the first aging voltage signal transmitted by the first signal line 31 to the plurality of first data lines D1 in the display area respectively, and use the first aging voltage signal to The first sub-pixel is subjected to aging processing.
  • the plurality of second detection subunits 12 that are turned on output the second aging voltage signal transmitted by the second signal line 32 to the plurality of second data lines D2 in the display area respectively, and use the second aging voltage signal to The second sub-pixel is subjected to aging treatment, and the aging voltages of the first display area and the second display area are different.
  • the working process of the detection circuit in this exemplary embodiment for lighting detection is as follows: the external device outputs a control signal through a control pin, outputs a conduction signal through a switching pin, and outputs a disconnection signal through a switch pin, The lighting voltage signal is output through the first signal pin or the lighting voltage signal is output through the second signal pin.
  • the control signal transmitted by the control line 20 controls multiple first detection sub-units 11 and multiple second detection sub-units 12 to be turned on, and the disconnection signal transmitted by the switch control line 43 controls the switch unit 44 to be disconnected, so that the signal leads 45 and the second detection sub-units 12 are turned on.
  • the two signal lines 32 are isolated, and the conduction signal transmitted by the switch control line 41 controls the switch unit 42 to conduct, so that the first signal line 31 and the second signal line 32 are connected, and the first signal line 31 and the second signal line 32 transmit the same Lighting voltage signal.
  • the plurality of first detection subunits 11 and the plurality of second detection subunits 12 that are turned on output the lighting voltage signals to the plurality of first data lines D1 and the plurality of second data lines D2 in the display area respectively, using the same lighting
  • the voltage signal performs lighting detection on the sub-pixels in the first display area and the second display area.
  • the technical scheme of partition aging and overall lighting proposed in this exemplary embodiment not only has different aging voltages between the first display area and the second display area, but also can eliminate the brightness difference between the first display area and the second display area, and the first display area
  • the same lighting voltage as the second display area can ensure the uniformity of the screen, and by using the switching unit, the aging of the partition and the reliability of the overall lighting can be improved.
  • Exemplary embodiments of the present disclosure also provide a display device including the display substrate of the foregoing embodiments.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator.

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Abstract

一种显示基板和显示装置。显示基板包括显示区域(AA)和绑定区域(BD)，显示区域(AA)包括第一显示区(A1)和第二显示区(A2)；第一显示区(A1)包括第一子像素和第一数据线(D1)，第二显示区包括第二子像素和第二数据线(D2)；绑定区域(BD)包括检测电路，检测电路包括控制线(20)、第一信号线(31)、第二信号线(32)、第一检测子单元(11)和第二检测子单元(12)；第一检测子单元(11)被配置为将第一信号线(31)传输的信号输出给第一数据线(D1)，第二检测子单元(12)被配置为将第二信号线(32)传输的信号输出给第二数据线(12)。

Description

显示基板和显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的显示装置已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开示例性实施例提供了一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区，所述第一显示区被配置为进行图像显示，所述第二显示区被配置为进行图像显示和透过光线；所述第一显示区包括多个第一子像素和至少一条与所述第一子像素连接的第一数据线，所述第二显示区包括多个第二子像素和至少一条与所述第二子像素连接的第二数据线；所述绑定区域包括检测电路，所述检测电路包括控制线、第一信号线、第二信号线、至少一个第一检测子单元和至少一个第二检测子单元；所述第一检测子单元的控制端与所述控制线连接，所述第一检测子单元的输入端与所述第一信号线连接，所述第一检测子单元的输出端与所述第一数据线连接，所述第一检测子单元被配置为将所述第一信号线传输的信号输出给所述第一数据线；所述第二检测子单元的控制端与所述控制线连接，所述第二检测子单元的输入端与所述第二信号线连接，所述第二检测子单元 的输出端与所述第二数据线连接，所述第二检测子单元被配置为将所述第二信号线传输的信号输出给所述第二数据线。
在示例性实施方式中，所述控制线包括第一控制线、第二控制线和第三控制线，所述第一信号线包括第一检测线、第三检测线和第五检测线，所述第二信号线包括第二检测线、第四检测线和第六检测线，所述第一检测子单元包括第十一开关单元、第十二开关单元和第十三开关单元，所述第二检测子单元包括第二十一开关单元、第二十二开关单元和第二十三开关单元；所述第十一开关单元被配置为在所述第一控制线的控制下，将所述第一检测线传输的信号发送给所述第一显示区中连接第一颜色子像素的第一数据线；所述第十二开关单元被配置为在所述第二控制线的控制下，将所述第三检测线传输的信号发送给所述第一显示区中连接第二颜色子像素的第一数据线；所述第十三开关单元被配置为在所述第三控制线的控制下，将所述第五检测线传输的信号发送给所述第一显示区中连接第三颜色子像素的第一数据线；所述第二十一开关单元被配置为在所述第一控制线的控制下，将所述第二检测线传输的信号发送给所述第二显示区中连接第一颜色子像素的第二数据线；所述第二十二开关单元被配置为在所述第二控制线的控制下，将所述第四检测线传输的信号发送给所述第二显示区中连接第二颜色子像素的第二数据线；所述第二十三开关单元被配置为在所述第三控制线的控制下，将所述第六检测线传输的信号发送给所述第二显示区中连接第三颜色子像素的第二数据线。
在示例性实施方式中，所述第十一开关单元的控制端与所述第一控制线连接，所述第十一开关单元的输入端与所述第一检测线连接，所述第十一开关单元的输出端与所述第一显示区中连接第一颜色子像素的第一数据线连接；所述第二十一开关单元的控制端与所述第一控制线连接，所述第二十一开关单元的输入端与所述第二检测线连接，所述第二十一开关单元的输出端与所述第二显示区中连接第一颜色子像素的第二数据线连接。
在示例性实施方式中，所述第十一开关单元包括至少一个第十一晶体管，所述第十一晶体管的控制极与所述第一控制线连接，所述第十一晶体管的第一极与所述第一检测线连接，所述第十一晶体管的第二极与所述第一显 示区中连接第一颜色子像素的第一数据线连接；所述第二十一开关单元包括至少一个第二十一晶体管，所述第二十一晶体管的控制极与所述第一控制线连接，所述第二十一晶体管的第一极与所述第二检测线连接，所述第二十一晶体管的第二极与所述第二显示区中连接第一颜色子像素的第二数据线连接。
在示例性实施方式中，所述第十二开关单元的控制端与所述第二控制线连接，所述第十二开关单元的输入端与所述第三检测线连接，所述第十二开关单元的输出端与所述第一显示区中连接第二颜色子像素的第一数据线连接；所述第二十二开关单元的控制端与所述第二控制线连接，所述第二十二开关单元的输入端与所述第四检测线连接，所述第二十二开关单元的输出端与所述第二显示区中连接第二颜色子像素的第二数据线连接。
在示例性实施方式中，所述第十二开关单元包括至少一个第十二晶体管和至少一个第十三晶体管，所述第十二晶体管和第十三晶体管的控制极与所述第二控制线连接，所述第十二晶体管和第十三晶体管的第一极与所述第三检测线连接，所述第十二晶体管和第十三晶体管的第二极与所述第一显示区中连接第二颜色子像素的第一数据线连接；所述第二十二开关单元包括至少一个第二十二晶体管和至少一个第二十三晶体管，所述第二十二晶体管和第二十三晶体管的控制极与所述第二控制线连接，所述第二十二晶体管和第二十三晶体管的第一极与所述第四检测线连接，所述第二十二晶体管和第二十三晶体管的第二极与所述第二显示区中连接第二颜色子像素的第二数据线连接。
在示例性实施方式中，所述第十三开关单元的控制端与所述第三控制线连接，所述第十三开关单元的输入端与所述第五检测线连接，所述第十三开关单元的输出端与所述第一显示区中连接第三颜色子像素的第一数据线连接；所述第二十三开关单元的控制端与所述第三控制线连接，所述第二十三开关单元的输入端与所述第六检测线连接，所述第二十三开关单元的输出端与所述第二显示区中连接第三颜色子像素的第二数据线连接。
在示例性实施方式中，所述第十三开关单元包括至少一个第十四晶体管和至少一个第十五晶体管，所述第十四晶体管和第十五晶体管的控制极与所 述第三控制线连接，所述第十四晶体管和第十五晶体管的第一极与所述第五检测线连接，所述第十四晶体管和第十五晶体管的第二极与所述第一显示区中连接第三颜色子像素的第一数据线连接；所述第二十三开关单元包括至少一个第二十四晶体管和至少一个第二十五晶体管，所述第二十四晶体管和第二十五晶体管的控制极与所述第三控制线连接，所述第二十四晶体管和第二十五晶体管的第一极与所述第六检测线连接，所述第二十四晶体管和第二十五晶体管的第二极与所述第二显示区中连接第三颜色子像素的第二数据线连接。
在示例性实施方式中，所述检测电路还包括切换控制线和切换单元，所述切换单元的控制极与所述切换控制线连接，所述切换单元的第一极与所述第一信号线连接，所述切换单元的第二极与所述第二信号线连接，所述切换单元被配置为在所述切换控制线的控制下，将所述第一信号线和第二信号线隔离或者导通。
在示例性实施方式中，所述切换单元包括第一切换子单元、第二切换子单元和第三切换子单元；所述第一信号线包括第一检测线、第三检测线和第五检测线；所述第二信号线包括第二检测线、第四检测线和第六检测线；所述第一切换子单元的控制极与所述切换控制线连接，所述第一切换子单元的第一极与所述第一检测线连接，所述第一切换子单元的第二极与所述第二检测线连接；所述第二切换子单元的控制极与所述切换控制线连接，所述第二切换子单元的第一极与所述第三检测线连接，所述第二切换子单元的第二极与所述第四检测线连接；所述第三切换子单元的控制极与所述切换控制线连接，所述第三切换子单元的第一极与所述第五检测线连接，所述第三切换子单元的第二极与所述第六检测线连接。
在示例性实施方式中，所述第一切换子单元包括两个串联的第一晶体管，两个第一晶体管的控制极与所述切换控制线连接，一个第一晶体管的第一极与所述第一检测线连接，另一个第一晶体管的第二极与所述第二检测线连接，所述一个第一晶体管的第二极和所述另一个第一晶体管的第一极相互连接。
在示例性实施方式中，所述第二切换子单元包括两个串联的第二晶体 管，两个第二晶体管的控制极与所述切换控制线连接，一个第二晶体管的第一极与所述第三检测线连接，另一个第二晶体管的第二极与所述第四检测线连接，所述一个第二晶体管的第二极和所述另一个第二晶体管的第一极相互连接。
在示例性实施方式中，所述第三切换子单元包括两个串联的第三晶体管，两个第三晶体管的控制极与所述切换控制线连接，一个第三晶体管的第一极与所述第五检测线连接，另一个第三晶体管的第二极与所述第六检测线连接，所述一个第三晶体管的第二极和所述另一个第三晶体管的第一极相互连接。
在示例性实施方式中，所述检测电路还包括开关控制线、开关单元和信号引线，所述开关单元的控制极与所述开关控制线连接，所述开关单元的第一极与所述信号引线连接，所述开关单元的第二极与所述第二信号线连接，所述开关单元被配置为在所述开关控制线的控制下，将所述信号引线和第二信号线隔离或者导通；在所述信号引线和第二信号线导通时，所述第一信号线和第二信号线隔离，所述第一信号线和第二信号线输出不同的老化电压信号；在所述信号引线和第二信号线隔离时，所述第一信号线和第二信号线导通，所述第一信号线和第二信号线输出相同的点灯电压信号。
在示例性实施方式中，在垂直于所述显示基板的平面上，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层，所述半导体层包括切换单元中多个晶体管的有源层、第一检测子单元中多个晶体管的有源层和第二检测子单元中多个晶体管的有源层，所述第一导电层包括切换单元中多个晶体管的栅电极、第一检测子单元中多个晶体管的栅电极和第二检测子单元中多个晶体管的栅电极，所述第三导电层包括所述控制线、第一信号线和第二信号线。
在示例性实施方式中，所述控制线包括第一控制线、第二控制线和第三控制线，所述第一控制线、第二控制线和第三控制线中的至少一条包括控制引出线和控制延伸线，所述控制引出线和控制延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述控制引出线和控制延伸线设置在所述第三导电层中。
在示例性实施方式中，所述第一信号线包括第一检测线、第三检测线和第五检测线，所述第二信号线包括第二检测线、第四检测线和第六检测线，所述第一检测线、第二信号线、第三检测线、第四检测线、第五检测线和第六检测线中的至少一条包括检测引出线和检测延伸线，所述检测引出线和检测延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述检测引出线和检测延伸线设置在所述第三导电层中。
在示例性实施方式中，所述第一导电层还包括切换连接线，所述第三导电层还包括切换控制线，所述切换连接线通过过孔与所述切换控制线连接，所述切换连接线与切换单元中多个晶体管的栅电极为相互连接的一体结构。
在示例性实施方式中，所述第一检测子单元包括第一传输线和第二传输线，所述第一传输线与所述第一显示区中连接第一颜色子像素的第一数据线连接，所述第二传输线与所述第一显示区中连接第二颜色子像素和第三颜色子像素的第一数据线连接；所述第一传输线设置在所述第一导电层中，所述第二传输线设置在所述第二导电层中。
在示例性实施方式中，所述第二传输线上设置有第二十一连接块和第二十二连接块；所述第二十一连接块通过第十二连接电极与所述第一检测子单元中的第十二有源层和第十三有源层连接，所述第二十一连接块设置在所述第十二有源层和第十三有源层之间；所述第二十二连接块通过第十三连接电极与所述第一检测子单元中的第十四有源层和第十五有源层连接，所述第二十二连接块设置在所述第十四有源层和第十五有源层之间。
在示例性实施方式中，所述第十二连接电极和第十三连接电极设置在所述第三导电层中。
在示例性实施方式中，所述第二检测子单元包括第三传输线和第四传输线，所述第三传输线与所述第二显示区中连接第一颜色子像素的第二数据线连接，所述第四传输线与所述第二显示区中连接第二颜色子像素和第三颜色子像素的第二数据线连接；所述第三传输线设置在所述第一导电层中，所述第四传输线设置在所述第二导电层中。
在示例性实施方式中，所述第四传输线上设置有第四十一连接块、第四 十二连接块、第四十三连接块和第四十四连接块；所述第四十一连接块通过第二十二连接电极与所述第二检测子单元中的第二十二有源层连接，所述第四十一连接块设置在所述第二十二有源层第一方向的一侧；所述第四十二连接块通过第二十三连接电极与所述第二检测子单元中的第二十三有源层连接，所述第四十二连接块设置在所述第二十三有源层第一方向的反方向的一侧；所述第四十三连接块通过第二十四连接电极与所述第二检测子单元中的第二十四有源层连接，所述第四十三连接块设置在所述第二十四有源层第一方向的一侧；所述第四十四连接块通过第二十五连接电极与所述第二检测子单元中的第二十五有源层连接，所述第四十四连接块设置在所述第二十五有源层第一方向的反方向的一侧；所述第一方向为所述第四传输线的延伸方向。
在示例性实施方式中，所述第二十二连接电极、第二十三连接电极、第二十四连接电极和第二十五连接电极设置在所述第三导电层中。
另一方面，本公开示例性实施例还提供了一种显示装置，包括前述任一项所述的显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为一种显示装置的结构示意图；
图2为一种显示基板的平面结构示意图；
图3为一种第一显示区的平面结构示意图；
图4为一种第一显示区的剖面结构示意图；
图5为一种像素驱动电路的等效电路图；
图6为一种像素驱动电路的工作时序图；
图7为一种显示基板中绑定区域的平面结构示意图；
图8为一种检测电路的等效电路示意图；
图9a和图9b为本公开示例性实施例一种检测电路的等效电路示意图；
图10为本公开示例性实施例另一种检测电路的等效电路示意图；
图11为本公开示例性实施例又一种检测电路的等效电路示意图；
图12a至图12c为本公开示例性实施例形成半导体层图案后的示意图；
图13a至图13c为本公开示例性实施例形成第一导电层图案后的示意图；
图14a和图14b为本公开示例性实施例形成第二导电层图案后的示意图；
图15a至图15c为本公开示例性实施例形成第四绝缘层图案后的示意图；
图16a至图16c为本公开示例性实施例形成第三导电层图案后的示意图；
图17为本公开示例性实施例一种检测电路与引脚连接的结构示意图；
图18为本公开示例性实施例又一种检测电路的等效电路示意图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的 混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下 的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和与电路单元连接的发光器件，电路单元可以包括至少一个扫描信号线、至少一个数据线、至少一个发光信号线和像素驱动电路。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的 控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。
随着显示技术的发展，全面屏或窄边框等产品以其较大的屏占比和超窄边框，已逐步成为显示产品的发展趋势。对于智能终端等产品，通常需要设置前置摄像头、指纹传感器或光线传感器等硬件，为提高屏占比，全面屏或窄边框产品通常采用屏下指纹或屏下摄像头技术(Full display with camera，简称FDC)，将摄像头等传感器放置于显示基板的屏下摄像区域(Under Display Camera，简称UDC)，屏下摄像区域不仅具有一定的透过率，而且具有显示功能。
图2为一种显示基板的平面结构示意图。如图2所示，在平行于显示基板的平面上，显示基板可以包括显示区域AA、位于显示区域AA一侧的绑定区域BD以及位于显示区域AA其它侧的边框区域BK。显示区域AA可以包括配置为显示动态图片或静止图像的多个子像素，绑定区域BD可以包括将多个数据线连接至集成电路的数据扇出线，边框区域BK可以至少包括传输电压信号的电源线，绑定区域BD和边框区域BK可以包括环形结构的隔离坝，本公开在此不做限定。
在示例性实施方式中，显示区域AA可以包括第一显示区A1和第二显示区A2，第一显示区A1可以至少部分围绕第二显示区A2。在示例性实施方式中，第一显示区A1被配置为进行图像显示，第二显示区A2的位置可以与光学装置的位置相对应，第二显示区A2被配置为进行图像显示和透过光线，透过的光线被光学装置接收。在示例性实施方式中，第一显示区可以称为正常显示区，第二显示区可以称为摄像显示区。
在示例性实施方式中，第二显示区A2在第一显示区A1中的位置不限， 可以位于第一显示区A1上部或下部，或者可以位于第一显示区A1的边缘位置。在平行于显示装置的平面内，第二显示区A2的形状可以是如下任意一种或多种：矩形、多边形、圆形和椭圆形，光学装置可以是指纹识别装置、摄像装置或3D成像等光学传感器。
在示例性实施方式中，第一显示区A1和第二显示区A2的分辨率可以相同，或者第二显示区A2的分辨率可以小于第一显示区A1的分辨率。例如，第二显示区A2的分辨率可以约为第一显示区200的分辨率的50％至70％左右。分辨率(Pixels Per Inch，简称PPI)是指单位面积所拥有像素的数量，可以称为像素密度，PPI数值越高，代表显示基板能够以越高的密度显示画面，画面的细节就越丰富。
图3为一种第一显示区的平面结构示意图。如图3所示，第一显示区可以包括以矩阵方式排布的多个像素单元P，多个像素单元P的至少一个可以包括出射第一颜色光线的第一子像素P1、出射第二颜色光线的第二子像素P2和出射第三颜色光线的第三子像素P3，三个子像素均包括像素驱动电路和发光器件，三个子像素中的像素驱动电路分别与扫描信号线、数据线和发光信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据线传输的数据电压，向所述发光器件输出相应的电流。三个子像素中的发光器件分别与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色(R)光线的红色子像素，第二子像素P2可以是出射蓝色(B)光线的蓝色子像素，第三子像素P3可以是出射绿色(G)光线的绿色子像素，子像素的形状可以是矩形状、菱形、五边形或六边形等，可以采用水平并列、竖直并列或品字等方式排列。
在示例性实施方式中，像素单元可以包括四个子像素，可以采用水平并列、竖直并列、正方形、钻石形等方式排列，本公开在此不做限定。
图4为一种第一显示区的剖面结构示意图，示意了第一显示区三个子像素的结构。如图4所示，在垂直于显示基板的平面上，第一显示区可以包括设置在基底100A上的驱动电路层100B、设置在驱动电路层100B远离基底一侧的发光结构层100C以及设置在发光结构层100C远离基底一侧的封装结 构层100D。在一些可能的实现方式中，显示基板可以包括其它膜层，如隔垫柱等，本公开在此不做限定。
在示例性实施方式中，基底100A可以是柔性基底，或者可以是刚性基底。柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，每个子像素的驱动电路层100B可以包括由多个晶体管和存储电容构成的像素驱动电路，图4中仅以一个像素驱动电路包括一个晶体管和一个存储电容作为示例。在一些可能的实现方式中，每个子像素的驱动电路层100B可以包括：设置在基底上的第一绝缘层；设置在第一绝缘层上的有源层；覆盖有源层的第二绝缘层；设置在第二绝缘层上的栅电极和第一电容电极；覆盖栅电极和第一电容电极的第三绝缘层；设置在第三绝缘层上的第二电容电极；覆盖第二电容电极的第四绝缘层，第二绝缘层、第三绝缘层和第四绝缘层上开设有过孔，过孔暴露出有源层；设置在第四绝缘层上的源电极和漏电极，源电极和漏电极分别通过过孔与有源层连接；覆盖前述结构的平坦层，平坦层上开设有过孔，过孔暴露出漏电极。有源层、栅电极、源电极和漏电极组成驱动晶体管，第一电容电极和第二电容电极组成存储电容。
在示例性实施方式中，每个子像素的发光结构层100C可以包括由多个膜层构成的发光器件，多个膜层可以至少包括阳极、像素定义层、有机发光层和阴极。阳极可以设置在平坦层上，通过平坦层上开设的过孔与驱动晶体管的漏电极连接。像素定义层设置在阳极和平坦层上，像素定义层上设置有像素开口，像素开口暴露出阳极。有机发光层至少部分设置在像素开口内，有机发光层与阳极连接。阴极设置在有机发光层上，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。
在示例性实施方式中，封装结构层100D可以包括叠设的第一封装层、 第二封装层和第三封装层，第一封装层和第三封装层可采用无机材料，第二封装层可采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层100C。
在示例性实施方式中，有机发光层可以包括发光层(EML)以及如下任意一层或多层：空穴注入层(HIL)、空穴传输层(HTL)、电子阻挡层(EBL)、、空穴阻挡层(HBL)、电子传输层(ETL)和电子注入层(EIL)。在示例性实施方式中，所有子像素的空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层和电子注入层可以是连接在一起的共通层，相邻子像素的发光层可以有少量的交叠，或者可以是相互隔离的。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，像素驱动电路分别与7个信号线(数据线D、第一扫描信号线S1、第二扫描信号线S2、发光信号线E、第一电源线VDD、初始信号线INIT和第二电源线VSS)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2和第三节点N3。其中，第一节点N1分别与第三晶体管T3的第一极、第四晶体管T4的第二极和第五晶体管T5的第二极连接，第二节点N2分别与第一晶体管的第二极、第二晶体管T2的第一极、第三晶体管T3的控制极和存储电容C的第二端连接，第三节点N3分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。
在示例性实施方式中，存储电容C的第一端与第一电源线VDD连接，存储电容C的第二端与第二节点N2连接，即存储电容C的第二端与第三晶体管T3的控制极连接。
第一晶体管T1的控制极与第二扫描信号线S2连接，第一晶体管T1的第一极与初始信号线INIT连接，第一晶体管的第二极与第二节点N2连接。当导通电平扫描信号施加到第二扫描信号线S2时，第一晶体管T1将第一初始电压传输到第三晶体管T3的控制极，以使第三晶体管T3的控制极的电荷量初始化。
第二晶体管T2的控制极与第一扫描信号线S1连接，第二晶体管T2的第一极与第二节点N2连接，第二晶体管T2的第二极与第三节点N3连接。当导通电平扫描信号施加到第一扫描信号线S1时，第二晶体管T2使第三晶体管T3的控制极与第二极连接。
第三晶体管T3的控制极与第二节点N2连接，即第三晶体管T3的控制极与存储电容C的第二端连接，第三晶体管T3的第一极与第一节点N1连接，第三晶体管T3的第二极与第三节点N3连接。第三晶体管T3可以称为驱动晶体管，第三晶体管T3根据其控制极与第一极之间的电位差来确定在第一电源线VDD与第二电源线VSS之间流动的驱动电流的量。
第四晶体管T4的控制极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据线D连接，第四晶体管T4的第二极与第一节点N1连接。第四晶体管T4可以称为开关晶体管、扫描晶体管等，当导通电平扫描信号施加到第一扫描信号线S1时，第四晶体管T4使数据线D的数据电压输入到像素驱动电路。
第五晶体管T5的控制极与发光信号线E连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第一节点N1连接。第六晶体管T6的控制极与发光信号线E连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与发光器件的第一极连接。第五晶体管T5和第六晶体管T6可以称为发光晶体管。当导通电平发光信号施加到发光信号线E时，第五晶体管T5和第六晶体管T6通过在第一电源线VDD与第二电源线VSS之间形成驱动电流路径而使发光器件发光。
第七晶体管T7的控制极与第一扫描信号线S1连接，第七晶体管T7的第一极与初始信号线INIT连接，第七晶体管T7的第二极与发光器件的第一极连接。当导通电平扫描信号施加到第一扫描信号线S1时，第七晶体管T7将第二初始电压传输到发光器件的第一极，以使发光器件的第一极中累积的电荷量初始化或释放发光器件的第一极中累积的电荷量。
在示例性实施方式中，发光器件可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，发光器件的第二极与第二电源线VSS连接，第二电源线VSS的信号为低电平信号，第一电源线VDD的信号为持续提供高电平信号。第一扫描信号线S1为本显示行像素驱动电路中的扫描信号线，第二扫描信号线S2为上一显示行像素驱动电路中的扫描信号线，即对于第n显示行，第一扫描信号线S1为S(n)，第二扫描信号线S2为S(n-1)，本显示行的第二扫描信号线S2与上一显示行像素驱动电路中的第一扫描信号线S1为同一信号线，可以减少显示面板的信号线，实现显示面板的窄边框。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第七晶体管T7可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1到第七晶体管T7可以采用低温多晶硅薄膜晶体管，或者可以采用氧化物薄膜晶体管，或者可以采用低温多晶硅薄膜晶体管和氧化物薄膜晶体管。低温多晶硅薄膜晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，氧化物薄膜晶体管的有源层采用氧化物半导体(Oxide)。低温多晶硅薄膜晶体管具有迁移率高、充电快等优点，氧化物薄膜晶体管具有漏电流低等优点，将低温多晶硅薄膜晶体管和氧化物薄膜晶体管集成在一个显示基板上，形成低温多晶氧化物(Low Temperature Polycrystalline Oxide，简称LTPO)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
图6为一种像素驱动电路的工作时序图。下面通过图5示例的像素驱动电路的工作过程说明本公开示例性实施例，图5中的像素驱动电路包括7个晶体管(第一晶体管T1到第七晶体管T7)和1个存储电容C，7个晶体管均为P型晶体管。
在示例性实施方式中，以OLED为例，像素驱动电路的工作过程可以包括：
第一阶段t1，称为复位阶段，第二扫描信号线S2的信号为低电平信号， 第一扫描信号线S1和发光信号线E的信号为高电平信号。第二扫描信号线S2的信号为低电平信号，使第一晶体管T1导通，初始信号线INIT的信号提供至第二节点N2，对存储电容C进行初始化，清除存储电容中原有数据电压。第一扫描信号线S1和发光信号线E的信号为高电平信号，使第二晶体管T2、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7断开，此阶段OLED不发光。
第二阶段t2、称为数据写入阶段或者阈值补偿阶段，第一扫描信号线S1的信号为低电平信号，第二扫描信号线S2和发光信号线E的信号为高电平信号，数据线D输出数据电压。此阶段由于存储电容C的第二端为低电平，因此第三晶体管T3导通。第一扫描信号线S1的信号为低电平信号使第二晶体管T2、第四晶体管T4和第七晶体管T7导通。第二晶体管T2和第四晶体管T4导通使得数据线D输出的数据电压经过第一节点N1、导通的第三晶体管T3、第三节点N3、导通的第二晶体管T2提供至第二节点N2，并将数据线D输出的数据电压与第三晶体管T3的阈值电压之差充入存储电容C，存储电容C的第二端(第二节点N2)的电压为Vd-|Vth|，Vd为数据线D输出的数据电压，Vth为第三晶体管T3的阈值电压。第七晶体管T7导通使得初始信号线INIT的初始电压提供至OLED的第一极，对OLED的第一极进行初始化(复位)，清空其内部的预存电压，完成初始化，确保OLED不发光。第二扫描信号线S2的信号为高电平信号，使第一晶体管T1断开。发光信号线E的信号为高电平信号，使第五晶体管T5和第六晶体管T6断开。
第三阶段t3、称为发光阶段，发光信号线E的信号为低电平信号，第一扫描信号线S1和第二扫描信号线S2的信号为高电平信号。发光信号线E的信号为低电平信号，使第五晶体管T5和第六晶体管T6导通，第一电源线VDD输出的电源电压通过导通的第五晶体管T5、第三晶体管T3和第六晶体管T6向OLED的第一极提供驱动电压，驱动OLED发光。
在像素驱动电路驱动过程中，流过第三晶体管T3(驱动晶体管)的驱动电流由其栅电极和第一极之间的电压差决定。由于第二节点N2的电压为Vdata-|Vth|，因而第三晶体管T3的驱动电流为：
I＝K*(Vgs-Vth) 2＝K*[(Vdd-Vd+|Vth|)-Vth] 2＝K*[(Vdd-Vd] 2
其中，I为流过第三晶体管T3的驱动电流，也就是驱动OLED的驱动电流，K为常数，Vgs为第三晶体管T3的栅电极和第一极之间的电压差，Vth为第三晶体管T3的阈值电压，Vd为数据线D输出的数据电压，Vdd为第一电源线VDD输出的电源电压。
图7为一种显示基板中绑定区域的平面结构示意图。如图7所示，在示例性实施方式中，在平行于显示基板的平面内，绑定区域BD可以位于显示区域AA的一侧，沿着远离显示区域AA的方向，绑定区域BD可以包括依次设置的扇出区B1、弯折区B2、检测电路区B3、驱动芯片区B4和绑定引脚区B5。第一扇出区B1可以至少包括第一电源线VDD、第二电源线VSS和多条数据传输线，多条数据传输线被配置为以扇出(Fanout)走线方式连接显示区域AA的数据线，第一电源线VDD被配置为连接显示区域AA的高电平电源线，第二电源线VSS被配置为连接边缘区域的低电平电源线。弯折区B2可以包括设置有凹槽的复合绝缘层，凹槽被配置为使绑定区域BD弯折到显示区域AA的背面。检测电路区B3可以设置对显示基板进行检测的检测电路CT，这些检测电路CT可以与显示区域的相应信号线连接。驱动芯片区B4可以设置集成电路IC，集成电路IC通过第一扇出区B1中的数据传输线与显示区域的数据信号线连接，集成电路IC被配置为产生用于驱动子像素所需的驱动信号，并且将驱动信号提供给显示区域的数据线。例如，驱动信号可以是驱动子像素发光亮度的数据信号。绑定引脚区B5可以设置多个引脚(PIN)，多个引脚被配置为与外部的柔性电路板(Flexible Printed Circuit，简称FPC)绑定连接。在示例性实施方式中，绑定区域可以包括其它电路和信号线，如防静电电路、多路复用电路(MUX)等，本公开在此不做限定。
在示例性实施方式中，检测电路区B3可以包括检测电路(Cell Test，简称CT)，检测电路可以实现显示基板的老化(Aging)程序和ET点灯检测。显示基板制备过程需要进行多个检测，其中一个重要的检测是单元检测(Cell Test，简称ET)点灯(Light-on)，简称ET点灯。ET点灯检测是显示基板未绑定驱动芯片(IC)和输入显示信号的柔性电路板(FPC)之前，通过对显示基板输入检测信号，使其像素呈现色彩，通过缺陷检测装置检查各个像 素是否良好，以确认显示基板是否存在缺陷。由于制备完成的发光器件存在界面不稳定(interface not stable)等情况，因而老化程序是显示装置出货前的一种必要的工艺，通过以一定大小的电流点亮发光器件一段时间，可以将界面不稳定老化掉，降低发光器件的亮度衰减，增加发光器件的寿命。
图8为一种检测电路的等效电路示意图。如图8所示，检测电路可以至少包括多个检测子单元10、控制线20和信号线30，每个检测子单元10可以包括控制端、输入端和输出端。控制线20的一端与绑定引脚区的引脚对应连接，控制线20的另一端可以与多个检测子单元10的控制端对应连接，信号线30的一端与绑定引脚区的引脚对应连接，信号线30的另一端可以与多个检测子单元10的输入端对应连接，多个检测子单元10的输出端可以与显示区域的多条数据线对应连接，检测子单元10被配置为在控制线20的控制下，将信号线30输出的信号输出给显示区域的数据线，实现显示基板的老化程序和点灯检测。
在示例性实施方式中，检测电路的老化处理过程为：在显示基板绑定驱动芯片(IC)和柔性电路板(FPC)之前，将外部装置连接在绑定区域的引脚上，外部装置通过引脚向信号线输出控制信号和老化电压信号，控制信号控制多个检测子单元导通，多个检测子单元将老化电压信号输出给显示区域的多条数据线，分别对红色子像素、蓝色子像素和绿色子像素进行老化程序。
一种显示基板的点灯检测中，显示基板出现竖线波纹(Mura)缺陷。研究发现，显示基板出现竖线波纹缺陷的主要原因，是现有老化程序中整个显示区域采用相同的老化电压导致的。进一步研究发现，对于采用FDC技术的显示基板，现有设计中通常会缩小第二显示区的阳极面积，以提高第二显示区的透过率，但该设计使得第一显示区中发光器件的寿命特性与第二显示区中发光器件的寿命特性存在差异。由于第一显示区和第二显示区采用相同的老化电压，使得第一显示区中发光器件老化后的亮度特性与第二显示区中发光器件的老化后亮度特性不同，因而在点灯检测时，第一显示区和第二显示区的亮度存在差异，使得第一显示区呈现竖线波纹缺陷。
图9a和图9b为本公开示例性实施例一种检测电路的等效电路示意图，图9a示意的显示基板中，第二显示区A2设置有像素驱动电路和发光器件(像 素驱动电路内置)，图9b示意的显示基板中，第二显示区A2仅设置发光器件(像素驱动电路外置)。在示例性实施方式中，显示基板可以包括显示区域AA和位于显示区域AA一侧的绑定区域BD，显示区域AA可以包括第一显示区A1和第二显示区A2，第一显示区A1可以至少部分围绕第二显示区A2，第一显示区A1被配置为进行图像显示，第二显示区A2被配置为进行图像显示和透过光线。
如图9a所示，在示例性实施方式中，第一显示区A1可以包括多个第一子像素，第一子像素可以包括第一像素驱动电路和第一发光器件，第二显示区A2可以包括多个第二子像素，第二子像素可以包括第二像素驱动电路和第二发光器件，第二像素驱动电路和第二发光器件均设置在第二显示区A2。第一显示区A1中的多个第一子像素规则排布，形成多个第一像素行和多个第一像素列，第二显示区A2中的多个第二子像素可以规则排布，形成多个第二像素行和多个第二像素列。显示区域还包括多条数据线D，多条数据线D可以包括多条第一数据线D1和多条第二数据线D2。多条第一数据线D1和多条第二数据线D2可以沿着第一方向X延伸，并沿着第二方向Y以设定的间隔依次设置，每条第一数据线D1与第一显示区A1中一个像素列的多个第一子像素的第一像素驱动电路电连接，每条第二数据线D2与第二显示区A2中一个像素列的多个第二子像素的第二像素驱动电路电连接，且与部分第一子像素的第一像素驱动电路连接。在示例性实施方式中，第一方向X可以是显示基板的列方向，第二方向Y可以是显示基板的行方向，第一方向X和第二方向Y可以相互垂直。
如图9b所示，在示例性实施方式中，第一显示区A1可以包括多个第一子像素，第一子像素可以包括第一像素驱动电路和第一发光器件，第二显示区A2可以包括多个第二子像素，第二子像素包括第二发光器件和第二像素驱动电路，第二子像素的第二发光器件设置在第二显示区A2，第二子像素的第二像素驱动电路设置在第一显示区A1，第二发光器件通过阳极连接线与第二像素驱动电路连接。显示区域还包括多条数据线D，多条数据线D可以包括多条第一数据线D1和多条第二数据线D2。多条第一数据线D1和多条第二数据线D2可以沿着第一方向X延伸，并沿着第二方向Y以设定的间隔依 次设置。每条第一数据线D1与一个像素列中多个第一子像素的第一像素驱动电路连接，每条第二数据线D2与一个像素列中多个第二子像素的第二像素驱动电路连接，且与部分第一子像素的第一像素驱动电路连接。
在示例性实施方式中，检测电路可以设置在绑定区域BD，检测电路可以至少包括多个第一检测子单元11、多个第二检测子单元12、至少一个控制线20、至少一个第一信号线31和至少一个第二信号线32。
在示例性实施方式中，多个第一检测子单元11和多个第二检测子单元12可以均包括控制端、输入端和输出端，多个第一检测子单元11和多个第二检测子单元12可以沿着第二方向Y以设定的间隔依次设置，多个第一检测子单元11的位置可以与显示区域中的多条第一数据线D1的位置一一对应，多个第二检测子单元12的位置可以与显示区域中的多条第二数据线D2的位置一一对应。
在示例性实施方式中，控制线20的一端与绑定引脚区的控制引脚对应连接，控制线20的另一端同时与多个第一检测子单元11和多个第二检测子单元12的控制端连接，控制线20被配置为控制多个第一检测子单元11和多个第二检测子单元12的导通或者断开。
在示例性实施方式中，第一信号线31的一端与绑定引脚区的第一信号引脚对应连接，第一信号线31的另一端与多个第一检测子单元11的输入端连接，多个第一检测子单元11的输出端与显示区域的多条第一数据线D1对应连接，第一信号线31被配置为通过第一信号引脚接收外部装置的第一信号，第一检测子单元11被配置为将第一信号输出到显示区域的第一数据线D1，对第一显示区中的第一子像素进行老化处理或者点灯检测。
在示例性实施方式中，第二信号线32的一端与绑定引脚区的第二信号引脚对应连接，第二信号线32的另一端与多个第二检测子单元12的输入端连接，多个第二检测子单元12的输出端与显示区域的多条第二数据线D2对应连接，第二信号线32被配置为通过第二信号引脚接收外部装置的第二信号，第二检测子单元12被配置为将第二信号输出到显示区域的第二数据线D2，对第二显示区中的第二子像素进行老化处理或者点灯检测。
在示例性实施方式中，本示例性实施例检测电路进行老化处理的工作过程为：将外部装置连接在绑定区域的控制引脚、第一信号引脚和第二信号引脚上，外部装置通过控制引脚输出控制信号，通过第一信号引脚输出第一老化电压信号，通过第二信号引脚输出第二老化电压信号，第一老化电压和第二老化电压不同。控制线20传输的控制信号控制多个第一检测子单元11和多个第二检测子单元12导通，导通的多个第一检测子单元11将第一信号线31传输的第一老化电压信号分别输出给显示区域的多条第一数据线D1，利用第一老化电压信号对第一显示区中的第一子像素进行老化处理，导通的多个第二检测子单元12将第二信号线32传输的第二老化电压信号分别输出给显示区域的多条第二数据线D2，利用第二老化电压信号对第二显示区中的第二子像素进行老化处理。
本公开示例性实施例提出了一种分区老化的技术方案，对第一显示区的第一子像素采用第一老化电压进行老化处理，对第二显示区的第二子像素采用第二老化电压进行老化处理，第一老化电压和第二老化电压不同。由于第一显示区和第二显示区采用不同的老化电压，因而可以保证第一显示区中老化后发光器件的亮度特性与第二显示区中老化后发光器件的亮度特性基本上相同，可以消除第一显示区和第二显示区的亮度差异，有效避免了显示区域出现竖线波纹缺陷。
图10为本公开示例性实施例另一种检测电路的等效电路示意图。如图10所示，检测电路可以包括多个第一检测子单元11、多个第二检测子单元12、至少一个控制线20、至少一个第一信号线31、至少一个第二信号线32、至少一个切换控制线41和至少一个切换单元42。控制线20、第一信号线31和第二信号线32与多个第一检测子单元11和多个第二检测子单元12的连接结构与图9所示结构基本上相同。
在示例性实施方式中，切换单元42可以包括切换控制端、切换第一端和切换第二端。切换控制线41的一端与绑定引脚区的切换引脚对应连接，切换控制线41的另一端与切换单元42的切换控制端连接，切换单元42的切换第一端与第一信号线31连接，切换单元42的切换第二端与第二信号线32连接，切换控制线41被配置为通过切换引脚接收外部的切换信号，切换单元42被 配置为在切换控制线41的控制下，使第一信号线31和第二信号线32隔离或者导通。在第一信号线31和第二信号线32隔离时，第一信号线31和第二信号线32输出不同的老化电压信号，在第一信号线31和第二信号线32导通时，第一信号线31和第二信号线32输出相同的点灯电压信号。
在示例性实施方式中，切换单元42可以包括切换晶体管，切换晶体管的控制极与切换控制线41连接，切换晶体管的第一极与第一信号线31连接，切换晶体管的第二极与第二信号线32连接。
在示例性实施方式中，本示例性实施例检测电路进行老化程序的工作过程为：外部装置通过控制引脚输出控制信号，通过切换引脚输出断开信号，通过第一信号引脚输出第一老化电压信号，通过第二信号引脚输出第二老化电压信号。控制线20传输的控制信号控制多个第一检测子单元11和多个第二检测子单元12导通，切换控制线41传输的断开信号控制切换单元42断开，使得第一信号线31和第二信号线32隔离。导通的多个第一检测子单元11将第一信号线31传输的第一老化电压信号分别输出给显示区域的多条第一数据线D1，利用第一老化电压信号对第一显示区中的第一子像素进行老化处理。导通的多个第二检测子单元12将第二信号线32传输的第二老化电压信号分别输出给显示区域的多条第二数据线D2，利用第二老化电压信号对第二显示区中第二子像素进行老化处理，第一显示区和第二显示区的老化电压不同。
在示例性实施方式中，本示例性实施例检测电路进行点灯检测的工作过程为：外部装置通过控制引脚输出控制信号，通过切换引脚输出导通信号，通过第一信号引脚输出点灯电压信号或者通过第二信号引脚输出点灯电压信号。控制线20传输的控制信号控制多个第一检测子单元11和多个第二检测子单元12导通，切换控制线41传输的导通信号控制切换单元42导通，使得第一信号线31和第二信号线32连通，第一信号线31和第二信号线32传输相同的点灯电压信号。导通的多个第一检测子单元11和多个第二检测子单元12将点灯电压信号分别输出给显示区域的多条第一数据线D1和多条第二数据线D2，利用相同的点灯电压信号对第一显示区和第二显示区中子像素进行点灯检测。
本公开示例性实施例提出了一种分区老化和整体点灯的技术方案，在进行老化程序时，通过设置的切换单元隔断第一信号线和第二信号线，对第一显示区的第一子像素采用第一老化电压进行老化处理，对第二显示区的第二子像素采用第二老化电压进行老化处理，第一显示区和第二显示区的老化电压不同，在进行点灯检测时，通过设置的切换单元导通第一信号线和第二信号线，对第一显示区的第一子像素和第二显示区的第二子像素采用相同的点灯电压进行点灯检测。由于第一显示区和第二显示区采用不同的老化电压，因而可以保证第一显示区中老化后发光器件的亮度特性与第二显示区中老化后发光器件的亮度特性基本上相同，可以消除第一显示区和第二显示区的亮度差异，有效避免了出现竖线波纹缺陷。由于第一显示区和第二显示区采用相同的点灯电压，因而可以保证画面均一性。
图11为本公开示例性实施例又一种检测电路的等效电路示意图。如图11所示，显示区域AA可以包括多条第一数据线D1和多条第二数据线D2，第一数据线D1与第一显示区中的第一子像素对应连接，第二数据线D2与第二显示区中的第二子像素对应连接，绑定区域BD可以包括检测电路。在示例性实施方式中，检测电路可以包括第一检测单元E1、第二检测单元E2、切换单元F和多条信号线，第一检测单元E1可以位于切换单元F第二方向Y的一侧，第二检测单元E2可以位于第一检测单元E1第二方向Y的一侧，第二检测单元E2第二方向Y的一侧还可以设置第一检测单元E1。
在示例性实施方式中，多条信号线可以至少包括切换控制线100、第一控制线110、第二控制线120、第三控制线130、第一检测线210、第二检测线220、第三检测线230、第四检测线240、第五检测线250、第六检测线260，上述信号线的第一端与绑定引脚区的引脚对应连接，第二端延伸到检测电路所在的检测电路区，与第一检测单元E1、第二检测单元E2和切换单元F相应连接。
在示例性实施方式中，第一检测单元E1可以包括沿着第二方向Y以设定的间隔依次设置的多个第一检测子单元EY1，多个第一检测子单元EY1的位置可以与显示区域中的多条第一数据线D1的位置相对应。每个第一检测子单元EY1可以包括沿着第一方向X以设定的间隔依次设置的第十一开 关单元EK11、第十二开关单元EK12、第十三开关单元EK13，每个开关单元可以均包括控制端、输入端和输出端。
在示例性实施方式中，第十一开关单元EK11的控制端与第一控制线110连接，第十一开关单元EK11的输入端与第一检测线210连接，第十一开关单元EK11的输出端通过第一传输线91与显示区域中连接G子像素的第一数据线D1连接。第十一开关单元EK11被配置为在第一控制线110的控制下，将第一检测线210传输的第一信号发送给连接G子像素的第一数据线D1。
在示例性实施方式中，第十二开关单元EK12的控制端与第二控制线120连接，第十二开关单元EK12的输入端与第三检测线230连接，第十二开关单元EK12的输出端通过第二传输线92与显示区域中连接B子像素的第一数据线D1连接。第十二开关单元EK12被配置为在第二控制线120的控制下，将第三检测线230传输的第三信号发送给连接B子像素的第一数据线D1。
在示例性实施方式中，第十三开关单元EK13的控制端与第三控制线130连接，第十三开关单元EK13的输入端与第五检测线250连接，第十三开关单元EK13的输出端通过第二传输线92与显示区域中连接R子像素的第一数据线D1连接。第十三开关单元EK13被配置为在第三控制线130的控制下，将第五检测线250传输的第五信号发送给连接R子像素的第一数据线D1。
在示例性实施方式中，第二检测单元E2可以包括沿着第二方向Y以设定的间隔依次设置的多个第二检测子单元EY2，多个第二检测子单元EY2的位置可以与显示区域中的多条第二数据线D2的位置相对应。每个第二检测子单元EY2可以包括沿着第一方向X以设定的间隔依次设置的第二十一开关单元EK21、第二十二开关单元EK22、第二十三开关单元EK23，每个开关单元可以均包括控制端、输入端和输出端。
在示例性实施方式中，第二十一开关单元EK21的控制端与第一控制线110连接，第二十一开关单元EK21的输入端与第二检测线220连接，第二十一开关单元EK21的输出端通过第三传输线93与显示区域中连接G子像素的第二数据线D2连接。第二十一开关单元EK21被配置为在第一控制线110的控制下，将第二检测线220传输的第二信号发送给连接G子像素的第 二数据线D2。
在示例性实施方式中，第二十二开关单元EK22的控制端与第二控制线120连接，第二十二开关单元EK22的输入端与第四检测线240连接，第二十二开关单元EK22的输出端通过与第四传输线94与显示区域中连接B子像素的第二数据线D2连接。第二十二开关单元EK22被配置为在第二控制线120的控制下，将第四检测线240传输的第四信号发送给连接B子像素的第二数据线D2。
在示例性实施方式中，第二十三开关单元EK23的控制端与第三控制线130连接，第二十三开关单元EK23的输入端与第六检测线260连接，第二十三开关单元EK23的输出端通过与第四传输线94与显示区域中连接R子像素的第二数据线D2连接。第二十三开关单元EK23被配置为在第三控制线130的控制下，将第六检测线260传输的第六信号发送给连接R子像素的第二数据线D2。
在示例性实施方式中，切换单元F可以包括第一切换子单元FK1、第二切换子单元FK2和第三切换子单元FK3，每个开关单元可以均包括控制极、第一极和第二极。
在示例性实施方式中，第一切换子单元FK1的控制极与切换控制线100连接，第一切换子单元FK1的第一极与第一检测线210连接，第一切换子单元FK1的第二极与第二检测线220连接。第一切换子单元FK1被配置为在切换控制线100的控制下，将第一检测线210和第二检测线220隔离或者导通，在第一检测线210和第二检测线220隔离时，第一检测线210和第二检测线220输出不同的老化电压信号，在第一检测线210和第二检测线220导通时，第一检测线210和第二检测线220输出相同的点灯电压信号。
在示例性实施方式中，第二切换子单元FK2的控制极与切换控制线100连接，第二切换子单元FK2的第一极与第三检测线230连接，第二切换子单元FK2的第二极与第四检测线240连接。第二切换子单元FK2被配置为在切换控制线100的控制下，将第三检测线230和第四检测线240隔离或者导通，在第三检测线230和第四检测线240隔离时，第三检测线230和第四检测线240输出不同的老化电压信号，在第三检测线230和第四检测线240导 通时，第三检测线230和第四检测线240输出相同的点灯电压信号。
在示例性实施方式中，第三切换子单元FK3的控制极与切换控制线100连接，第三切换子单元FK3的第一极与第五检测线250连接，第三切换子单元FK3的第二极与第六检测线260连接。第三切换子单元FK3被配置为在切换控制线100的控制下，将第五检测线250和第六检测线260隔离或者导通，在第五检测线250和第六检测线260隔离时，第五检测线250和第六检测线260输出不同的老化电压信号，在第五检测线250和第六检测线260导通时，第五检测线250和第六检测线260输出相同的点灯电压信号。
在示例性实施方式中，本示例性实施例检测电路进行老化程序的工作过程为：
对显示区域的G子像素进行老化程序时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第一控制线110输出第一控制信号、第一检测线210输出第一老化电压信号、以及第二检测线220输出第二老化电压信号，切换控制信号为断开信号，第一控制信号为导通信号，第一老化电压信号与第二老化电压信号不同。切换控制线100输出的断开信号使第一切换子单元FK1断开，第一检测线210和第二检测线220隔离。第一控制线110输出的导通信号分别使第十一开关单元EK11和第二十一开关单元EK21导通，第一检测线210输出的第一老化电压信号通过导通的第十一开关单元EK11输出给显示区域中连接G子像素的第一数据线D1，对第一显示区中的G子像素进行老化处理，第二检测线220输出的第二老化电压信号通过导通的第二十一开关单元EK21输出给显示区域中连接G子像素的第二数据线D2，对第二显示区中的G子像素进行老化处理，第一显示区和第二显示区的老化电压不同。
对显示区域的B子像素进行老化程序时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第二控制线120输出第二控制信号、第三检测线230输出第三老化电压信号、以及第四检测线240输出第四老化电压信号，切换控制信号为断开信号，第二控制信号为导通信号，第三老化电压信号与第四老化电压信号不同。切换控制线100输出的断开信号使第二切换子单元FK2断开，第三检测线230和第四检测线240隔离。第二控制线120输 出的导通信号分别使第十二开关单元EK12和第二十二开关单元EK22导通，第三检测线230输出的第三老化电压信号通过导通的第十二开关单元EK12输出给显示区域中连接B子像素的第一数据线D1，对第一显示区中的B子像素进行老化处理，第四检测线240输出的第四老化电压信号通过导通的第二十二开关单元EK22输出给显示区域中连接B子像素的第二数据线D2，对第二显示区中的B子像素进行老化处理，第一显示区和第二显示区的老化电压不同。
对显示区域的R子像素进行老化程序时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第三控制线130输出第三控制信号、第五检测线250输出第五老化电压信号、以及第六检测线260输出第六老化电压信号，切换控制信号为断开信号，第三控制信号为导通信号，第五老化电压信号与第六老化电压信号不同。切换控制线100输出的断开信号使第三切换子单元FK3断开，第五检测线250和第六检测线260隔离。第三控制线130输出的导通信号分别使第十三开关单元EK13和第二十三开关单元EK23导通，第五检测线250输出的第五老化电压信号通过导通的第十三开关单元EK13输出给显示区域中连接R子像素的第一数据线D1，对第一显示区中的R子像素进行老化处理，第六检测线260输出的第六老化电压信号通过导通的第二十三开关单元EK23输出给显示区域中连接R子像素的第二数据线D2，对第二显示区中的R子像素进行老化处理，第一显示区和第二显示区的老化电压不同。
在示例性实施方式中，本示例性实施例检测电路进行点灯检测的工作过程为：
对显示区域的G子像素进行点灯检测时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第一控制线110输出第一控制信号、以及第一检测线210或者第二检测线220输出第一点灯电压信号，切换控制信号为导通信号，第一控制信号为导通信号。切换控制线100输出的导通信号使第一切换子单元FK1导通，第一检测线210和第二检测线220相互连接，因而第一检测线210和第二检测线220输出相同的第一点灯电压信号。第一控制线110输出的导通信号分别使第十一开关单元EK11和第二十一开关单元 EK21导通，第一检测线210和第二检测线220输出的第一点灯电压信号通过导通的第十一开关单元EK11和第二十一开关单元EK21分别输出给显示区域中连接G子像素的第一数据线D1和连接G子像素的第二数据线D2，采用相同的点灯电压对第一显示区和第二显示区中的G子像素进行点灯处理。
对显示区域的B子像素进行点灯检测时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第二控制线120输出第二控制信号、以及第三检测线230或者第四检测线240输出第二点灯电压信号，切换控制信号为导通信号，第二控制信号为导通信号。切换控制线100输出的导通信号使第二切换子单元FK2导通，第三检测线230和第四检测线240相互连接，因而第三检测线230和第四检测线240输出相同的第二点灯电压信号。第二控制线120输出的导通信号分别使第十二开关单元EK12和第二十二开关单元EK22导通，第三检测线230和第四检测线240输出的第二点灯电压信号通过导通的第十二开关单元EK12和第二十二开关单元EK22分别输出给显示区域中连接B子像素的第一数据线D1和连接B子像素的第二数据线D2，采用相同的点灯电压对第一显示区和第二显示区中的B子像素进行点灯处理。
对显示区域的R子像素进行点灯检测时，外部装置通过多个引脚使切换控制线100输出切换控制信号、第三控制线130输出第三控制信号、以及第五检测线250或者第六检测线260输出第三点灯电压信号，切换控制信号为导通信号，第三控制信号为导通信号。切换控制线100输出的导通信号使第三切换子单元FK3导通，第五检测线250和第六检测线260相互连接，因而第五检测线250和第六检测线260输出相同的第三点灯电压信号。第三控制线130输出的导通信号分别使第十三开关单元EK13和第二十三开关单元EK23导通，第五检测线250和第六检测线260输出的第三点灯电压信号通过导通的第十三开关单元EK13和第二十三开关单元EK23分别输出给显示区域中连接R子像素的第一数据线D1和连接R子像素的第二数据线D2，采用相同的点灯电压对第一显示区和第二显示区中的R子像素进行点灯处理。
在示例性实施方式中，第一切换子单元FK1可以包括两个串联的第一晶体管，两个第一晶体管的控制极与切换控制线连接，一个第一晶体管的第一极与第一检测线连接，另一个第一晶体管的第二极与第二检测线连接，一个第一晶体管的第二极和另一个第一晶体管的第一极相互连接。
在示例性实施方式中，第二切换子单元FK2可以包括两个串联的第二晶体管，两个第二晶体管的控制极与切换控制线连接，一个第二晶体管的第一极与第三检测线连接，另一个第二晶体管的第二极与第四检测线连接，一个第二晶体管的第二极和另一个第二晶体管的第一极相互连接。
在示例性实施方式中，第三切换子单元FK3可以包括两个串联的第三晶体管，两个第三晶体管的控制极与切换控制线连接，一个第三晶体管的第一极与第五检测线连接，另一个第三晶体管的第二极与第六检测线连接，一个第三晶体管的第二极和另一个第三晶体管的第一极相互连接。
在示例性实施方式中，第十一开关单元EK11可以包括至少一个第十一晶体管，第十一晶体管的控制极与第一控制线连接，第十一晶体管的第一极与第一检测线连接，第十一晶体管的第二极与第一显示区中连接G子像素的第一数据线连接。
在示例性实施方式中，第十二开关单元EK12可以包括至少一个第十二晶体管和至少一个第十三晶体管，第十二晶体管和第十三晶体管的控制极与第二控制线连接，第十二晶体管和第十三晶体管的第一极与第三检测线连接，第十二晶体管和第十三晶体管的第二极与第一显示区中连接B子像素的第一数据线连接。
在示例性实施方式中，第十三开关单元EK13可以包括至少一个第十四晶体管和至少一个第十五晶体管，第十四晶体管和第十五晶体管的控制极与第三控制线连接，第十四晶体管和第十五晶体管的第一极与第五检测线连接，第十四晶体管和第十五晶体管的第二极与第一显示区中连接R子像素的第一数据线连接。
在示例性实施方式中，第二十一开关单元EK21可以包括至少一个第二十一晶体管，第二十一晶体管的控制极与第一控制线连接，第二十一晶体管 的第一极与第二检测线连接，第二十一晶体管的第二极与第二显示区中连接G子像素的第二数据线连接。
在示例性实施方式中，第二十二开关单元EK22可以包括至少一个第二十二晶体管和至少一个第二十三晶体管，第二十二晶体管和第二十三晶体管的控制极与第二控制线连接，第二十二晶体管和第二十三晶体管的第一极与第四检测线连接，第二十二晶体管和第二十三晶体管的第二极与第二显示区中连接B子像素的第二数据线连接。
在示例性实施方式中，第二十三开关单元EK23可以包括至少一个第二十四晶体管和至少一个第二十五晶体管，第二十四晶体管和第二十五晶体管的控制极与第三控制线连接，第二十四晶体管和第二十五晶体管的第一极与第六检测线连接，第二十四晶体管和第二十五晶体管的第二极与第二显示区中连接R子像素的第二数据线连接。
在示例性实施方式中，在垂直于显示基板的平面内，检测电路可以包括：
设置在基底上的第一绝缘层；
设置在第一绝缘层上的半导体层，半导体层可以包括切换单元中多个晶体管的有源层、第一检测子单元中多个晶体管的有源层和第二检测子单元中多个晶体管的有源层；
覆盖半导体层的第二绝缘层，以及设置在第二绝缘层上的第一导电层，第一导电层可以包括切换单元中多个晶体管的栅电极、第一检测子单元中多个晶体管的栅电极和第二检测子单元中多个晶体管的栅电极；
覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层；
覆盖第二导电层的第四绝缘层，第四绝缘层上设置有多个过孔；
设置在第四绝缘层上的第三导电层，第三导电层可以包括所述控制线、第一信号线和第二信号线。
在示例性实施方式中，所述控制线包括第一控制线、第二控制线和第三控制线，所述第一控制线、第二控制线和第三控制线中的至少一条包括控制 引出线和控制延伸线，所述控制引出线和控制延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述控制引出线和控制延伸线设置在所述第三导电层中。
在示例性实施方式中，所述第一信号线包括第一检测线、第三检测线和第五检测线，所述第二信号线包括第二检测线、第四检测线和第六检测线，所述第一检测线、第二信号线、第三检测线、第四检测线、第五检测线和第六检测线中的至少一条包括检测引出线和检测延伸线，所述检测引出线和检测延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述检测引出线和检测延伸线设置在所述第三导电层中。
在示例性实施方式中，所述第一导电层还包括切换连接线，所述第三导电层还包括切换控制线，所述切换连接线通过过孔与所述切换控制线连接，所述切换连接线与切换单元中多个晶体管的栅电极为相互连接的一体结构。
在示例性实施方式中，所述第一检测子单元包括第一传输线和第二传输线，所述第一传输线与所述第一显示区中连接第一颜色子像素的第一数据线连接，所述第二传输线与所述第一显示区中连接第二颜色子像素和第三颜色子像素的第一数据线连接；所述第一传输线设置在所述第一导电层中，所述第二传输线设置在所述第二导电层中。
在示例性实施方式中，所述第二传输线上设置有第二十一连接块和第二十二连接块；所述第二十一连接块通过第十二连接电极与所述第一检测子单元中的第十二有源层和第十三有源层连接，所述第二十一连接块设置在所述第十二有源层和第十三有源层之间；所述第二十二连接块通过第十三连接电极与所述第一检测子单元中的第十四有源层和第十五有源层连接，所述第二十二连接块设置在所述第十四有源层和第十五有源层之间。
在示例性实施方式中，所述第十二连接电极和第十三连接电极设置在所述第三导电层中。
在示例性实施方式中，所述第二检测子单元包括第三传输线和第四传输线，所述第三传输线与所述第二显示区中连接第一颜色子像素的第二数据线连接，所述第四传输线与所述第二显示区中连接第二颜色子像素和第三颜色 子像素的第二数据线连接；所述第三传输线设置在所述第一导电层中，所述第四传输线设置在所述第二导电层中。
在示例性实施方式中，所述第四传输线上设置有第四十一连接块、第四十二连接块、第四十三连接块和第四十四连接块；所述第四十一连接块通过第二十二连接电极与所述第二检测子单元中的第二十二有源层连接，所述第四十一连接块设置在所述第二十二有源层第一方向的一侧；所述第四十二连接块通过第二十三连接电极与所述第二检测子单元中的第二十三有源层连接，所述第四十二连接块设置在所述第二十三有源层第一方向的反方向的一侧；所述第四十三连接块通过第二十四连接电极与所述第二检测子单元中的第二十四有源层连接，所述第四十三连接块设置在所述第二十四有源层第一方向的一侧；所述第四十四连接块通过第二十五连接电极与所述第二检测子单元中的第二十五有源层连接，所述第四十四连接块设置在所述第二十五有源层第一方向的反方向的一侧；所述第一方向为所述第四传输线的延伸方向。
在示例性实施方式中，所述第二十二连接电极、第二十三连接电极、第二十四连接电极和第二十五连接电极设置在所述第三导电层中。
下面通过检测电路的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施例中，“A的正投影包含B的正投影”或“B的正投影位于“A的正投影范围之内”，是指B的正投影的边界落入A的正投影的边界范围 内，或者A的正投影的边界与B的正投影的边界重叠。
在一种示例性实施方式中，检测电路的制备过程可以包括如下操作。
(1)在基底上形成半导体层图案。在示例性实施方式中，在基底上形成半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和半导体薄膜，通过图案化工艺对半导体薄膜进行图案化，形成覆盖整个基底的第一绝缘层，以及设置在第一绝缘层上的半导体层图案，半导体层图案至少包括切换单元的多个有源层、第一检测子单元的多个有源层以及第二检测子单元的多个有源层，如图12a、图12b和图12c所示，图12a为图11中A区域的结构，图12b为图11中B区域的结构，示意了4个第一检测子单元，图12c为图11中C区域的结构，示意了4个第二检测子单元。
如图12a所示，在示例性实施方式中，切换单元的多个有源层可以包括沿着第一方向X依次设置第一有源层101、第二有源层102和第三有源层103，每个有源层可以为沿着第二方向Y延伸的条形状。
在示例性实施方式中，第一有源层101可以作为两个第一晶体管T1的有源层，第二有源层102可以作为两个第二晶体管T2的有源层，第三有源层103可以作为两个第三晶体管T3的有源层。
如图12b所示，在示例性实施方式中，多个第一检测子单元可以沿着第二方向Y依次设置，每个第一检测子单元的多个有源层可以包括沿着第一方向X依次设置第十一有源层111、第十二有源层112、第十三有源层113、第十四有源层114和第十五有源层115，每个有源层可以为沿着第一方向X延伸的条形状。
在示例性实施方式中，第十一有源层111可以作为第十一晶体管T11的有源层，第十二有源层112可以作为第十二晶体管T12的有源层，第十三有源层113可以作为第十三晶体管T13的有源层，第十四有源层114可以作为第十四晶体管T14的有源层，第十五有源层115可以作为第十五晶体管T15的有源层。
如图12c所示，在示例性实施方式中，多个第二检测子单元可以沿着第二方向Y依次设置，每个第二检测子单元的多个有源层可以包括沿着第一方 向X依次设置第二十一有源层121、第二十二有源层122、第二十三有源层123、第二十四有源层124和第二十五有源层125，每个有源层可以为沿着第一方向X延伸的条形状。
在示例性实施方式中，第二十一有源层121可以作为第二十一晶体管T21的有源层，第二十二有源层122可以作为第二十二晶体管T22的有源层，第二十三有源层123可以作为第二十三晶体管T23的有源层，第二十四有源层124可以作为第二十四晶体管T24的有源层，第二十五有源层125可以作为第二十五晶体管T25的有源层。
在示例性实施方式中，切换单元中多个有源层的形状可以基本上相同，多个第一检测子单元的半导体图案可以基本上相同，多个第二检测子单元的半导体图案可以基本上相同。
在示例性实施方式中，基底可以是柔性基底，或者是刚性基底，本公开在此不做限定。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，第一导电层图案至少包括：切换单元的切换连接线、多条信号连接线和多个栅电极，第一检测子单元的多条栅极连接线、多个栅电极和第一传输线，以及第二检测子单元的多条栅极连接线、多个栅电极和第三传输线，如图13a、图13b和图13c所示，图13a为图11中A区域的结构，图13b为图11中B区域的结构，图13c为图11中C区域的结构。在示例性实施方式中，第一导电层可以称为第一栅金属层(GATE1)。
如图13a所示，在示例性实施方式中，切换单元的多个栅电极可以包括沿着第一方向X依次设置第一栅电极201、第二栅电极202和第三栅电极203，每个栅电极可以为矩形环状，矩形环状中沿着第一方向X延伸的两个边在基底上的正投影与对应的有源层在基底上的正投影至少部分交叠，形成两个晶体管的栅电极。第一栅电极201中沿着第一方向X延伸的两个边在基底上的正投影与第一有源层101在基底上的正投影至少部分交叠，作为两个 第一晶体管T1的栅电极。第二栅电极202中沿着第一方向X延伸的两个边在基底上的正投影与第二有源层102在基底上的正投影至少部分交叠，作为两个第二晶体管T2的栅电极。第三栅电极203中沿着第一方向X延伸的两个边在基底上的正投影与第三有源层103在基底上的正投影至少部分交叠，作为两个第三晶体管T3的栅电极。
在示例性实施方式中，切换单元的切换连接线56可以为沿着第一方向X延伸的线形状，且分别与第一栅电极201、第二栅电极202和第三栅电极203连接，切换连接线56被配置为与后续形成的切换控制线连接。
在示例性实施方式中，第一栅电极201、第二栅电极202、第三栅电极203和切换连接线56可以为相互连接的一体结构。
在示例性实施方式中，切换单元的多条信号连接线可以包括沿着第一方向X依次设置的第一信号连接线51、第二信号连接线52、第三信号连接线53、第四信号连接线54和第五信号连接线55，5条信号连接线均位于切换连接线56第二方向Y的一侧。
在示例性实施方式中，第一信号连接线51被配置为作为后续形成的第二检测线的连接线，第二信号连接线52被配置为作为后续形成的第一检测线的连接线，第三信号连接线53被配置为作为后续形成的第三检测线的连接线，第四信号连接线54被配置为作为后续形成的第三控制线的连接线，第五信号连接线55被配置为作为后续形成的第五检测线的连接线。第一信号连接线51至第五信号连接线55作为后续形成的信号线的连接线，可以避免信号线的交叉，有利于后续形成的信号线的排布布局。
如图13b所示，在示例性实施方式中，第一检测子单元的多个栅电极可以包括沿着第一方向X依次设置第十一栅电极211、第十二栅电极212、第十三栅电极213、第十四栅电极214和第十五栅电极215，每个栅电极可以为沿着第二方向Y延伸的条形状，可以位于对应的有源层第一方向X的中部区域，条形状在基底上的正投影与对应的有源层在基底上的正投影至少部分交叠。第十一栅电极211可以作为第十一晶体管T11的栅电极，第十二栅电极212可以作为第十二晶体管T12的栅电极，第十三栅电极213可以作为第十三晶体管T13的栅电极，第十四栅电极214可以作为第十四晶体管T14的栅 电极，第十五栅电极215可以作为第十五晶体管T15的栅电极。
在示例性实施方式中，第一检测子单元的栅极连接线可以包括第十一栅极连接线61、第十二栅极连接线62和第十三栅极连接线63。
在示例性实施方式中，第十一栅极连接线61可以为主体部分沿着第一方向X延伸的线形状，第十一栅极连接线61中第一方向X的反方向的端部与第十一栅电极211连接，第十一栅极连接线61被配置为与后续形成的第一控制线连接。
在示例性实施方式中，第十二栅极连接线62可以为主体部分沿着第一方向X延伸的线形状，第十二栅极连接线62中第一方向X的反方向的端部同时与第十二栅电极212和第十三栅电极213连接，第十二栅极连接线62被配置为与后续形成的第二控制线连接。
在示例性实施方式中，第十三栅极连接线63可以为主体部分沿着第一方向X延伸的线形状，第十三栅极连接线63中第一方向X的端部同时与第十四栅电极214和第十五栅电极215连接，第十三栅极连接线63被配置为与后续形成的第三控制线连接。
在示例性实施方式中，第一检测子单元的第一传输线91可以为主体部分沿着第一方向X延伸的线形状，可以位于多个有源层第二方向Y的一侧，第一传输线91被配置为与显示区域中连接G子像素的第一数据线连接。
在示例性实施方式中，第一传输线91上设置有第十一连接块91-1，第十一连接块91-1位于第十一有源层111第一方向X的反方向的一侧，第十一连接块91-1被配置为通过后续形成的第十一连接电极与第十一有源层111连接。
在示例性实施方式中，沿着第一方向X方向，奇数的第一检测子单元的第一导电层图案可以基本上相同，偶数的第一检测子单元的第一导电层图案可以基本上相同，但奇数的第一检测子单元和偶数的第一检测子单元的第一导电层图案可以不同。
在示例性实施方式中，多个第一检测子单元中，第十一栅电极211至第十五栅电极215、第十一栅极连接线61和第一传输线91的形状和位置基本 上相同，奇数的第一检测子单元和偶数的第一检测子单元中第十二栅极连接线62和第十三栅极连接线63的形状不同。
如图13c所示，在示例性实施方式中，第二检测子单元的多个栅电极可以包括沿着第一方向X依次设置第二十一栅电极221、第二十二栅电极222、第二十三栅电极223、第二十四栅电极224和第二十五栅电极225，每个栅电极可以为沿着第二方向Y延伸的条形状，可以位于对应的有源层第一方向X的中部区域，条形状在基底上的正投影与对应的有源层在基底上的正投影至少部分交叠。第二十一栅电极221可以作为第二十一晶体管T21的栅电极，第二十二栅电极222可以作为第二十二晶体管T22的栅电极，第二十三栅电极223可以作为第二十三晶体管T23的栅电极，第二十四栅电极224可以作为第二十四晶体管T24的栅电极，第二十五栅电极225可以作为第二十五晶体管T25的栅电极。
在示例性实施方式中，第二检测子单元的栅极连接线可以包括第二十一栅极连接线71、第二十二栅极连接线72和第二十三栅极连接线73。
在示例性实施方式中，第二十一栅极连接线71可以为主体部分沿着第一方向X延伸的线形状，第二十一栅极连接线71中第一方向X的反方向的端部与第二十一栅电极221连接，第二十一栅极连接线71被配置为与后续形成的第一控制线连接。
在示例性实施方式中，第二十二栅极连接线72可以为主体部分沿着第一方向X延伸的线形状，第二十二栅极连接线72中第一方向X的反方向的端部同时与第二十二栅电极222和第二十三栅电极223连接，第二十二栅极连接线72被配置为与后续形成的第二控制线连接。
在示例性实施方式中，第二十三栅极连接线73可以为主体部分沿着第一方向X延伸的线形状，第二十三栅极连接线73中第一方向X的端部同时与第二十四栅电极224和第二十五栅电极225连接，第二十三栅极连接线73被配置为与后续形成的第三控制线连接。
在示例性实施方式中，第二检测子单元的第三传输线93可以为主体部分沿着第一方向X延伸的线形状，可以位于多个有源层第二方向Y的一侧，第三传输线93被配置为与显示区域中连接G子像素的第二数据线连接。
在示例性实施方式中，第三传输线93上设置有第三十一连接块93-1，第三十一连接块93-1位于第二十一有源层121第一方向X的反方向的一侧，第三十一连接块93-1被配置为通过后续形成的第二十一连接电极与第二十一有源层121连接。
在示例性实施方式中，沿着第一方向X方向，奇数的第二检测子单元的第一导电层图案可以基本上相同，偶数的第二检测子单元的第一导电层图案可以基本上相同，但奇数的第二检测子单元和偶数的第二检测子单元的第一导电层图案可以不同。
在示例性实施方式中，多个第二检测子单元中，第二十一栅电极221至第二十五栅电极225、第二十一栅极连接线71和第三传输线93的形状和位置基本上相同，奇数的第二检测子单元和偶数的第二检测子单元中第二十二栅极连接线72和第二十三栅极连接线73的形状不同。
(2)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上依次沉积第三绝缘薄膜和第二导电薄膜，通过图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层图案的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，第二导电层图案至少包括：第一检测子单元的第二传输线和第二检测子单元的第四传输线，如图14a和图14b所示，图14a为图11中B区域的结构，图14b为图11中C区域的结构。在示例性实施方式中，第二导电层可以称为第二栅金属层(GATE2)。
如图14a所示，在示例性实施方式中，第一检测子单元的第二传输线92可以为主体部分沿着第一方向X延伸的线形状，可以位于多个有源层第二方向Y的反方向的一侧，第二传输线92被配置为与显示区域中连接B子像素和R子像素的第一数据线连接。
在示例性实施方式中，第二传输线92上可以设置有第二十一连接块92-1和第二十二连接块92-2。第二十一连接块92-1可以位于第十二有源层112和第十三有源层113之间，第二十一连接块92-1被配置为通过后续形成的第十二连接电极同时与第十二有源层112和第十三有源层113连接。第二十二连接块92-2可以位于第十四有源层114和第十五有源层115之间，第二十二 连接块92-2被配置为通过后续形成的第十三连接电极同时与第十四有源层114和第十五有源层115连接。
在示例性实施方式中，多个第一检测子单元的第二导电层图案可以基本上相同。
如图14b所示，在示例性实施方式中，第二检测子单元的第四传输线94可以为主体部分沿着第一方向X延伸的线形状，可以位于多个有源层第二方向Y的反方向的一侧，第四传输线94被配置为与显示区域中连接B子像素和R子像素的第二数据线连接。
在示例性实施方式中，第四传输线94上可以设置有第四十一连接块94-1、第四十二连接块94-2、第四十三连接块94-3和第四十四连接块94-4。第四十一连接块94-1可以位于第二十二有源层122第一方向X的一侧，第四十一连接块94-1被配置为通过后续形成的第二十二连接电极与第二十二有源层122连接。第四十二连接块94-2可以位于第二十三有源层123第一方向X的反方向的一侧，第四十二连接块94-2被配置为通过后续形成的第二十三连接电极与第二十三有源层123连接。第四十三连接块94-3可以位于第二十四有源层124第一方向X的一侧，第四十三连接块94-3被配置为通过后续形成的第二十四连接电极与第二十四有源层124连接。第四十四连接块94-4可以位于第二十五有源层125第一方向X的反方向的一侧，第四十四连接块94-4被配置为通过后续形成的第二十五连接电极与第二十五有源层125连接。
在示例性实施方式中，多个第二检测子单元的第二导电层图案可以基本上相同。
(4)形成第四绝缘层图案。在示例性实施方式中，形成第四绝缘层图案可以包括：在形成前述图案的基底上沉积第四绝缘薄膜，通过图案化工艺对第四绝缘薄膜进行图案化，形成覆盖第二导电层的第四绝缘层图案，第四绝缘层上形成有多个过孔，如图15a、图15b和图15c所示，图15a为图11中A区域的结构，图15b为图11中B区域的结构，图15c为图11中C区域的结构。
如图15a所示，在示例性实施方式中，切换单元中的多个可以包括第一 过孔K1、第二过孔K2、第三过孔K3、第四过孔K4、第五过孔K5、第六过孔K6、第七过孔K7、第八过孔K8、第九过孔K9、第十过孔K10、第十一过孔K11、第十二过孔K12、第十三过孔K13、第十四过孔K14和第十五过孔K15。
在示例性实施方式中，第一过孔K1在基底上的正投影可以位于第一有源层101的第一区在基底上的正投影的范围之内，第一过孔K1内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一有源层101的第一区的表面，第一过孔K1被配置为使后续形成的第一检测线通过该过孔与第一有源层101的第一区连接。
在示例性实施方式中，第二过孔K2在基底上的正投影可以位于第一有源层101的第二区在基底上的正投影的范围之内，第二过孔K2内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一有源层101的第二区的表面，第二过孔K2被配置为使后续形成的第二检测线通过该过孔与第一有源层101的第二区连接。
在示例性实施方式中，至少两个第三过孔K3在基底上的正投影可以位于第一有源层101的第三区在基底上的正投影的范围之内，两个第三过孔K3位于第一过孔K1和第二过孔K2之间，第三过孔K3内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一有源层101的第三区的表面，两个第三过孔K3被配置为使后续形成的第一连接电极通过该过孔与第一有源层101的第三区连接。
在示例性实施方式中，第四过孔K4在基底上的正投影可以位于第二有源层102的第一区在基底上的正投影的范围之内，第四过孔K4内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二有源层102的第一区的表面，第四过孔K4被配置为使后续形成的第三检测线通过该过孔与第二有源层102的第一区连接。
在示例性实施方式中，第五过孔K5在基底上的正投影可以位于第二有源层102的第二区在基底上的正投影的范围之内，第五过孔K5内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二有源层102的第二区的表面，第五过孔K5被配置为使后续形成的第四检测线通过该过孔与第二 有源层102的第二区连接。
在示例性实施方式中，至少两个第六过孔K6在基底上的正投影可以位于第二有源层102的第三区在基底上的正投影的范围之内，两个第六过孔K6位于第四过孔K4和第五过孔K5之间，第六过孔K6内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二有源层102的第三区的表面，两个第六过孔K6被配置为使后续形成的第二连接电极通过该过孔与第二有源层102的第三区连接。
在示例性实施方式中，第七过孔K7在基底上的正投影可以位于第三有源层103的第一区在基底上的正投影的范围之内，第七过孔K7内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三有源层103的第一区的表面，第七过孔K7被配置为使后续形成的第五检测线通过该过孔与第三有源层103的第一区连接。
在示例性实施方式中，第八过孔K8在基底上的正投影可以位于第三有源层103的第二区在基底上的正投影的范围之内，第八过孔K8内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三有源层103的第二区的表面，第八过孔K8被配置为使后续形成的第六检测线通过该过孔与第三有源层103的第二区连接。
在示例性实施方式中，至少两个第九过孔K9在基底上的正投影可以位于第三有源层103的第三区在基底上的正投影的范围之内，两个第九过孔K9位于第七过孔K7和第八过孔K8之间，第九过孔K9内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三有源层103的第三区的表面，两个第九过孔K9被配置为使后续形成的第三连接电极通过该过孔与第三有源层103的第三区连接。
在示例性实施方式中，第十过孔K10在基底上的正投影可以位于切换连接线56在基底上的正投影的范围之内，第十过孔K10内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出切换连接线56的表面，第十过孔K10被配置为使后续形成的切换控制线通过该过孔与切换连接线56连接。
在示例性实施方式中，至少两个第十一过孔K11在基底上的正投影可以位于第一信号连接线51的两端在基底上的正投影的范围之内，第十一过孔 K11内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第一信号连接线51两端的表面，第十一过孔K11被配置为使后续形成的第二检测线通过该过孔与第一信号连接线51连接，使第一信号连接线51作为后续形成的第二检测线的桥接线。
在示例性实施方式中，至少两个第十二过孔K12在基底上的正投影可以位于第二信号连接线52的两端在基底上的正投影的范围之内，第十二过孔K12内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二信号连接线52两端的表面，第十二过孔K12被配置为使后续形成的第一检测线通过该过孔与第二信号连接线52连接，使第二信号连接线52作为后续形成的第一检测线的桥接线。
在示例性实施方式中，至少两个第十三过孔K13在基底上的正投影可以位于第三信号连接线53的两端在基底上的正投影的范围之内，第十三过孔K13内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三信号连接线53两端的表面，第十三过孔K13被配置为使后续形成的第三检测线通过该过孔与第三信号连接线53连接，使第三信号连接线53作为后续形成的第三检测线的桥接线。
在示例性实施方式中，至少两个第十四过孔K14在基底上的正投影可以位于第四信号连接线54的两端在基底上的正投影的范围之内，第十四过孔K14内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第四信号连接线54两端的表面，第十四过孔K14被配置为使后续形成的第三控制线通过该过孔与第四信号连接线54连接，使第四信号连接线54作为后续形成的第三控制线的桥接线。
在示例性实施方式中，至少两个第十五过孔K15在基底上的正投影可以位于第三信号连接线53的两端在基底上的正投影的范围之内，第十五过孔K15内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三信号连接线53两端的表面，第十五过孔K15被配置为使后续形成的第五检测线通过该过孔与第三信号连接线53连接，使第三信号连接线53作为后续形成的第五检测线的桥接线。
在示例性实施方式中，第十过孔K10至第十五过孔K15可以为多个，以 提高连接可靠性。
如图15b所示，在示例性实施方式中，第一检测子单元中的多个可以包括第二十一过孔K21、第二十二过孔K22、第二十三过孔K23、第二十四过孔K24、第二十五过孔K25、第二十六过孔K26、第二十七过孔K27、第二十八过孔K28、第二十九过孔K29、第三十过孔K30、第三十一过孔K31、第三十二过孔K32、第三十三过孔K33、第三十四过孔K34、第三十五过孔K35和第三十六过孔K36。
在示例性实施方式中，第二十一过孔K21在基底上的正投影可以位于第十一有源层111的第一区在基底上的正投影的范围之内，第二十一过孔K21内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十一有源层111的第一区的表面，第二十一过孔K21被配置为使后续形成的第一检测线通过该过孔与第十一有源层111的第一区连接。
在示例性实施方式中，第二十二过孔K22在基底上的正投影可以位于第十一有源层111的第二区在基底上的正投影的范围之内，第二十二过孔K22内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十一有源层111的第二区的表面，第二十二过孔K22被配置为使后续形成的第十一连接电极通过该过孔与第十一有源层111的第二区连接。
在示例性实施方式中，第二十三过孔K23在基底上的正投影可以位于第十二有源层112的第一区在基底上的正投影的范围之内，第二十三过孔K23内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十二有源层112的第一区的表面，第二十三过孔K23被配置为使后续形成的第三检测线通过该过孔与第十二有源层112的第一区连接。
在示例性实施方式中，第二十四过孔K24在基底上的正投影可以位于第十二有源层112的第二区在基底上的正投影的范围之内，第二十四过孔K24内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十二有源层112的第二区的表面，第二十四过孔K24被配置为使后续形成的第十二连接电极通过该过孔与第十二有源层112的第二区连接。
在示例性实施方式中，第二十五过孔K25在基底上的正投影可以位于第十三有源层113的第一区在基底上的正投影的范围之内，第二十五过孔K25 内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十三有源层113的第一区的表面，第二十五过孔K25被配置为使后续形成的第三检测线通过该过孔与第十三有源层113的第一区连接。
在示例性实施方式中，第二十六过孔K26在基底上的正投影可以位于第十三有源层113的第二区在基底上的正投影的范围之内，第二十六过孔K26内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十三有源层113的第二区的表面，第二十六过孔K26被配置为使后续形成的第十二连接电极通过该过孔与第十三有源层113的第二区连接。
在示例性实施方式中，第二十七过孔K27在基底上的正投影可以位于第十四有源层114的第一区在基底上的正投影的范围之内，第二十七过孔K27内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十四有源层114的第一区的表面，第二十七过孔K27被配置为使后续形成的第五检测线通过该过孔与第十四有源层114的第一区连接。
在示例性实施方式中，第二十八过孔K28在基底上的正投影可以位于第十四有源层114的第二区在基底上的正投影的范围之内，第二十八过孔K28内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十四有源层114的第二区的表面，第二十八过孔K28被配置为使后续形成的第十三连接电极通过该过孔与第十四有源层114的第二区连接。
在示例性实施方式中，第二十九过孔K29在基底上的正投影可以位于第十五有源层115的第一区在基底上的正投影的范围之内，第二十九过孔K29内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十五有源层115的第一区的表面，第二十九过孔K29被配置为使后续形成的第五检测线通过该过孔与第十五有源层115的第一区连接。
在示例性实施方式中，第三十过孔K30在基底上的正投影可以位于第十五有源层115的第二区在基底上的正投影的范围之内，第三十过孔K30内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十五有源层115的第二区的表面，第三十过孔K30被配置为使后续形成的第十三连接电极通过该过孔与第十五有源层115的第二区连接。
在示例性实施方式中，第三十一过孔K31在基底上的正投影可以位于第 一传输线91的第十一连接块91-1在基底上的正投影的范围之内，第三十一过孔K31内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十一连接块91-1的表面，第三十一过孔K31被配置为使后续形成的第十一连接电极通过该过孔与第十一连接块91-1连接。
在示例性实施方式中，第三十二过孔K32在基底上的正投影可以位于第二传输线92的第二十一连接块92-1在基底上的正投影的范围之内，第三十二过孔K32内的第四绝缘层被刻蚀掉，暴露出第二十一连接块92-1的表面，第三十二过孔K32被配置为使后续形成的第十二连接电极通过该过孔与第二十一连接块92-1连接。
在示例性实施方式中，第三十三过孔K33在基底上的正投影可以位于第二传输线92的第二十二连接块92-2在基底上的正投影的范围之内，第三十三过孔K33内的第四绝缘层被刻蚀掉，暴露出第二十二连接块92-2的表面，第三十三过孔K33被配置为使后续形成的第十三连接电极通过该过孔与第二十二连接块92-2连接。
在示例性实施方式中，第三十四过孔K34在基底上的正投影可以位于第十一栅极连接线61在基底上的正投影的范围之内，第三十四过孔K34内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十一栅极连接线61的表面，第三十四过孔K34被配置为使后续形成的第一控制线通过该过孔与第十一栅极连接线61连接。
在示例性实施方式中，第三十五过孔K35在基底上的正投影可以位于第十二栅极连接线62在基底上的正投影的范围之内，第三十五过孔K35内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十二栅极连接线62的表面，奇数的第一检测子单元中的第三十五过孔K35被配置为使后续形成的第三控制线通过该过孔与第十二栅极连接线62连接，偶数的第一检测子单元中的第三十五过孔K35被配置为使后续形成的第二控制线通过该过孔与第十二栅极连接线62连接。
在示例性实施方式中，第三十六过孔K36在基底上的正投影可以位于第十三栅极连接线63在基底上的正投影的范围之内，第三十六过孔K36内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第十三栅极连接线63的表面，奇 数的第一检测子单元中的第三十六过孔K36被配置为使后续形成的第二控制线通过该过孔与第十三栅极连接线63连接，偶数的第一检测子单元中的第三十六过孔K36被配置为使后续形成的第三控制线通过该过孔与第十三栅极连接线63连接。
如图15c所示，在示例性实施方式中，第二检测子单元中的多个可以包括第四十一过孔K41、第四十二过孔K42、第四十三过孔K43、第四十四过孔K44、第四十五过孔K45、第四十六过孔K46、第四十七过孔K47、第四十八过孔K48、第四十九过孔K49、第五十过孔K50、第五十一过孔K51、第五十二过孔K52、第五十三过孔K53、第五十四过孔K54、第五十五过孔K55、第五十六过孔K56、第五十七过孔K57和第五十八过孔K58。
在示例性实施方式中，第四十一过孔K41在基底上的正投影可以位于第二十一有源层121的第一区在基底上的正投影的范围之内，第四十一过孔K41内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十一有源层121的第一区的表面，第四十一过孔K41被配置为使后续形成的第二检测线通过该过孔与第二十一有源层121的第一区连接。
在示例性实施方式中，第四十二过孔K42在基底上的正投影可以位于第二十一有源层121的第二区在基底上的正投影的范围之内，第四十二过孔K42内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十一有源层121的第二区的表面，第四十二过孔K42被配置为使后续形成的第二十一连接电极通过该过孔与第二十一有源层121的第二区连接。
在示例性实施方式中，第四十三过孔K43在基底上的正投影可以位于第二十二有源层122的第一区在基底上的正投影的范围之内，第四十三过孔K43内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十二有源层122的第一区的表面，第四十三过孔K43被配置为使后续形成的第四检测线通过该过孔与第二十二有源层122的第一区连接。
在示例性实施方式中，第四十四过孔K44在基底上的正投影可以位于第二十二有源层122的第二区在基底上的正投影的范围之内，第四十四过孔K44内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十二有源层122的第二区的表面，第四十四过孔K44被配置为使后续形成的第二 十二连接电极通过该过孔与第二十二有源层122的第二区连接。
在示例性实施方式中，第四十五过孔K45在基底上的正投影可以位于第二十三有源层123的第一区在基底上的正投影的范围之内，第四十五过孔K45内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十三有源层123的第一区的表面，第四十五过孔K45被配置为使后续形成的第四检测线通过该过孔与第二十三有源层123的第一区连接。
在示例性实施方式中，第四十六过孔K46在基底上的正投影可以位于第二十三有源层123的第二区在基底上的正投影的范围之内，第四十六过孔K46内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十三有源层123的第二区的表面，第四十六过孔K46被配置为使后续形成的第二十三连接电极通过该过孔与第二十三有源层123的第二区连接。
在示例性实施方式中，第四十七过孔K47在基底上的正投影可以位于第二十四有源层124的第一区在基底上的正投影的范围之内，第四十七过孔K47内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十四有源层124的第一区的表面，第四十七过孔K47被配置为使后续形成的第六检测线通过该过孔与第二十四有源层124的第一区连接。
在示例性实施方式中，第四十八过孔K48在基底上的正投影可以位于第二十四有源层124的第二区在基底上的正投影的范围之内，第四十八过孔K48内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十四有源层124的第二区的表面，第四十八过孔K48被配置为使后续形成的第二十四连接电极通过该过孔与第二十四有源层124的第二区连接。
在示例性实施方式中，第四十九过孔K49在基底上的正投影可以位于第二十五有源层125的第一区在基底上的正投影的范围之内，第四十九过孔K49内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十五有源层125的第一区的表面，第四十九过孔K49被配置为使后续形成的第六检测线通过该过孔与第二十五有源层125的第一区连接。
在示例性实施方式中，第五十过孔K50在基底上的正投影可以位于第二十五有源层125的第二区在基底上的正投影的范围之内，第五十过孔K50内的第二绝缘层、第三绝缘层和第四绝缘层被刻蚀掉，暴露出第二十五有源层 125的第二区的表面，第五十过孔K50被配置为使后续形成的第二十五连接电极通过该过孔与第二十五有源层125的第二区连接。
在示例性实施方式中，第五十一过孔K51在基底上的正投影可以位于第三传输线93的第三十一连接块93-1在基底上的正投影的范围之内，第五十一过孔K51内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三十一连接块93-1的表面，第五十一过孔K51被配置为使后续形成的第二十一连接电极通过该过孔与第三十一连接块93-1连接。
在示例性实施方式中，第五十二过孔K52在基底上的正投影可以位于第四传输线94的第四十一连接块94-1在基底上的正投影的范围之内，第五十二过孔K52内的第四绝缘层被刻蚀掉，暴露出第四十一连接块94-1的表面，第五十二过孔K52被配置为使后续形成的第二十二连接电极通过该过孔与第四十一连接块94-1连接。
在示例性实施方式中，第五十三过孔K53在基底上的正投影可以位于第四传输线94的第四十二连接块94-2在基底上的正投影的范围之内，第五十三过孔K53内的第四绝缘层被刻蚀掉，暴露出第四十二连接块94-2的表面，第五十三过孔K53被配置为使后续形成的第二十三连接电极通过该过孔与第四十二连接块94-2连接。
在示例性实施方式中，第五十四过孔K54在基底上的正投影可以位于第四传输线94的第四十三连接块94-3在基底上的正投影的范围之内，第五十四过孔K54内的第四绝缘层被刻蚀掉，暴露出第四十三连接块94-3的表面，第五十四过孔K54被配置为使后续形成的第二十四连接电极通过该过孔与第四十三连接块94-3连接。
在示例性实施方式中，第五十五过孔K55在基底上的正投影可以位于第四传输线94的第四十四连接块94-4在基底上的正投影的范围之内，第五十五过孔K55内的第四绝缘层被刻蚀掉，暴露出第四十四连接块94-4的表面，第五十五过孔K55被配置为使后续形成的第二十五连接电极通过该过孔与第四十四连接块94-4连接。
在示例性实施方式中，第五十六过孔K56在基底上的正投影可以位于第三十一栅极连接线71在基底上的正投影的范围之内，第五十六过孔K56内 的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三十一栅极连接线71的表面，第五十六过孔K56被配置为使后续形成的第一控制线通过该过孔与第三十一栅极连接线71连接。
在示例性实施方式中，第五十七过孔K57在基底上的正投影可以位于第三十二栅极连接线72在基底上的正投影的范围之内，第五十七过孔K57内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三十二栅极连接线72的表面，奇数的第二检测子单元中的第五十七过孔K57被配置为使后续形成的第二控制线通过该过孔与第三十二栅极连接线72连接，偶数的第二检测子单元中的第五十七过孔K57被配置为使后续形成的第三控制线通过该过孔与第三十二栅极连接线72连接。
在示例性实施方式中，第五十八过孔K58在基底上的正投影可以位于第三十三栅极连接线73在基底上的正投影的范围之内，第五十八过孔K58内的第三绝缘层和第四绝缘层被刻蚀掉，暴露出第三十三栅极连接线73的表面，奇数的第二检测子单元中的第五十八过孔K58被配置为使后续形成的第三控制线通过该过孔与第三十三栅极连接线73连接，偶数的第二检测子单元中的第五十八过孔K58被配置为使后续形成的第二控制线通过该过孔与第三十三栅极连接线73连接。
(4)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上沉积第三导电薄膜，通过图案化工艺对第三导电薄膜进行图案化，在第四绝缘层上形成第三导电层图案，如图16a、图16b和图16c所示，图16a为图11中A区域的结构，图16b为图11中B区域的结构，图16c为图11中C区域的结构。在示例性实施方式中，第三导电层可以称为第一源漏金属层(SD1)。
如图16a、图16b和图16c所示，第三导电层图案可以包括切换控制线100、第一控制线110、第二控制线120、第三控制线130、第一检测线210、第二检测线220、第三检测线230、第四检测线240、第五检测线250、第六检测线260、第一连接电极301、第二连接电极302、第三连接电极303、第十一连接电极311、第十二连接电极312、第十三连接电极313、第二十一连接电极321、第二十二连接电极322、第二十三连接电极323、第二十四连接 电极324和第二十五连接电极325。
在示例性实施方式中，切换控制线100的第一端与绑定引脚区的切换控制引脚连接，第二端延伸到检测电路区，通过第十过孔K10与切换连接线56连接。由于切换连接线56与第一栅电极201、第二栅电极202和第三栅电极203连接，因而切换控制线100传输的切换控制信号可以通过切换连接线56传输给第一栅电极201、第二栅电极202和第三栅电极203，控制第一晶体管T1、第二晶体管T2和第三晶体管T3的导通和断开。
在示例性实施方式中，第一控制线110的第一端与绑定引脚区的第一控制引脚连接，第二端延伸到检测电路区，第一控制线110一方面通过第三十四过孔K34与每个第一检测子单元中的第十一栅极连接线61连接，另一方面通过第五十六过孔K56与每个第二检测子单元中的第三十一栅极连接线71连接。由于第十一栅极连接线61与第十一栅电极211连接，第三十一栅极连接线71与第二十一栅电极221连接，因而第一控制线110传输的第一控制信号可以分别通过第十一栅极连接线61和第三十一栅极连接线71传输给第十一栅电极211和第二十一栅电极221，控制第十一晶体管T11和第二十一晶体管T21的导通和断开。
在示例性实施方式中，第二控制线120的第一端与绑定引脚区的第二控制引脚连接，第二端延伸到检测电路区。在第一检测单元，第二控制线120一方面通过奇数的第一检测子单元中的第三十六过孔K36与第十三栅极连接线63连接，另一方面通过偶数的第一检测子单元中的第三十五过孔K35与第十二栅极连接线62连接。在第二检测单元，第二控制线120一方面通过奇数的第二检测子单元中的第五十七过孔K57与第三十二栅极连接线72连接，另一方面通过偶数的第二检测子单元中的第五十八过孔K58与第三十三栅极连接线73连接。
由于第十二栅极连接线62与第十二栅电极212和第十三栅电极213连接，因而第二控制线120传输的第二控制信号可以控制偶数的第一检测子单元中的第十二晶体管T12和第十三晶体管T13的导通和断开。由于第十三栅极连接线63与第十四栅电极214和第十五栅电极215连接，因而第二控制线120传输的第二控制信号可以控制奇数的第一检测子单元中的第十四晶体管 T14和第十五晶体管T15的导通和断开。
由于第三十二栅极连接线72与第二十二栅电极222和第二十三栅电极223连接，因而第二控制线120传输的第二控制信号可以控制奇数的第二检测子单元中的第二十二晶体管T22和第二十三晶体管T23的导通和断开。由于第三十三栅极连接线73与第二十四栅电极224和第二十五栅电极225连接，因而第二控制线120传输的第二控制信号可以控制偶数的第二检测子单元中的第二十四晶体管T24和第二十五晶体管T25的导通和断开。
在示例性实施方式中，第三控制线130可以包括第三控制引出线130-1和第三控制延伸线130-2。第三控制引出线130-1的第一端与绑定引脚区的第三控制引脚连接，第二端延伸到检测电路区后，通过第十四过孔K14与第四信号连接线54的第一端连接，第三控制延伸线130-2的第一端通过第十四过孔K14与第四信号连接线54的第二端连接，第二端沿着第二方向Y延伸，使得第三控制引出线130-1和第三控制延伸线130-2通过第四信号连接线54构成第三控制线130。
在第一检测单元，第三控制线130一方面通过奇数的第一检测子单元中的第三十五过孔K35与第十二栅极连接线62连接，另一方面通过偶数的第一检测子单元中的第三十六过孔K36与第十三栅极连接线63连接。在第二检测单元，第三控制线130一方面通过奇数的第二检测子单元中的第五十八过孔K58与第三十三栅极连接线73连接，另一方面通过偶数的第二检测子单元中的第五十七过孔K57与第三十二栅极连接线72连接。
由于第十二栅极连接线62与第十二栅电极212和第十三栅电极213连接，因而第三控制线130传输的第三控制信号可以控制奇数的第一检测子单元中的第十二晶体管T12和第十三晶体管T13的导通和断开。由于第十三栅极连接线63与第十四栅电极214和第十五栅电极215连接，因而第三控制线130传输的第三控制信号可以控制偶数的第一检测子单元中的第十四晶体管T14和第十五晶体管T15的导通和断开。
由于第三十二栅极连接线72与第二十二栅电极222和第二十三栅电极223连接，因而第三控制线130传输的第三控制信号可以控制偶数的第二检测子单元中的第二十二晶体管T22和第二十三晶体管T23的导通和断开。由 于第三十三栅极连接线73与第二十四栅电极224和第二十五栅电极225连接，因而第三控制线130传输的第三控制信号可以控制奇数的第二检测子单元中的第二十四晶体管T24和第二十五晶体管T25的导通和断开。
在示例性实施方式中，第一检测线210可以包括第一检测引出线210-1和第一检测延伸线210-2。第一检测引出线210-1的第一端与绑定引脚区的第一检测引脚连接，第二端延伸到检测电路区后，通过第十二过孔K12与第二信号连接线52的第一端连接，第一检测延伸线210-2的第一端通过第十二过孔K12与第二信号连接线52的第二端连接，第二端沿着第二方向Y延伸，使得第一检测引出线210-1和第一检测延伸线210-2通过第二信号连接线52构成第一检测线210。
在示例性实施方式中，第一检测线210一方面通过第一过孔K1与第一有源层101的第一区连接，另一方面通过第二十一过孔K21与第一检测子单元中的第十一有源层111的第一区连接。
在示例性实施方式中，第二检测线220可以包括第二检测引出线220-1和第二检测延伸线220-2。第二检测引出线220-1的第一端与绑定引脚区的第二检测引脚连接，第二端延伸到检测电路区后，通过第十一过孔K11与第一信号连接线51的第一端连接，第二检测延伸线220-2的第一端通过第十一过孔K11与第一信号连接线51的第二端连接，第二端沿着第二方向Y延伸，使得第二检测引出线220-1和第二检测延伸线220-2通过第一信号连接线51构成第二检测线220。
在示例性实施方式中，第二检测线220一方面通过第二过孔K2与第一有源层101的第二区连接，另一方面通过第四十一过孔K41与第二检测子单元中的第二十一有源层121的第一区连接。
在示例性实施方式中，第三检测线230可以包括第三检测引出线230-1和第三检测延伸线230-2。第三检测引出线230-1的第一端与绑定引脚区的第三检测引脚连接，第二端延伸到检测电路区后，通过第十三过孔K13与第三信号连接线53的第一端连接，第三检测延伸线230-2的第一端通过第十三过孔K13与第三信号连接线53的第二端连接，第二端沿着第二方向Y延伸，使得第三检测引出线230-1和第三检测延伸线230-2通过第三信号连接线53 构成第三检测线230。
在示例性实施方式中，第三检测线230一方面通过第四过孔K4与第二有源层102的第一区连接，另一方面扩展成两条第三检测线230，一条第三检测线230通过第二十三过孔K23与第一检测子单元中的第十二有源层112的第一区连接，另一条第三检测线230通过第二十五过孔K25与第一检测子单元中的第十三有源层113的第一区连接。
在示例性实施方式中，第四检测线240的第一端与绑定引脚区的第四检测引脚连接，第二端延伸到检测电路区后，一方面通过第五过孔K5与第二有源层102的第二区连接，另一方面扩展成两条第四检测线240，一条第四检测线240通过第四十三过孔K43与第二十二有源层122的第一区连接，另一条第四检测线240通过第四十五过孔K45与第二十三有源层123的第一区连接。
在示例性实施方式中，第五检测线250可以包括第五检测引出线250-1和第五检测延伸线250-2。第五检测引出线250-1的第一端与绑定引脚区的第五检测引脚连接，第二端延伸到检测电路区后，通过第十五过孔K15与第五信号连接线55的第一端连接，第五检测延伸线250-2的第一端通过第十五过孔K15与第五信号连接线55的第二端连接，第二端沿着第二方向Y延伸，使得第五检测引出线250-1和第五检测延伸线250-2通过第五信号连接线55构成第五检测线250。
在示例性实施方式中，第五检测线250一方面通过第七过孔K7与第三有源层103的第一区连接，另一方面扩展成两条第五检测线250，一条第五检测线250通过第二十七过孔K27与第十四有源层114的第一区连接，另一条第五检测线250通过第二十九过孔K29与第十五有源层115的第一区连接。
在示例性实施方式中，第六检测线260的第一端与绑定引脚区的第六检测引脚连接，第二端延伸到检测电路区后，一方面通过第八过孔K8与第三有源层103的第二区连接，另一方面扩展成两条第六检测线260，一条第六检测线260通过第四十七过孔K47与第二十四有源层124的第一区连接，另一条第六检测线260通过第四十九过孔K49与第二十五有源层125的第一区连接。
在示例性实施方式中，第一连接电极301设置在第一检测线210和第二检测线220之间，通过两个第三过孔K3与第一有源层101的第三区连接，第一连接电极301可以作为两个第一晶体管T1的连接电极，既作为一个第一晶体管T1的第一极，又作为另一个第一晶体管T1的第二极，实现两个第一晶体管T1的串联结构。
在示例性实施方式中，第二连接电极302设置在第三检测线230和第四检测线240之间，通过两个第六过孔K6与第二有源层102的第三区连接，第二连接电极302可以作为两个第二晶体管T2的连接电极，既作为一个第二晶体管T2的第一极，又作为另一个第二晶体管T2的第二极，实现两个第二晶体管T2的串联结构。
在示例性实施方式中，第三连接电极303设置在第五检测线250和第六检测线260之间，通过两个第九过孔K9与第三有源层103的第三区连接，第三连接电极303可以作为两个第三晶体管T3的连接电极，既作为一个第三晶体管T3的第一极，又作为另一个第三晶体管T3的第二极，实现两个第三晶体管T3的串联结构。
在示例性实施方式中，第十一连接电极311可以设置在第一检测子单元中第十一栅电极211第一方向X的反方向的一侧，第十一连接电极311一方面通过第二十二过孔K22与第十一有源层111的第二区连接，另一方面通过第三十一过孔K31与第一传输线91的第十一连接块91-1连接，实现第十一晶体管T11控制第一检测线210和第一传输线91之间的导通和断开。在第十一晶体管T11导通时，第一检测线210传输的第一信号传输给第一传输线91，第一传输线91将第一信号传输给显示区域中连接G子像素的第一数据线。
在示例性实施方式中，第十二连接电极312可以设置在第一检测子单元中第十二栅电极212和第十三栅电极213之间，第十二连接电极312一方面通过第二十四过孔K24与第十二有源层112的第二区连接，另一方面通过第二十六过孔K26与第十三有源层113的第二区连接，又一方面通过第三十二过孔K32与第二传输线92的第二十一连接块92-1连接，实现第十二晶体管T12和第十三晶体管T13控制第三检测线230和第二传输线92之间的导通和 断开。在第十二晶体管T12和第十三晶体管T13导通时，第三检测线230传输的第三信号传输给第二传输线92，第二传输线92将第三信号传输给显示区域中连接B子像素和R子像素的第一数据线。
在示例性实施方式中，第十三连接电极313可以设置在第一检测子单元中第十四栅电极214和第十五栅电极215之间，第十三连接电极313一方面通过第二十八过孔K28与第十四有源层114的第二区连接，另一方面通过第三十过孔K30与第十五有源层115的第二区连接，又一方面通过第三十三过孔K33与第二传输线92的第二十二连接块92-2连接，实现第十四晶体管T14和第十五晶体管T15控制第五检测线250和第二传输线92之间的导通和断开。在第十四晶体管T14和第十五晶体管T15导通时，第五检测线250传输的第五信号传输给第二传输线92，第二传输线92将第五信号传输给显示区域中连接B子像素和R子像素的第一数据线。
在示例性实施方式中，第二十一连接电极321可以设置在第二检测子单元中第二十一栅电极221第一方向X的反方向的一侧，第二十一连接电极321一方面通过第四十二过孔K42与第二十一有源层121的第二区连接，另一方面通过第五十一过孔K51与第三传输线93的第三十一连接块93-1连接，实现第二十一晶体管T21控制第二检测线220和第三传输线93之间的导通和断开。在第二十一晶体管T21导通时，第二检测线220传输的第二信号传输给第三传输线93，第三传输线93将第三信号传输给显示区域中连接G子像素的第二数据线。
在示例性实施方式中，第二十二连接电极322可以设置在第二检测子单元中第二十二栅电极222第一方向X的一侧，第二十二连接电极322一方面通过第四十四过孔K44与第二十二有源层122的第二区连接，另一方面通过五十二过孔K52与第四传输线94的第四十一连接块94-1连接，实现第二十二晶体管T22控制第四检测线240和第四传输线94之间的导通和断开。在第二十二晶体管T22导通时，第四检测线240传输的第四信号传输给第四传输线94，第四传输线94将第四信号传输给显示区域中连接B子像素和R子像素的第二数据线。
在示例性实施方式中，第二十三连接电极323可以设置在第二检测子单 元中第二十三栅电极223第一方向X的反方向的一侧，第二十三连接电极323一方面通过第四十六过孔K46与第二十三有源层123的第二区连接，另一方面通过第五十三过孔K53与第四传输线94的第四十二连接块94-2连接，实现第二十三晶体管T23控制第四检测线240和第四传输线94之间的导通和断开。在第二十三晶体管T23导通时，第四检测线240传输的第四信号传输给第四传输线94，第四传输线94将第四信号传输给显示区域中连接B子像素和R子像素的第二数据线。
在示例性实施方式中，第二十四连接电极324可以设置在第二检测子单元中第二十四栅电极224第一方向X的一侧，第二十四连接电极324一方面通过第四十八过孔K48与第二十四有源层124的第二区连接，另一方面通过第五十四过孔K54与第四传输线94的第四十三连接块94-3连接，实现第二十四晶体管T24控制第六检测线260和第四传输线94之间的导通和断开。在第二十四晶体管T24导通时，第六检测线260传输的第六信号传输给第四传输线94，第四传输线94将第六信号传输给显示区域中连接B子像素和R子像素的第二数据线。
在示例性实施方式中，第二十五连接电极325可以设置在第二检测子单元中第二十五栅电极225第一方向X的反方向的一侧，第二十五连接电极325一方面通过第五十过孔K50与第二十五有源层125的第二区连接，另一方面通过第五十五过孔K55与第四传输线94的第四十四连接块94-4连接，实现第二十五晶体管T25控制第六检测线260和第四传输线94之间的导通和断开。在第二十五晶体管T25导通时，第六检测线260传输的第六信号传输给第四传输线94，第四传输线94将第六信号传输给显示区域中连接B子像素和R子像素的第二数据线。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一绝缘层可称为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层可称之为栅绝缘(GI)层，第四绝缘层可称之为层间绝缘(ILD)层。第一导电薄膜、第二导电薄膜和第三导电薄膜可以采用金属材料，如银(Ag)、铜(Cu)、 铝(Al)、钛(Ti)和钼(Mo)中的任意一种或多种，或者上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩或聚噻吩等材料，即本公开适用于基于氧化物(Oxide)技术、硅技术或有机物技术制造的晶体管。
图17为本公开示例性实施例一种检测电路与引脚连接的结构示意图。如图17所示，绑定区域的绑定引脚区可以至少包括切换控制引脚PN-A、第一控制引脚PN-B、第二控制引脚PN-C、第三控制引脚PN-D、第一检测引脚PN-E、第二检测引脚PN-F、第三检测引脚PN-G、第四检测引脚PN-H、第五检测引脚PN-I和第六检测引脚PN-J。
在示例性实施方式中，切换控制引脚PN-A可以与切换控制线100连接，第一控制引脚PN-B可以与第一控制线110连接，第二控制引脚PN-C可以与第二控制线120连接，第三控制引脚PN-D可以与第三控制线130连接，第一检测引脚PN-E可以与第一检测线210连接，第二检测引脚PN-F可以与第二检测线220连接，第三检测引脚PN-G可以与第三检测线230连接，第四检测引脚PN-H可以与第四检测线240连接，第五检测引脚PN-I可以与第五检测线250连接，第六检测引脚PN-J可以与第六检测线260连接。
在示例性实施方式中，检测电路的多条信号线可以采用折线方式从绑定引脚区延伸到检测电路区，本公开在此不做限定。
本公开所示检测电路的结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少图案化工艺，检测电路还可以设置其它电极、引线或膜层，本公开在此不做限定。
图18为本公开示例性实施例又一种检测电路的等效电路示意图。如图18所示，检测电路可以包括多个第一检测子单元11、多个第二检测子单元12、至少一个控制线20、至少一个第一信号线31、至少一个第二信号线32、至少一个切换控制线41、至少一个切换单元42、至少一个开关控制线43和至少一个开关单元44。
在示例性实施方式中，多个第一检测子单元11和多个第二检测子单元 12可以均包括控制端、输入端和输出端，多个第一检测子单元11和多个第二检测子单元12可以沿着第二方向Y以设定的间隔依次设置，多个第一检测子单元11的位置可以与显示区域中的多条第一数据线D1的位置一一对应，多个第二检测子单元12的位置可以与显示区域中的多条第二数据线D2的位置一一对应。
在示例性实施方式中，控制线20的一端与绑定引脚区的控制引脚对应连接，控制线20的另一端同时与多个第一检测子单元11和多个第二检测子单元12的控制端连接，控制线20被配置为控制多个第一检测子单元11和多个第二检测子单元12的导通或者断开。
在示例性实施方式中，第一信号线31的一端与绑定引脚区的第一信号引脚对应连接，第一信号线31的另一端与多个第一检测子单元11的输入端连接，多个第一检测子单元11的输出端与显示区域的多条第一数据线D1对应连接。
在示例性实施方式中，第二信号线32的一端与开关单元44的开关第二端连接，第二信号线32的另一端与多个第二检测子单元12的输入端连接，多个第二检测子单元12的输出端与显示区域的多条第二数据线D2对应连接。
在示例性实施方式中，切换控制线41的一端与绑定引脚区的切换引脚对应连接，切换控制线41的另一端与切换单元42的切换控制端连接，切换单元42的切换第一端与第一信号线31连接，切换单元42的切换第二端与第二信号线32连接，切换单元42被配置为在切换控制线41的控制下，使第一信号线31和第二信号线32隔离或者导通。在第一信号线31和第二信号线32隔离时，第一信号线31和第二信号线32输出不同的老化电压信号，在第一信号线31和第二信号线32导通时，第一信号线31和第二信号线32输出相同的点灯电压信号。
在示例性实施方式中，开关控制线43的一端与绑定引脚区的开关引脚对应连接，开关控制线43的另一端与开关单元44的开关控制端连接，开关单元44的开关第一端与信号引线45的一端连接，开关单元44的开关第二端与第二信号线32连接，信号引线45的另一端与绑定引脚区的第二信号引脚 对应连接，开关单元44被配置为在开关控制线43的控制下，使信号引线45和第二信号线32隔离或者导通。在信号引线45和第二信号线32隔离时，第一信号线31和第二信号线32导通，第一信号线31和第二信号线32输出相同的点灯电压信号。在信号引线45和第二信号线32导通时，第一信号线31和第二信号线32隔离，第一信号线31和第二信号线32输出不同的老化电压信号。
在示例性实施方式中，开关单元44可以包括开关晶体管，开关晶体管的控制极与开关控制线43连接，开关晶体管的第一极与信号引线45连接，开关晶体管的第二极与第二信号线32连接。
在示例性实施方式中，本示例性实施例检测电路进行老化程序的工作过程为：外部装置通过控制引脚输出控制信号，通过切换引脚输出断开信号，通过开关引脚输出导通信号，通过第一信号引脚输出第一老化电压信号，通过第二信号引脚输出第二老化电压信号。控制线20传输的控制信号控制多个第一检测子单元11和多个第二检测子单元12导通，切换控制线41传输的断开信号控制切换单元42断开，使得第一信号线31和第二信号线32隔离，开关控制线43传输的导通信号控制开关单元44导通，使得信号引线45和第二信号线32导通。导通的多个第一检测子单元11将第一信号线31传输的第一老化电压信号分别输出给显示区域的多条第一数据线D1，利用第一老化电压信号对第一显示区中的第一子像素进行老化处理。导通的多个第二检测子单元12将第二信号线32传输的第二老化电压信号分别输出给显示区域的多条第二数据线D2，利用第二老化电压信号对第二显示区中第二子像素进行老化处理，第一显示区和第二显示区的老化电压不同。
在示例性实施方式中，本示例性实施例检测电路进行点灯检测的工作过程为：外部装置通过控制引脚输出控制信号，通过切换引脚输出导通信号，通过开关引脚输出断开信号，通过第一信号引脚输出点灯电压信号或者通过第二信号引脚输出点灯电压信号。控制线20传输的控制信号控制多个第一检测子单元11和多个第二检测子单元12导通，开关控制线43传输的断开信号控制开关单元44断开，使得信号引线45和第二信号线32隔离，切换控制线41传输的导通信号控制切换单元42导通，使得第一信号线31和第二信号线 32连通，第一信号线31和第二信号线32传输相同的点灯电压信号。导通的多个第一检测子单元11和多个第二检测子单元12将点灯电压信号分别输出给显示区域的多条第一数据线D1和多条第二数据线D2，利用相同的点灯电压信号对第一显示区和第二显示区中子像素进行点灯检测。
本示例性实施例提出的分区老化和整体点灯的技术方案，不仅第一显示区和第二显示区的老化电压不同，可以消除第一显示区和第二显示区的亮度差异，第一显示区和第二显示区采用相同的点灯电压，因而可以保证画面均一性，而且通过采用开关单元，可以提高分区老化和整体点灯的可靠性。
本公开示例性实施例还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。

Claims (25)

  1. 一种显示基板，包括显示区域和位于所述显示区域一侧的绑定区域，所述显示区域包括第一显示区和第二显示区，所述第一显示区至少部分围绕所述第二显示区，所述第一显示区被配置为进行图像显示，所述第二显示区被配置为进行图像显示和透过光线；所述第一显示区包括多个第一子像素和至少一条与所述第一子像素电连接的第一数据线，所述第二显示区包括多个第二子像素和至少一条与所述第二子像素电连接的第二数据线；所述绑定区域包括检测电路，所述检测电路包括控制线、第一信号线、第二信号线、至少一个第一检测子单元和至少一个第二检测子单元；所述第一检测子单元的控制端与所述控制线连接，所述第一检测子单元的输入端与所述第一信号线连接，所述第一检测子单元的输出端与所述第一数据线连接，所述第一检测子单元被配置为将所述第一信号线传输的信号输出给所述第一数据线；所述第二检测子单元的控制端与所述控制线连接，所述第二检测子单元的输入端与所述第二信号线连接，所述第二检测子单元的输出端与所述第二数据线连接，所述第二检测子单元被配置为将所述第二信号线传输的信号输出给所述第二数据线。
  2. 根据权利要求1所述的显示基板，其中，所述控制线包括第一控制线、第二控制线和第三控制线，所述第一信号线包括第一检测线、第三检测线和第五检测线，所述第二信号线包括第二检测线、第四检测线和第六检测线，所述第一检测子单元包括第十一开关单元、第十二开关单元和第十三开关单元，所述第二检测子单元包括第二十一开关单元、第二十二开关单元和第二十三开关单元；所述第十一开关单元被配置为在所述第一控制线的控制下，将所述第一检测线传输的信号发送给所述第一显示区中连接第一颜色子像素的第一数据线；所述第十二开关单元被配置为在所述第二控制线的控制下，将所述第三检测线传输的信号发送给所述第一显示区中连接第二颜色子像素的第一数据线；所述第十三开关单元被配置为在所述第三控制线的控制下，将所述第五检测线传输的信号发送给所述第一显示区中连接第三颜色子像素的第一数据线；所述第二十一开关单元被配置为在所述第一控制线的控制下，将所述第二检测线传输的信号发送给所述第二显示区中连接第一颜色 子像素的第二数据线；所述第二十二开关单元被配置为在所述第二控制线的控制下，将所述第四检测线传输的信号发送给所述第二显示区中连接第二颜色子像素的第二数据线；所述第二十三开关单元被配置为在所述第三控制线的控制下，将所述第六检测线传输的信号发送给所述第二显示区中连接第三颜色子像素的第二数据线。
  3. 根据权利要求2所述的显示基板，其中，所述第十一开关单元的控制端与所述第一控制线连接，所述第十一开关单元的输入端与所述第一检测线连接，所述第十一开关单元的输出端与所述第一显示区中连接第一颜色子像素的第一数据线连接；所述第二十一开关单元的控制端与所述第一控制线连接，所述第二十一开关单元的输入端与所述第二检测线连接，所述第二十一开关单元的输出端与所述第二显示区中连接第一颜色子像素的第二数据线连接。
  4. 根据权利要求3所述的显示基板，其中，所述第十一开关单元包括至少一个第十一晶体管，所述第十一晶体管的控制极与所述第一控制线连接，所述第十一晶体管的第一极与所述第一检测线连接，所述第十一晶体管的第二极与所述第一显示区中连接第一颜色子像素的第一数据线连接；所述第二十一开关单元包括至少一个第二十一晶体管，所述第二十一晶体管的控制极与所述第一控制线连接，所述第二十一晶体管的第一极与所述第二检测线连接，所述第二十一晶体管的第二极与所述第二显示区中连接第一颜色子像素的第二数据线连接。
  5. 根据权利要求2所述的显示基板，其中，所述第十二开关单元的控制端与所述第二控制线连接，所述第十二开关单元的输入端与所述第三检测线连接，所述第十二开关单元的输出端与所述第一显示区中连接第二颜色子像素的第一数据线连接；所述第二十二开关单元的控制端与所述第二控制线连接，所述第二十二开关单元的输入端与所述第四检测线连接，所述第二十二开关单元的输出端与所述第二显示区中连接第二颜色子像素的第二数据线连接。
  6. 根据权利要求5所述的显示基板，其中，所述第十二开关单元包括至少一个第十二晶体管和至少一个第十三晶体管，所述第十二晶体管和第十 三晶体管的控制极与所述第二控制线连接，所述第十二晶体管和第十三晶体管的第一极与所述第三检测线连接，所述第十二晶体管和第十三晶体管的第二极与所述第一显示区中连接第二颜色子像素的第一数据线连接；所述第二十二开关单元包括至少一个第二十二晶体管和至少一个第二十三晶体管，所述第二十二晶体管和第二十三晶体管的控制极与所述第二控制线连接，所述第二十二晶体管和第二十三晶体管的第一极与所述第四检测线连接，所述第二十二晶体管和第二十三晶体管的第二极与所述第二显示区中连接第二颜色子像素的第二数据线连接。
  7. 根据权利要求2所述的显示基板，其中，所述第十三开关单元的控制端与所述第三控制线连接，所述第十三开关单元的输入端与所述第五检测线连接，所述第十三开关单元的输出端与所述第一显示区中连接第三颜色子像素的第一数据线连接；所述第二十三开关单元的控制端与所述第三控制线连接，所述第二十三开关单元的输入端与所述第六检测线连接，所述第二十三开关单元的输出端与所述第二显示区中连接第三颜色子像素的第二数据线连接。
  8. 根据权利要求7所述的显示基板，其中，所述第十三开关单元包括至少一个第十四晶体管和至少一个第十五晶体管，所述第十四晶体管和第十五晶体管的控制极与所述第三控制线连接，所述第十四晶体管和第十五晶体管的第一极与所述第五检测线连接，所述第十四晶体管和第十五晶体管的第二极与所述第一显示区中连接第三颜色子像素的第一数据线连接；所述第二十三开关单元包括至少一个第二十四晶体管和至少一个第二十五晶体管，所述第二十四晶体管和第二十五晶体管的控制极与所述第三控制线连接，所述第二十四晶体管和第二十五晶体管的第一极与所述第六检测线连接，所述第二十四晶体管和第二十五晶体管的第二极与所述第二显示区中连接第三颜色子像素的第二数据线连接。
  9. 根据权利要求1至8任一项所述的显示基板，其中，所述检测电路还包括切换控制线和切换单元，所述切换单元的控制极与所述切换控制线连接，所述切换单元的第一极与所述第一信号线连接，所述切换单元的第二极与所述第二信号线连接，所述切换单元被配置为在所述切换控制线的控制下，将 所述第一信号线和第二信号线隔离或者导通。
  10. 根据权利要求9所述的显示基板，其中，所述切换单元包括第一切换子单元、第二切换子单元和第三切换子单元；所述第一信号线包括第一检测线、第三检测线和第五检测线；所述第二信号线包括第二检测线、第四检测线和第六检测线；所述第一切换子单元的控制极与所述切换控制线连接，所述第一切换子单元的第一极与所述第一检测线连接，所述第一切换子单元的第二极与所述第二检测线连接；所述第二切换子单元的控制极与所述切换控制线连接，所述第二切换子单元的第一极与所述第三检测线连接，所述第二切换子单元的第二极与所述第四检测线连接；所述第三切换子单元的控制极与所述切换控制线连接，所述第三切换子单元的第一极与所述第五检测线连接，所述第三切换子单元的第二极与所述第六检测线连接。
  11. 根据权利要求10所述的显示基板，其中，所述第一切换子单元包括两个串联的第一晶体管，两个第一晶体管的控制极与所述切换控制线连接，一个第一晶体管的第一极与所述第一检测线连接，另一个第一晶体管的第二极与所述第二检测线连接，所述一个第一晶体管的第二极和所述另一个第一晶体管的第一极相互连接。
  12. 根据权利要求10所述的显示基板，其中，所述第二切换子单元包括两个串联的第二晶体管，两个第二晶体管的控制极与所述切换控制线连接，一个第二晶体管的第一极与所述第三检测线连接，另一个第二晶体管的第二极与所述第四检测线连接，所述一个第二晶体管的第二极和所述另一个第二晶体管的第一极相互连接。
  13. 根据权利要求10所述的显示基板，其中，所述第三切换子单元包括两个串联的第三晶体管，两个第三晶体管的控制极与所述切换控制线连接，一个第三晶体管的第一极与所述第五检测线连接，另一个第三晶体管的第二极与所述第六检测线连接，所述一个第三晶体管的第二极和所述另一个第三晶体管的第一极相互连接。
  14. 根据权利要求9所述的显示基板，其中，所述检测电路还包括开关 控制线、开关单元和信号引线，所述开关单元的控制极与所述开关控制线连接，所述开关单元的第一极与所述信号引线连接，所述开关单元的第二极与所述第二信号线连接，所述开关单元被配置为在所述开关控制线的控制下，将所述信号引线和第二信号线隔离或者导通；在所述信号引线和第二信号线导通时，所述第一信号线和第二信号线隔离，所述第一信号线和第二信号线输出不同的老化电压信号；在所述信号引线和第二信号线隔离时，所述第一信号线和第二信号线导通，所述第一信号线和第二信号线输出相同的点灯电压信号。
  15. 根据权利要求1至14任一项所述的显示基板，其中，在垂直于所述显示基板的平面上，所述显示基板包括在基底上依次设置的半导体层、第一导电层、第二导电层和第三导电层，所述半导体层包括切换单元中多个晶体管的有源层、第一检测子单元中多个晶体管的有源层和第二检测子单元中多个晶体管的有源层，所述第一导电层包括切换单元中多个晶体管的栅电极、第一检测子单元中多个晶体管的栅电极和第二检测子单元中多个晶体管的栅电极，所述第三导电层包括所述控制线、第一信号线和第二信号线。
  16. 根据权利要求15所述的显示基板，其中，所述控制线包括第一控制线、第二控制线和第三控制线，所述第一控制线、第二控制线和第三控制线中的至少一条包括控制引出线和控制延伸线，所述控制引出线和控制延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述控制引出线和控制延伸线设置在所述第三导电层中。
  17. 根据权利要求15所述的显示基板，其中，所述第一信号线包括第一检测线、第三检测线和第五检测线，所述第二信号线包括第二检测线、第四检测线和第六检测线，所述第一检测线、第二信号线、第三检测线、第四检测线、第五检测线和第六检测线中的至少一条包括检测引出线和检测延伸线，所述检测引出线和检测延伸线通过信号连接线连接，所述信号连接线设置在所述第一导电层中，所述检测引出线和检测延伸线设置在所述第三导电层中。
  18. 根据权利要求15所述的显示基板，其中，所述第一导电层还包括 切换连接线，所述第三导电层还包括切换控制线，所述切换连接线通过过孔与所述切换控制线连接，所述切换连接线与切换单元中多个晶体管的栅电极为相互连接的一体结构。
  19. 根据权利要求15所述的显示基板，其中，所述第一检测子单元包括第一传输线和第二传输线，所述第一传输线与所述第一显示区中连接第一颜色子像素的第一数据线连接，所述第二传输线与所述第一显示区中连接第二颜色子像素和第三颜色子像素的第一数据线连接；所述第一传输线设置在所述第一导电层中，所述第二传输线设置在所述第二导电层中。
  20. 根据权利要求19所述的显示基板，其中，所述第二传输线上设置有第二十一连接块和第二十二连接块；所述第二十一连接块通过第十二连接电极与所述第一检测子单元中的第十二有源层和第十三有源层连接，所述第二十一连接块设置在所述第十二有源层和第十三有源层之间；所述第二十二连接块通过第十三连接电极与所述第一检测子单元中的第十四有源层和第十五有源层连接，所述第二十二连接块设置在所述第十四有源层和第十五有源层之间。
  21. 根据权利要求20所述的显示基板，其中，所述第十二连接电极和第十三连接电极设置在所述第三导电层中。
  22. 根据权利要求15所述的显示基板，其中，所述第二检测子单元包括第三传输线和第四传输线，所述第三传输线与所述第二显示区中连接第一颜色子像素的第二数据线连接，所述第四传输线与所述第二显示区中连接第二颜色子像素和第三颜色子像素的第二数据线连接；所述第三传输线设置在所述第一导电层中，所述第四传输线设置在所述第二导电层中。
  23. 根据权利要求22所述的显示基板，其中，所述第四传输线上设置有第四十一连接块、第四十二连接块、第四十三连接块和第四十四连接块；所述第四十一连接块通过第二十二连接电极与所述第二检测子单元中的第二十二有源层连接，所述第四十一连接块设置在所述第二十二有源层第一方向的一侧；所述第四十二连接块通过第二十三连接电极与所述第二检测子单元 中的第二十三有源层连接，所述第四十二连接块设置在所述第二十三有源层第一方向的反方向的一侧；所述第四十三连接块通过第二十四连接电极与所述第二检测子单元中的第二十四有源层连接，所述第四十三连接块设置在所述第二十四有源层第一方向的一侧；所述第四十四连接块通过第二十五连接电极与所述第二检测子单元中的第二十五有源层连接，所述第四十四连接块设置在所述第二十五有源层第一方向的反方向的一侧；所述第一方向为所述第四传输线的延伸方向。
  24. 根据权利要求23所述的显示基板，其中，所述第二十二连接电极、第二十三连接电极、第二十四连接电极和第二十五连接电极设置在所述第三导电层中。
  25. 一种显示装置，包括如权利要求1至24任一项所述的显示基板。
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